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[mesa.git] / src / amd / vulkan / winsys / amdgpu / radv_amdgpu_cs.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <stdlib.h>
26 #include <amdgpu.h>
27 #include <amdgpu_drm.h>
28 #include <assert.h>
29
30 #include "ac_debug.h"
31 #include "radv_radeon_winsys.h"
32 #include "radv_amdgpu_cs.h"
33 #include "radv_amdgpu_bo.h"
34 #include "sid.h"
35
36
37 enum {
38 VIRTUAL_BUFFER_HASH_TABLE_SIZE = 1024
39 };
40
41 struct radv_amdgpu_cs {
42 struct radeon_winsys_cs base;
43 struct radv_amdgpu_winsys *ws;
44
45 struct amdgpu_cs_ib_info ib;
46
47 struct radeon_winsys_bo *ib_buffer;
48 uint8_t *ib_mapped;
49 unsigned max_num_buffers;
50 unsigned num_buffers;
51 amdgpu_bo_handle *handles;
52 uint8_t *priorities;
53
54 struct radeon_winsys_bo **old_ib_buffers;
55 unsigned num_old_ib_buffers;
56 unsigned max_num_old_ib_buffers;
57 unsigned *ib_size_ptr;
58 bool failed;
59 bool is_chained;
60
61 int buffer_hash_table[1024];
62 unsigned hw_ip;
63
64 unsigned num_virtual_buffers;
65 unsigned max_num_virtual_buffers;
66 struct radeon_winsys_bo **virtual_buffers;
67 uint8_t *virtual_buffer_priorities;
68 int *virtual_buffer_hash_table;
69 };
70
71 static inline struct radv_amdgpu_cs *
72 radv_amdgpu_cs(struct radeon_winsys_cs *base)
73 {
74 return (struct radv_amdgpu_cs*)base;
75 }
76
77 static int ring_to_hw_ip(enum ring_type ring)
78 {
79 switch (ring) {
80 case RING_GFX:
81 return AMDGPU_HW_IP_GFX;
82 case RING_DMA:
83 return AMDGPU_HW_IP_DMA;
84 case RING_COMPUTE:
85 return AMDGPU_HW_IP_COMPUTE;
86 default:
87 unreachable("unsupported ring");
88 }
89 }
90
91 static int radv_amdgpu_signal_sems(struct radv_amdgpu_ctx *ctx,
92 uint32_t ip_type,
93 uint32_t ring,
94 struct radv_winsys_sem_info *sem_info);
95 static int radv_amdgpu_cs_submit(struct radv_amdgpu_ctx *ctx,
96 struct amdgpu_cs_request *request,
97 struct radv_winsys_sem_info *sem_info);
98
99 static void radv_amdgpu_request_to_fence(struct radv_amdgpu_ctx *ctx,
100 struct radv_amdgpu_fence *fence,
101 struct amdgpu_cs_request *req)
102 {
103 fence->fence.context = ctx->ctx;
104 fence->fence.ip_type = req->ip_type;
105 fence->fence.ip_instance = req->ip_instance;
106 fence->fence.ring = req->ring;
107 fence->fence.fence = req->seq_no;
108 fence->user_ptr = (volatile uint64_t*)(ctx->fence_map + (req->ip_type * MAX_RINGS_PER_TYPE + req->ring) * sizeof(uint64_t));
109 }
110
111 static struct radeon_winsys_fence *radv_amdgpu_create_fence()
112 {
113 struct radv_amdgpu_fence *fence = calloc(1, sizeof(struct radv_amdgpu_fence));
114 return (struct radeon_winsys_fence*)fence;
115 }
116
117 static void radv_amdgpu_destroy_fence(struct radeon_winsys_fence *_fence)
118 {
119 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
120 free(fence);
121 }
122
123 static bool radv_amdgpu_fence_wait(struct radeon_winsys *_ws,
124 struct radeon_winsys_fence *_fence,
125 bool absolute,
126 uint64_t timeout)
127 {
128 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
129 unsigned flags = absolute ? AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE : 0;
130 int r;
131 uint32_t expired = 0;
132
133 if (fence->user_ptr) {
134 if (*fence->user_ptr >= fence->fence.fence)
135 return true;
136 if (!absolute && !timeout)
137 return false;
138 }
139
140 /* Now use the libdrm query. */
141 r = amdgpu_cs_query_fence_status(&fence->fence,
142 timeout,
143 flags,
144 &expired);
145
146 if (r) {
147 fprintf(stderr, "amdgpu: radv_amdgpu_cs_query_fence_status failed.\n");
148 return false;
149 }
150
151 if (expired)
152 return true;
153
154 return false;
155 }
156
157 static void radv_amdgpu_cs_destroy(struct radeon_winsys_cs *rcs)
158 {
159 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(rcs);
160
161 if (cs->ib_buffer)
162 cs->ws->base.buffer_destroy(cs->ib_buffer);
163 else
164 free(cs->base.buf);
165
166 for (unsigned i = 0; i < cs->num_old_ib_buffers; ++i)
167 cs->ws->base.buffer_destroy(cs->old_ib_buffers[i]);
168
169 free(cs->old_ib_buffers);
170 free(cs->virtual_buffers);
171 free(cs->virtual_buffer_priorities);
172 free(cs->virtual_buffer_hash_table);
173 free(cs->handles);
174 free(cs->priorities);
175 free(cs);
176 }
177
178 static boolean radv_amdgpu_init_cs(struct radv_amdgpu_cs *cs,
179 enum ring_type ring_type)
180 {
181 for (int i = 0; i < ARRAY_SIZE(cs->buffer_hash_table); ++i)
182 cs->buffer_hash_table[i] = -1;
183
184 cs->hw_ip = ring_to_hw_ip(ring_type);
185 return true;
186 }
187
188 static struct radeon_winsys_cs *
189 radv_amdgpu_cs_create(struct radeon_winsys *ws,
190 enum ring_type ring_type)
191 {
192 struct radv_amdgpu_cs *cs;
193 uint32_t ib_size = 20 * 1024 * 4;
194 cs = calloc(1, sizeof(struct radv_amdgpu_cs));
195 if (!cs)
196 return NULL;
197
198 cs->ws = radv_amdgpu_winsys(ws);
199 radv_amdgpu_init_cs(cs, ring_type);
200
201 if (cs->ws->use_ib_bos) {
202 cs->ib_buffer = ws->buffer_create(ws, ib_size, 0,
203 RADEON_DOMAIN_GTT,
204 RADEON_FLAG_CPU_ACCESS|
205 RADEON_FLAG_NO_INTERPROCESS_SHARING);
206 if (!cs->ib_buffer) {
207 free(cs);
208 return NULL;
209 }
210
211 cs->ib_mapped = ws->buffer_map(cs->ib_buffer);
212 if (!cs->ib_mapped) {
213 ws->buffer_destroy(cs->ib_buffer);
214 free(cs);
215 return NULL;
216 }
217
218 cs->ib.ib_mc_address = radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va;
219 cs->base.buf = (uint32_t *)cs->ib_mapped;
220 cs->base.max_dw = ib_size / 4 - 4;
221 cs->ib_size_ptr = &cs->ib.size;
222 cs->ib.size = 0;
223
224 ws->cs_add_buffer(&cs->base, cs->ib_buffer, 8);
225 } else {
226 cs->base.buf = malloc(16384);
227 cs->base.max_dw = 4096;
228 if (!cs->base.buf) {
229 free(cs);
230 return NULL;
231 }
232 }
233
234 return &cs->base;
235 }
236
237 static void radv_amdgpu_cs_grow(struct radeon_winsys_cs *_cs, size_t min_size)
238 {
239 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
240
241 if (cs->failed) {
242 cs->base.cdw = 0;
243 return;
244 }
245
246 if (!cs->ws->use_ib_bos) {
247 const uint64_t limit_dws = 0xffff8;
248 uint64_t ib_dws = MAX2(cs->base.cdw + min_size,
249 MIN2(cs->base.max_dw * 2, limit_dws));
250
251 /* The total ib size cannot exceed limit_dws dwords. */
252 if (ib_dws > limit_dws)
253 {
254 cs->failed = true;
255 cs->base.cdw = 0;
256 return;
257 }
258
259 uint32_t *new_buf = realloc(cs->base.buf, ib_dws * 4);
260 if (new_buf) {
261 cs->base.buf = new_buf;
262 cs->base.max_dw = ib_dws;
263 } else {
264 cs->failed = true;
265 cs->base.cdw = 0;
266 }
267 return;
268 }
269
270 uint64_t ib_size = MAX2(min_size * 4 + 16, cs->base.max_dw * 4 * 2);
271
272 /* max that fits in the chain size field. */
273 ib_size = MIN2(ib_size, 0xfffff);
274
275 while (!cs->base.cdw || (cs->base.cdw & 7) != 4)
276 cs->base.buf[cs->base.cdw++] = 0xffff1000;
277
278 *cs->ib_size_ptr |= cs->base.cdw + 4;
279
280 if (cs->num_old_ib_buffers == cs->max_num_old_ib_buffers) {
281 cs->max_num_old_ib_buffers = MAX2(1, cs->max_num_old_ib_buffers * 2);
282 cs->old_ib_buffers = realloc(cs->old_ib_buffers,
283 cs->max_num_old_ib_buffers * sizeof(void*));
284 }
285
286 cs->old_ib_buffers[cs->num_old_ib_buffers++] = cs->ib_buffer;
287
288 cs->ib_buffer = cs->ws->base.buffer_create(&cs->ws->base, ib_size, 0,
289 RADEON_DOMAIN_GTT,
290 RADEON_FLAG_CPU_ACCESS|
291 RADEON_FLAG_NO_INTERPROCESS_SHARING);
292
293 if (!cs->ib_buffer) {
294 cs->base.cdw = 0;
295 cs->failed = true;
296 cs->ib_buffer = cs->old_ib_buffers[--cs->num_old_ib_buffers];
297 }
298
299 cs->ib_mapped = cs->ws->base.buffer_map(cs->ib_buffer);
300 if (!cs->ib_mapped) {
301 cs->ws->base.buffer_destroy(cs->ib_buffer);
302 cs->base.cdw = 0;
303 cs->failed = true;
304 cs->ib_buffer = cs->old_ib_buffers[--cs->num_old_ib_buffers];
305 }
306
307 cs->ws->base.cs_add_buffer(&cs->base, cs->ib_buffer, 8);
308
309 cs->base.buf[cs->base.cdw++] = PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0);
310 cs->base.buf[cs->base.cdw++] = radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va;
311 cs->base.buf[cs->base.cdw++] = radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va >> 32;
312 cs->ib_size_ptr = cs->base.buf + cs->base.cdw;
313 cs->base.buf[cs->base.cdw++] = S_3F2_CHAIN(1) | S_3F2_VALID(1);
314
315 cs->base.buf = (uint32_t *)cs->ib_mapped;
316 cs->base.cdw = 0;
317 cs->base.max_dw = ib_size / 4 - 4;
318
319 }
320
321 static bool radv_amdgpu_cs_finalize(struct radeon_winsys_cs *_cs)
322 {
323 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
324
325 if (cs->ws->use_ib_bos) {
326 while (!cs->base.cdw || (cs->base.cdw & 7) != 0)
327 cs->base.buf[cs->base.cdw++] = 0xffff1000;
328
329 *cs->ib_size_ptr |= cs->base.cdw;
330
331 cs->is_chained = false;
332 }
333
334 return !cs->failed;
335 }
336
337 static void radv_amdgpu_cs_reset(struct radeon_winsys_cs *_cs)
338 {
339 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
340 cs->base.cdw = 0;
341 cs->failed = false;
342
343 for (unsigned i = 0; i < cs->num_buffers; ++i) {
344 unsigned hash = ((uintptr_t)cs->handles[i] >> 6) &
345 (ARRAY_SIZE(cs->buffer_hash_table) - 1);
346 cs->buffer_hash_table[hash] = -1;
347 }
348
349 for (unsigned i = 0; i < cs->num_virtual_buffers; ++i) {
350 unsigned hash = ((uintptr_t)cs->virtual_buffers[i] >> 6) & (VIRTUAL_BUFFER_HASH_TABLE_SIZE - 1);
351 cs->virtual_buffer_hash_table[hash] = -1;
352 }
353
354 cs->num_buffers = 0;
355 cs->num_virtual_buffers = 0;
356
357 if (cs->ws->use_ib_bos) {
358 cs->ws->base.cs_add_buffer(&cs->base, cs->ib_buffer, 8);
359
360 for (unsigned i = 0; i < cs->num_old_ib_buffers; ++i)
361 cs->ws->base.buffer_destroy(cs->old_ib_buffers[i]);
362
363 cs->num_old_ib_buffers = 0;
364 cs->ib.ib_mc_address = radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va;
365 cs->ib_size_ptr = &cs->ib.size;
366 cs->ib.size = 0;
367 }
368 }
369
370 static int radv_amdgpu_cs_find_buffer(struct radv_amdgpu_cs *cs,
371 amdgpu_bo_handle bo)
372 {
373 unsigned hash = ((uintptr_t)bo >> 6) & (ARRAY_SIZE(cs->buffer_hash_table) - 1);
374 int index = cs->buffer_hash_table[hash];
375
376 if (index == -1)
377 return -1;
378
379 if (cs->handles[index] == bo)
380 return index;
381
382 for (unsigned i = 0; i < cs->num_buffers; ++i) {
383 if (cs->handles[i] == bo) {
384 cs->buffer_hash_table[hash] = i;
385 return i;
386 }
387 }
388
389 return -1;
390 }
391
392 static void radv_amdgpu_cs_add_buffer_internal(struct radv_amdgpu_cs *cs,
393 amdgpu_bo_handle bo,
394 uint8_t priority)
395 {
396 unsigned hash;
397 int index = radv_amdgpu_cs_find_buffer(cs, bo);
398
399 if (index != -1) {
400 cs->priorities[index] = MAX2(cs->priorities[index], priority);
401 return;
402 }
403
404 if (cs->num_buffers == cs->max_num_buffers) {
405 unsigned new_count = MAX2(1, cs->max_num_buffers * 2);
406 cs->handles = realloc(cs->handles, new_count * sizeof(amdgpu_bo_handle));
407 cs->priorities = realloc(cs->priorities, new_count * sizeof(uint8_t));
408 cs->max_num_buffers = new_count;
409 }
410
411 cs->handles[cs->num_buffers] = bo;
412 cs->priorities[cs->num_buffers] = priority;
413
414 hash = ((uintptr_t)bo >> 6) & (ARRAY_SIZE(cs->buffer_hash_table) - 1);
415 cs->buffer_hash_table[hash] = cs->num_buffers;
416
417 ++cs->num_buffers;
418 }
419
420 static void radv_amdgpu_cs_add_virtual_buffer(struct radeon_winsys_cs *_cs,
421 struct radeon_winsys_bo *bo,
422 uint8_t priority)
423 {
424 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
425 unsigned hash = ((uintptr_t)bo >> 6) & (VIRTUAL_BUFFER_HASH_TABLE_SIZE - 1);
426
427
428 if (!cs->virtual_buffer_hash_table) {
429 cs->virtual_buffer_hash_table = malloc(VIRTUAL_BUFFER_HASH_TABLE_SIZE * sizeof(int));
430 for (int i = 0; i < VIRTUAL_BUFFER_HASH_TABLE_SIZE; ++i)
431 cs->virtual_buffer_hash_table[i] = -1;
432 }
433
434 if (cs->virtual_buffer_hash_table[hash] >= 0) {
435 int idx = cs->virtual_buffer_hash_table[hash];
436 if (cs->virtual_buffers[idx] == bo) {
437 cs->virtual_buffer_priorities[idx] = MAX2(cs->virtual_buffer_priorities[idx], priority);
438 return;
439 }
440 for (unsigned i = 0; i < cs->num_virtual_buffers; ++i) {
441 if (cs->virtual_buffers[i] == bo) {
442 cs->virtual_buffer_priorities[i] = MAX2(cs->virtual_buffer_priorities[i], priority);
443 cs->virtual_buffer_hash_table[hash] = i;
444 return;
445 }
446 }
447 }
448
449 if(cs->max_num_virtual_buffers <= cs->num_virtual_buffers) {
450 cs->max_num_virtual_buffers = MAX2(2, cs->max_num_virtual_buffers * 2);
451 cs->virtual_buffers = realloc(cs->virtual_buffers, sizeof(struct radv_amdgpu_virtual_virtual_buffer*) * cs->max_num_virtual_buffers);
452 cs->virtual_buffer_priorities = realloc(cs->virtual_buffer_priorities, sizeof(uint8_t) * cs->max_num_virtual_buffers);
453 }
454
455 cs->virtual_buffers[cs->num_virtual_buffers] = bo;
456 cs->virtual_buffer_priorities[cs->num_virtual_buffers] = priority;
457
458 cs->virtual_buffer_hash_table[hash] = cs->num_virtual_buffers;
459 ++cs->num_virtual_buffers;
460
461 }
462
463 static void radv_amdgpu_cs_add_buffer(struct radeon_winsys_cs *_cs,
464 struct radeon_winsys_bo *_bo,
465 uint8_t priority)
466 {
467 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
468 struct radv_amdgpu_winsys_bo *bo = radv_amdgpu_winsys_bo(_bo);
469
470 if (bo->is_virtual) {
471 radv_amdgpu_cs_add_virtual_buffer(_cs, _bo, priority);
472 return;
473 }
474
475 if (bo->base.is_local)
476 return;
477
478 radv_amdgpu_cs_add_buffer_internal(cs, bo->bo, priority);
479 }
480
481 static void radv_amdgpu_cs_execute_secondary(struct radeon_winsys_cs *_parent,
482 struct radeon_winsys_cs *_child)
483 {
484 struct radv_amdgpu_cs *parent = radv_amdgpu_cs(_parent);
485 struct radv_amdgpu_cs *child = radv_amdgpu_cs(_child);
486
487 for (unsigned i = 0; i < child->num_buffers; ++i) {
488 radv_amdgpu_cs_add_buffer_internal(parent, child->handles[i],
489 child->priorities[i]);
490 }
491
492 for (unsigned i = 0; i < child->num_virtual_buffers; ++i) {
493 radv_amdgpu_cs_add_buffer(&parent->base, child->virtual_buffers[i],
494 child->virtual_buffer_priorities[i]);
495 }
496
497 if (parent->ws->use_ib_bos) {
498 if (parent->base.cdw + 4 > parent->base.max_dw)
499 radv_amdgpu_cs_grow(&parent->base, 4);
500
501 parent->base.buf[parent->base.cdw++] = PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0);
502 parent->base.buf[parent->base.cdw++] = child->ib.ib_mc_address;
503 parent->base.buf[parent->base.cdw++] = child->ib.ib_mc_address >> 32;
504 parent->base.buf[parent->base.cdw++] = child->ib.size;
505 } else {
506 if (parent->base.cdw + child->base.cdw > parent->base.max_dw)
507 radv_amdgpu_cs_grow(&parent->base, child->base.cdw);
508
509 memcpy(parent->base.buf + parent->base.cdw, child->base.buf, 4 * child->base.cdw);
510 parent->base.cdw += child->base.cdw;
511 }
512 }
513
514 static int radv_amdgpu_create_bo_list(struct radv_amdgpu_winsys *ws,
515 struct radeon_winsys_cs **cs_array,
516 unsigned count,
517 struct radv_amdgpu_winsys_bo *extra_bo,
518 struct radeon_winsys_cs *extra_cs,
519 amdgpu_bo_list_handle *bo_list)
520 {
521 int r;
522 if (ws->debug_all_bos) {
523 struct radv_amdgpu_winsys_bo *bo;
524 amdgpu_bo_handle *handles;
525 unsigned num = 0;
526
527 pthread_mutex_lock(&ws->global_bo_list_lock);
528
529 handles = malloc(sizeof(handles[0]) * ws->num_buffers);
530 if (!handles) {
531 pthread_mutex_unlock(&ws->global_bo_list_lock);
532 return -ENOMEM;
533 }
534
535 LIST_FOR_EACH_ENTRY(bo, &ws->global_bo_list, global_list_item) {
536 assert(num < ws->num_buffers);
537 handles[num++] = bo->bo;
538 }
539
540 r = amdgpu_bo_list_create(ws->dev, ws->num_buffers,
541 handles, NULL,
542 bo_list);
543 free(handles);
544 pthread_mutex_unlock(&ws->global_bo_list_lock);
545 } else if (count == 1 && !extra_bo && !extra_cs &&
546 !radv_amdgpu_cs(cs_array[0])->num_virtual_buffers) {
547 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs*)cs_array[0];
548 if (cs->num_buffers == 0) {
549 *bo_list = 0;
550 return 0;
551 }
552 r = amdgpu_bo_list_create(ws->dev, cs->num_buffers, cs->handles,
553 cs->priorities, bo_list);
554 } else {
555 unsigned total_buffer_count = !!extra_bo;
556 unsigned unique_bo_count = !!extra_bo;
557 for (unsigned i = 0; i < count; ++i) {
558 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs*)cs_array[i];
559 total_buffer_count += cs->num_buffers;
560 for (unsigned j = 0; j < cs->num_virtual_buffers; ++j)
561 total_buffer_count += radv_amdgpu_winsys_bo(cs->virtual_buffers[j])->bo_count;
562 }
563
564 if (extra_cs) {
565 total_buffer_count += ((struct radv_amdgpu_cs*)extra_cs)->num_buffers;
566 }
567 if (total_buffer_count == 0) {
568 *bo_list = 0;
569 return 0;
570 }
571 amdgpu_bo_handle *handles = malloc(sizeof(amdgpu_bo_handle) * total_buffer_count);
572 uint8_t *priorities = malloc(sizeof(uint8_t) * total_buffer_count);
573 if (!handles || !priorities) {
574 free(handles);
575 free(priorities);
576 return -ENOMEM;
577 }
578
579 if (extra_bo) {
580 handles[0] = extra_bo->bo;
581 priorities[0] = 8;
582 }
583
584 for (unsigned i = 0; i < count + !!extra_cs; ++i) {
585 struct radv_amdgpu_cs *cs;
586
587 if (i == count)
588 cs = (struct radv_amdgpu_cs*)extra_cs;
589 else
590 cs = (struct radv_amdgpu_cs*)cs_array[i];
591
592 if (!cs->num_buffers)
593 continue;
594
595 if (unique_bo_count == 0) {
596 memcpy(handles, cs->handles, cs->num_buffers * sizeof(amdgpu_bo_handle));
597 memcpy(priorities, cs->priorities, cs->num_buffers * sizeof(uint8_t));
598 unique_bo_count = cs->num_buffers;
599 continue;
600 }
601 int unique_bo_so_far = unique_bo_count;
602 for (unsigned j = 0; j < cs->num_buffers; ++j) {
603 bool found = false;
604 for (unsigned k = 0; k < unique_bo_so_far; ++k) {
605 if (handles[k] == cs->handles[j]) {
606 found = true;
607 priorities[k] = MAX2(priorities[k],
608 cs->priorities[j]);
609 break;
610 }
611 }
612 if (!found) {
613 handles[unique_bo_count] = cs->handles[j];
614 priorities[unique_bo_count] = cs->priorities[j];
615 ++unique_bo_count;
616 }
617 }
618 for (unsigned j = 0; j < cs->num_virtual_buffers; ++j) {
619 struct radv_amdgpu_winsys_bo *virtual_bo = radv_amdgpu_winsys_bo(cs->virtual_buffers[j]);
620 for(unsigned k = 0; k < virtual_bo->bo_count; ++k) {
621 struct radv_amdgpu_winsys_bo *bo = virtual_bo->bos[k];
622 bool found = false;
623 for (unsigned m = 0; m < unique_bo_count; ++m) {
624 if (handles[m] == bo->bo) {
625 found = true;
626 priorities[m] = MAX2(priorities[m],
627 cs->virtual_buffer_priorities[j]);
628 break;
629 }
630 }
631 if (!found) {
632 handles[unique_bo_count] = bo->bo;
633 priorities[unique_bo_count] = cs->virtual_buffer_priorities[j];
634 ++unique_bo_count;
635 }
636 }
637 }
638 }
639 r = amdgpu_bo_list_create(ws->dev, unique_bo_count, handles,
640 priorities, bo_list);
641
642 free(handles);
643 free(priorities);
644 }
645
646 return r;
647 }
648
649 static struct amdgpu_cs_fence_info radv_set_cs_fence(struct radv_amdgpu_ctx *ctx, int ip_type, int ring)
650 {
651 struct amdgpu_cs_fence_info ret = {0};
652 if (ctx->fence_map) {
653 ret.handle = radv_amdgpu_winsys_bo(ctx->fence_bo)->bo;
654 ret.offset = (ip_type * MAX_RINGS_PER_TYPE + ring) * sizeof(uint64_t);
655 }
656 return ret;
657 }
658
659 static void radv_assign_last_submit(struct radv_amdgpu_ctx *ctx,
660 struct amdgpu_cs_request *request)
661 {
662 radv_amdgpu_request_to_fence(ctx,
663 &ctx->last_submission[request->ip_type][request->ring],
664 request);
665 }
666
667 static int radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx *_ctx,
668 int queue_idx,
669 struct radv_winsys_sem_info *sem_info,
670 struct radeon_winsys_cs **cs_array,
671 unsigned cs_count,
672 struct radeon_winsys_cs *initial_preamble_cs,
673 struct radeon_winsys_cs *continue_preamble_cs,
674 struct radeon_winsys_fence *_fence)
675 {
676 int r;
677 struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
678 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
679 struct radv_amdgpu_cs *cs0 = radv_amdgpu_cs(cs_array[0]);
680 amdgpu_bo_list_handle bo_list;
681 struct amdgpu_cs_request request = {0};
682 struct amdgpu_cs_ib_info ibs[2];
683
684 for (unsigned i = cs_count; i--;) {
685 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]);
686
687 if (cs->is_chained) {
688 *cs->ib_size_ptr -= 4;
689 cs->is_chained = false;
690 }
691
692 if (i + 1 < cs_count) {
693 struct radv_amdgpu_cs *next = radv_amdgpu_cs(cs_array[i + 1]);
694 assert(cs->base.cdw + 4 <= cs->base.max_dw);
695
696 cs->is_chained = true;
697 *cs->ib_size_ptr += 4;
698
699 cs->base.buf[cs->base.cdw + 0] = PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0);
700 cs->base.buf[cs->base.cdw + 1] = next->ib.ib_mc_address;
701 cs->base.buf[cs->base.cdw + 2] = next->ib.ib_mc_address >> 32;
702 cs->base.buf[cs->base.cdw + 3] = S_3F2_CHAIN(1) | S_3F2_VALID(1) | next->ib.size;
703 }
704 }
705
706 r = radv_amdgpu_create_bo_list(cs0->ws, cs_array, cs_count, NULL, initial_preamble_cs, &bo_list);
707 if (r) {
708 fprintf(stderr, "amdgpu: Failed to created the BO list for submission\n");
709 return r;
710 }
711
712 request.ip_type = cs0->hw_ip;
713 request.ring = queue_idx;
714 request.number_of_ibs = 1;
715 request.ibs = &cs0->ib;
716 request.resources = bo_list;
717 request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, queue_idx);
718
719 if (initial_preamble_cs) {
720 request.ibs = ibs;
721 request.number_of_ibs = 2;
722 ibs[1] = cs0->ib;
723 ibs[0] = ((struct radv_amdgpu_cs*)initial_preamble_cs)->ib;
724 }
725
726 r = radv_amdgpu_cs_submit(ctx, &request, sem_info);
727 if (r) {
728 if (r == -ENOMEM)
729 fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
730 else
731 fprintf(stderr, "amdgpu: The CS has been rejected, "
732 "see dmesg for more information.\n");
733 }
734
735 if (bo_list)
736 amdgpu_bo_list_destroy(bo_list);
737
738 if (fence)
739 radv_amdgpu_request_to_fence(ctx, fence, &request);
740
741 radv_assign_last_submit(ctx, &request);
742
743 return r;
744 }
745
746 static int radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx *_ctx,
747 int queue_idx,
748 struct radv_winsys_sem_info *sem_info,
749 struct radeon_winsys_cs **cs_array,
750 unsigned cs_count,
751 struct radeon_winsys_cs *initial_preamble_cs,
752 struct radeon_winsys_cs *continue_preamble_cs,
753 struct radeon_winsys_fence *_fence)
754 {
755 int r;
756 struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
757 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
758 amdgpu_bo_list_handle bo_list;
759 struct amdgpu_cs_request request;
760 bool emit_signal_sem = sem_info->cs_emit_signal;
761 assert(cs_count);
762
763 for (unsigned i = 0; i < cs_count;) {
764 struct radv_amdgpu_cs *cs0 = radv_amdgpu_cs(cs_array[i]);
765 struct amdgpu_cs_ib_info ibs[AMDGPU_CS_MAX_IBS_PER_SUBMIT];
766 struct radeon_winsys_cs *preamble_cs = i ? continue_preamble_cs : initial_preamble_cs;
767 unsigned cnt = MIN2(AMDGPU_CS_MAX_IBS_PER_SUBMIT - !!preamble_cs,
768 cs_count - i);
769
770 memset(&request, 0, sizeof(request));
771
772 r = radv_amdgpu_create_bo_list(cs0->ws, &cs_array[i], cnt, NULL,
773 preamble_cs, &bo_list);
774 if (r) {
775 fprintf(stderr, "amdgpu: Failed to created the BO list for submission\n");
776 return r;
777 }
778
779 request.ip_type = cs0->hw_ip;
780 request.ring = queue_idx;
781 request.resources = bo_list;
782 request.number_of_ibs = cnt + !!preamble_cs;
783 request.ibs = ibs;
784 request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, queue_idx);
785
786 if (preamble_cs) {
787 ibs[0] = radv_amdgpu_cs(preamble_cs)->ib;
788 }
789
790 for (unsigned j = 0; j < cnt; ++j) {
791 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i + j]);
792 ibs[j + !!preamble_cs] = cs->ib;
793
794 if (cs->is_chained) {
795 *cs->ib_size_ptr -= 4;
796 cs->is_chained = false;
797 }
798 }
799
800 sem_info->cs_emit_signal = (i == cs_count - cnt) ? emit_signal_sem : false;
801 r = radv_amdgpu_cs_submit(ctx, &request, sem_info);
802 if (r) {
803 if (r == -ENOMEM)
804 fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
805 else
806 fprintf(stderr, "amdgpu: The CS has been rejected, "
807 "see dmesg for more information.\n");
808 }
809
810 if (bo_list)
811 amdgpu_bo_list_destroy(bo_list);
812
813 if (r)
814 return r;
815
816 i += cnt;
817 }
818 if (fence)
819 radv_amdgpu_request_to_fence(ctx, fence, &request);
820
821 radv_assign_last_submit(ctx, &request);
822
823 return 0;
824 }
825
826 static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx,
827 int queue_idx,
828 struct radv_winsys_sem_info *sem_info,
829 struct radeon_winsys_cs **cs_array,
830 unsigned cs_count,
831 struct radeon_winsys_cs *initial_preamble_cs,
832 struct radeon_winsys_cs *continue_preamble_cs,
833 struct radeon_winsys_fence *_fence)
834 {
835 int r;
836 struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
837 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
838 struct radv_amdgpu_cs *cs0 = radv_amdgpu_cs(cs_array[0]);
839 struct radeon_winsys *ws = (struct radeon_winsys*)cs0->ws;
840 amdgpu_bo_list_handle bo_list;
841 struct amdgpu_cs_request request;
842 uint32_t pad_word = 0xffff1000U;
843 bool emit_signal_sem = sem_info->cs_emit_signal;
844
845 if (radv_amdgpu_winsys(ws)->info.chip_class == SI)
846 pad_word = 0x80000000;
847
848 assert(cs_count);
849
850 for (unsigned i = 0; i < cs_count;) {
851 struct amdgpu_cs_ib_info ib = {0};
852 struct radeon_winsys_bo *bo = NULL;
853 struct radeon_winsys_cs *preamble_cs = i ? continue_preamble_cs : initial_preamble_cs;
854 uint32_t *ptr;
855 unsigned cnt = 0;
856 unsigned size = 0;
857 unsigned pad_words = 0;
858 if (preamble_cs)
859 size += preamble_cs->cdw;
860
861 while (i + cnt < cs_count && 0xffff8 - size >= radv_amdgpu_cs(cs_array[i + cnt])->base.cdw) {
862 size += radv_amdgpu_cs(cs_array[i + cnt])->base.cdw;
863 ++cnt;
864 }
865
866 while(!size || (size & 7)) {
867 size++;
868 pad_words++;
869 }
870 assert(cnt);
871
872 bo = ws->buffer_create(ws, 4 * size, 4096, RADEON_DOMAIN_GTT, RADEON_FLAG_CPU_ACCESS|RADEON_FLAG_NO_INTERPROCESS_SHARING);
873 ptr = ws->buffer_map(bo);
874
875 if (preamble_cs) {
876 memcpy(ptr, preamble_cs->buf, preamble_cs->cdw * 4);
877 ptr += preamble_cs->cdw;
878 }
879
880 for (unsigned j = 0; j < cnt; ++j) {
881 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i + j]);
882 memcpy(ptr, cs->base.buf, 4 * cs->base.cdw);
883 ptr += cs->base.cdw;
884
885 }
886
887 for (unsigned j = 0; j < pad_words; ++j)
888 *ptr++ = pad_word;
889
890 memset(&request, 0, sizeof(request));
891
892
893 r = radv_amdgpu_create_bo_list(cs0->ws, &cs_array[i], cnt,
894 (struct radv_amdgpu_winsys_bo*)bo,
895 preamble_cs, &bo_list);
896 if (r) {
897 fprintf(stderr, "amdgpu: Failed to created the BO list for submission\n");
898 return r;
899 }
900
901 ib.size = size;
902 ib.ib_mc_address = radv_buffer_get_va(bo);
903
904 request.ip_type = cs0->hw_ip;
905 request.ring = queue_idx;
906 request.resources = bo_list;
907 request.number_of_ibs = 1;
908 request.ibs = &ib;
909 request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, queue_idx);
910
911 sem_info->cs_emit_signal = (i == cs_count - cnt) ? emit_signal_sem : false;
912 r = radv_amdgpu_cs_submit(ctx, &request, sem_info);
913 if (r) {
914 if (r == -ENOMEM)
915 fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
916 else
917 fprintf(stderr, "amdgpu: The CS has been rejected, "
918 "see dmesg for more information.\n");
919 }
920
921 if (bo_list)
922 amdgpu_bo_list_destroy(bo_list);
923
924 ws->buffer_destroy(bo);
925 if (r)
926 return r;
927
928 i += cnt;
929 }
930 if (fence)
931 radv_amdgpu_request_to_fence(ctx, fence, &request);
932
933 radv_assign_last_submit(ctx, &request);
934
935 return 0;
936 }
937
938 static int radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx *_ctx,
939 int queue_idx,
940 struct radeon_winsys_cs **cs_array,
941 unsigned cs_count,
942 struct radeon_winsys_cs *initial_preamble_cs,
943 struct radeon_winsys_cs *continue_preamble_cs,
944 struct radv_winsys_sem_info *sem_info,
945 bool can_patch,
946 struct radeon_winsys_fence *_fence)
947 {
948 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[0]);
949 struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
950 int ret;
951
952 assert(sem_info);
953 if (!cs->ws->use_ib_bos) {
954 ret = radv_amdgpu_winsys_cs_submit_sysmem(_ctx, queue_idx, sem_info, cs_array,
955 cs_count, initial_preamble_cs, continue_preamble_cs, _fence);
956 } else if (can_patch && cs_count > AMDGPU_CS_MAX_IBS_PER_SUBMIT && cs->ws->batchchain) {
957 ret = radv_amdgpu_winsys_cs_submit_chained(_ctx, queue_idx, sem_info, cs_array,
958 cs_count, initial_preamble_cs, continue_preamble_cs, _fence);
959 } else {
960 ret = radv_amdgpu_winsys_cs_submit_fallback(_ctx, queue_idx, sem_info, cs_array,
961 cs_count, initial_preamble_cs, continue_preamble_cs, _fence);
962 }
963
964 radv_amdgpu_signal_sems(ctx, cs->hw_ip, queue_idx, sem_info);
965 return ret;
966 }
967
968 static void *radv_amdgpu_winsys_get_cpu_addr(void *_cs, uint64_t addr)
969 {
970 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs *)_cs;
971 void *ret = NULL;
972
973 if (!cs->ib_buffer)
974 return NULL;
975 for (unsigned i = 0; i <= cs->num_old_ib_buffers; ++i) {
976 struct radv_amdgpu_winsys_bo *bo;
977
978 bo = (struct radv_amdgpu_winsys_bo*)
979 (i == cs->num_old_ib_buffers ? cs->ib_buffer : cs->old_ib_buffers[i]);
980 if (addr >= bo->base.va && addr - bo->base.va < bo->size) {
981 if (amdgpu_bo_cpu_map(bo->bo, &ret) == 0)
982 return (char *)ret + (addr - bo->base.va);
983 }
984 }
985 if(cs->ws->debug_all_bos) {
986 pthread_mutex_lock(&cs->ws->global_bo_list_lock);
987 list_for_each_entry(struct radv_amdgpu_winsys_bo, bo,
988 &cs->ws->global_bo_list, global_list_item) {
989 if (addr >= bo->base.va && addr - bo->base.va < bo->size) {
990 if (amdgpu_bo_cpu_map(bo->bo, &ret) == 0) {
991 pthread_mutex_unlock(&cs->ws->global_bo_list_lock);
992 return (char *)ret + (addr - bo->base.va);
993 }
994 }
995 }
996 pthread_mutex_unlock(&cs->ws->global_bo_list_lock);
997 }
998 return ret;
999 }
1000
1001 static void radv_amdgpu_winsys_cs_dump(struct radeon_winsys_cs *_cs,
1002 FILE* file,
1003 const int *trace_ids, int trace_id_count)
1004 {
1005 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs *)_cs;
1006 void *ib = cs->base.buf;
1007 int num_dw = cs->base.cdw;
1008
1009 if (cs->ws->use_ib_bos) {
1010 ib = radv_amdgpu_winsys_get_cpu_addr(cs, cs->ib.ib_mc_address);
1011 num_dw = cs->ib.size;
1012 }
1013 assert(ib);
1014 ac_parse_ib(file, ib, num_dw, trace_ids, trace_id_count, "main IB",
1015 cs->ws->info.chip_class, radv_amdgpu_winsys_get_cpu_addr, cs);
1016 }
1017
1018 static uint32_t radv_to_amdgpu_priority(enum radeon_ctx_priority radv_priority)
1019 {
1020 switch (radv_priority) {
1021 case RADEON_CTX_PRIORITY_REALTIME:
1022 return AMDGPU_CTX_PRIORITY_VERY_HIGH;
1023 case RADEON_CTX_PRIORITY_HIGH:
1024 return AMDGPU_CTX_PRIORITY_HIGH;
1025 case RADEON_CTX_PRIORITY_MEDIUM:
1026 return AMDGPU_CTX_PRIORITY_NORMAL;
1027 case RADEON_CTX_PRIORITY_LOW:
1028 return AMDGPU_CTX_PRIORITY_LOW;
1029 default:
1030 unreachable("Invalid context priority");
1031 }
1032 }
1033
1034 static struct radeon_winsys_ctx *radv_amdgpu_ctx_create(struct radeon_winsys *_ws,
1035 enum radeon_ctx_priority priority)
1036 {
1037 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1038 struct radv_amdgpu_ctx *ctx = CALLOC_STRUCT(radv_amdgpu_ctx);
1039 uint32_t amdgpu_priority = radv_to_amdgpu_priority(priority);
1040 int r;
1041
1042 if (!ctx)
1043 return NULL;
1044
1045 r = amdgpu_cs_ctx_create2(ws->dev, amdgpu_priority, &ctx->ctx);
1046 if (r) {
1047 fprintf(stderr, "amdgpu: radv_amdgpu_cs_ctx_create2 failed. (%i)\n", r);
1048 goto error_create;
1049 }
1050 ctx->ws = ws;
1051
1052 assert(AMDGPU_HW_IP_NUM * MAX_RINGS_PER_TYPE * sizeof(uint64_t) <= 4096);
1053 ctx->fence_bo = ws->base.buffer_create(&ws->base, 4096, 8,
1054 RADEON_DOMAIN_GTT,
1055 RADEON_FLAG_CPU_ACCESS|
1056 RADEON_FLAG_NO_INTERPROCESS_SHARING);
1057 if (ctx->fence_bo)
1058 ctx->fence_map = (uint64_t*)ws->base.buffer_map(ctx->fence_bo);
1059 if (ctx->fence_map)
1060 memset(ctx->fence_map, 0, 4096);
1061 return (struct radeon_winsys_ctx *)ctx;
1062 error_create:
1063 FREE(ctx);
1064 return NULL;
1065 }
1066
1067 static void radv_amdgpu_ctx_destroy(struct radeon_winsys_ctx *rwctx)
1068 {
1069 struct radv_amdgpu_ctx *ctx = (struct radv_amdgpu_ctx *)rwctx;
1070 ctx->ws->base.buffer_destroy(ctx->fence_bo);
1071 amdgpu_cs_ctx_free(ctx->ctx);
1072 FREE(ctx);
1073 }
1074
1075 static bool radv_amdgpu_ctx_wait_idle(struct radeon_winsys_ctx *rwctx,
1076 enum ring_type ring_type, int ring_index)
1077 {
1078 struct radv_amdgpu_ctx *ctx = (struct radv_amdgpu_ctx *)rwctx;
1079 int ip_type = ring_to_hw_ip(ring_type);
1080
1081 if (ctx->last_submission[ip_type][ring_index].fence.fence) {
1082 uint32_t expired;
1083 int ret = amdgpu_cs_query_fence_status(&ctx->last_submission[ip_type][ring_index].fence,
1084 1000000000ull, 0, &expired);
1085
1086 if (ret || !expired)
1087 return false;
1088 }
1089
1090 return true;
1091 }
1092
1093 static struct radeon_winsys_sem *radv_amdgpu_create_sem(struct radeon_winsys *_ws)
1094 {
1095 struct amdgpu_cs_fence *sem = CALLOC_STRUCT(amdgpu_cs_fence);
1096 if (!sem)
1097 return NULL;
1098
1099 return (struct radeon_winsys_sem *)sem;
1100 }
1101
1102 static void radv_amdgpu_destroy_sem(struct radeon_winsys_sem *_sem)
1103 {
1104 struct amdgpu_cs_fence *sem = (struct amdgpu_cs_fence *)_sem;
1105 FREE(sem);
1106 }
1107
1108 static int radv_amdgpu_signal_sems(struct radv_amdgpu_ctx *ctx,
1109 uint32_t ip_type,
1110 uint32_t ring,
1111 struct radv_winsys_sem_info *sem_info)
1112 {
1113 for (unsigned i = 0; i < sem_info->signal.sem_count; i++) {
1114 struct amdgpu_cs_fence *sem = (struct amdgpu_cs_fence *)(sem_info->signal.sem)[i];
1115
1116 if (sem->context)
1117 return -EINVAL;
1118
1119 *sem = ctx->last_submission[ip_type][ring].fence;
1120 }
1121 return 0;
1122 }
1123
1124 static struct drm_amdgpu_cs_chunk_sem *radv_amdgpu_cs_alloc_syncobj_chunk(struct radv_winsys_sem_counts *counts,
1125 struct drm_amdgpu_cs_chunk *chunk, int chunk_id)
1126 {
1127 struct drm_amdgpu_cs_chunk_sem *syncobj = malloc(sizeof(struct drm_amdgpu_cs_chunk_sem) * counts->syncobj_count);
1128 if (!syncobj)
1129 return NULL;
1130
1131 for (unsigned i = 0; i < counts->syncobj_count; i++) {
1132 struct drm_amdgpu_cs_chunk_sem *sem = &syncobj[i];
1133 sem->handle = counts->syncobj[i];
1134 }
1135
1136 chunk->chunk_id = chunk_id;
1137 chunk->length_dw = sizeof(struct drm_amdgpu_cs_chunk_sem) / 4 * counts->syncobj_count;
1138 chunk->chunk_data = (uint64_t)(uintptr_t)syncobj;
1139 return syncobj;
1140 }
1141
1142 static int radv_amdgpu_cs_submit(struct radv_amdgpu_ctx *ctx,
1143 struct amdgpu_cs_request *request,
1144 struct radv_winsys_sem_info *sem_info)
1145 {
1146 int r;
1147 int num_chunks;
1148 int size;
1149 bool user_fence;
1150 struct drm_amdgpu_cs_chunk *chunks;
1151 struct drm_amdgpu_cs_chunk_data *chunk_data;
1152 struct drm_amdgpu_cs_chunk_dep *sem_dependencies = NULL;
1153 struct drm_amdgpu_cs_chunk_sem *wait_syncobj = NULL, *signal_syncobj = NULL;
1154 int i;
1155 struct amdgpu_cs_fence *sem;
1156
1157 user_fence = (request->fence_info.handle != NULL);
1158 size = request->number_of_ibs + (user_fence ? 2 : 1) + 3;
1159
1160 chunks = alloca(sizeof(struct drm_amdgpu_cs_chunk) * size);
1161
1162 size = request->number_of_ibs + (user_fence ? 1 : 0);
1163
1164 chunk_data = alloca(sizeof(struct drm_amdgpu_cs_chunk_data) * size);
1165
1166 num_chunks = request->number_of_ibs;
1167 for (i = 0; i < request->number_of_ibs; i++) {
1168 struct amdgpu_cs_ib_info *ib;
1169 chunks[i].chunk_id = AMDGPU_CHUNK_ID_IB;
1170 chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
1171 chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
1172
1173 ib = &request->ibs[i];
1174
1175 chunk_data[i].ib_data._pad = 0;
1176 chunk_data[i].ib_data.va_start = ib->ib_mc_address;
1177 chunk_data[i].ib_data.ib_bytes = ib->size * 4;
1178 chunk_data[i].ib_data.ip_type = request->ip_type;
1179 chunk_data[i].ib_data.ip_instance = request->ip_instance;
1180 chunk_data[i].ib_data.ring = request->ring;
1181 chunk_data[i].ib_data.flags = ib->flags;
1182 }
1183
1184 if (user_fence) {
1185 i = num_chunks++;
1186
1187 chunks[i].chunk_id = AMDGPU_CHUNK_ID_FENCE;
1188 chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_fence) / 4;
1189 chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
1190
1191 amdgpu_cs_chunk_fence_info_to_data(&request->fence_info,
1192 &chunk_data[i]);
1193 }
1194
1195 if (sem_info->wait.syncobj_count && sem_info->cs_emit_wait) {
1196 wait_syncobj = radv_amdgpu_cs_alloc_syncobj_chunk(&sem_info->wait,
1197 &chunks[num_chunks],
1198 AMDGPU_CHUNK_ID_SYNCOBJ_IN);
1199 if (!wait_syncobj) {
1200 r = -ENOMEM;
1201 goto error_out;
1202 }
1203 num_chunks++;
1204
1205 if (sem_info->wait.sem_count == 0)
1206 sem_info->cs_emit_wait = false;
1207
1208 }
1209
1210 if (sem_info->wait.sem_count && sem_info->cs_emit_wait) {
1211 sem_dependencies = malloc(sizeof(struct drm_amdgpu_cs_chunk_dep) * sem_info->wait.sem_count);
1212 if (!sem_dependencies) {
1213 r = -ENOMEM;
1214 goto error_out;
1215 }
1216 int sem_count = 0;
1217 for (unsigned j = 0; j < sem_info->wait.sem_count; j++) {
1218 sem = (struct amdgpu_cs_fence *)sem_info->wait.sem[j];
1219 if (!sem->context)
1220 continue;
1221 struct drm_amdgpu_cs_chunk_dep *dep = &sem_dependencies[sem_count++];
1222
1223 amdgpu_cs_chunk_fence_to_dep(sem, dep);
1224
1225 sem->context = NULL;
1226 }
1227 i = num_chunks++;
1228
1229 /* dependencies chunk */
1230 chunks[i].chunk_id = AMDGPU_CHUNK_ID_DEPENDENCIES;
1231 chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_dep) / 4 * sem_count;
1232 chunks[i].chunk_data = (uint64_t)(uintptr_t)sem_dependencies;
1233
1234 sem_info->cs_emit_wait = false;
1235 }
1236
1237 if (sem_info->signal.syncobj_count && sem_info->cs_emit_signal) {
1238 signal_syncobj = radv_amdgpu_cs_alloc_syncobj_chunk(&sem_info->signal,
1239 &chunks[num_chunks],
1240 AMDGPU_CHUNK_ID_SYNCOBJ_OUT);
1241 if (!signal_syncobj) {
1242 r = -ENOMEM;
1243 goto error_out;
1244 }
1245 num_chunks++;
1246 }
1247
1248 r = amdgpu_cs_submit_raw(ctx->ws->dev,
1249 ctx->ctx,
1250 request->resources,
1251 num_chunks,
1252 chunks,
1253 &request->seq_no);
1254 error_out:
1255 free(sem_dependencies);
1256 free(wait_syncobj);
1257 free(signal_syncobj);
1258 return r;
1259 }
1260
1261 static int radv_amdgpu_create_syncobj(struct radeon_winsys *_ws,
1262 uint32_t *handle)
1263 {
1264 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1265 return amdgpu_cs_create_syncobj(ws->dev, handle);
1266 }
1267
1268 static void radv_amdgpu_destroy_syncobj(struct radeon_winsys *_ws,
1269 uint32_t handle)
1270 {
1271 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1272 amdgpu_cs_destroy_syncobj(ws->dev, handle);
1273 }
1274
1275 static int radv_amdgpu_export_syncobj(struct radeon_winsys *_ws,
1276 uint32_t syncobj,
1277 int *fd)
1278 {
1279 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1280
1281 return amdgpu_cs_export_syncobj(ws->dev, syncobj, fd);
1282 }
1283
1284 static int radv_amdgpu_import_syncobj(struct radeon_winsys *_ws,
1285 int fd,
1286 uint32_t *syncobj)
1287 {
1288 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1289
1290 return amdgpu_cs_import_syncobj(ws->dev, fd, syncobj);
1291 }
1292
1293 void radv_amdgpu_cs_init_functions(struct radv_amdgpu_winsys *ws)
1294 {
1295 ws->base.ctx_create = radv_amdgpu_ctx_create;
1296 ws->base.ctx_destroy = radv_amdgpu_ctx_destroy;
1297 ws->base.ctx_wait_idle = radv_amdgpu_ctx_wait_idle;
1298 ws->base.cs_create = radv_amdgpu_cs_create;
1299 ws->base.cs_destroy = radv_amdgpu_cs_destroy;
1300 ws->base.cs_grow = radv_amdgpu_cs_grow;
1301 ws->base.cs_finalize = radv_amdgpu_cs_finalize;
1302 ws->base.cs_reset = radv_amdgpu_cs_reset;
1303 ws->base.cs_add_buffer = radv_amdgpu_cs_add_buffer;
1304 ws->base.cs_execute_secondary = radv_amdgpu_cs_execute_secondary;
1305 ws->base.cs_submit = radv_amdgpu_winsys_cs_submit;
1306 ws->base.cs_dump = radv_amdgpu_winsys_cs_dump;
1307 ws->base.create_fence = radv_amdgpu_create_fence;
1308 ws->base.destroy_fence = radv_amdgpu_destroy_fence;
1309 ws->base.create_sem = radv_amdgpu_create_sem;
1310 ws->base.destroy_sem = radv_amdgpu_destroy_sem;
1311 ws->base.create_syncobj = radv_amdgpu_create_syncobj;
1312 ws->base.destroy_syncobj = radv_amdgpu_destroy_syncobj;
1313 ws->base.export_syncobj = radv_amdgpu_export_syncobj;
1314 ws->base.import_syncobj = radv_amdgpu_import_syncobj;
1315 ws->base.fence_wait = radv_amdgpu_fence_wait;
1316 }