2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include <amdgpu_drm.h>
33 #include "radv_radeon_winsys.h"
34 #include "radv_amdgpu_cs.h"
35 #include "radv_amdgpu_bo.h"
40 VIRTUAL_BUFFER_HASH_TABLE_SIZE
= 1024
43 struct radv_amdgpu_cs
{
44 struct radeon_cmdbuf base
;
45 struct radv_amdgpu_winsys
*ws
;
47 struct amdgpu_cs_ib_info ib
;
49 struct radeon_winsys_bo
*ib_buffer
;
51 unsigned max_num_buffers
;
53 struct drm_amdgpu_bo_list_entry
*handles
;
55 struct radeon_winsys_bo
**old_ib_buffers
;
56 unsigned num_old_ib_buffers
;
57 unsigned max_num_old_ib_buffers
;
58 unsigned *ib_size_ptr
;
62 int buffer_hash_table
[1024];
65 unsigned num_virtual_buffers
;
66 unsigned max_num_virtual_buffers
;
67 struct radeon_winsys_bo
**virtual_buffers
;
68 int *virtual_buffer_hash_table
;
70 /* For chips that don't support chaining. */
71 struct radeon_cmdbuf
*old_cs_buffers
;
72 unsigned num_old_cs_buffers
;
75 static inline struct radv_amdgpu_cs
*
76 radv_amdgpu_cs(struct radeon_cmdbuf
*base
)
78 return (struct radv_amdgpu_cs
*)base
;
81 static int ring_to_hw_ip(enum ring_type ring
)
85 return AMDGPU_HW_IP_GFX
;
87 return AMDGPU_HW_IP_DMA
;
89 return AMDGPU_HW_IP_COMPUTE
;
91 unreachable("unsupported ring");
95 struct radv_amdgpu_cs_request
{
96 /** Specify flags with additional information */
99 /** Specify HW IP block type to which to send the IB. */
102 /** IP instance index if there are several IPs of the same type. */
103 unsigned ip_instance
;
106 * Specify ring index of the IP. We could have several rings
107 * in the same IP. E.g. 0 for SDMA0 and 1 for SDMA1.
112 * List handle with resources used by this request. This is a raw
113 * bo list handle used by the kernel.
118 * Number of dependencies this Command submission needs to
119 * wait for before starting execution.
121 uint32_t number_of_dependencies
;
124 * Array of dependencies which need to be met before
125 * execution can start.
127 struct amdgpu_cs_fence
*dependencies
;
129 /** Number of IBs to submit in the field ibs. */
130 uint32_t number_of_ibs
;
133 * IBs to submit. Those IBs will be submit together as single entity
135 struct amdgpu_cs_ib_info
*ibs
;
138 * The returned sequence number for the command submission
143 * The fence information
145 struct amdgpu_cs_fence_info fence_info
;
149 static int radv_amdgpu_signal_sems(struct radv_amdgpu_ctx
*ctx
,
152 struct radv_winsys_sem_info
*sem_info
);
153 static int radv_amdgpu_cs_submit(struct radv_amdgpu_ctx
*ctx
,
154 struct radv_amdgpu_cs_request
*request
,
155 struct radv_winsys_sem_info
*sem_info
);
157 static void radv_amdgpu_request_to_fence(struct radv_amdgpu_ctx
*ctx
,
158 struct radv_amdgpu_fence
*fence
,
159 struct radv_amdgpu_cs_request
*req
)
161 fence
->fence
.context
= ctx
->ctx
;
162 fence
->fence
.ip_type
= req
->ip_type
;
163 fence
->fence
.ip_instance
= req
->ip_instance
;
164 fence
->fence
.ring
= req
->ring
;
165 fence
->fence
.fence
= req
->seq_no
;
166 fence
->user_ptr
= (volatile uint64_t*)(ctx
->fence_map
+ (req
->ip_type
* MAX_RINGS_PER_TYPE
+ req
->ring
) * sizeof(uint64_t));
169 static struct radeon_winsys_fence
*radv_amdgpu_create_fence()
171 struct radv_amdgpu_fence
*fence
= calloc(1, sizeof(struct radv_amdgpu_fence
));
172 fence
->fence
.fence
= UINT64_MAX
;
173 return (struct radeon_winsys_fence
*)fence
;
176 static void radv_amdgpu_destroy_fence(struct radeon_winsys_fence
*_fence
)
178 struct radv_amdgpu_fence
*fence
= (struct radv_amdgpu_fence
*)_fence
;
182 static void radv_amdgpu_reset_fence(struct radeon_winsys_fence
*_fence
)
184 struct radv_amdgpu_fence
*fence
= (struct radv_amdgpu_fence
*)_fence
;
185 fence
->fence
.fence
= UINT64_MAX
;
188 static void radv_amdgpu_signal_fence(struct radeon_winsys_fence
*_fence
)
190 struct radv_amdgpu_fence
*fence
= (struct radv_amdgpu_fence
*)_fence
;
191 fence
->fence
.fence
= 0;
194 static bool radv_amdgpu_is_fence_waitable(struct radeon_winsys_fence
*_fence
)
196 struct radv_amdgpu_fence
*fence
= (struct radv_amdgpu_fence
*)_fence
;
197 return fence
->fence
.fence
< UINT64_MAX
;
200 static bool radv_amdgpu_fence_wait(struct radeon_winsys
*_ws
,
201 struct radeon_winsys_fence
*_fence
,
205 struct radv_amdgpu_fence
*fence
= (struct radv_amdgpu_fence
*)_fence
;
206 unsigned flags
= absolute
? AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE
: 0;
208 uint32_t expired
= 0;
210 /* Special casing 0 and UINT64_MAX so that they work without user_ptr/fence.ctx */
211 if (fence
->fence
.fence
== UINT64_MAX
)
214 if (fence
->fence
.fence
== 0)
217 if (fence
->user_ptr
) {
218 if (*fence
->user_ptr
>= fence
->fence
.fence
)
220 if (!absolute
&& !timeout
)
224 /* Now use the libdrm query. */
225 r
= amdgpu_cs_query_fence_status(&fence
->fence
,
231 fprintf(stderr
, "amdgpu: radv_amdgpu_cs_query_fence_status failed.\n");
242 static bool radv_amdgpu_fences_wait(struct radeon_winsys
*_ws
,
243 struct radeon_winsys_fence
*const *_fences
,
244 uint32_t fence_count
,
248 struct amdgpu_cs_fence
*fences
= malloc(sizeof(struct amdgpu_cs_fence
) * fence_count
);
250 uint32_t expired
= 0, first
= 0;
255 for (uint32_t i
= 0; i
< fence_count
; ++i
)
256 fences
[i
] = ((struct radv_amdgpu_fence
*)_fences
[i
])->fence
;
258 /* Now use the libdrm query. */
259 r
= amdgpu_cs_wait_fences(fences
, fence_count
, wait_all
,
260 timeout
, &expired
, &first
);
264 fprintf(stderr
, "amdgpu: amdgpu_cs_wait_fences failed.\n");
274 static void radv_amdgpu_cs_destroy(struct radeon_cmdbuf
*rcs
)
276 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(rcs
);
279 cs
->ws
->base
.buffer_destroy(cs
->ib_buffer
);
283 for (unsigned i
= 0; i
< cs
->num_old_ib_buffers
; ++i
)
284 cs
->ws
->base
.buffer_destroy(cs
->old_ib_buffers
[i
]);
286 for (unsigned i
= 0; i
< cs
->num_old_cs_buffers
; ++i
) {
287 struct radeon_cmdbuf
*rcs
= &cs
->old_cs_buffers
[i
];
291 free(cs
->old_cs_buffers
);
292 free(cs
->old_ib_buffers
);
293 free(cs
->virtual_buffers
);
294 free(cs
->virtual_buffer_hash_table
);
299 static void radv_amdgpu_init_cs(struct radv_amdgpu_cs
*cs
,
300 enum ring_type ring_type
)
302 for (int i
= 0; i
< ARRAY_SIZE(cs
->buffer_hash_table
); ++i
)
303 cs
->buffer_hash_table
[i
] = -1;
305 cs
->hw_ip
= ring_to_hw_ip(ring_type
);
308 static struct radeon_cmdbuf
*
309 radv_amdgpu_cs_create(struct radeon_winsys
*ws
,
310 enum ring_type ring_type
)
312 struct radv_amdgpu_cs
*cs
;
313 uint32_t ib_size
= 20 * 1024 * 4;
314 cs
= calloc(1, sizeof(struct radv_amdgpu_cs
));
318 cs
->ws
= radv_amdgpu_winsys(ws
);
319 radv_amdgpu_init_cs(cs
, ring_type
);
321 if (cs
->ws
->use_ib_bos
) {
322 cs
->ib_buffer
= ws
->buffer_create(ws
, ib_size
, 0,
324 RADEON_FLAG_CPU_ACCESS
|
325 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
326 RADEON_FLAG_READ_ONLY
,
327 RADV_BO_PRIORITY_CS
);
328 if (!cs
->ib_buffer
) {
333 cs
->ib_mapped
= ws
->buffer_map(cs
->ib_buffer
);
334 if (!cs
->ib_mapped
) {
335 ws
->buffer_destroy(cs
->ib_buffer
);
340 cs
->ib
.ib_mc_address
= radv_amdgpu_winsys_bo(cs
->ib_buffer
)->base
.va
;
341 cs
->base
.buf
= (uint32_t *)cs
->ib_mapped
;
342 cs
->base
.max_dw
= ib_size
/ 4 - 4;
343 cs
->ib_size_ptr
= &cs
->ib
.size
;
346 ws
->cs_add_buffer(&cs
->base
, cs
->ib_buffer
);
348 cs
->base
.buf
= malloc(16384);
349 cs
->base
.max_dw
= 4096;
359 static void radv_amdgpu_cs_grow(struct radeon_cmdbuf
*_cs
, size_t min_size
)
361 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(_cs
);
368 if (!cs
->ws
->use_ib_bos
) {
369 const uint64_t limit_dws
= 0xffff8;
370 uint64_t ib_dws
= MAX2(cs
->base
.cdw
+ min_size
,
371 MIN2(cs
->base
.max_dw
* 2, limit_dws
));
373 /* The total ib size cannot exceed limit_dws dwords. */
374 if (ib_dws
> limit_dws
)
376 /* The maximum size in dwords has been reached,
377 * try to allocate a new one.
380 realloc(cs
->old_cs_buffers
,
381 (cs
->num_old_cs_buffers
+ 1) * sizeof(*cs
->old_cs_buffers
));
382 if (!cs
->old_cs_buffers
) {
388 /* Store the current one for submitting it later. */
389 cs
->old_cs_buffers
[cs
->num_old_cs_buffers
].cdw
= cs
->base
.cdw
;
390 cs
->old_cs_buffers
[cs
->num_old_cs_buffers
].max_dw
= cs
->base
.max_dw
;
391 cs
->old_cs_buffers
[cs
->num_old_cs_buffers
].buf
= cs
->base
.buf
;
392 cs
->num_old_cs_buffers
++;
394 /* Reset the cs, it will be re-allocated below. */
398 /* Re-compute the number of dwords to allocate. */
399 ib_dws
= MAX2(cs
->base
.cdw
+ min_size
,
400 MIN2(cs
->base
.max_dw
* 2, limit_dws
));
401 if (ib_dws
> limit_dws
) {
402 fprintf(stderr
, "amdgpu: Too high number of "
403 "dwords to allocate\n");
409 uint32_t *new_buf
= realloc(cs
->base
.buf
, ib_dws
* 4);
411 cs
->base
.buf
= new_buf
;
412 cs
->base
.max_dw
= ib_dws
;
420 uint64_t ib_size
= MAX2(min_size
* 4 + 16, cs
->base
.max_dw
* 4 * 2);
422 /* max that fits in the chain size field. */
423 ib_size
= MIN2(ib_size
, 0xfffff);
425 while (!cs
->base
.cdw
|| (cs
->base
.cdw
& 7) != 4)
426 radeon_emit(&cs
->base
, 0xffff1000);
428 *cs
->ib_size_ptr
|= cs
->base
.cdw
+ 4;
430 if (cs
->num_old_ib_buffers
== cs
->max_num_old_ib_buffers
) {
431 cs
->max_num_old_ib_buffers
= MAX2(1, cs
->max_num_old_ib_buffers
* 2);
432 cs
->old_ib_buffers
= realloc(cs
->old_ib_buffers
,
433 cs
->max_num_old_ib_buffers
* sizeof(void*));
436 cs
->old_ib_buffers
[cs
->num_old_ib_buffers
++] = cs
->ib_buffer
;
438 cs
->ib_buffer
= cs
->ws
->base
.buffer_create(&cs
->ws
->base
, ib_size
, 0,
440 RADEON_FLAG_CPU_ACCESS
|
441 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
442 RADEON_FLAG_READ_ONLY
,
443 RADV_BO_PRIORITY_CS
);
445 if (!cs
->ib_buffer
) {
448 cs
->ib_buffer
= cs
->old_ib_buffers
[--cs
->num_old_ib_buffers
];
451 cs
->ib_mapped
= cs
->ws
->base
.buffer_map(cs
->ib_buffer
);
452 if (!cs
->ib_mapped
) {
453 cs
->ws
->base
.buffer_destroy(cs
->ib_buffer
);
456 cs
->ib_buffer
= cs
->old_ib_buffers
[--cs
->num_old_ib_buffers
];
459 cs
->ws
->base
.cs_add_buffer(&cs
->base
, cs
->ib_buffer
);
461 radeon_emit(&cs
->base
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
462 radeon_emit(&cs
->base
, radv_amdgpu_winsys_bo(cs
->ib_buffer
)->base
.va
);
463 radeon_emit(&cs
->base
, radv_amdgpu_winsys_bo(cs
->ib_buffer
)->base
.va
>> 32);
464 radeon_emit(&cs
->base
, S_3F2_CHAIN(1) | S_3F2_VALID(1));
466 cs
->ib_size_ptr
= cs
->base
.buf
+ cs
->base
.cdw
- 1;
468 cs
->base
.buf
= (uint32_t *)cs
->ib_mapped
;
470 cs
->base
.max_dw
= ib_size
/ 4 - 4;
474 static bool radv_amdgpu_cs_finalize(struct radeon_cmdbuf
*_cs
)
476 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(_cs
);
478 if (cs
->ws
->use_ib_bos
) {
479 while (!cs
->base
.cdw
|| (cs
->base
.cdw
& 7) != 0)
480 radeon_emit(&cs
->base
, 0xffff1000);
482 *cs
->ib_size_ptr
|= cs
->base
.cdw
;
484 cs
->is_chained
= false;
490 static void radv_amdgpu_cs_reset(struct radeon_cmdbuf
*_cs
)
492 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(_cs
);
496 for (unsigned i
= 0; i
< cs
->num_buffers
; ++i
) {
497 unsigned hash
= cs
->handles
[i
].bo_handle
&
498 (ARRAY_SIZE(cs
->buffer_hash_table
) - 1);
499 cs
->buffer_hash_table
[hash
] = -1;
502 for (unsigned i
= 0; i
< cs
->num_virtual_buffers
; ++i
) {
503 unsigned hash
= ((uintptr_t)cs
->virtual_buffers
[i
] >> 6) & (VIRTUAL_BUFFER_HASH_TABLE_SIZE
- 1);
504 cs
->virtual_buffer_hash_table
[hash
] = -1;
508 cs
->num_virtual_buffers
= 0;
510 if (cs
->ws
->use_ib_bos
) {
511 cs
->ws
->base
.cs_add_buffer(&cs
->base
, cs
->ib_buffer
);
513 for (unsigned i
= 0; i
< cs
->num_old_ib_buffers
; ++i
)
514 cs
->ws
->base
.buffer_destroy(cs
->old_ib_buffers
[i
]);
516 cs
->num_old_ib_buffers
= 0;
517 cs
->ib
.ib_mc_address
= radv_amdgpu_winsys_bo(cs
->ib_buffer
)->base
.va
;
518 cs
->ib_size_ptr
= &cs
->ib
.size
;
521 for (unsigned i
= 0; i
< cs
->num_old_cs_buffers
; ++i
) {
522 struct radeon_cmdbuf
*rcs
= &cs
->old_cs_buffers
[i
];
526 free(cs
->old_cs_buffers
);
527 cs
->old_cs_buffers
= NULL
;
528 cs
->num_old_cs_buffers
= 0;
532 static int radv_amdgpu_cs_find_buffer(struct radv_amdgpu_cs
*cs
,
535 unsigned hash
= bo
& (ARRAY_SIZE(cs
->buffer_hash_table
) - 1);
536 int index
= cs
->buffer_hash_table
[hash
];
541 if (cs
->handles
[index
].bo_handle
== bo
)
544 for (unsigned i
= 0; i
< cs
->num_buffers
; ++i
) {
545 if (cs
->handles
[i
].bo_handle
== bo
) {
546 cs
->buffer_hash_table
[hash
] = i
;
554 static void radv_amdgpu_cs_add_buffer_internal(struct radv_amdgpu_cs
*cs
,
555 uint32_t bo
, uint8_t priority
)
558 int index
= radv_amdgpu_cs_find_buffer(cs
, bo
);
563 if (cs
->num_buffers
== cs
->max_num_buffers
) {
564 unsigned new_count
= MAX2(1, cs
->max_num_buffers
* 2);
565 cs
->handles
= realloc(cs
->handles
, new_count
* sizeof(struct drm_amdgpu_bo_list_entry
));
566 cs
->max_num_buffers
= new_count
;
569 cs
->handles
[cs
->num_buffers
].bo_handle
= bo
;
570 cs
->handles
[cs
->num_buffers
].bo_priority
= priority
;
572 hash
= bo
& (ARRAY_SIZE(cs
->buffer_hash_table
) - 1);
573 cs
->buffer_hash_table
[hash
] = cs
->num_buffers
;
578 static void radv_amdgpu_cs_add_virtual_buffer(struct radeon_cmdbuf
*_cs
,
579 struct radeon_winsys_bo
*bo
)
581 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(_cs
);
582 unsigned hash
= ((uintptr_t)bo
>> 6) & (VIRTUAL_BUFFER_HASH_TABLE_SIZE
- 1);
585 if (!cs
->virtual_buffer_hash_table
) {
586 cs
->virtual_buffer_hash_table
= malloc(VIRTUAL_BUFFER_HASH_TABLE_SIZE
* sizeof(int));
587 for (int i
= 0; i
< VIRTUAL_BUFFER_HASH_TABLE_SIZE
; ++i
)
588 cs
->virtual_buffer_hash_table
[i
] = -1;
591 if (cs
->virtual_buffer_hash_table
[hash
] >= 0) {
592 int idx
= cs
->virtual_buffer_hash_table
[hash
];
593 if (cs
->virtual_buffers
[idx
] == bo
) {
596 for (unsigned i
= 0; i
< cs
->num_virtual_buffers
; ++i
) {
597 if (cs
->virtual_buffers
[i
] == bo
) {
598 cs
->virtual_buffer_hash_table
[hash
] = i
;
604 if(cs
->max_num_virtual_buffers
<= cs
->num_virtual_buffers
) {
605 cs
->max_num_virtual_buffers
= MAX2(2, cs
->max_num_virtual_buffers
* 2);
606 cs
->virtual_buffers
= realloc(cs
->virtual_buffers
, sizeof(struct radv_amdgpu_virtual_virtual_buffer
*) * cs
->max_num_virtual_buffers
);
609 cs
->virtual_buffers
[cs
->num_virtual_buffers
] = bo
;
611 cs
->virtual_buffer_hash_table
[hash
] = cs
->num_virtual_buffers
;
612 ++cs
->num_virtual_buffers
;
616 static void radv_amdgpu_cs_add_buffer(struct radeon_cmdbuf
*_cs
,
617 struct radeon_winsys_bo
*_bo
)
619 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(_cs
);
620 struct radv_amdgpu_winsys_bo
*bo
= radv_amdgpu_winsys_bo(_bo
);
622 if (bo
->is_virtual
) {
623 radv_amdgpu_cs_add_virtual_buffer(_cs
, _bo
);
627 if (bo
->base
.is_local
)
630 radv_amdgpu_cs_add_buffer_internal(cs
, bo
->bo_handle
, bo
->priority
);
633 static void radv_amdgpu_cs_execute_secondary(struct radeon_cmdbuf
*_parent
,
634 struct radeon_cmdbuf
*_child
)
636 struct radv_amdgpu_cs
*parent
= radv_amdgpu_cs(_parent
);
637 struct radv_amdgpu_cs
*child
= radv_amdgpu_cs(_child
);
639 for (unsigned i
= 0; i
< child
->num_buffers
; ++i
) {
640 radv_amdgpu_cs_add_buffer_internal(parent
,
641 child
->handles
[i
].bo_handle
,
642 child
->handles
[i
].bo_priority
);
645 for (unsigned i
= 0; i
< child
->num_virtual_buffers
; ++i
) {
646 radv_amdgpu_cs_add_buffer(&parent
->base
, child
->virtual_buffers
[i
]);
649 if (parent
->ws
->use_ib_bos
) {
650 if (parent
->base
.cdw
+ 4 > parent
->base
.max_dw
)
651 radv_amdgpu_cs_grow(&parent
->base
, 4);
653 radeon_emit(&parent
->base
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
654 radeon_emit(&parent
->base
, child
->ib
.ib_mc_address
);
655 radeon_emit(&parent
->base
, child
->ib
.ib_mc_address
>> 32);
656 radeon_emit(&parent
->base
, child
->ib
.size
);
658 if (parent
->base
.cdw
+ child
->base
.cdw
> parent
->base
.max_dw
)
659 radv_amdgpu_cs_grow(&parent
->base
, child
->base
.cdw
);
661 memcpy(parent
->base
.buf
+ parent
->base
.cdw
, child
->base
.buf
, 4 * child
->base
.cdw
);
662 parent
->base
.cdw
+= child
->base
.cdw
;
666 static int radv_amdgpu_create_bo_list(struct radv_amdgpu_winsys
*ws
,
667 struct radeon_cmdbuf
**cs_array
,
669 struct radv_amdgpu_winsys_bo
**extra_bo_array
,
670 unsigned num_extra_bo
,
671 struct radeon_cmdbuf
*extra_cs
,
672 const struct radv_winsys_bo_list
*radv_bo_list
,
677 if (ws
->debug_all_bos
) {
678 struct radv_amdgpu_winsys_bo
*bo
;
679 struct drm_amdgpu_bo_list_entry
*handles
;
682 pthread_mutex_lock(&ws
->global_bo_list_lock
);
684 handles
= malloc(sizeof(handles
[0]) * ws
->num_buffers
);
686 pthread_mutex_unlock(&ws
->global_bo_list_lock
);
690 LIST_FOR_EACH_ENTRY(bo
, &ws
->global_bo_list
, global_list_item
) {
691 assert(num
< ws
->num_buffers
);
692 handles
[num
].bo_handle
= bo
->bo_handle
;
693 handles
[num
].bo_priority
= bo
->priority
;
697 r
= amdgpu_bo_list_create_raw(ws
->dev
, ws
->num_buffers
,
700 pthread_mutex_unlock(&ws
->global_bo_list_lock
);
701 } else if (count
== 1 && !num_extra_bo
&& !extra_cs
&& !radv_bo_list
&&
702 !radv_amdgpu_cs(cs_array
[0])->num_virtual_buffers
) {
703 struct radv_amdgpu_cs
*cs
= (struct radv_amdgpu_cs
*)cs_array
[0];
704 if (cs
->num_buffers
== 0) {
708 r
= amdgpu_bo_list_create_raw(ws
->dev
, cs
->num_buffers
, cs
->handles
,
711 unsigned total_buffer_count
= num_extra_bo
;
712 unsigned unique_bo_count
= num_extra_bo
;
713 for (unsigned i
= 0; i
< count
; ++i
) {
714 struct radv_amdgpu_cs
*cs
= (struct radv_amdgpu_cs
*)cs_array
[i
];
715 total_buffer_count
+= cs
->num_buffers
;
716 for (unsigned j
= 0; j
< cs
->num_virtual_buffers
; ++j
)
717 total_buffer_count
+= radv_amdgpu_winsys_bo(cs
->virtual_buffers
[j
])->bo_count
;
721 total_buffer_count
+= ((struct radv_amdgpu_cs
*)extra_cs
)->num_buffers
;
725 total_buffer_count
+= radv_bo_list
->count
;
728 if (total_buffer_count
== 0) {
732 struct drm_amdgpu_bo_list_entry
*handles
= malloc(sizeof(struct drm_amdgpu_bo_list_entry
) * total_buffer_count
);
738 for (unsigned i
= 0; i
< num_extra_bo
; i
++) {
739 handles
[i
].bo_handle
= extra_bo_array
[i
]->bo_handle
;
740 handles
[i
].bo_priority
= extra_bo_array
[i
]->priority
;
743 for (unsigned i
= 0; i
< count
+ !!extra_cs
; ++i
) {
744 struct radv_amdgpu_cs
*cs
;
747 cs
= (struct radv_amdgpu_cs
*)extra_cs
;
749 cs
= (struct radv_amdgpu_cs
*)cs_array
[i
];
751 if (!cs
->num_buffers
)
754 if (unique_bo_count
== 0 && !cs
->num_virtual_buffers
) {
755 memcpy(handles
, cs
->handles
, cs
->num_buffers
* sizeof(struct drm_amdgpu_bo_list_entry
));
756 unique_bo_count
= cs
->num_buffers
;
759 int unique_bo_so_far
= unique_bo_count
;
760 for (unsigned j
= 0; j
< cs
->num_buffers
; ++j
) {
762 for (unsigned k
= 0; k
< unique_bo_so_far
; ++k
) {
763 if (handles
[k
].bo_handle
== cs
->handles
[j
].bo_handle
) {
769 handles
[unique_bo_count
] = cs
->handles
[j
];
773 for (unsigned j
= 0; j
< cs
->num_virtual_buffers
; ++j
) {
774 struct radv_amdgpu_winsys_bo
*virtual_bo
= radv_amdgpu_winsys_bo(cs
->virtual_buffers
[j
]);
775 for(unsigned k
= 0; k
< virtual_bo
->bo_count
; ++k
) {
776 struct radv_amdgpu_winsys_bo
*bo
= virtual_bo
->bos
[k
];
778 for (unsigned m
= 0; m
< unique_bo_count
; ++m
) {
779 if (handles
[m
].bo_handle
== bo
->bo_handle
) {
785 handles
[unique_bo_count
].bo_handle
= bo
->bo_handle
;
786 handles
[unique_bo_count
].bo_priority
= bo
->priority
;
794 unsigned unique_bo_so_far
= unique_bo_count
;
795 for (unsigned i
= 0; i
< radv_bo_list
->count
; ++i
) {
796 struct radv_amdgpu_winsys_bo
*bo
= radv_amdgpu_winsys_bo(radv_bo_list
->bos
[i
]);
798 for (unsigned j
= 0; j
< unique_bo_so_far
; ++j
) {
799 if (bo
->bo_handle
== handles
[j
].bo_handle
) {
805 handles
[unique_bo_count
].bo_handle
= bo
->bo_handle
;
806 handles
[unique_bo_count
].bo_priority
= bo
->priority
;
812 if (unique_bo_count
> 0) {
813 r
= amdgpu_bo_list_create_raw(ws
->dev
, unique_bo_count
, handles
,
825 static struct amdgpu_cs_fence_info
radv_set_cs_fence(struct radv_amdgpu_ctx
*ctx
, int ip_type
, int ring
)
827 struct amdgpu_cs_fence_info ret
= {0};
828 if (ctx
->fence_map
) {
829 ret
.handle
= radv_amdgpu_winsys_bo(ctx
->fence_bo
)->bo
;
830 ret
.offset
= (ip_type
* MAX_RINGS_PER_TYPE
+ ring
) * sizeof(uint64_t);
835 static void radv_assign_last_submit(struct radv_amdgpu_ctx
*ctx
,
836 struct radv_amdgpu_cs_request
*request
)
838 radv_amdgpu_request_to_fence(ctx
,
839 &ctx
->last_submission
[request
->ip_type
][request
->ring
],
843 static int radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx
*_ctx
,
845 struct radv_winsys_sem_info
*sem_info
,
846 const struct radv_winsys_bo_list
*radv_bo_list
,
847 struct radeon_cmdbuf
**cs_array
,
849 struct radeon_cmdbuf
*initial_preamble_cs
,
850 struct radeon_cmdbuf
*continue_preamble_cs
,
851 struct radeon_winsys_fence
*_fence
)
854 struct radv_amdgpu_ctx
*ctx
= radv_amdgpu_ctx(_ctx
);
855 struct radv_amdgpu_fence
*fence
= (struct radv_amdgpu_fence
*)_fence
;
856 struct radv_amdgpu_cs
*cs0
= radv_amdgpu_cs(cs_array
[0]);
858 struct radv_amdgpu_cs_request request
= {0};
859 struct amdgpu_cs_ib_info ibs
[2];
860 unsigned number_of_ibs
= 1;
862 for (unsigned i
= cs_count
; i
--;) {
863 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(cs_array
[i
]);
865 if (cs
->is_chained
) {
866 *cs
->ib_size_ptr
-= 4;
867 cs
->is_chained
= false;
870 if (i
+ 1 < cs_count
) {
871 struct radv_amdgpu_cs
*next
= radv_amdgpu_cs(cs_array
[i
+ 1]);
872 assert(cs
->base
.cdw
+ 4 <= cs
->base
.max_dw
);
874 cs
->is_chained
= true;
875 *cs
->ib_size_ptr
+= 4;
877 cs
->base
.buf
[cs
->base
.cdw
+ 0] = PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0);
878 cs
->base
.buf
[cs
->base
.cdw
+ 1] = next
->ib
.ib_mc_address
;
879 cs
->base
.buf
[cs
->base
.cdw
+ 2] = next
->ib
.ib_mc_address
>> 32;
880 cs
->base
.buf
[cs
->base
.cdw
+ 3] = S_3F2_CHAIN(1) | S_3F2_VALID(1) | next
->ib
.size
;
884 /* Create a buffer object list. */
885 r
= radv_amdgpu_create_bo_list(cs0
->ws
, cs_array
, cs_count
, NULL
, 0,
886 initial_preamble_cs
, radv_bo_list
,
889 fprintf(stderr
, "amdgpu: buffer list creation failed for the "
890 "chained submission(%d)\n", r
);
894 /* Configure the CS request. */
895 if (initial_preamble_cs
) {
896 ibs
[0] = radv_amdgpu_cs(initial_preamble_cs
)->ib
;
903 request
.ip_type
= cs0
->hw_ip
;
904 request
.ring
= queue_idx
;
905 request
.number_of_ibs
= number_of_ibs
;
907 request
.resources
= bo_list
;
908 request
.fence_info
= radv_set_cs_fence(ctx
, cs0
->hw_ip
, queue_idx
);
911 r
= radv_amdgpu_cs_submit(ctx
, &request
, sem_info
);
914 fprintf(stderr
, "amdgpu: Not enough memory for command submission.\n");
916 fprintf(stderr
, "amdgpu: The CS has been rejected, "
917 "see dmesg for more information.\n");
920 amdgpu_bo_list_destroy_raw(ctx
->ws
->dev
, bo_list
);
926 radv_amdgpu_request_to_fence(ctx
, fence
, &request
);
928 radv_assign_last_submit(ctx
, &request
);
933 static int radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx
*_ctx
,
935 struct radv_winsys_sem_info
*sem_info
,
936 const struct radv_winsys_bo_list
*radv_bo_list
,
937 struct radeon_cmdbuf
**cs_array
,
939 struct radeon_cmdbuf
*initial_preamble_cs
,
940 struct radeon_cmdbuf
*continue_preamble_cs
,
941 struct radeon_winsys_fence
*_fence
)
944 struct radv_amdgpu_ctx
*ctx
= radv_amdgpu_ctx(_ctx
);
945 struct radv_amdgpu_fence
*fence
= (struct radv_amdgpu_fence
*)_fence
;
947 struct radv_amdgpu_cs_request request
= {};
948 struct amdgpu_cs_ib_info
*ibs
;
949 struct radv_amdgpu_cs
*cs0
;
950 unsigned number_of_ibs
;
953 cs0
= radv_amdgpu_cs(cs_array
[0]);
955 /* Compute the number of IBs for this submit. */
956 number_of_ibs
= cs_count
+ !!initial_preamble_cs
;
958 /* Create a buffer object list. */
959 r
= radv_amdgpu_create_bo_list(cs0
->ws
, &cs_array
[0], cs_count
, NULL
, 0,
960 initial_preamble_cs
, radv_bo_list
,
963 fprintf(stderr
, "amdgpu: buffer list creation failed "
964 "for the fallback submission (%d)\n", r
);
968 ibs
= malloc(number_of_ibs
* sizeof(*ibs
));
970 amdgpu_bo_list_destroy_raw(ctx
->ws
->dev
, bo_list
);
974 /* Configure the CS request. */
975 if (initial_preamble_cs
)
976 ibs
[0] = radv_amdgpu_cs(initial_preamble_cs
)->ib
;
978 for (unsigned i
= 0; i
< cs_count
; i
++) {
979 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(cs_array
[i
]);
981 ibs
[i
+ !!initial_preamble_cs
] = cs
->ib
;
983 if (cs
->is_chained
) {
984 *cs
->ib_size_ptr
-= 4;
985 cs
->is_chained
= false;
989 request
.ip_type
= cs0
->hw_ip
;
990 request
.ring
= queue_idx
;
991 request
.resources
= bo_list
;
992 request
.number_of_ibs
= number_of_ibs
;
994 request
.fence_info
= radv_set_cs_fence(ctx
, cs0
->hw_ip
, queue_idx
);
997 r
= radv_amdgpu_cs_submit(ctx
, &request
, sem_info
);
1000 fprintf(stderr
, "amdgpu: Not enough memory for command submission.\n");
1002 fprintf(stderr
, "amdgpu: The CS has been rejected, "
1003 "see dmesg for more information.\n");
1006 amdgpu_bo_list_destroy_raw(ctx
->ws
->dev
, bo_list
);
1013 radv_amdgpu_request_to_fence(ctx
, fence
, &request
);
1015 radv_assign_last_submit(ctx
, &request
);
1020 static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx
*_ctx
,
1022 struct radv_winsys_sem_info
*sem_info
,
1023 const struct radv_winsys_bo_list
*radv_bo_list
,
1024 struct radeon_cmdbuf
**cs_array
,
1026 struct radeon_cmdbuf
*initial_preamble_cs
,
1027 struct radeon_cmdbuf
*continue_preamble_cs
,
1028 struct radeon_winsys_fence
*_fence
)
1031 struct radv_amdgpu_ctx
*ctx
= radv_amdgpu_ctx(_ctx
);
1032 struct radv_amdgpu_fence
*fence
= (struct radv_amdgpu_fence
*)_fence
;
1033 struct radv_amdgpu_cs
*cs0
= radv_amdgpu_cs(cs_array
[0]);
1034 struct radeon_winsys
*ws
= (struct radeon_winsys
*)cs0
->ws
;
1036 struct radv_amdgpu_cs_request request
;
1037 uint32_t pad_word
= 0xffff1000U
;
1038 bool emit_signal_sem
= sem_info
->cs_emit_signal
;
1040 if (radv_amdgpu_winsys(ws
)->info
.chip_class
== GFX6
)
1041 pad_word
= 0x80000000;
1045 for (unsigned i
= 0; i
< cs_count
;) {
1046 struct amdgpu_cs_ib_info
*ibs
;
1047 struct radeon_winsys_bo
**bos
;
1048 struct radeon_cmdbuf
*preamble_cs
= i
? continue_preamble_cs
: initial_preamble_cs
;
1049 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(cs_array
[i
]);
1050 unsigned number_of_ibs
;
1054 unsigned pad_words
= 0;
1056 /* Compute the number of IBs for this submit. */
1057 number_of_ibs
= cs
->num_old_cs_buffers
+ 1;
1059 ibs
= malloc(number_of_ibs
* sizeof(*ibs
));
1063 bos
= malloc(number_of_ibs
* sizeof(*bos
));
1069 if (number_of_ibs
> 1) {
1070 /* Special path when the maximum size in dwords has
1071 * been reached because we need to handle more than one
1074 struct radeon_cmdbuf
**new_cs_array
;
1077 new_cs_array
= malloc(cs
->num_old_cs_buffers
*
1078 sizeof(*new_cs_array
));
1079 assert(new_cs_array
);
1081 for (unsigned j
= 0; j
< cs
->num_old_cs_buffers
; j
++)
1082 new_cs_array
[idx
++] = &cs
->old_cs_buffers
[j
];
1083 new_cs_array
[idx
++] = cs_array
[i
];
1085 for (unsigned j
= 0; j
< number_of_ibs
; j
++) {
1086 struct radeon_cmdbuf
*rcs
= new_cs_array
[j
];
1087 bool needs_preamble
= preamble_cs
&& j
== 0;
1091 size
+= preamble_cs
->cdw
;
1094 assert(size
< 0xffff8);
1096 while (!size
|| (size
& 7)) {
1101 bos
[j
] = ws
->buffer_create(ws
, 4 * size
, 4096,
1103 RADEON_FLAG_CPU_ACCESS
|
1104 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
1105 RADEON_FLAG_READ_ONLY
,
1106 RADV_BO_PRIORITY_CS
);
1107 ptr
= ws
->buffer_map(bos
[j
]);
1109 if (needs_preamble
) {
1110 memcpy(ptr
, preamble_cs
->buf
, preamble_cs
->cdw
* 4);
1111 ptr
+= preamble_cs
->cdw
;
1114 memcpy(ptr
, rcs
->buf
, 4 * rcs
->cdw
);
1117 for (unsigned k
= 0; k
< pad_words
; ++k
)
1121 ibs
[j
].ib_mc_address
= radv_buffer_get_va(bos
[j
]);
1128 size
+= preamble_cs
->cdw
;
1130 while (i
+ cnt
< cs_count
&& 0xffff8 - size
>= radv_amdgpu_cs(cs_array
[i
+ cnt
])->base
.cdw
) {
1131 size
+= radv_amdgpu_cs(cs_array
[i
+ cnt
])->base
.cdw
;
1135 while (!size
|| (size
& 7)) {
1141 bos
[0] = ws
->buffer_create(ws
, 4 * size
, 4096,
1143 RADEON_FLAG_CPU_ACCESS
|
1144 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
1145 RADEON_FLAG_READ_ONLY
,
1146 RADV_BO_PRIORITY_CS
);
1147 ptr
= ws
->buffer_map(bos
[0]);
1150 memcpy(ptr
, preamble_cs
->buf
, preamble_cs
->cdw
* 4);
1151 ptr
+= preamble_cs
->cdw
;
1154 for (unsigned j
= 0; j
< cnt
; ++j
) {
1155 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(cs_array
[i
+ j
]);
1156 memcpy(ptr
, cs
->base
.buf
, 4 * cs
->base
.cdw
);
1157 ptr
+= cs
->base
.cdw
;
1161 for (unsigned j
= 0; j
< pad_words
; ++j
)
1165 ibs
[0].ib_mc_address
= radv_buffer_get_va(bos
[0]);
1168 r
= radv_amdgpu_create_bo_list(cs0
->ws
, &cs_array
[i
], cnt
,
1169 (struct radv_amdgpu_winsys_bo
**)bos
,
1170 number_of_ibs
, preamble_cs
,
1171 radv_bo_list
, &bo_list
);
1173 fprintf(stderr
, "amdgpu: buffer list creation failed "
1174 "for the sysmem submission (%d)\n", r
);
1180 memset(&request
, 0, sizeof(request
));
1182 request
.ip_type
= cs0
->hw_ip
;
1183 request
.ring
= queue_idx
;
1184 request
.resources
= bo_list
;
1185 request
.number_of_ibs
= number_of_ibs
;
1187 request
.fence_info
= radv_set_cs_fence(ctx
, cs0
->hw_ip
, queue_idx
);
1189 sem_info
->cs_emit_signal
= (i
== cs_count
- cnt
) ? emit_signal_sem
: false;
1190 r
= radv_amdgpu_cs_submit(ctx
, &request
, sem_info
);
1193 fprintf(stderr
, "amdgpu: Not enough memory for command submission.\n");
1195 fprintf(stderr
, "amdgpu: The CS has been rejected, "
1196 "see dmesg for more information.\n");
1199 amdgpu_bo_list_destroy_raw(ctx
->ws
->dev
, bo_list
);
1201 for (unsigned j
= 0; j
< number_of_ibs
; j
++) {
1202 ws
->buffer_destroy(bos
[j
]);
1214 radv_amdgpu_request_to_fence(ctx
, fence
, &request
);
1216 radv_assign_last_submit(ctx
, &request
);
1221 static int radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx
*_ctx
,
1223 struct radeon_cmdbuf
**cs_array
,
1225 struct radeon_cmdbuf
*initial_preamble_cs
,
1226 struct radeon_cmdbuf
*continue_preamble_cs
,
1227 struct radv_winsys_sem_info
*sem_info
,
1228 const struct radv_winsys_bo_list
*bo_list
,
1230 struct radeon_winsys_fence
*_fence
)
1232 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(cs_array
[0]);
1233 struct radv_amdgpu_ctx
*ctx
= radv_amdgpu_ctx(_ctx
);
1237 if (!cs
->ws
->use_ib_bos
) {
1238 ret
= radv_amdgpu_winsys_cs_submit_sysmem(_ctx
, queue_idx
, sem_info
, bo_list
, cs_array
,
1239 cs_count
, initial_preamble_cs
, continue_preamble_cs
, _fence
);
1240 } else if (can_patch
&& cs
->ws
->batchchain
) {
1241 ret
= radv_amdgpu_winsys_cs_submit_chained(_ctx
, queue_idx
, sem_info
, bo_list
, cs_array
,
1242 cs_count
, initial_preamble_cs
, continue_preamble_cs
, _fence
);
1244 ret
= radv_amdgpu_winsys_cs_submit_fallback(_ctx
, queue_idx
, sem_info
, bo_list
, cs_array
,
1245 cs_count
, initial_preamble_cs
, continue_preamble_cs
, _fence
);
1248 radv_amdgpu_signal_sems(ctx
, cs
->hw_ip
, queue_idx
, sem_info
);
1252 static void *radv_amdgpu_winsys_get_cpu_addr(void *_cs
, uint64_t addr
)
1254 struct radv_amdgpu_cs
*cs
= (struct radv_amdgpu_cs
*)_cs
;
1259 for (unsigned i
= 0; i
<= cs
->num_old_ib_buffers
; ++i
) {
1260 struct radv_amdgpu_winsys_bo
*bo
;
1262 bo
= (struct radv_amdgpu_winsys_bo
*)
1263 (i
== cs
->num_old_ib_buffers
? cs
->ib_buffer
: cs
->old_ib_buffers
[i
]);
1264 if (addr
>= bo
->base
.va
&& addr
- bo
->base
.va
< bo
->size
) {
1265 if (amdgpu_bo_cpu_map(bo
->bo
, &ret
) == 0)
1266 return (char *)ret
+ (addr
- bo
->base
.va
);
1269 if(cs
->ws
->debug_all_bos
) {
1270 pthread_mutex_lock(&cs
->ws
->global_bo_list_lock
);
1271 list_for_each_entry(struct radv_amdgpu_winsys_bo
, bo
,
1272 &cs
->ws
->global_bo_list
, global_list_item
) {
1273 if (addr
>= bo
->base
.va
&& addr
- bo
->base
.va
< bo
->size
) {
1274 if (amdgpu_bo_cpu_map(bo
->bo
, &ret
) == 0) {
1275 pthread_mutex_unlock(&cs
->ws
->global_bo_list_lock
);
1276 return (char *)ret
+ (addr
- bo
->base
.va
);
1280 pthread_mutex_unlock(&cs
->ws
->global_bo_list_lock
);
1285 static void radv_amdgpu_winsys_cs_dump(struct radeon_cmdbuf
*_cs
,
1287 const int *trace_ids
, int trace_id_count
)
1289 struct radv_amdgpu_cs
*cs
= (struct radv_amdgpu_cs
*)_cs
;
1290 void *ib
= cs
->base
.buf
;
1291 int num_dw
= cs
->base
.cdw
;
1293 if (cs
->ws
->use_ib_bos
) {
1294 ib
= radv_amdgpu_winsys_get_cpu_addr(cs
, cs
->ib
.ib_mc_address
);
1295 num_dw
= cs
->ib
.size
;
1298 ac_parse_ib(file
, ib
, num_dw
, trace_ids
, trace_id_count
, "main IB",
1299 cs
->ws
->info
.chip_class
, radv_amdgpu_winsys_get_cpu_addr
, cs
);
1302 static uint32_t radv_to_amdgpu_priority(enum radeon_ctx_priority radv_priority
)
1304 switch (radv_priority
) {
1305 case RADEON_CTX_PRIORITY_REALTIME
:
1306 return AMDGPU_CTX_PRIORITY_VERY_HIGH
;
1307 case RADEON_CTX_PRIORITY_HIGH
:
1308 return AMDGPU_CTX_PRIORITY_HIGH
;
1309 case RADEON_CTX_PRIORITY_MEDIUM
:
1310 return AMDGPU_CTX_PRIORITY_NORMAL
;
1311 case RADEON_CTX_PRIORITY_LOW
:
1312 return AMDGPU_CTX_PRIORITY_LOW
;
1314 unreachable("Invalid context priority");
1318 static struct radeon_winsys_ctx
*radv_amdgpu_ctx_create(struct radeon_winsys
*_ws
,
1319 enum radeon_ctx_priority priority
)
1321 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1322 struct radv_amdgpu_ctx
*ctx
= CALLOC_STRUCT(radv_amdgpu_ctx
);
1323 uint32_t amdgpu_priority
= radv_to_amdgpu_priority(priority
);
1329 r
= amdgpu_cs_ctx_create2(ws
->dev
, amdgpu_priority
, &ctx
->ctx
);
1331 fprintf(stderr
, "amdgpu: radv_amdgpu_cs_ctx_create2 failed. (%i)\n", r
);
1336 assert(AMDGPU_HW_IP_NUM
* MAX_RINGS_PER_TYPE
* sizeof(uint64_t) <= 4096);
1337 ctx
->fence_bo
= ws
->base
.buffer_create(&ws
->base
, 4096, 8,
1339 RADEON_FLAG_CPU_ACCESS
|
1340 RADEON_FLAG_NO_INTERPROCESS_SHARING
,
1341 RADV_BO_PRIORITY_CS
);
1343 ctx
->fence_map
= (uint64_t*)ws
->base
.buffer_map(ctx
->fence_bo
);
1345 memset(ctx
->fence_map
, 0, 4096);
1346 return (struct radeon_winsys_ctx
*)ctx
;
1352 static void radv_amdgpu_ctx_destroy(struct radeon_winsys_ctx
*rwctx
)
1354 struct radv_amdgpu_ctx
*ctx
= (struct radv_amdgpu_ctx
*)rwctx
;
1355 ctx
->ws
->base
.buffer_destroy(ctx
->fence_bo
);
1356 amdgpu_cs_ctx_free(ctx
->ctx
);
1360 static bool radv_amdgpu_ctx_wait_idle(struct radeon_winsys_ctx
*rwctx
,
1361 enum ring_type ring_type
, int ring_index
)
1363 struct radv_amdgpu_ctx
*ctx
= (struct radv_amdgpu_ctx
*)rwctx
;
1364 int ip_type
= ring_to_hw_ip(ring_type
);
1366 if (ctx
->last_submission
[ip_type
][ring_index
].fence
.fence
) {
1368 int ret
= amdgpu_cs_query_fence_status(&ctx
->last_submission
[ip_type
][ring_index
].fence
,
1369 1000000000ull, 0, &expired
);
1371 if (ret
|| !expired
)
1378 static struct radeon_winsys_sem
*radv_amdgpu_create_sem(struct radeon_winsys
*_ws
)
1380 struct amdgpu_cs_fence
*sem
= CALLOC_STRUCT(amdgpu_cs_fence
);
1384 return (struct radeon_winsys_sem
*)sem
;
1387 static void radv_amdgpu_destroy_sem(struct radeon_winsys_sem
*_sem
)
1389 struct amdgpu_cs_fence
*sem
= (struct amdgpu_cs_fence
*)_sem
;
1393 static int radv_amdgpu_signal_sems(struct radv_amdgpu_ctx
*ctx
,
1396 struct radv_winsys_sem_info
*sem_info
)
1398 for (unsigned i
= 0; i
< sem_info
->signal
.sem_count
; i
++) {
1399 struct amdgpu_cs_fence
*sem
= (struct amdgpu_cs_fence
*)(sem_info
->signal
.sem
)[i
];
1404 *sem
= ctx
->last_submission
[ip_type
][ring
].fence
;
1409 static struct drm_amdgpu_cs_chunk_sem
*radv_amdgpu_cs_alloc_syncobj_chunk(struct radv_winsys_sem_counts
*counts
,
1410 struct drm_amdgpu_cs_chunk
*chunk
, int chunk_id
)
1412 struct drm_amdgpu_cs_chunk_sem
*syncobj
= malloc(sizeof(struct drm_amdgpu_cs_chunk_sem
) * counts
->syncobj_count
);
1416 for (unsigned i
= 0; i
< counts
->syncobj_count
; i
++) {
1417 struct drm_amdgpu_cs_chunk_sem
*sem
= &syncobj
[i
];
1418 sem
->handle
= counts
->syncobj
[i
];
1421 chunk
->chunk_id
= chunk_id
;
1422 chunk
->length_dw
= sizeof(struct drm_amdgpu_cs_chunk_sem
) / 4 * counts
->syncobj_count
;
1423 chunk
->chunk_data
= (uint64_t)(uintptr_t)syncobj
;
1427 static int radv_amdgpu_cs_submit(struct radv_amdgpu_ctx
*ctx
,
1428 struct radv_amdgpu_cs_request
*request
,
1429 struct radv_winsys_sem_info
*sem_info
)
1435 struct drm_amdgpu_cs_chunk
*chunks
;
1436 struct drm_amdgpu_cs_chunk_data
*chunk_data
;
1437 struct drm_amdgpu_cs_chunk_dep
*sem_dependencies
= NULL
;
1438 struct drm_amdgpu_cs_chunk_sem
*wait_syncobj
= NULL
, *signal_syncobj
= NULL
;
1440 struct amdgpu_cs_fence
*sem
;
1442 user_fence
= (request
->fence_info
.handle
!= NULL
);
1443 size
= request
->number_of_ibs
+ (user_fence
? 2 : 1) + 3;
1445 chunks
= alloca(sizeof(struct drm_amdgpu_cs_chunk
) * size
);
1447 size
= request
->number_of_ibs
+ (user_fence
? 1 : 0);
1449 chunk_data
= alloca(sizeof(struct drm_amdgpu_cs_chunk_data
) * size
);
1451 num_chunks
= request
->number_of_ibs
;
1452 for (i
= 0; i
< request
->number_of_ibs
; i
++) {
1453 struct amdgpu_cs_ib_info
*ib
;
1454 chunks
[i
].chunk_id
= AMDGPU_CHUNK_ID_IB
;
1455 chunks
[i
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_ib
) / 4;
1456 chunks
[i
].chunk_data
= (uint64_t)(uintptr_t)&chunk_data
[i
];
1458 ib
= &request
->ibs
[i
];
1460 chunk_data
[i
].ib_data
._pad
= 0;
1461 chunk_data
[i
].ib_data
.va_start
= ib
->ib_mc_address
;
1462 chunk_data
[i
].ib_data
.ib_bytes
= ib
->size
* 4;
1463 chunk_data
[i
].ib_data
.ip_type
= request
->ip_type
;
1464 chunk_data
[i
].ib_data
.ip_instance
= request
->ip_instance
;
1465 chunk_data
[i
].ib_data
.ring
= request
->ring
;
1466 chunk_data
[i
].ib_data
.flags
= ib
->flags
;
1472 chunks
[i
].chunk_id
= AMDGPU_CHUNK_ID_FENCE
;
1473 chunks
[i
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_fence
) / 4;
1474 chunks
[i
].chunk_data
= (uint64_t)(uintptr_t)&chunk_data
[i
];
1476 amdgpu_cs_chunk_fence_info_to_data(&request
->fence_info
,
1480 if (sem_info
->wait
.syncobj_count
&& sem_info
->cs_emit_wait
) {
1481 wait_syncobj
= radv_amdgpu_cs_alloc_syncobj_chunk(&sem_info
->wait
,
1482 &chunks
[num_chunks
],
1483 AMDGPU_CHUNK_ID_SYNCOBJ_IN
);
1484 if (!wait_syncobj
) {
1490 if (sem_info
->wait
.sem_count
== 0)
1491 sem_info
->cs_emit_wait
= false;
1495 if (sem_info
->wait
.sem_count
&& sem_info
->cs_emit_wait
) {
1496 sem_dependencies
= alloca(sizeof(struct drm_amdgpu_cs_chunk_dep
) * sem_info
->wait
.sem_count
);
1499 for (unsigned j
= 0; j
< sem_info
->wait
.sem_count
; j
++) {
1500 sem
= (struct amdgpu_cs_fence
*)sem_info
->wait
.sem
[j
];
1503 struct drm_amdgpu_cs_chunk_dep
*dep
= &sem_dependencies
[sem_count
++];
1505 amdgpu_cs_chunk_fence_to_dep(sem
, dep
);
1507 sem
->context
= NULL
;
1511 /* dependencies chunk */
1512 chunks
[i
].chunk_id
= AMDGPU_CHUNK_ID_DEPENDENCIES
;
1513 chunks
[i
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_dep
) / 4 * sem_count
;
1514 chunks
[i
].chunk_data
= (uint64_t)(uintptr_t)sem_dependencies
;
1516 sem_info
->cs_emit_wait
= false;
1519 if (sem_info
->signal
.syncobj_count
&& sem_info
->cs_emit_signal
) {
1520 signal_syncobj
= radv_amdgpu_cs_alloc_syncobj_chunk(&sem_info
->signal
,
1521 &chunks
[num_chunks
],
1522 AMDGPU_CHUNK_ID_SYNCOBJ_OUT
);
1523 if (!signal_syncobj
) {
1530 r
= amdgpu_cs_submit_raw2(ctx
->ws
->dev
,
1538 free(signal_syncobj
);
1542 static int radv_amdgpu_create_syncobj(struct radeon_winsys
*_ws
,
1545 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1546 return amdgpu_cs_create_syncobj(ws
->dev
, handle
);
1549 static void radv_amdgpu_destroy_syncobj(struct radeon_winsys
*_ws
,
1552 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1553 amdgpu_cs_destroy_syncobj(ws
->dev
, handle
);
1556 static void radv_amdgpu_reset_syncobj(struct radeon_winsys
*_ws
,
1559 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1560 amdgpu_cs_syncobj_reset(ws
->dev
, &handle
, 1);
1563 static void radv_amdgpu_signal_syncobj(struct radeon_winsys
*_ws
,
1566 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1567 amdgpu_cs_syncobj_signal(ws
->dev
, &handle
, 1);
1570 static bool radv_amdgpu_wait_syncobj(struct radeon_winsys
*_ws
, const uint32_t *handles
,
1571 uint32_t handle_count
, bool wait_all
, uint64_t timeout
)
1573 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1576 /* The timeouts are signed, while vulkan timeouts are unsigned. */
1577 timeout
= MIN2(timeout
, INT64_MAX
);
1579 int ret
= amdgpu_cs_syncobj_wait(ws
->dev
, (uint32_t*)handles
, handle_count
, timeout
,
1580 DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT
|
1581 (wait_all
? DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL
: 0),
1585 } else if (ret
== -ETIME
) {
1588 fprintf(stderr
, "amdgpu: radv_amdgpu_wait_syncobj failed!\nerrno: %d\n", errno
);
1593 static int radv_amdgpu_export_syncobj(struct radeon_winsys
*_ws
,
1597 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1599 return amdgpu_cs_export_syncobj(ws
->dev
, syncobj
, fd
);
1602 static int radv_amdgpu_import_syncobj(struct radeon_winsys
*_ws
,
1606 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1608 return amdgpu_cs_import_syncobj(ws
->dev
, fd
, syncobj
);
1612 static int radv_amdgpu_export_syncobj_to_sync_file(struct radeon_winsys
*_ws
,
1616 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1618 return amdgpu_cs_syncobj_export_sync_file(ws
->dev
, syncobj
, fd
);
1621 static int radv_amdgpu_import_syncobj_from_sync_file(struct radeon_winsys
*_ws
,
1625 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1627 return amdgpu_cs_syncobj_import_sync_file(ws
->dev
, syncobj
, fd
);
1630 void radv_amdgpu_cs_init_functions(struct radv_amdgpu_winsys
*ws
)
1632 ws
->base
.ctx_create
= radv_amdgpu_ctx_create
;
1633 ws
->base
.ctx_destroy
= radv_amdgpu_ctx_destroy
;
1634 ws
->base
.ctx_wait_idle
= radv_amdgpu_ctx_wait_idle
;
1635 ws
->base
.cs_create
= radv_amdgpu_cs_create
;
1636 ws
->base
.cs_destroy
= radv_amdgpu_cs_destroy
;
1637 ws
->base
.cs_grow
= radv_amdgpu_cs_grow
;
1638 ws
->base
.cs_finalize
= radv_amdgpu_cs_finalize
;
1639 ws
->base
.cs_reset
= radv_amdgpu_cs_reset
;
1640 ws
->base
.cs_add_buffer
= radv_amdgpu_cs_add_buffer
;
1641 ws
->base
.cs_execute_secondary
= radv_amdgpu_cs_execute_secondary
;
1642 ws
->base
.cs_submit
= radv_amdgpu_winsys_cs_submit
;
1643 ws
->base
.cs_dump
= radv_amdgpu_winsys_cs_dump
;
1644 ws
->base
.create_fence
= radv_amdgpu_create_fence
;
1645 ws
->base
.destroy_fence
= radv_amdgpu_destroy_fence
;
1646 ws
->base
.reset_fence
= radv_amdgpu_reset_fence
;
1647 ws
->base
.signal_fence
= radv_amdgpu_signal_fence
;
1648 ws
->base
.is_fence_waitable
= radv_amdgpu_is_fence_waitable
;
1649 ws
->base
.create_sem
= radv_amdgpu_create_sem
;
1650 ws
->base
.destroy_sem
= radv_amdgpu_destroy_sem
;
1651 ws
->base
.create_syncobj
= radv_amdgpu_create_syncobj
;
1652 ws
->base
.destroy_syncobj
= radv_amdgpu_destroy_syncobj
;
1653 ws
->base
.reset_syncobj
= radv_amdgpu_reset_syncobj
;
1654 ws
->base
.signal_syncobj
= radv_amdgpu_signal_syncobj
;
1655 ws
->base
.wait_syncobj
= radv_amdgpu_wait_syncobj
;
1656 ws
->base
.export_syncobj
= radv_amdgpu_export_syncobj
;
1657 ws
->base
.import_syncobj
= radv_amdgpu_import_syncobj
;
1658 ws
->base
.export_syncobj_to_sync_file
= radv_amdgpu_export_syncobj_to_sync_file
;
1659 ws
->base
.import_syncobj_from_sync_file
= radv_amdgpu_import_syncobj_from_sync_file
;
1660 ws
->base
.fence_wait
= radv_amdgpu_fence_wait
;
1661 ws
->base
.fences_wait
= radv_amdgpu_fences_wait
;