2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include <amdgpu_drm.h>
33 #include "radv_radeon_winsys.h"
34 #include "radv_amdgpu_cs.h"
35 #include "radv_amdgpu_bo.h"
40 VIRTUAL_BUFFER_HASH_TABLE_SIZE
= 1024
43 struct radv_amdgpu_cs
{
44 struct radeon_winsys_cs base
;
45 struct radv_amdgpu_winsys
*ws
;
47 struct amdgpu_cs_ib_info ib
;
49 struct radeon_winsys_bo
*ib_buffer
;
51 unsigned max_num_buffers
;
53 amdgpu_bo_handle
*handles
;
56 struct radeon_winsys_bo
**old_ib_buffers
;
57 unsigned num_old_ib_buffers
;
58 unsigned max_num_old_ib_buffers
;
59 unsigned *ib_size_ptr
;
63 int buffer_hash_table
[1024];
66 unsigned num_virtual_buffers
;
67 unsigned max_num_virtual_buffers
;
68 struct radeon_winsys_bo
**virtual_buffers
;
69 uint8_t *virtual_buffer_priorities
;
70 int *virtual_buffer_hash_table
;
72 /* For chips that don't support chaining. */
73 struct radeon_winsys_cs
*old_cs_buffers
;
74 unsigned num_old_cs_buffers
;
77 static inline struct radv_amdgpu_cs
*
78 radv_amdgpu_cs(struct radeon_winsys_cs
*base
)
80 return (struct radv_amdgpu_cs
*)base
;
83 static int ring_to_hw_ip(enum ring_type ring
)
87 return AMDGPU_HW_IP_GFX
;
89 return AMDGPU_HW_IP_DMA
;
91 return AMDGPU_HW_IP_COMPUTE
;
93 unreachable("unsupported ring");
97 static int radv_amdgpu_signal_sems(struct radv_amdgpu_ctx
*ctx
,
100 struct radv_winsys_sem_info
*sem_info
);
101 static int radv_amdgpu_cs_submit(struct radv_amdgpu_ctx
*ctx
,
102 struct amdgpu_cs_request
*request
,
103 struct radv_winsys_sem_info
*sem_info
);
105 static void radv_amdgpu_request_to_fence(struct radv_amdgpu_ctx
*ctx
,
106 struct radv_amdgpu_fence
*fence
,
107 struct amdgpu_cs_request
*req
)
109 fence
->fence
.context
= ctx
->ctx
;
110 fence
->fence
.ip_type
= req
->ip_type
;
111 fence
->fence
.ip_instance
= req
->ip_instance
;
112 fence
->fence
.ring
= req
->ring
;
113 fence
->fence
.fence
= req
->seq_no
;
114 fence
->user_ptr
= (volatile uint64_t*)(ctx
->fence_map
+ (req
->ip_type
* MAX_RINGS_PER_TYPE
+ req
->ring
) * sizeof(uint64_t));
117 static struct radeon_winsys_fence
*radv_amdgpu_create_fence()
119 struct radv_amdgpu_fence
*fence
= calloc(1, sizeof(struct radv_amdgpu_fence
));
120 return (struct radeon_winsys_fence
*)fence
;
123 static void radv_amdgpu_destroy_fence(struct radeon_winsys_fence
*_fence
)
125 struct radv_amdgpu_fence
*fence
= (struct radv_amdgpu_fence
*)_fence
;
129 static bool radv_amdgpu_fence_wait(struct radeon_winsys
*_ws
,
130 struct radeon_winsys_fence
*_fence
,
134 struct radv_amdgpu_fence
*fence
= (struct radv_amdgpu_fence
*)_fence
;
135 unsigned flags
= absolute
? AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE
: 0;
137 uint32_t expired
= 0;
139 if (fence
->user_ptr
) {
140 if (*fence
->user_ptr
>= fence
->fence
.fence
)
142 if (!absolute
&& !timeout
)
146 /* Now use the libdrm query. */
147 r
= amdgpu_cs_query_fence_status(&fence
->fence
,
153 fprintf(stderr
, "amdgpu: radv_amdgpu_cs_query_fence_status failed.\n");
164 static bool radv_amdgpu_fences_wait(struct radeon_winsys
*_ws
,
165 struct radeon_winsys_fence
*const *_fences
,
166 uint32_t fence_count
,
170 struct amdgpu_cs_fence
*fences
= malloc(sizeof(struct amdgpu_cs_fence
) * fence_count
);
172 uint32_t expired
= 0, first
= 0;
177 for (uint32_t i
= 0; i
< fence_count
; ++i
)
178 fences
[i
] = ((struct radv_amdgpu_fence
*)_fences
[i
])->fence
;
180 /* Now use the libdrm query. */
181 r
= amdgpu_cs_wait_fences(fences
, fence_count
, wait_all
,
182 timeout
, &expired
, &first
);
186 fprintf(stderr
, "amdgpu: amdgpu_cs_wait_fences failed.\n");
196 static void radv_amdgpu_cs_destroy(struct radeon_winsys_cs
*rcs
)
198 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(rcs
);
201 cs
->ws
->base
.buffer_destroy(cs
->ib_buffer
);
205 for (unsigned i
= 0; i
< cs
->num_old_ib_buffers
; ++i
)
206 cs
->ws
->base
.buffer_destroy(cs
->old_ib_buffers
[i
]);
208 for (unsigned i
= 0; i
< cs
->num_old_cs_buffers
; ++i
) {
209 struct radeon_winsys_cs
*rcs
= &cs
->old_cs_buffers
[i
];
213 free(cs
->old_cs_buffers
);
214 free(cs
->old_ib_buffers
);
215 free(cs
->virtual_buffers
);
216 free(cs
->virtual_buffer_priorities
);
217 free(cs
->virtual_buffer_hash_table
);
219 free(cs
->priorities
);
223 static void radv_amdgpu_init_cs(struct radv_amdgpu_cs
*cs
,
224 enum ring_type ring_type
)
226 for (int i
= 0; i
< ARRAY_SIZE(cs
->buffer_hash_table
); ++i
)
227 cs
->buffer_hash_table
[i
] = -1;
229 cs
->hw_ip
= ring_to_hw_ip(ring_type
);
232 static struct radeon_winsys_cs
*
233 radv_amdgpu_cs_create(struct radeon_winsys
*ws
,
234 enum ring_type ring_type
)
236 struct radv_amdgpu_cs
*cs
;
237 uint32_t ib_size
= 20 * 1024 * 4;
238 cs
= calloc(1, sizeof(struct radv_amdgpu_cs
));
242 cs
->ws
= radv_amdgpu_winsys(ws
);
243 radv_amdgpu_init_cs(cs
, ring_type
);
245 if (cs
->ws
->use_ib_bos
) {
246 cs
->ib_buffer
= ws
->buffer_create(ws
, ib_size
, 0,
248 RADEON_FLAG_CPU_ACCESS
|
249 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
250 RADEON_FLAG_READ_ONLY
);
251 if (!cs
->ib_buffer
) {
256 cs
->ib_mapped
= ws
->buffer_map(cs
->ib_buffer
);
257 if (!cs
->ib_mapped
) {
258 ws
->buffer_destroy(cs
->ib_buffer
);
263 cs
->ib
.ib_mc_address
= radv_amdgpu_winsys_bo(cs
->ib_buffer
)->base
.va
;
264 cs
->base
.buf
= (uint32_t *)cs
->ib_mapped
;
265 cs
->base
.max_dw
= ib_size
/ 4 - 4;
266 cs
->ib_size_ptr
= &cs
->ib
.size
;
269 ws
->cs_add_buffer(&cs
->base
, cs
->ib_buffer
, 8);
271 cs
->base
.buf
= malloc(16384);
272 cs
->base
.max_dw
= 4096;
282 static void radv_amdgpu_cs_grow(struct radeon_winsys_cs
*_cs
, size_t min_size
)
284 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(_cs
);
291 if (!cs
->ws
->use_ib_bos
) {
292 const uint64_t limit_dws
= 0xffff8;
293 uint64_t ib_dws
= MAX2(cs
->base
.cdw
+ min_size
,
294 MIN2(cs
->base
.max_dw
* 2, limit_dws
));
296 /* The total ib size cannot exceed limit_dws dwords. */
297 if (ib_dws
> limit_dws
)
299 /* The maximum size in dwords has been reached,
300 * try to allocate a new one.
302 if (cs
->num_old_cs_buffers
+ 1 >= AMDGPU_CS_MAX_IBS_PER_SUBMIT
) {
303 /* TODO: Allow to submit more than 4 IBs. */
304 fprintf(stderr
, "amdgpu: Maximum number of IBs "
305 "per submit reached.\n");
312 realloc(cs
->old_cs_buffers
,
313 (cs
->num_old_cs_buffers
+ 1) * sizeof(*cs
->old_cs_buffers
));
314 if (!cs
->old_cs_buffers
) {
320 /* Store the current one for submitting it later. */
321 cs
->old_cs_buffers
[cs
->num_old_cs_buffers
].cdw
= cs
->base
.cdw
;
322 cs
->old_cs_buffers
[cs
->num_old_cs_buffers
].max_dw
= cs
->base
.max_dw
;
323 cs
->old_cs_buffers
[cs
->num_old_cs_buffers
].buf
= cs
->base
.buf
;
324 cs
->num_old_cs_buffers
++;
326 /* Reset the cs, it will be re-allocated below. */
330 /* Re-compute the number of dwords to allocate. */
331 ib_dws
= MAX2(cs
->base
.cdw
+ min_size
,
332 MIN2(cs
->base
.max_dw
* 2, limit_dws
));
333 if (ib_dws
> limit_dws
) {
334 fprintf(stderr
, "amdgpu: Too high number of "
335 "dwords to allocate\n");
341 uint32_t *new_buf
= realloc(cs
->base
.buf
, ib_dws
* 4);
343 cs
->base
.buf
= new_buf
;
344 cs
->base
.max_dw
= ib_dws
;
352 uint64_t ib_size
= MAX2(min_size
* 4 + 16, cs
->base
.max_dw
* 4 * 2);
354 /* max that fits in the chain size field. */
355 ib_size
= MIN2(ib_size
, 0xfffff);
357 while (!cs
->base
.cdw
|| (cs
->base
.cdw
& 7) != 4)
358 cs
->base
.buf
[cs
->base
.cdw
++] = 0xffff1000;
360 *cs
->ib_size_ptr
|= cs
->base
.cdw
+ 4;
362 if (cs
->num_old_ib_buffers
== cs
->max_num_old_ib_buffers
) {
363 cs
->max_num_old_ib_buffers
= MAX2(1, cs
->max_num_old_ib_buffers
* 2);
364 cs
->old_ib_buffers
= realloc(cs
->old_ib_buffers
,
365 cs
->max_num_old_ib_buffers
* sizeof(void*));
368 cs
->old_ib_buffers
[cs
->num_old_ib_buffers
++] = cs
->ib_buffer
;
370 cs
->ib_buffer
= cs
->ws
->base
.buffer_create(&cs
->ws
->base
, ib_size
, 0,
372 RADEON_FLAG_CPU_ACCESS
|
373 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
374 RADEON_FLAG_READ_ONLY
);
376 if (!cs
->ib_buffer
) {
379 cs
->ib_buffer
= cs
->old_ib_buffers
[--cs
->num_old_ib_buffers
];
382 cs
->ib_mapped
= cs
->ws
->base
.buffer_map(cs
->ib_buffer
);
383 if (!cs
->ib_mapped
) {
384 cs
->ws
->base
.buffer_destroy(cs
->ib_buffer
);
387 cs
->ib_buffer
= cs
->old_ib_buffers
[--cs
->num_old_ib_buffers
];
390 cs
->ws
->base
.cs_add_buffer(&cs
->base
, cs
->ib_buffer
, 8);
392 cs
->base
.buf
[cs
->base
.cdw
++] = PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0);
393 cs
->base
.buf
[cs
->base
.cdw
++] = radv_amdgpu_winsys_bo(cs
->ib_buffer
)->base
.va
;
394 cs
->base
.buf
[cs
->base
.cdw
++] = radv_amdgpu_winsys_bo(cs
->ib_buffer
)->base
.va
>> 32;
395 cs
->ib_size_ptr
= cs
->base
.buf
+ cs
->base
.cdw
;
396 cs
->base
.buf
[cs
->base
.cdw
++] = S_3F2_CHAIN(1) | S_3F2_VALID(1);
398 cs
->base
.buf
= (uint32_t *)cs
->ib_mapped
;
400 cs
->base
.max_dw
= ib_size
/ 4 - 4;
404 static bool radv_amdgpu_cs_finalize(struct radeon_winsys_cs
*_cs
)
406 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(_cs
);
408 if (cs
->ws
->use_ib_bos
) {
409 while (!cs
->base
.cdw
|| (cs
->base
.cdw
& 7) != 0)
410 cs
->base
.buf
[cs
->base
.cdw
++] = 0xffff1000;
412 *cs
->ib_size_ptr
|= cs
->base
.cdw
;
414 cs
->is_chained
= false;
420 static void radv_amdgpu_cs_reset(struct radeon_winsys_cs
*_cs
)
422 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(_cs
);
426 for (unsigned i
= 0; i
< cs
->num_buffers
; ++i
) {
427 unsigned hash
= ((uintptr_t)cs
->handles
[i
] >> 6) &
428 (ARRAY_SIZE(cs
->buffer_hash_table
) - 1);
429 cs
->buffer_hash_table
[hash
] = -1;
432 for (unsigned i
= 0; i
< cs
->num_virtual_buffers
; ++i
) {
433 unsigned hash
= ((uintptr_t)cs
->virtual_buffers
[i
] >> 6) & (VIRTUAL_BUFFER_HASH_TABLE_SIZE
- 1);
434 cs
->virtual_buffer_hash_table
[hash
] = -1;
438 cs
->num_virtual_buffers
= 0;
440 if (cs
->ws
->use_ib_bos
) {
441 cs
->ws
->base
.cs_add_buffer(&cs
->base
, cs
->ib_buffer
, 8);
443 for (unsigned i
= 0; i
< cs
->num_old_ib_buffers
; ++i
)
444 cs
->ws
->base
.buffer_destroy(cs
->old_ib_buffers
[i
]);
446 cs
->num_old_ib_buffers
= 0;
447 cs
->ib
.ib_mc_address
= radv_amdgpu_winsys_bo(cs
->ib_buffer
)->base
.va
;
448 cs
->ib_size_ptr
= &cs
->ib
.size
;
451 for (unsigned i
= 0; i
< cs
->num_old_cs_buffers
; ++i
) {
452 struct radeon_winsys_cs
*rcs
= &cs
->old_cs_buffers
[i
];
456 free(cs
->old_cs_buffers
);
457 cs
->old_cs_buffers
= NULL
;
458 cs
->num_old_cs_buffers
= 0;
462 static int radv_amdgpu_cs_find_buffer(struct radv_amdgpu_cs
*cs
,
465 unsigned hash
= ((uintptr_t)bo
>> 6) & (ARRAY_SIZE(cs
->buffer_hash_table
) - 1);
466 int index
= cs
->buffer_hash_table
[hash
];
471 if (cs
->handles
[index
] == bo
)
474 for (unsigned i
= 0; i
< cs
->num_buffers
; ++i
) {
475 if (cs
->handles
[i
] == bo
) {
476 cs
->buffer_hash_table
[hash
] = i
;
484 static void radv_amdgpu_cs_add_buffer_internal(struct radv_amdgpu_cs
*cs
,
489 int index
= radv_amdgpu_cs_find_buffer(cs
, bo
);
492 cs
->priorities
[index
] = MAX2(cs
->priorities
[index
], priority
);
496 if (cs
->num_buffers
== cs
->max_num_buffers
) {
497 unsigned new_count
= MAX2(1, cs
->max_num_buffers
* 2);
498 cs
->handles
= realloc(cs
->handles
, new_count
* sizeof(amdgpu_bo_handle
));
499 cs
->priorities
= realloc(cs
->priorities
, new_count
* sizeof(uint8_t));
500 cs
->max_num_buffers
= new_count
;
503 cs
->handles
[cs
->num_buffers
] = bo
;
504 cs
->priorities
[cs
->num_buffers
] = priority
;
506 hash
= ((uintptr_t)bo
>> 6) & (ARRAY_SIZE(cs
->buffer_hash_table
) - 1);
507 cs
->buffer_hash_table
[hash
] = cs
->num_buffers
;
512 static void radv_amdgpu_cs_add_virtual_buffer(struct radeon_winsys_cs
*_cs
,
513 struct radeon_winsys_bo
*bo
,
516 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(_cs
);
517 unsigned hash
= ((uintptr_t)bo
>> 6) & (VIRTUAL_BUFFER_HASH_TABLE_SIZE
- 1);
520 if (!cs
->virtual_buffer_hash_table
) {
521 cs
->virtual_buffer_hash_table
= malloc(VIRTUAL_BUFFER_HASH_TABLE_SIZE
* sizeof(int));
522 for (int i
= 0; i
< VIRTUAL_BUFFER_HASH_TABLE_SIZE
; ++i
)
523 cs
->virtual_buffer_hash_table
[i
] = -1;
526 if (cs
->virtual_buffer_hash_table
[hash
] >= 0) {
527 int idx
= cs
->virtual_buffer_hash_table
[hash
];
528 if (cs
->virtual_buffers
[idx
] == bo
) {
529 cs
->virtual_buffer_priorities
[idx
] = MAX2(cs
->virtual_buffer_priorities
[idx
], priority
);
532 for (unsigned i
= 0; i
< cs
->num_virtual_buffers
; ++i
) {
533 if (cs
->virtual_buffers
[i
] == bo
) {
534 cs
->virtual_buffer_priorities
[i
] = MAX2(cs
->virtual_buffer_priorities
[i
], priority
);
535 cs
->virtual_buffer_hash_table
[hash
] = i
;
541 if(cs
->max_num_virtual_buffers
<= cs
->num_virtual_buffers
) {
542 cs
->max_num_virtual_buffers
= MAX2(2, cs
->max_num_virtual_buffers
* 2);
543 cs
->virtual_buffers
= realloc(cs
->virtual_buffers
, sizeof(struct radv_amdgpu_virtual_virtual_buffer
*) * cs
->max_num_virtual_buffers
);
544 cs
->virtual_buffer_priorities
= realloc(cs
->virtual_buffer_priorities
, sizeof(uint8_t) * cs
->max_num_virtual_buffers
);
547 cs
->virtual_buffers
[cs
->num_virtual_buffers
] = bo
;
548 cs
->virtual_buffer_priorities
[cs
->num_virtual_buffers
] = priority
;
550 cs
->virtual_buffer_hash_table
[hash
] = cs
->num_virtual_buffers
;
551 ++cs
->num_virtual_buffers
;
555 static void radv_amdgpu_cs_add_buffer(struct radeon_winsys_cs
*_cs
,
556 struct radeon_winsys_bo
*_bo
,
559 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(_cs
);
560 struct radv_amdgpu_winsys_bo
*bo
= radv_amdgpu_winsys_bo(_bo
);
562 if (bo
->is_virtual
) {
563 radv_amdgpu_cs_add_virtual_buffer(_cs
, _bo
, priority
);
567 if (bo
->base
.is_local
)
570 radv_amdgpu_cs_add_buffer_internal(cs
, bo
->bo
, priority
);
573 static void radv_amdgpu_cs_execute_secondary(struct radeon_winsys_cs
*_parent
,
574 struct radeon_winsys_cs
*_child
)
576 struct radv_amdgpu_cs
*parent
= radv_amdgpu_cs(_parent
);
577 struct radv_amdgpu_cs
*child
= radv_amdgpu_cs(_child
);
579 for (unsigned i
= 0; i
< child
->num_buffers
; ++i
) {
580 radv_amdgpu_cs_add_buffer_internal(parent
, child
->handles
[i
],
581 child
->priorities
[i
]);
584 for (unsigned i
= 0; i
< child
->num_virtual_buffers
; ++i
) {
585 radv_amdgpu_cs_add_buffer(&parent
->base
, child
->virtual_buffers
[i
],
586 child
->virtual_buffer_priorities
[i
]);
589 if (parent
->ws
->use_ib_bos
) {
590 if (parent
->base
.cdw
+ 4 > parent
->base
.max_dw
)
591 radv_amdgpu_cs_grow(&parent
->base
, 4);
593 parent
->base
.buf
[parent
->base
.cdw
++] = PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0);
594 parent
->base
.buf
[parent
->base
.cdw
++] = child
->ib
.ib_mc_address
;
595 parent
->base
.buf
[parent
->base
.cdw
++] = child
->ib
.ib_mc_address
>> 32;
596 parent
->base
.buf
[parent
->base
.cdw
++] = child
->ib
.size
;
598 if (parent
->base
.cdw
+ child
->base
.cdw
> parent
->base
.max_dw
)
599 radv_amdgpu_cs_grow(&parent
->base
, child
->base
.cdw
);
601 memcpy(parent
->base
.buf
+ parent
->base
.cdw
, child
->base
.buf
, 4 * child
->base
.cdw
);
602 parent
->base
.cdw
+= child
->base
.cdw
;
606 static int radv_amdgpu_create_bo_list(struct radv_amdgpu_winsys
*ws
,
607 struct radeon_winsys_cs
**cs_array
,
609 struct radv_amdgpu_winsys_bo
**extra_bo_array
,
610 unsigned num_extra_bo
,
611 struct radeon_winsys_cs
*extra_cs
,
612 const struct radv_winsys_bo_list
*radv_bo_list
,
613 amdgpu_bo_list_handle
*bo_list
)
617 if (ws
->debug_all_bos
) {
618 struct radv_amdgpu_winsys_bo
*bo
;
619 amdgpu_bo_handle
*handles
;
622 pthread_mutex_lock(&ws
->global_bo_list_lock
);
624 handles
= malloc(sizeof(handles
[0]) * ws
->num_buffers
);
626 pthread_mutex_unlock(&ws
->global_bo_list_lock
);
630 LIST_FOR_EACH_ENTRY(bo
, &ws
->global_bo_list
, global_list_item
) {
631 assert(num
< ws
->num_buffers
);
632 handles
[num
++] = bo
->bo
;
635 r
= amdgpu_bo_list_create(ws
->dev
, ws
->num_buffers
,
639 pthread_mutex_unlock(&ws
->global_bo_list_lock
);
640 } else if (count
== 1 && !num_extra_bo
&& !extra_cs
&& !radv_bo_list
&&
641 !radv_amdgpu_cs(cs_array
[0])->num_virtual_buffers
) {
642 struct radv_amdgpu_cs
*cs
= (struct radv_amdgpu_cs
*)cs_array
[0];
643 if (cs
->num_buffers
== 0) {
647 r
= amdgpu_bo_list_create(ws
->dev
, cs
->num_buffers
, cs
->handles
,
648 cs
->priorities
, bo_list
);
650 unsigned total_buffer_count
= num_extra_bo
;
651 unsigned unique_bo_count
= num_extra_bo
;
652 for (unsigned i
= 0; i
< count
; ++i
) {
653 struct radv_amdgpu_cs
*cs
= (struct radv_amdgpu_cs
*)cs_array
[i
];
654 total_buffer_count
+= cs
->num_buffers
;
655 for (unsigned j
= 0; j
< cs
->num_virtual_buffers
; ++j
)
656 total_buffer_count
+= radv_amdgpu_winsys_bo(cs
->virtual_buffers
[j
])->bo_count
;
660 total_buffer_count
+= ((struct radv_amdgpu_cs
*)extra_cs
)->num_buffers
;
664 total_buffer_count
+= radv_bo_list
->count
;
667 if (total_buffer_count
== 0) {
671 amdgpu_bo_handle
*handles
= malloc(sizeof(amdgpu_bo_handle
) * total_buffer_count
);
672 uint8_t *priorities
= malloc(sizeof(uint8_t) * total_buffer_count
);
673 if (!handles
|| !priorities
) {
679 for (unsigned i
= 0; i
< num_extra_bo
; i
++) {
680 handles
[i
] = extra_bo_array
[i
]->bo
;
684 for (unsigned i
= 0; i
< count
+ !!extra_cs
; ++i
) {
685 struct radv_amdgpu_cs
*cs
;
688 cs
= (struct radv_amdgpu_cs
*)extra_cs
;
690 cs
= (struct radv_amdgpu_cs
*)cs_array
[i
];
692 if (!cs
->num_buffers
)
695 if (unique_bo_count
== 0) {
696 memcpy(handles
, cs
->handles
, cs
->num_buffers
* sizeof(amdgpu_bo_handle
));
697 memcpy(priorities
, cs
->priorities
, cs
->num_buffers
* sizeof(uint8_t));
698 unique_bo_count
= cs
->num_buffers
;
701 int unique_bo_so_far
= unique_bo_count
;
702 for (unsigned j
= 0; j
< cs
->num_buffers
; ++j
) {
704 for (unsigned k
= 0; k
< unique_bo_so_far
; ++k
) {
705 if (handles
[k
] == cs
->handles
[j
]) {
707 priorities
[k
] = MAX2(priorities
[k
],
713 handles
[unique_bo_count
] = cs
->handles
[j
];
714 priorities
[unique_bo_count
] = cs
->priorities
[j
];
718 for (unsigned j
= 0; j
< cs
->num_virtual_buffers
; ++j
) {
719 struct radv_amdgpu_winsys_bo
*virtual_bo
= radv_amdgpu_winsys_bo(cs
->virtual_buffers
[j
]);
720 for(unsigned k
= 0; k
< virtual_bo
->bo_count
; ++k
) {
721 struct radv_amdgpu_winsys_bo
*bo
= virtual_bo
->bos
[k
];
723 for (unsigned m
= 0; m
< unique_bo_count
; ++m
) {
724 if (handles
[m
] == bo
->bo
) {
726 priorities
[m
] = MAX2(priorities
[m
],
727 cs
->virtual_buffer_priorities
[j
]);
732 handles
[unique_bo_count
] = bo
->bo
;
733 priorities
[unique_bo_count
] = cs
->virtual_buffer_priorities
[j
];
741 unsigned unique_bo_so_far
= unique_bo_count
;
742 const unsigned default_bo_priority
= 7;
743 for (unsigned i
= 0; i
< radv_bo_list
->count
; ++i
) {
744 struct radv_amdgpu_winsys_bo
*bo
= radv_amdgpu_winsys_bo(radv_bo_list
->bos
[i
]);
746 for (unsigned j
= 0; j
< unique_bo_so_far
; ++j
) {
747 if (bo
->bo
== handles
[j
]) {
749 priorities
[j
] = MAX2(priorities
[j
], default_bo_priority
);
754 handles
[unique_bo_count
] = bo
->bo
;
755 priorities
[unique_bo_count
] = default_bo_priority
;
761 if (unique_bo_count
> 0) {
762 r
= amdgpu_bo_list_create(ws
->dev
, unique_bo_count
, handles
,
763 priorities
, bo_list
);
775 static struct amdgpu_cs_fence_info
radv_set_cs_fence(struct radv_amdgpu_ctx
*ctx
, int ip_type
, int ring
)
777 struct amdgpu_cs_fence_info ret
= {0};
778 if (ctx
->fence_map
) {
779 ret
.handle
= radv_amdgpu_winsys_bo(ctx
->fence_bo
)->bo
;
780 ret
.offset
= (ip_type
* MAX_RINGS_PER_TYPE
+ ring
) * sizeof(uint64_t);
785 static void radv_assign_last_submit(struct radv_amdgpu_ctx
*ctx
,
786 struct amdgpu_cs_request
*request
)
788 radv_amdgpu_request_to_fence(ctx
,
789 &ctx
->last_submission
[request
->ip_type
][request
->ring
],
793 static int radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx
*_ctx
,
795 struct radv_winsys_sem_info
*sem_info
,
796 const struct radv_winsys_bo_list
*radv_bo_list
,
797 struct radeon_winsys_cs
**cs_array
,
799 struct radeon_winsys_cs
*initial_preamble_cs
,
800 struct radeon_winsys_cs
*continue_preamble_cs
,
801 struct radeon_winsys_fence
*_fence
)
804 struct radv_amdgpu_ctx
*ctx
= radv_amdgpu_ctx(_ctx
);
805 struct radv_amdgpu_fence
*fence
= (struct radv_amdgpu_fence
*)_fence
;
806 struct radv_amdgpu_cs
*cs0
= radv_amdgpu_cs(cs_array
[0]);
807 amdgpu_bo_list_handle bo_list
;
808 struct amdgpu_cs_request request
= {0};
809 struct amdgpu_cs_ib_info ibs
[2];
811 for (unsigned i
= cs_count
; i
--;) {
812 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(cs_array
[i
]);
814 if (cs
->is_chained
) {
815 *cs
->ib_size_ptr
-= 4;
816 cs
->is_chained
= false;
819 if (i
+ 1 < cs_count
) {
820 struct radv_amdgpu_cs
*next
= radv_amdgpu_cs(cs_array
[i
+ 1]);
821 assert(cs
->base
.cdw
+ 4 <= cs
->base
.max_dw
);
823 cs
->is_chained
= true;
824 *cs
->ib_size_ptr
+= 4;
826 cs
->base
.buf
[cs
->base
.cdw
+ 0] = PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0);
827 cs
->base
.buf
[cs
->base
.cdw
+ 1] = next
->ib
.ib_mc_address
;
828 cs
->base
.buf
[cs
->base
.cdw
+ 2] = next
->ib
.ib_mc_address
>> 32;
829 cs
->base
.buf
[cs
->base
.cdw
+ 3] = S_3F2_CHAIN(1) | S_3F2_VALID(1) | next
->ib
.size
;
833 r
= radv_amdgpu_create_bo_list(cs0
->ws
, cs_array
, cs_count
, NULL
, 0, initial_preamble_cs
,
834 radv_bo_list
, &bo_list
);
836 fprintf(stderr
, "amdgpu: buffer list creation failed for the "
837 "chained submission(%d)\n", r
);
841 request
.ip_type
= cs0
->hw_ip
;
842 request
.ring
= queue_idx
;
843 request
.number_of_ibs
= 1;
844 request
.ibs
= &cs0
->ib
;
845 request
.resources
= bo_list
;
846 request
.fence_info
= radv_set_cs_fence(ctx
, cs0
->hw_ip
, queue_idx
);
848 if (initial_preamble_cs
) {
850 request
.number_of_ibs
= 2;
852 ibs
[0] = ((struct radv_amdgpu_cs
*)initial_preamble_cs
)->ib
;
855 r
= radv_amdgpu_cs_submit(ctx
, &request
, sem_info
);
858 fprintf(stderr
, "amdgpu: Not enough memory for command submission.\n");
860 fprintf(stderr
, "amdgpu: The CS has been rejected, "
861 "see dmesg for more information.\n");
865 amdgpu_bo_list_destroy(bo_list
);
868 radv_amdgpu_request_to_fence(ctx
, fence
, &request
);
870 radv_assign_last_submit(ctx
, &request
);
875 static int radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx
*_ctx
,
877 struct radv_winsys_sem_info
*sem_info
,
878 const struct radv_winsys_bo_list
*radv_bo_list
,
879 struct radeon_winsys_cs
**cs_array
,
881 struct radeon_winsys_cs
*initial_preamble_cs
,
882 struct radeon_winsys_cs
*continue_preamble_cs
,
883 struct radeon_winsys_fence
*_fence
)
886 struct radv_amdgpu_ctx
*ctx
= radv_amdgpu_ctx(_ctx
);
887 struct radv_amdgpu_fence
*fence
= (struct radv_amdgpu_fence
*)_fence
;
888 amdgpu_bo_list_handle bo_list
;
889 struct amdgpu_cs_request request
;
890 bool emit_signal_sem
= sem_info
->cs_emit_signal
;
893 for (unsigned i
= 0; i
< cs_count
;) {
894 struct radv_amdgpu_cs
*cs0
= radv_amdgpu_cs(cs_array
[i
]);
895 struct amdgpu_cs_ib_info ibs
[AMDGPU_CS_MAX_IBS_PER_SUBMIT
];
896 struct radeon_winsys_cs
*preamble_cs
= i
? continue_preamble_cs
: initial_preamble_cs
;
897 unsigned cnt
= MIN2(AMDGPU_CS_MAX_IBS_PER_SUBMIT
- !!preamble_cs
,
900 memset(&request
, 0, sizeof(request
));
902 r
= radv_amdgpu_create_bo_list(cs0
->ws
, &cs_array
[i
], cnt
, NULL
, 0,
903 preamble_cs
, radv_bo_list
, &bo_list
);
905 fprintf(stderr
, "amdgpu: buffer list creation failed "
906 "for the fallback submission (%d)\n", r
);
910 request
.ip_type
= cs0
->hw_ip
;
911 request
.ring
= queue_idx
;
912 request
.resources
= bo_list
;
913 request
.number_of_ibs
= cnt
+ !!preamble_cs
;
915 request
.fence_info
= radv_set_cs_fence(ctx
, cs0
->hw_ip
, queue_idx
);
918 ibs
[0] = radv_amdgpu_cs(preamble_cs
)->ib
;
921 for (unsigned j
= 0; j
< cnt
; ++j
) {
922 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(cs_array
[i
+ j
]);
923 ibs
[j
+ !!preamble_cs
] = cs
->ib
;
925 if (cs
->is_chained
) {
926 *cs
->ib_size_ptr
-= 4;
927 cs
->is_chained
= false;
931 sem_info
->cs_emit_signal
= (i
== cs_count
- cnt
) ? emit_signal_sem
: false;
932 r
= radv_amdgpu_cs_submit(ctx
, &request
, sem_info
);
935 fprintf(stderr
, "amdgpu: Not enough memory for command submission.\n");
937 fprintf(stderr
, "amdgpu: The CS has been rejected, "
938 "see dmesg for more information.\n");
942 amdgpu_bo_list_destroy(bo_list
);
950 radv_amdgpu_request_to_fence(ctx
, fence
, &request
);
952 radv_assign_last_submit(ctx
, &request
);
957 static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx
*_ctx
,
959 struct radv_winsys_sem_info
*sem_info
,
960 const struct radv_winsys_bo_list
*radv_bo_list
,
961 struct radeon_winsys_cs
**cs_array
,
963 struct radeon_winsys_cs
*initial_preamble_cs
,
964 struct radeon_winsys_cs
*continue_preamble_cs
,
965 struct radeon_winsys_fence
*_fence
)
968 struct radv_amdgpu_ctx
*ctx
= radv_amdgpu_ctx(_ctx
);
969 struct radv_amdgpu_fence
*fence
= (struct radv_amdgpu_fence
*)_fence
;
970 struct radv_amdgpu_cs
*cs0
= radv_amdgpu_cs(cs_array
[0]);
971 struct radeon_winsys
*ws
= (struct radeon_winsys
*)cs0
->ws
;
972 amdgpu_bo_list_handle bo_list
;
973 struct amdgpu_cs_request request
;
974 uint32_t pad_word
= 0xffff1000U
;
975 bool emit_signal_sem
= sem_info
->cs_emit_signal
;
977 if (radv_amdgpu_winsys(ws
)->info
.chip_class
== SI
)
978 pad_word
= 0x80000000;
982 for (unsigned i
= 0; i
< cs_count
;) {
983 struct amdgpu_cs_ib_info ibs
[AMDGPU_CS_MAX_IBS_PER_SUBMIT
] = {0};
984 unsigned number_of_ibs
= 1;
985 struct radeon_winsys_bo
*bos
[AMDGPU_CS_MAX_IBS_PER_SUBMIT
] = {0};
986 struct radeon_winsys_cs
*preamble_cs
= i
? continue_preamble_cs
: initial_preamble_cs
;
987 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(cs_array
[i
]);
991 unsigned pad_words
= 0;
993 if (cs
->num_old_cs_buffers
> 0) {
994 /* Special path when the maximum size in dwords has
995 * been reached because we need to handle more than one
998 unsigned new_cs_count
= cs
->num_old_cs_buffers
+ 1;
999 struct radeon_winsys_cs
*new_cs_array
[AMDGPU_CS_MAX_IBS_PER_SUBMIT
];
1002 for (unsigned j
= 0; j
< cs
->num_old_cs_buffers
; j
++)
1003 new_cs_array
[idx
++] = &cs
->old_cs_buffers
[j
];
1004 new_cs_array
[idx
++] = cs_array
[i
];
1006 for (unsigned j
= 0; j
< new_cs_count
; j
++) {
1007 struct radeon_winsys_cs
*rcs
= new_cs_array
[j
];
1008 bool needs_preamble
= preamble_cs
&& j
== 0;
1012 size
+= preamble_cs
->cdw
;
1015 assert(size
< 0xffff8);
1017 while (!size
|| (size
& 7)) {
1022 bos
[j
] = ws
->buffer_create(ws
, 4 * size
, 4096,
1024 RADEON_FLAG_CPU_ACCESS
|
1025 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
1026 RADEON_FLAG_READ_ONLY
);
1027 ptr
= ws
->buffer_map(bos
[j
]);
1029 if (needs_preamble
) {
1030 memcpy(ptr
, preamble_cs
->buf
, preamble_cs
->cdw
* 4);
1031 ptr
+= preamble_cs
->cdw
;
1034 memcpy(ptr
, rcs
->buf
, 4 * rcs
->cdw
);
1037 for (unsigned k
= 0; k
< pad_words
; ++k
)
1041 ibs
[j
].ib_mc_address
= radv_buffer_get_va(bos
[j
]);
1044 number_of_ibs
= new_cs_count
;
1048 size
+= preamble_cs
->cdw
;
1050 while (i
+ cnt
< cs_count
&& 0xffff8 - size
>= radv_amdgpu_cs(cs_array
[i
+ cnt
])->base
.cdw
) {
1051 size
+= radv_amdgpu_cs(cs_array
[i
+ cnt
])->base
.cdw
;
1055 while (!size
|| (size
& 7)) {
1061 bos
[0] = ws
->buffer_create(ws
, 4 * size
, 4096,
1063 RADEON_FLAG_CPU_ACCESS
|
1064 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
1065 RADEON_FLAG_READ_ONLY
);
1066 ptr
= ws
->buffer_map(bos
[0]);
1069 memcpy(ptr
, preamble_cs
->buf
, preamble_cs
->cdw
* 4);
1070 ptr
+= preamble_cs
->cdw
;
1073 for (unsigned j
= 0; j
< cnt
; ++j
) {
1074 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(cs_array
[i
+ j
]);
1075 memcpy(ptr
, cs
->base
.buf
, 4 * cs
->base
.cdw
);
1076 ptr
+= cs
->base
.cdw
;
1080 for (unsigned j
= 0; j
< pad_words
; ++j
)
1084 ibs
[0].ib_mc_address
= radv_buffer_get_va(bos
[0]);
1087 r
= radv_amdgpu_create_bo_list(cs0
->ws
, &cs_array
[i
], cnt
,
1088 (struct radv_amdgpu_winsys_bo
**)bos
,
1089 number_of_ibs
, preamble_cs
,
1090 radv_bo_list
, &bo_list
);
1092 fprintf(stderr
, "amdgpu: buffer list creation failed "
1093 "for the sysmem submission (%d)\n", r
);
1097 memset(&request
, 0, sizeof(request
));
1099 request
.ip_type
= cs0
->hw_ip
;
1100 request
.ring
= queue_idx
;
1101 request
.resources
= bo_list
;
1102 request
.number_of_ibs
= number_of_ibs
;
1104 request
.fence_info
= radv_set_cs_fence(ctx
, cs0
->hw_ip
, queue_idx
);
1106 sem_info
->cs_emit_signal
= (i
== cs_count
- cnt
) ? emit_signal_sem
: false;
1107 r
= radv_amdgpu_cs_submit(ctx
, &request
, sem_info
);
1110 fprintf(stderr
, "amdgpu: Not enough memory for command submission.\n");
1112 fprintf(stderr
, "amdgpu: The CS has been rejected, "
1113 "see dmesg for more information.\n");
1117 amdgpu_bo_list_destroy(bo_list
);
1119 for (unsigned j
= 0; j
< number_of_ibs
; j
++) {
1120 ws
->buffer_destroy(bos
[j
]);
1128 radv_amdgpu_request_to_fence(ctx
, fence
, &request
);
1130 radv_assign_last_submit(ctx
, &request
);
1135 static int radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx
*_ctx
,
1137 struct radeon_winsys_cs
**cs_array
,
1139 struct radeon_winsys_cs
*initial_preamble_cs
,
1140 struct radeon_winsys_cs
*continue_preamble_cs
,
1141 struct radv_winsys_sem_info
*sem_info
,
1142 const struct radv_winsys_bo_list
*bo_list
,
1144 struct radeon_winsys_fence
*_fence
)
1146 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(cs_array
[0]);
1147 struct radv_amdgpu_ctx
*ctx
= radv_amdgpu_ctx(_ctx
);
1151 if (!cs
->ws
->use_ib_bos
) {
1152 ret
= radv_amdgpu_winsys_cs_submit_sysmem(_ctx
, queue_idx
, sem_info
, bo_list
, cs_array
,
1153 cs_count
, initial_preamble_cs
, continue_preamble_cs
, _fence
);
1154 } else if (can_patch
&& cs_count
> AMDGPU_CS_MAX_IBS_PER_SUBMIT
&& cs
->ws
->batchchain
) {
1155 ret
= radv_amdgpu_winsys_cs_submit_chained(_ctx
, queue_idx
, sem_info
, bo_list
, cs_array
,
1156 cs_count
, initial_preamble_cs
, continue_preamble_cs
, _fence
);
1158 ret
= radv_amdgpu_winsys_cs_submit_fallback(_ctx
, queue_idx
, sem_info
, bo_list
, cs_array
,
1159 cs_count
, initial_preamble_cs
, continue_preamble_cs
, _fence
);
1162 radv_amdgpu_signal_sems(ctx
, cs
->hw_ip
, queue_idx
, sem_info
);
1166 static void *radv_amdgpu_winsys_get_cpu_addr(void *_cs
, uint64_t addr
)
1168 struct radv_amdgpu_cs
*cs
= (struct radv_amdgpu_cs
*)_cs
;
1173 for (unsigned i
= 0; i
<= cs
->num_old_ib_buffers
; ++i
) {
1174 struct radv_amdgpu_winsys_bo
*bo
;
1176 bo
= (struct radv_amdgpu_winsys_bo
*)
1177 (i
== cs
->num_old_ib_buffers
? cs
->ib_buffer
: cs
->old_ib_buffers
[i
]);
1178 if (addr
>= bo
->base
.va
&& addr
- bo
->base
.va
< bo
->size
) {
1179 if (amdgpu_bo_cpu_map(bo
->bo
, &ret
) == 0)
1180 return (char *)ret
+ (addr
- bo
->base
.va
);
1183 if(cs
->ws
->debug_all_bos
) {
1184 pthread_mutex_lock(&cs
->ws
->global_bo_list_lock
);
1185 list_for_each_entry(struct radv_amdgpu_winsys_bo
, bo
,
1186 &cs
->ws
->global_bo_list
, global_list_item
) {
1187 if (addr
>= bo
->base
.va
&& addr
- bo
->base
.va
< bo
->size
) {
1188 if (amdgpu_bo_cpu_map(bo
->bo
, &ret
) == 0) {
1189 pthread_mutex_unlock(&cs
->ws
->global_bo_list_lock
);
1190 return (char *)ret
+ (addr
- bo
->base
.va
);
1194 pthread_mutex_unlock(&cs
->ws
->global_bo_list_lock
);
1199 static void radv_amdgpu_winsys_cs_dump(struct radeon_winsys_cs
*_cs
,
1201 const int *trace_ids
, int trace_id_count
)
1203 struct radv_amdgpu_cs
*cs
= (struct radv_amdgpu_cs
*)_cs
;
1204 void *ib
= cs
->base
.buf
;
1205 int num_dw
= cs
->base
.cdw
;
1207 if (cs
->ws
->use_ib_bos
) {
1208 ib
= radv_amdgpu_winsys_get_cpu_addr(cs
, cs
->ib
.ib_mc_address
);
1209 num_dw
= cs
->ib
.size
;
1212 ac_parse_ib(file
, ib
, num_dw
, trace_ids
, trace_id_count
, "main IB",
1213 cs
->ws
->info
.chip_class
, radv_amdgpu_winsys_get_cpu_addr
, cs
);
1216 static uint32_t radv_to_amdgpu_priority(enum radeon_ctx_priority radv_priority
)
1218 switch (radv_priority
) {
1219 case RADEON_CTX_PRIORITY_REALTIME
:
1220 return AMDGPU_CTX_PRIORITY_VERY_HIGH
;
1221 case RADEON_CTX_PRIORITY_HIGH
:
1222 return AMDGPU_CTX_PRIORITY_HIGH
;
1223 case RADEON_CTX_PRIORITY_MEDIUM
:
1224 return AMDGPU_CTX_PRIORITY_NORMAL
;
1225 case RADEON_CTX_PRIORITY_LOW
:
1226 return AMDGPU_CTX_PRIORITY_LOW
;
1228 unreachable("Invalid context priority");
1232 static struct radeon_winsys_ctx
*radv_amdgpu_ctx_create(struct radeon_winsys
*_ws
,
1233 enum radeon_ctx_priority priority
)
1235 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1236 struct radv_amdgpu_ctx
*ctx
= CALLOC_STRUCT(radv_amdgpu_ctx
);
1237 uint32_t amdgpu_priority
= radv_to_amdgpu_priority(priority
);
1243 r
= amdgpu_cs_ctx_create2(ws
->dev
, amdgpu_priority
, &ctx
->ctx
);
1245 fprintf(stderr
, "amdgpu: radv_amdgpu_cs_ctx_create2 failed. (%i)\n", r
);
1250 assert(AMDGPU_HW_IP_NUM
* MAX_RINGS_PER_TYPE
* sizeof(uint64_t) <= 4096);
1251 ctx
->fence_bo
= ws
->base
.buffer_create(&ws
->base
, 4096, 8,
1253 RADEON_FLAG_CPU_ACCESS
|
1254 RADEON_FLAG_NO_INTERPROCESS_SHARING
);
1256 ctx
->fence_map
= (uint64_t*)ws
->base
.buffer_map(ctx
->fence_bo
);
1258 memset(ctx
->fence_map
, 0, 4096);
1259 return (struct radeon_winsys_ctx
*)ctx
;
1265 static void radv_amdgpu_ctx_destroy(struct radeon_winsys_ctx
*rwctx
)
1267 struct radv_amdgpu_ctx
*ctx
= (struct radv_amdgpu_ctx
*)rwctx
;
1268 ctx
->ws
->base
.buffer_destroy(ctx
->fence_bo
);
1269 amdgpu_cs_ctx_free(ctx
->ctx
);
1273 static bool radv_amdgpu_ctx_wait_idle(struct radeon_winsys_ctx
*rwctx
,
1274 enum ring_type ring_type
, int ring_index
)
1276 struct radv_amdgpu_ctx
*ctx
= (struct radv_amdgpu_ctx
*)rwctx
;
1277 int ip_type
= ring_to_hw_ip(ring_type
);
1279 if (ctx
->last_submission
[ip_type
][ring_index
].fence
.fence
) {
1281 int ret
= amdgpu_cs_query_fence_status(&ctx
->last_submission
[ip_type
][ring_index
].fence
,
1282 1000000000ull, 0, &expired
);
1284 if (ret
|| !expired
)
1291 static struct radeon_winsys_sem
*radv_amdgpu_create_sem(struct radeon_winsys
*_ws
)
1293 struct amdgpu_cs_fence
*sem
= CALLOC_STRUCT(amdgpu_cs_fence
);
1297 return (struct radeon_winsys_sem
*)sem
;
1300 static void radv_amdgpu_destroy_sem(struct radeon_winsys_sem
*_sem
)
1302 struct amdgpu_cs_fence
*sem
= (struct amdgpu_cs_fence
*)_sem
;
1306 static int radv_amdgpu_signal_sems(struct radv_amdgpu_ctx
*ctx
,
1309 struct radv_winsys_sem_info
*sem_info
)
1311 for (unsigned i
= 0; i
< sem_info
->signal
.sem_count
; i
++) {
1312 struct amdgpu_cs_fence
*sem
= (struct amdgpu_cs_fence
*)(sem_info
->signal
.sem
)[i
];
1317 *sem
= ctx
->last_submission
[ip_type
][ring
].fence
;
1322 static struct drm_amdgpu_cs_chunk_sem
*radv_amdgpu_cs_alloc_syncobj_chunk(struct radv_winsys_sem_counts
*counts
,
1323 struct drm_amdgpu_cs_chunk
*chunk
, int chunk_id
)
1325 struct drm_amdgpu_cs_chunk_sem
*syncobj
= malloc(sizeof(struct drm_amdgpu_cs_chunk_sem
) * counts
->syncobj_count
);
1329 for (unsigned i
= 0; i
< counts
->syncobj_count
; i
++) {
1330 struct drm_amdgpu_cs_chunk_sem
*sem
= &syncobj
[i
];
1331 sem
->handle
= counts
->syncobj
[i
];
1334 chunk
->chunk_id
= chunk_id
;
1335 chunk
->length_dw
= sizeof(struct drm_amdgpu_cs_chunk_sem
) / 4 * counts
->syncobj_count
;
1336 chunk
->chunk_data
= (uint64_t)(uintptr_t)syncobj
;
1340 static int radv_amdgpu_cs_submit(struct radv_amdgpu_ctx
*ctx
,
1341 struct amdgpu_cs_request
*request
,
1342 struct radv_winsys_sem_info
*sem_info
)
1348 struct drm_amdgpu_cs_chunk
*chunks
;
1349 struct drm_amdgpu_cs_chunk_data
*chunk_data
;
1350 struct drm_amdgpu_cs_chunk_dep
*sem_dependencies
= NULL
;
1351 struct drm_amdgpu_cs_chunk_sem
*wait_syncobj
= NULL
, *signal_syncobj
= NULL
;
1353 struct amdgpu_cs_fence
*sem
;
1355 user_fence
= (request
->fence_info
.handle
!= NULL
);
1356 size
= request
->number_of_ibs
+ (user_fence
? 2 : 1) + 3;
1358 chunks
= alloca(sizeof(struct drm_amdgpu_cs_chunk
) * size
);
1360 size
= request
->number_of_ibs
+ (user_fence
? 1 : 0);
1362 chunk_data
= alloca(sizeof(struct drm_amdgpu_cs_chunk_data
) * size
);
1364 num_chunks
= request
->number_of_ibs
;
1365 for (i
= 0; i
< request
->number_of_ibs
; i
++) {
1366 struct amdgpu_cs_ib_info
*ib
;
1367 chunks
[i
].chunk_id
= AMDGPU_CHUNK_ID_IB
;
1368 chunks
[i
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_ib
) / 4;
1369 chunks
[i
].chunk_data
= (uint64_t)(uintptr_t)&chunk_data
[i
];
1371 ib
= &request
->ibs
[i
];
1373 chunk_data
[i
].ib_data
._pad
= 0;
1374 chunk_data
[i
].ib_data
.va_start
= ib
->ib_mc_address
;
1375 chunk_data
[i
].ib_data
.ib_bytes
= ib
->size
* 4;
1376 chunk_data
[i
].ib_data
.ip_type
= request
->ip_type
;
1377 chunk_data
[i
].ib_data
.ip_instance
= request
->ip_instance
;
1378 chunk_data
[i
].ib_data
.ring
= request
->ring
;
1379 chunk_data
[i
].ib_data
.flags
= ib
->flags
;
1385 chunks
[i
].chunk_id
= AMDGPU_CHUNK_ID_FENCE
;
1386 chunks
[i
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_fence
) / 4;
1387 chunks
[i
].chunk_data
= (uint64_t)(uintptr_t)&chunk_data
[i
];
1389 amdgpu_cs_chunk_fence_info_to_data(&request
->fence_info
,
1393 if (sem_info
->wait
.syncobj_count
&& sem_info
->cs_emit_wait
) {
1394 wait_syncobj
= radv_amdgpu_cs_alloc_syncobj_chunk(&sem_info
->wait
,
1395 &chunks
[num_chunks
],
1396 AMDGPU_CHUNK_ID_SYNCOBJ_IN
);
1397 if (!wait_syncobj
) {
1403 if (sem_info
->wait
.sem_count
== 0)
1404 sem_info
->cs_emit_wait
= false;
1408 if (sem_info
->wait
.sem_count
&& sem_info
->cs_emit_wait
) {
1409 sem_dependencies
= malloc(sizeof(struct drm_amdgpu_cs_chunk_dep
) * sem_info
->wait
.sem_count
);
1410 if (!sem_dependencies
) {
1415 for (unsigned j
= 0; j
< sem_info
->wait
.sem_count
; j
++) {
1416 sem
= (struct amdgpu_cs_fence
*)sem_info
->wait
.sem
[j
];
1419 struct drm_amdgpu_cs_chunk_dep
*dep
= &sem_dependencies
[sem_count
++];
1421 amdgpu_cs_chunk_fence_to_dep(sem
, dep
);
1423 sem
->context
= NULL
;
1427 /* dependencies chunk */
1428 chunks
[i
].chunk_id
= AMDGPU_CHUNK_ID_DEPENDENCIES
;
1429 chunks
[i
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_dep
) / 4 * sem_count
;
1430 chunks
[i
].chunk_data
= (uint64_t)(uintptr_t)sem_dependencies
;
1432 sem_info
->cs_emit_wait
= false;
1435 if (sem_info
->signal
.syncobj_count
&& sem_info
->cs_emit_signal
) {
1436 signal_syncobj
= radv_amdgpu_cs_alloc_syncobj_chunk(&sem_info
->signal
,
1437 &chunks
[num_chunks
],
1438 AMDGPU_CHUNK_ID_SYNCOBJ_OUT
);
1439 if (!signal_syncobj
) {
1446 r
= amdgpu_cs_submit_raw(ctx
->ws
->dev
,
1453 free(sem_dependencies
);
1455 free(signal_syncobj
);
1459 static int radv_amdgpu_create_syncobj(struct radeon_winsys
*_ws
,
1462 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1463 return amdgpu_cs_create_syncobj(ws
->dev
, handle
);
1466 static void radv_amdgpu_destroy_syncobj(struct radeon_winsys
*_ws
,
1469 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1470 amdgpu_cs_destroy_syncobj(ws
->dev
, handle
);
1473 static void radv_amdgpu_reset_syncobj(struct radeon_winsys
*_ws
,
1476 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1477 amdgpu_cs_syncobj_reset(ws
->dev
, &handle
, 1);
1480 static void radv_amdgpu_signal_syncobj(struct radeon_winsys
*_ws
,
1483 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1484 amdgpu_cs_syncobj_signal(ws
->dev
, &handle
, 1);
1487 static bool radv_amdgpu_wait_syncobj(struct radeon_winsys
*_ws
, const uint32_t *handles
,
1488 uint32_t handle_count
, bool wait_all
, uint64_t timeout
)
1490 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1493 /* The timeouts are signed, while vulkan timeouts are unsigned. */
1494 timeout
= MIN2(timeout
, INT64_MAX
);
1496 int ret
= amdgpu_cs_syncobj_wait(ws
->dev
, (uint32_t*)handles
, handle_count
, timeout
,
1497 DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT
|
1498 (wait_all
? DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL
: 0),
1502 } else if (ret
== -1 && errno
== ETIME
) {
1505 fprintf(stderr
, "amdgpu: radv_amdgpu_wait_syncobj failed!\nerrno: %d\n", errno
);
1510 static int radv_amdgpu_export_syncobj(struct radeon_winsys
*_ws
,
1514 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1516 return amdgpu_cs_export_syncobj(ws
->dev
, syncobj
, fd
);
1519 static int radv_amdgpu_import_syncobj(struct radeon_winsys
*_ws
,
1523 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1525 return amdgpu_cs_import_syncobj(ws
->dev
, fd
, syncobj
);
1529 static int radv_amdgpu_export_syncobj_to_sync_file(struct radeon_winsys
*_ws
,
1533 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1535 return amdgpu_cs_syncobj_export_sync_file(ws
->dev
, syncobj
, fd
);
1538 static int radv_amdgpu_import_syncobj_from_sync_file(struct radeon_winsys
*_ws
,
1542 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1544 return amdgpu_cs_syncobj_import_sync_file(ws
->dev
, syncobj
, fd
);
1547 void radv_amdgpu_cs_init_functions(struct radv_amdgpu_winsys
*ws
)
1549 ws
->base
.ctx_create
= radv_amdgpu_ctx_create
;
1550 ws
->base
.ctx_destroy
= radv_amdgpu_ctx_destroy
;
1551 ws
->base
.ctx_wait_idle
= radv_amdgpu_ctx_wait_idle
;
1552 ws
->base
.cs_create
= radv_amdgpu_cs_create
;
1553 ws
->base
.cs_destroy
= radv_amdgpu_cs_destroy
;
1554 ws
->base
.cs_grow
= radv_amdgpu_cs_grow
;
1555 ws
->base
.cs_finalize
= radv_amdgpu_cs_finalize
;
1556 ws
->base
.cs_reset
= radv_amdgpu_cs_reset
;
1557 ws
->base
.cs_add_buffer
= radv_amdgpu_cs_add_buffer
;
1558 ws
->base
.cs_execute_secondary
= radv_amdgpu_cs_execute_secondary
;
1559 ws
->base
.cs_submit
= radv_amdgpu_winsys_cs_submit
;
1560 ws
->base
.cs_dump
= radv_amdgpu_winsys_cs_dump
;
1561 ws
->base
.create_fence
= radv_amdgpu_create_fence
;
1562 ws
->base
.destroy_fence
= radv_amdgpu_destroy_fence
;
1563 ws
->base
.create_sem
= radv_amdgpu_create_sem
;
1564 ws
->base
.destroy_sem
= radv_amdgpu_destroy_sem
;
1565 ws
->base
.create_syncobj
= radv_amdgpu_create_syncobj
;
1566 ws
->base
.destroy_syncobj
= radv_amdgpu_destroy_syncobj
;
1567 ws
->base
.reset_syncobj
= radv_amdgpu_reset_syncobj
;
1568 ws
->base
.signal_syncobj
= radv_amdgpu_signal_syncobj
;
1569 ws
->base
.wait_syncobj
= radv_amdgpu_wait_syncobj
;
1570 ws
->base
.export_syncobj
= radv_amdgpu_export_syncobj
;
1571 ws
->base
.import_syncobj
= radv_amdgpu_import_syncobj
;
1572 ws
->base
.export_syncobj_to_sync_file
= radv_amdgpu_export_syncobj_to_sync_file
;
1573 ws
->base
.import_syncobj_from_sync_file
= radv_amdgpu_import_syncobj_from_sync_file
;
1574 ws
->base
.fence_wait
= radv_amdgpu_fence_wait
;
1575 ws
->base
.fences_wait
= radv_amdgpu_fences_wait
;