amd: rename SIENNA -> SIENNA_CICHLID
[mesa.git] / src / amd / vulkan / winsys / null / radv_null_winsys.c
1 /*
2 * Copyright © 2020 Valve Corporation
3 *
4 * based on amdgpu winsys.
5 * Copyright © 2016 Red Hat.
6 * Copyright © 2016 Bas Nieuwenhuizen
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27 #include "radv_null_winsys_public.h"
28
29 #include "radv_null_bo.h"
30 #include "radv_null_cs.h"
31
32 #include "ac_llvm_util.h"
33
34 /* Hardcode some GPU info that are needed for the driver or for some tools. */
35 static const struct {
36 uint32_t pci_id;
37 uint32_t num_render_backends;
38 } gpu_info[] = {
39 [CHIP_TAHITI] = { 0x6780, 8 },
40 [CHIP_PITCAIRN] = { 0x6800, 8, },
41 [CHIP_VERDE] = { 0x6820, 4 },
42 [CHIP_OLAND] = { 0x6060, 2 },
43 [CHIP_HAINAN] = { 0x6660, 2 },
44 [CHIP_BONAIRE] = { 0x6640, 4 },
45 [CHIP_KAVERI] = { 0x1304, 2 },
46 [CHIP_KABINI] = { 0x9830, 2 },
47 [CHIP_HAWAII] = { 0x67A0, 16 },
48 [CHIP_TONGA] = { 0x6920, 8 },
49 [CHIP_ICELAND] = { 0x6900, 2 },
50 [CHIP_CARRIZO] = { 0x9870, 2 },
51 [CHIP_FIJI] = { 0x7300, 16 },
52 [CHIP_STONEY] = { 0x98E4, 2 },
53 [CHIP_POLARIS10] = { 0x67C0, 8 },
54 [CHIP_POLARIS11] = { 0x67E0, 4 },
55 [CHIP_POLARIS12] = { 0x6980, 4 },
56 [CHIP_VEGAM] = { 0x694C, 4 },
57 [CHIP_VEGA10] = { 0x6860, 16 },
58 [CHIP_VEGA12] = { 0x69A0, 8 },
59 [CHIP_VEGA20] = { 0x66A0, 16 },
60 [CHIP_RAVEN] = { 0x15DD, 2 },
61 [CHIP_RENOIR] = { 0x1636, 2 },
62 [CHIP_ARCTURUS] = { 0x738C, 2 },
63 [CHIP_NAVI10] = { 0x7310, 16 },
64 [CHIP_NAVI12] = { 0x7360, 8 },
65 [CHIP_NAVI14] = { 0x7340, 8 },
66 };
67
68 static void radv_null_winsys_query_info(struct radeon_winsys *rws,
69 struct radeon_info *info)
70 {
71 const char *family = getenv("RADV_FORCE_FAMILY");
72 unsigned i;
73
74 info->chip_class = CLASS_UNKNOWN;
75 info->family = CHIP_UNKNOWN;
76
77 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
78 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
79 /* Override family and chip_class. */
80 info->family = i;
81 info->name = "OVERRIDDEN";
82
83 if (i >= CHIP_SIENNA_CICHLID)
84 info->chip_class = GFX10_3;
85 else if (i >= CHIP_NAVI10)
86 info->chip_class = GFX10;
87 else if (i >= CHIP_VEGA10)
88 info->chip_class = GFX9;
89 else if (i >= CHIP_TONGA)
90 info->chip_class = GFX8;
91 else if (i >= CHIP_BONAIRE)
92 info->chip_class = GFX7;
93 else
94 info->chip_class = GFX6;
95 }
96 }
97
98 if (info->family == CHIP_UNKNOWN) {
99 fprintf(stderr, "radv: Unknown family: %s\n", family);
100 abort();
101 }
102
103 info->pci_id = gpu_info[info->family].pci_id;
104 info->has_syncobj_wait_for_submit = true;
105 info->max_se = 4;
106 if (info->chip_class >= GFX10_3)
107 info->max_wave64_per_simd = 16;
108 else if (info->chip_class >= GFX10)
109 info->max_wave64_per_simd = 20;
110 else if (info->family >= CHIP_POLARIS10 && info->family <= CHIP_VEGAM)
111 info->max_wave64_per_simd = 8;
112 else
113 info->max_wave64_per_simd = 10;
114
115 if (info->chip_class >= GFX10)
116 info->num_physical_sgprs_per_simd = 128 * info->max_wave64_per_simd * 2;
117 else if (info->chip_class >= GFX8)
118 info->num_physical_sgprs_per_simd = 800;
119 else
120 info->num_physical_sgprs_per_simd = 512;
121
122 info->num_physical_wave64_vgprs_per_simd = info->chip_class >= GFX10 ? 512 : 256;
123 info->num_simd_per_compute_unit = info->chip_class >= GFX10 ? 2 : 4;
124 info->lds_size_per_workgroup = info->chip_class >= GFX10 ? 128 * 1024 : 64 * 1024;
125 info->num_render_backends = gpu_info[info->family].num_render_backends;
126 }
127
128 static void radv_null_winsys_destroy(struct radeon_winsys *rws)
129 {
130 FREE(rws);
131 }
132
133 struct radeon_winsys *
134 radv_null_winsys_create()
135 {
136 struct radv_null_winsys *ws;
137
138 ws = calloc(1, sizeof(struct radv_null_winsys));
139 if (!ws)
140 return NULL;
141
142 ws->base.destroy = radv_null_winsys_destroy;
143 ws->base.query_info = radv_null_winsys_query_info;
144 radv_null_bo_init_functions(ws);
145 radv_null_cs_init_functions(ws);
146
147 return &ws->base;
148 }