2 * Copyright © 2016 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "util/format/u_format.h"
26 #include "util/u_helpers.h"
27 #include "util/u_math.h"
28 #include "util/u_memory.h"
29 #include "util/ralloc.h"
30 #include "util/hash_table.h"
31 #include "compiler/nir/nir.h"
32 #include "compiler/nir/nir_builder.h"
33 #include "common/v3d_device_info.h"
34 #include "v3d_compiler.h"
36 /* We don't do any address packing. */
37 #define __gen_user_data void
38 #define __gen_address_type uint32_t
39 #define __gen_address_offset(reloc) (*reloc)
40 #define __gen_emit_reloc(cl, reloc)
41 #include "cle/v3d_packet_v41_pack.h"
43 #define GENERAL_TMU_LOOKUP_PER_QUAD (0 << 7)
44 #define GENERAL_TMU_LOOKUP_PER_PIXEL (1 << 7)
45 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_I (0 << 0)
46 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_I (1 << 0)
47 #define GENERAL_TMU_LOOKUP_TYPE_VEC2 (2 << 0)
48 #define GENERAL_TMU_LOOKUP_TYPE_VEC3 (3 << 0)
49 #define GENERAL_TMU_LOOKUP_TYPE_VEC4 (4 << 0)
50 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_UI (5 << 0)
51 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_UI (6 << 0)
52 #define GENERAL_TMU_LOOKUP_TYPE_32BIT_UI (7 << 0)
54 #define V3D_TSY_SET_QUORUM 0
55 #define V3D_TSY_INC_WAITERS 1
56 #define V3D_TSY_DEC_WAITERS 2
57 #define V3D_TSY_INC_QUORUM 3
58 #define V3D_TSY_DEC_QUORUM 4
59 #define V3D_TSY_FREE_ALL 5
60 #define V3D_TSY_RELEASE 6
61 #define V3D_TSY_ACQUIRE 7
62 #define V3D_TSY_WAIT 8
63 #define V3D_TSY_WAIT_INC 9
64 #define V3D_TSY_WAIT_CHECK 10
65 #define V3D_TSY_WAIT_INC_CHECK 11
66 #define V3D_TSY_WAIT_CV 12
67 #define V3D_TSY_INC_SEMAPHORE 13
68 #define V3D_TSY_DEC_SEMAPHORE 14
69 #define V3D_TSY_SET_QUORUM_FREE_ALL 15
72 ntq_emit_cf_list(struct v3d_compile
*c
, struct exec_list
*list
);
75 resize_qreg_array(struct v3d_compile
*c
,
80 if (*size
>= decl_size
)
83 uint32_t old_size
= *size
;
84 *size
= MAX2(*size
* 2, decl_size
);
85 *regs
= reralloc(c
, *regs
, struct qreg
, *size
);
87 fprintf(stderr
, "Malloc failure\n");
91 for (uint32_t i
= old_size
; i
< *size
; i
++)
92 (*regs
)[i
] = c
->undef
;
96 vir_emit_thrsw(struct v3d_compile
*c
)
101 /* Always thread switch after each texture operation for now.
103 * We could do better by batching a bunch of texture fetches up and
104 * then doing one thread switch and collecting all their results
107 c
->last_thrsw
= vir_NOP(c
);
108 c
->last_thrsw
->qpu
.sig
.thrsw
= true;
109 c
->last_thrsw_at_top_level
= !c
->in_control_flow
;
111 /* We need to lock the scoreboard before any tlb acess happens. If this
112 * thread switch comes after we have emitted a tlb load, then it means
113 * that we can't lock on the last thread switch any more.
115 if (c
->emitted_tlb_load
)
116 c
->lock_scoreboard_on_first_thrsw
= true;
120 v3d_get_op_for_atomic_add(nir_intrinsic_instr
*instr
, unsigned src
)
122 if (nir_src_is_const(instr
->src
[src
])) {
123 int64_t add_val
= nir_src_as_int(instr
->src
[src
]);
125 return V3D_TMU_OP_WRITE_AND_READ_INC
;
126 else if (add_val
== -1)
127 return V3D_TMU_OP_WRITE_OR_READ_DEC
;
130 return V3D_TMU_OP_WRITE_ADD_READ_PREFETCH
;
134 v3d_general_tmu_op(nir_intrinsic_instr
*instr
)
136 switch (instr
->intrinsic
) {
137 case nir_intrinsic_load_ssbo
:
138 case nir_intrinsic_load_ubo
:
139 case nir_intrinsic_load_uniform
:
140 case nir_intrinsic_load_shared
:
141 case nir_intrinsic_load_scratch
:
142 case nir_intrinsic_store_ssbo
:
143 case nir_intrinsic_store_shared
:
144 case nir_intrinsic_store_scratch
:
145 return V3D_TMU_OP_REGULAR
;
146 case nir_intrinsic_ssbo_atomic_add
:
147 return v3d_get_op_for_atomic_add(instr
, 2);
148 case nir_intrinsic_shared_atomic_add
:
149 return v3d_get_op_for_atomic_add(instr
, 1);
150 case nir_intrinsic_ssbo_atomic_imin
:
151 case nir_intrinsic_shared_atomic_imin
:
152 return V3D_TMU_OP_WRITE_SMIN
;
153 case nir_intrinsic_ssbo_atomic_umin
:
154 case nir_intrinsic_shared_atomic_umin
:
155 return V3D_TMU_OP_WRITE_UMIN_FULL_L1_CLEAR
;
156 case nir_intrinsic_ssbo_atomic_imax
:
157 case nir_intrinsic_shared_atomic_imax
:
158 return V3D_TMU_OP_WRITE_SMAX
;
159 case nir_intrinsic_ssbo_atomic_umax
:
160 case nir_intrinsic_shared_atomic_umax
:
161 return V3D_TMU_OP_WRITE_UMAX
;
162 case nir_intrinsic_ssbo_atomic_and
:
163 case nir_intrinsic_shared_atomic_and
:
164 return V3D_TMU_OP_WRITE_AND_READ_INC
;
165 case nir_intrinsic_ssbo_atomic_or
:
166 case nir_intrinsic_shared_atomic_or
:
167 return V3D_TMU_OP_WRITE_OR_READ_DEC
;
168 case nir_intrinsic_ssbo_atomic_xor
:
169 case nir_intrinsic_shared_atomic_xor
:
170 return V3D_TMU_OP_WRITE_XOR_READ_NOT
;
171 case nir_intrinsic_ssbo_atomic_exchange
:
172 case nir_intrinsic_shared_atomic_exchange
:
173 return V3D_TMU_OP_WRITE_XCHG_READ_FLUSH
;
174 case nir_intrinsic_ssbo_atomic_comp_swap
:
175 case nir_intrinsic_shared_atomic_comp_swap
:
176 return V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH
;
178 unreachable("unknown intrinsic op");
183 * Implements indirect uniform loads and SSBO accesses through the TMU general
184 * memory access interface.
187 ntq_emit_tmu_general(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
,
188 bool is_shared_or_scratch
)
190 uint32_t tmu_op
= v3d_general_tmu_op(instr
);
192 /* If we were able to replace atomic_add for an inc/dec, then we
193 * need/can to do things slightly different, like not loading the
194 * amount to add/sub, as that is implicit.
196 bool atomic_add_replaced
=
197 ((instr
->intrinsic
== nir_intrinsic_ssbo_atomic_add
||
198 instr
->intrinsic
== nir_intrinsic_shared_atomic_add
) &&
199 (tmu_op
== V3D_TMU_OP_WRITE_AND_READ_INC
||
200 tmu_op
== V3D_TMU_OP_WRITE_OR_READ_DEC
));
202 bool is_store
= (instr
->intrinsic
== nir_intrinsic_store_ssbo
||
203 instr
->intrinsic
== nir_intrinsic_store_scratch
||
204 instr
->intrinsic
== nir_intrinsic_store_shared
);
206 bool is_load
= (instr
->intrinsic
== nir_intrinsic_load_uniform
||
207 instr
->intrinsic
== nir_intrinsic_load_ubo
||
208 instr
->intrinsic
== nir_intrinsic_load_ssbo
||
209 instr
->intrinsic
== nir_intrinsic_load_scratch
||
210 instr
->intrinsic
== nir_intrinsic_load_shared
);
213 c
->tmu_dirty_rcl
= true;
215 bool has_index
= !is_shared_or_scratch
;
218 if (instr
->intrinsic
== nir_intrinsic_load_uniform
) {
220 } else if (instr
->intrinsic
== nir_intrinsic_load_ssbo
||
221 instr
->intrinsic
== nir_intrinsic_load_ubo
||
222 instr
->intrinsic
== nir_intrinsic_load_scratch
||
223 instr
->intrinsic
== nir_intrinsic_load_shared
||
224 atomic_add_replaced
) {
225 offset_src
= 0 + has_index
;
226 } else if (is_store
) {
227 offset_src
= 1 + has_index
;
229 offset_src
= 0 + has_index
;
232 bool dynamic_src
= !nir_src_is_const(instr
->src
[offset_src
]);
233 uint32_t const_offset
= 0;
235 const_offset
= nir_src_as_uint(instr
->src
[offset_src
]);
237 struct qreg base_offset
;
238 if (instr
->intrinsic
== nir_intrinsic_load_uniform
) {
239 const_offset
+= nir_intrinsic_base(instr
);
240 base_offset
= vir_uniform(c
, QUNIFORM_UBO_ADDR
,
241 v3d_unit_data_create(0, const_offset
));
243 } else if (instr
->intrinsic
== nir_intrinsic_load_ubo
) {
244 uint32_t index
= nir_src_as_uint(instr
->src
[0]) + 1;
245 /* Note that QUNIFORM_UBO_ADDR takes a UBO index shifted up by
246 * 1 (0 is gallium's constant buffer 0).
249 vir_uniform(c
, QUNIFORM_UBO_ADDR
,
250 v3d_unit_data_create(index
, const_offset
));
252 } else if (is_shared_or_scratch
) {
253 /* Shared and scratch variables have no buffer index, and all
254 * start from a common base that we set up at the start of
257 if (instr
->intrinsic
== nir_intrinsic_load_scratch
||
258 instr
->intrinsic
== nir_intrinsic_store_scratch
) {
259 base_offset
= c
->spill_base
;
261 base_offset
= c
->cs_shared_offset
;
262 const_offset
+= nir_intrinsic_base(instr
);
265 base_offset
= vir_uniform(c
, QUNIFORM_SSBO_OFFSET
,
266 nir_src_as_uint(instr
->src
[is_store
?
270 struct qreg tmud
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_TMUD
);
271 unsigned writemask
= is_store
? nir_intrinsic_write_mask(instr
) : 0;
272 uint32_t base_const_offset
= const_offset
;
273 int first_component
= -1;
274 int last_component
= -1;
276 int tmu_writes
= 1; /* address */
279 /* Find the first set of consecutive components that
280 * are enabled in the writemask and emit the TMUD
281 * instructions for them.
283 first_component
= ffs(writemask
) - 1;
284 last_component
= first_component
;
285 while (writemask
& BITFIELD_BIT(last_component
+ 1))
288 assert(first_component
>= 0 &&
289 first_component
<= last_component
&&
290 last_component
< instr
->num_components
);
292 struct qreg tmud
= vir_reg(QFILE_MAGIC
,
294 for (int i
= first_component
; i
<= last_component
; i
++) {
296 ntq_get_src(c
, instr
->src
[0], i
);
297 vir_MOV_dest(c
, tmud
, data
);
301 /* Update the offset for the TMU write based on the
302 * the first component we are writing.
304 const_offset
= base_const_offset
+ first_component
* 4;
306 /* Clear these components from the writemask */
307 uint32_t written_mask
=
308 BITFIELD_RANGE(first_component
, tmu_writes
- 1);
309 writemask
&= ~written_mask
;
310 } else if (!is_load
&& !atomic_add_replaced
) {
312 ntq_get_src(c
, instr
->src
[1 + has_index
], 0);
313 vir_MOV_dest(c
, tmud
, data
);
315 if (tmu_op
== V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH
) {
316 data
= ntq_get_src(c
, instr
->src
[2 + has_index
],
318 vir_MOV_dest(c
, tmud
, data
);
323 /* Make sure we won't exceed the 16-entry TMU fifo if each
324 * thread is storing at the same time.
326 while (tmu_writes
> 16 / c
->threads
)
329 /* The spec says that for atomics, the TYPE field is ignored,
330 * but that doesn't seem to be the case for CMPXCHG. Just use
331 * the number of tmud writes we did to decide the type (or
332 * choose "32bit" for atomic reads, which has been fine).
334 uint32_t num_components
;
335 if (is_load
|| atomic_add_replaced
) {
336 num_components
= instr
->num_components
;
338 assert(tmu_writes
> 1);
339 num_components
= tmu_writes
- 1;
342 uint32_t config
= (0xffffff00 |
344 GENERAL_TMU_LOOKUP_PER_PIXEL
);
345 if (num_components
== 1) {
346 config
|= GENERAL_TMU_LOOKUP_TYPE_32BIT_UI
;
348 config
|= GENERAL_TMU_LOOKUP_TYPE_VEC2
+
352 if (vir_in_nonuniform_control_flow(c
)) {
353 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
),
359 tmua
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_TMUA
);
361 tmua
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_TMUAU
);
365 struct qreg offset
= base_offset
;
366 if (const_offset
!= 0) {
367 offset
= vir_ADD(c
, offset
,
368 vir_uniform_ui(c
, const_offset
));
371 ntq_get_src(c
, instr
->src
[offset_src
], 0);
372 tmu
= vir_ADD_dest(c
, tmua
, offset
, data
);
374 if (const_offset
!= 0) {
375 tmu
= vir_ADD_dest(c
, tmua
, base_offset
,
376 vir_uniform_ui(c
, const_offset
));
378 tmu
= vir_MOV_dest(c
, tmua
, base_offset
);
384 vir_get_uniform_index(c
, QUNIFORM_CONSTANT
,
388 if (vir_in_nonuniform_control_flow(c
))
389 vir_set_cond(tmu
, V3D_QPU_COND_IFA
);
393 /* Read the result, or wait for the TMU op to complete. */
394 for (int i
= 0; i
< nir_intrinsic_dest_components(instr
); i
++) {
395 ntq_store_dest(c
, &instr
->dest
, i
,
396 vir_MOV(c
, vir_LDTMU(c
)));
399 if (nir_intrinsic_dest_components(instr
) == 0)
401 } while (is_store
&& writemask
!= 0);
405 ntq_init_ssa_def(struct v3d_compile
*c
, nir_ssa_def
*def
)
407 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
408 def
->num_components
);
409 _mesa_hash_table_insert(c
->def_ht
, def
, qregs
);
414 is_ld_signal(const struct v3d_qpu_sig
*sig
)
416 return (sig
->ldunif
||
428 * This function is responsible for getting VIR results into the associated
429 * storage for a NIR instruction.
431 * If it's a NIR SSA def, then we just set the associated hash table entry to
434 * If it's a NIR reg, then we need to update the existing qreg assigned to the
435 * NIR destination with the incoming value. To do that without introducing
436 * new MOVs, we require that the incoming qreg either be a uniform, or be
437 * SSA-defined by the previous VIR instruction in the block and rewritable by
438 * this function. That lets us sneak ahead and insert the SF flag beforehand
439 * (knowing that the previous instruction doesn't depend on flags) and rewrite
440 * its destination to be the NIR reg's destination
443 ntq_store_dest(struct v3d_compile
*c
, nir_dest
*dest
, int chan
,
446 struct qinst
*last_inst
= NULL
;
447 if (!list_is_empty(&c
->cur_block
->instructions
))
448 last_inst
= (struct qinst
*)c
->cur_block
->instructions
.prev
;
450 assert((result
.file
== QFILE_TEMP
&&
451 last_inst
&& last_inst
== c
->defs
[result
.index
]));
454 assert(chan
< dest
->ssa
.num_components
);
457 struct hash_entry
*entry
=
458 _mesa_hash_table_search(c
->def_ht
, &dest
->ssa
);
463 qregs
= ntq_init_ssa_def(c
, &dest
->ssa
);
465 qregs
[chan
] = result
;
467 nir_register
*reg
= dest
->reg
.reg
;
468 assert(dest
->reg
.base_offset
== 0);
469 assert(reg
->num_array_elems
== 0);
470 struct hash_entry
*entry
=
471 _mesa_hash_table_search(c
->def_ht
, reg
);
472 struct qreg
*qregs
= entry
->data
;
474 /* If the previous instruction can't be predicated for
475 * the store into the nir_register, then emit a MOV
478 if (vir_in_nonuniform_control_flow(c
) &&
479 is_ld_signal(&c
->defs
[last_inst
->dst
.index
]->qpu
.sig
)) {
480 result
= vir_MOV(c
, result
);
481 last_inst
= c
->defs
[result
.index
];
484 /* We know they're both temps, so just rewrite index. */
485 c
->defs
[last_inst
->dst
.index
] = NULL
;
486 last_inst
->dst
.index
= qregs
[chan
].index
;
488 /* If we're in control flow, then make this update of the reg
489 * conditional on the execution mask.
491 if (vir_in_nonuniform_control_flow(c
)) {
492 last_inst
->dst
.index
= qregs
[chan
].index
;
494 /* Set the flags to the current exec mask.
496 c
->cursor
= vir_before_inst(last_inst
);
497 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
),
499 c
->cursor
= vir_after_inst(last_inst
);
501 vir_set_cond(last_inst
, V3D_QPU_COND_IFA
);
507 ntq_get_src(struct v3d_compile
*c
, nir_src src
, int i
)
509 struct hash_entry
*entry
;
511 entry
= _mesa_hash_table_search(c
->def_ht
, src
.ssa
);
512 assert(i
< src
.ssa
->num_components
);
514 nir_register
*reg
= src
.reg
.reg
;
515 entry
= _mesa_hash_table_search(c
->def_ht
, reg
);
516 assert(reg
->num_array_elems
== 0);
517 assert(src
.reg
.base_offset
== 0);
518 assert(i
< reg
->num_components
);
521 struct qreg
*qregs
= entry
->data
;
526 ntq_get_alu_src(struct v3d_compile
*c
, nir_alu_instr
*instr
,
529 assert(util_is_power_of_two_or_zero(instr
->dest
.write_mask
));
530 unsigned chan
= ffs(instr
->dest
.write_mask
) - 1;
531 struct qreg r
= ntq_get_src(c
, instr
->src
[src
].src
,
532 instr
->src
[src
].swizzle
[chan
]);
534 assert(!instr
->src
[src
].abs
);
535 assert(!instr
->src
[src
].negate
);
541 ntq_minify(struct v3d_compile
*c
, struct qreg size
, struct qreg level
)
543 return vir_MAX(c
, vir_SHR(c
, size
, level
), vir_uniform_ui(c
, 1));
547 ntq_emit_txs(struct v3d_compile
*c
, nir_tex_instr
*instr
)
549 unsigned unit
= instr
->texture_index
;
550 int lod_index
= nir_tex_instr_src_index(instr
, nir_tex_src_lod
);
551 int dest_size
= nir_tex_instr_dest_size(instr
);
553 struct qreg lod
= c
->undef
;
555 lod
= ntq_get_src(c
, instr
->src
[lod_index
].src
, 0);
557 for (int i
= 0; i
< dest_size
; i
++) {
559 enum quniform_contents contents
;
561 if (instr
->is_array
&& i
== dest_size
- 1)
562 contents
= QUNIFORM_TEXTURE_ARRAY_SIZE
;
564 contents
= QUNIFORM_TEXTURE_WIDTH
+ i
;
566 struct qreg size
= vir_uniform(c
, contents
, unit
);
568 switch (instr
->sampler_dim
) {
569 case GLSL_SAMPLER_DIM_1D
:
570 case GLSL_SAMPLER_DIM_2D
:
571 case GLSL_SAMPLER_DIM_MS
:
572 case GLSL_SAMPLER_DIM_3D
:
573 case GLSL_SAMPLER_DIM_CUBE
:
574 /* Don't minify the array size. */
575 if (!(instr
->is_array
&& i
== dest_size
- 1)) {
576 size
= ntq_minify(c
, size
, lod
);
580 case GLSL_SAMPLER_DIM_RECT
:
581 /* There's no LOD field for rects */
585 unreachable("Bad sampler type");
588 ntq_store_dest(c
, &instr
->dest
, i
, size
);
593 ntq_emit_tex(struct v3d_compile
*c
, nir_tex_instr
*instr
)
595 unsigned unit
= instr
->texture_index
;
597 /* Since each texture sampling op requires uploading uniforms to
598 * reference the texture, there's no HW support for texture size and
599 * you just upload uniforms containing the size.
602 case nir_texop_query_levels
:
603 ntq_store_dest(c
, &instr
->dest
, 0,
604 vir_uniform(c
, QUNIFORM_TEXTURE_LEVELS
, unit
));
607 ntq_emit_txs(c
, instr
);
613 if (c
->devinfo
->ver
>= 40)
614 v3d40_vir_emit_tex(c
, instr
);
616 v3d33_vir_emit_tex(c
, instr
);
620 ntq_fsincos(struct v3d_compile
*c
, struct qreg src
, bool is_cos
)
622 struct qreg input
= vir_FMUL(c
, src
, vir_uniform_f(c
, 1.0f
/ M_PI
));
624 input
= vir_FADD(c
, input
, vir_uniform_f(c
, 0.5));
626 struct qreg periods
= vir_FROUND(c
, input
);
627 struct qreg sin_output
= vir_SIN(c
, vir_FSUB(c
, input
, periods
));
628 return vir_XOR(c
, sin_output
, vir_SHL(c
,
629 vir_FTOIN(c
, periods
),
630 vir_uniform_ui(c
, -1)));
634 ntq_fsign(struct v3d_compile
*c
, struct qreg src
)
636 struct qreg t
= vir_get_temp(c
);
638 vir_MOV_dest(c
, t
, vir_uniform_f(c
, 0.0));
639 vir_set_pf(vir_FMOV_dest(c
, vir_nop_reg(), src
), V3D_QPU_PF_PUSHZ
);
640 vir_MOV_cond(c
, V3D_QPU_COND_IFNA
, t
, vir_uniform_f(c
, 1.0));
641 vir_set_pf(vir_FMOV_dest(c
, vir_nop_reg(), src
), V3D_QPU_PF_PUSHN
);
642 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, t
, vir_uniform_f(c
, -1.0));
643 return vir_MOV(c
, t
);
647 emit_fragcoord_input(struct v3d_compile
*c
, int attr
)
649 c
->inputs
[attr
* 4 + 0] = vir_FXCD(c
);
650 c
->inputs
[attr
* 4 + 1] = vir_FYCD(c
);
651 c
->inputs
[attr
* 4 + 2] = c
->payload_z
;
652 c
->inputs
[attr
* 4 + 3] = vir_RECIP(c
, c
->payload_w
);
656 emit_fragment_varying(struct v3d_compile
*c
, nir_variable
*var
,
657 uint8_t swizzle
, int array_index
)
659 struct qreg r3
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_R3
);
660 struct qreg r5
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_R5
);
663 if (c
->devinfo
->ver
>= 41) {
664 struct qinst
*ldvary
= vir_add_inst(V3D_QPU_A_NOP
, c
->undef
,
666 ldvary
->qpu
.sig
.ldvary
= true;
667 vary
= vir_emit_def(c
, ldvary
);
669 vir_NOP(c
)->qpu
.sig
.ldvary
= true;
673 /* For gl_PointCoord input or distance along a line, we'll be called
674 * with no nir_variable, and we don't count toward VPM size so we
675 * don't track an input slot.
678 return vir_FADD(c
, vir_FMUL(c
, vary
, c
->payload_w
), r5
);
681 int i
= c
->num_inputs
++;
683 v3d_slot_from_slot_and_component(var
->data
.location
+
684 array_index
, swizzle
);
686 switch (var
->data
.interpolation
) {
687 case INTERP_MODE_NONE
:
688 /* If a gl_FrontColor or gl_BackColor input has no interp
689 * qualifier, then if we're using glShadeModel(GL_FLAT) it
690 * needs to be flat shaded.
692 switch (var
->data
.location
+ array_index
) {
693 case VARYING_SLOT_COL0
:
694 case VARYING_SLOT_COL1
:
695 case VARYING_SLOT_BFC0
:
696 case VARYING_SLOT_BFC1
:
697 if (c
->fs_key
->shade_model_flat
) {
698 BITSET_SET(c
->flat_shade_flags
, i
);
699 vir_MOV_dest(c
, c
->undef
, vary
);
700 return vir_MOV(c
, r5
);
702 return vir_FADD(c
, vir_FMUL(c
, vary
,
709 case INTERP_MODE_SMOOTH
:
710 if (var
->data
.centroid
) {
711 BITSET_SET(c
->centroid_flags
, i
);
712 return vir_FADD(c
, vir_FMUL(c
, vary
,
713 c
->payload_w_centroid
), r5
);
715 return vir_FADD(c
, vir_FMUL(c
, vary
, c
->payload_w
), r5
);
717 case INTERP_MODE_NOPERSPECTIVE
:
718 BITSET_SET(c
->noperspective_flags
, i
);
719 return vir_FADD(c
, vir_MOV(c
, vary
), r5
);
720 case INTERP_MODE_FLAT
:
721 BITSET_SET(c
->flat_shade_flags
, i
);
722 vir_MOV_dest(c
, c
->undef
, vary
);
723 return vir_MOV(c
, r5
);
725 unreachable("Bad interp mode");
730 emit_fragment_input(struct v3d_compile
*c
, int attr
, nir_variable
*var
,
733 for (int i
= 0; i
< glsl_get_vector_elements(var
->type
); i
++) {
734 int chan
= var
->data
.location_frac
+ i
;
735 c
->inputs
[attr
* 4 + chan
] =
736 emit_fragment_varying(c
, var
, chan
, array_index
);
741 add_output(struct v3d_compile
*c
,
742 uint32_t decl_offset
,
746 uint32_t old_array_size
= c
->outputs_array_size
;
747 resize_qreg_array(c
, &c
->outputs
, &c
->outputs_array_size
,
750 if (old_array_size
!= c
->outputs_array_size
) {
751 c
->output_slots
= reralloc(c
,
753 struct v3d_varying_slot
,
754 c
->outputs_array_size
);
757 c
->output_slots
[decl_offset
] =
758 v3d_slot_from_slot_and_component(slot
, swizzle
);
762 * If compare_instr is a valid comparison instruction, emits the
763 * compare_instr's comparison and returns the sel_instr's return value based
764 * on the compare_instr's result.
767 ntq_emit_comparison(struct v3d_compile
*c
,
768 nir_alu_instr
*compare_instr
,
769 enum v3d_qpu_cond
*out_cond
)
771 struct qreg src0
= ntq_get_alu_src(c
, compare_instr
, 0);
773 if (nir_op_infos
[compare_instr
->op
].num_inputs
> 1)
774 src1
= ntq_get_alu_src(c
, compare_instr
, 1);
775 bool cond_invert
= false;
776 struct qreg nop
= vir_nop_reg();
778 switch (compare_instr
->op
) {
781 vir_set_pf(vir_FCMP_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
784 vir_set_pf(vir_XOR_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
789 vir_set_pf(vir_FCMP_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
793 vir_set_pf(vir_XOR_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
799 vir_set_pf(vir_FCMP_dest(c
, nop
, src1
, src0
), V3D_QPU_PF_PUSHC
);
802 vir_set_pf(vir_MIN_dest(c
, nop
, src1
, src0
), V3D_QPU_PF_PUSHC
);
806 vir_set_pf(vir_SUB_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHC
);
812 vir_set_pf(vir_FCMP_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHN
);
815 vir_set_pf(vir_MIN_dest(c
, nop
, src1
, src0
), V3D_QPU_PF_PUSHC
);
818 vir_set_pf(vir_SUB_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHC
);
822 vir_set_pf(vir_MOV_dest(c
, nop
, src0
), V3D_QPU_PF_PUSHZ
);
827 vir_set_pf(vir_FMOV_dest(c
, nop
, src0
), V3D_QPU_PF_PUSHZ
);
835 *out_cond
= cond_invert
? V3D_QPU_COND_IFNA
: V3D_QPU_COND_IFA
;
840 /* Finds an ALU instruction that generates our src value that could
841 * (potentially) be greedily emitted in the consuming instruction.
843 static struct nir_alu_instr
*
844 ntq_get_alu_parent(nir_src src
)
846 if (!src
.is_ssa
|| src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
848 nir_alu_instr
*instr
= nir_instr_as_alu(src
.ssa
->parent_instr
);
852 /* If the ALU instr's srcs are non-SSA, then we would have to avoid
853 * moving emission of the ALU instr down past another write of the
856 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
857 if (!instr
->src
[i
].src
.is_ssa
)
864 /* Turns a NIR bool into a condition code to predicate on. */
865 static enum v3d_qpu_cond
866 ntq_emit_bool_to_cond(struct v3d_compile
*c
, nir_src src
)
868 nir_alu_instr
*compare
= ntq_get_alu_parent(src
);
872 enum v3d_qpu_cond cond
;
873 if (ntq_emit_comparison(c
, compare
, &cond
))
877 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), ntq_get_src(c
, src
, 0)),
879 return V3D_QPU_COND_IFNA
;
883 ntq_emit_alu(struct v3d_compile
*c
, nir_alu_instr
*instr
)
885 /* This should always be lowered to ALU operations for V3D. */
886 assert(!instr
->dest
.saturate
);
888 /* Vectors are special in that they have non-scalarized writemasks,
889 * and just take the first swizzle channel for each argument in order
890 * into each writemask channel.
892 if (instr
->op
== nir_op_vec2
||
893 instr
->op
== nir_op_vec3
||
894 instr
->op
== nir_op_vec4
) {
896 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
897 srcs
[i
] = ntq_get_src(c
, instr
->src
[i
].src
,
898 instr
->src
[i
].swizzle
[0]);
899 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
900 ntq_store_dest(c
, &instr
->dest
.dest
, i
,
901 vir_MOV(c
, srcs
[i
]));
905 /* General case: We can just grab the one used channel per src. */
906 struct qreg src
[nir_op_infos
[instr
->op
].num_inputs
];
907 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
908 src
[i
] = ntq_get_alu_src(c
, instr
, i
);
915 result
= vir_MOV(c
, src
[0]);
919 result
= vir_XOR(c
, src
[0], vir_uniform_ui(c
, 1 << 31));
922 result
= vir_NEG(c
, src
[0]);
926 result
= vir_FMUL(c
, src
[0], src
[1]);
929 result
= vir_FADD(c
, src
[0], src
[1]);
932 result
= vir_FSUB(c
, src
[0], src
[1]);
935 result
= vir_FMIN(c
, src
[0], src
[1]);
938 result
= vir_FMAX(c
, src
[0], src
[1]);
942 nir_alu_instr
*src0_alu
= ntq_get_alu_parent(instr
->src
[0].src
);
943 if (src0_alu
&& src0_alu
->op
== nir_op_fround_even
) {
944 result
= vir_FTOIN(c
, ntq_get_alu_src(c
, src0_alu
, 0));
946 result
= vir_FTOIZ(c
, src
[0]);
952 result
= vir_FTOUZ(c
, src
[0]);
955 result
= vir_ITOF(c
, src
[0]);
958 result
= vir_UTOF(c
, src
[0]);
961 result
= vir_AND(c
, src
[0], vir_uniform_f(c
, 1.0));
964 result
= vir_AND(c
, src
[0], vir_uniform_ui(c
, 1));
968 result
= vir_ADD(c
, src
[0], src
[1]);
971 result
= vir_SHR(c
, src
[0], src
[1]);
974 result
= vir_SUB(c
, src
[0], src
[1]);
977 result
= vir_ASR(c
, src
[0], src
[1]);
980 result
= vir_SHL(c
, src
[0], src
[1]);
983 result
= vir_MIN(c
, src
[0], src
[1]);
986 result
= vir_UMIN(c
, src
[0], src
[1]);
989 result
= vir_MAX(c
, src
[0], src
[1]);
992 result
= vir_UMAX(c
, src
[0], src
[1]);
995 result
= vir_AND(c
, src
[0], src
[1]);
998 result
= vir_OR(c
, src
[0], src
[1]);
1001 result
= vir_XOR(c
, src
[0], src
[1]);
1004 result
= vir_NOT(c
, src
[0]);
1007 case nir_op_ufind_msb
:
1008 result
= vir_SUB(c
, vir_uniform_ui(c
, 31), vir_CLZ(c
, src
[0]));
1012 result
= vir_UMUL(c
, src
[0], src
[1]);
1019 enum v3d_qpu_cond cond
;
1020 ASSERTED
bool ok
= ntq_emit_comparison(c
, instr
, &cond
);
1022 result
= vir_MOV(c
, vir_SEL(c
, cond
,
1023 vir_uniform_f(c
, 1.0),
1024 vir_uniform_f(c
, 0.0)));
1039 case nir_op_ult32
: {
1040 enum v3d_qpu_cond cond
;
1041 ASSERTED
bool ok
= ntq_emit_comparison(c
, instr
, &cond
);
1043 result
= vir_MOV(c
, vir_SEL(c
, cond
,
1044 vir_uniform_ui(c
, ~0),
1045 vir_uniform_ui(c
, 0)));
1049 case nir_op_b32csel
:
1052 ntq_emit_bool_to_cond(c
, instr
->src
[0].src
),
1057 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), src
[0]),
1059 result
= vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFNA
,
1064 result
= vir_RECIP(c
, src
[0]);
1067 result
= vir_RSQRT(c
, src
[0]);
1070 result
= vir_EXP(c
, src
[0]);
1073 result
= vir_LOG(c
, src
[0]);
1077 result
= vir_FCEIL(c
, src
[0]);
1080 result
= vir_FFLOOR(c
, src
[0]);
1082 case nir_op_fround_even
:
1083 result
= vir_FROUND(c
, src
[0]);
1086 result
= vir_FTRUNC(c
, src
[0]);
1090 result
= ntq_fsincos(c
, src
[0], false);
1093 result
= ntq_fsincos(c
, src
[0], true);
1097 result
= ntq_fsign(c
, src
[0]);
1101 result
= vir_FMOV(c
, src
[0]);
1102 vir_set_unpack(c
->defs
[result
.index
], 0, V3D_QPU_UNPACK_ABS
);
1107 result
= vir_MAX(c
, src
[0], vir_NEG(c
, src
[0]));
1111 case nir_op_fddx_coarse
:
1112 case nir_op_fddx_fine
:
1113 result
= vir_FDX(c
, src
[0]);
1117 case nir_op_fddy_coarse
:
1118 case nir_op_fddy_fine
:
1119 result
= vir_FDY(c
, src
[0]);
1122 case nir_op_uadd_carry
:
1123 vir_set_pf(vir_ADD_dest(c
, vir_nop_reg(), src
[0], src
[1]),
1125 result
= vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFA
,
1126 vir_uniform_ui(c
, ~0),
1127 vir_uniform_ui(c
, 0)));
1130 case nir_op_pack_half_2x16_split
:
1131 result
= vir_VFPACK(c
, src
[0], src
[1]);
1134 case nir_op_unpack_half_2x16_split_x
:
1135 result
= vir_FMOV(c
, src
[0]);
1136 vir_set_unpack(c
->defs
[result
.index
], 0, V3D_QPU_UNPACK_L
);
1139 case nir_op_unpack_half_2x16_split_y
:
1140 result
= vir_FMOV(c
, src
[0]);
1141 vir_set_unpack(c
->defs
[result
.index
], 0, V3D_QPU_UNPACK_H
);
1145 fprintf(stderr
, "unknown NIR ALU inst: ");
1146 nir_print_instr(&instr
->instr
, stderr
);
1147 fprintf(stderr
, "\n");
1151 /* We have a scalar result, so the instruction should only have a
1152 * single channel written to.
1154 assert(util_is_power_of_two_or_zero(instr
->dest
.write_mask
));
1155 ntq_store_dest(c
, &instr
->dest
.dest
,
1156 ffs(instr
->dest
.write_mask
) - 1, result
);
1159 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
1160 * specifier. They come from a register that's preloaded with 0xffffffff
1161 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
1162 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
1164 #define TLB_TYPE_F16_COLOR (3 << 6)
1165 #define TLB_TYPE_I32_COLOR (1 << 6)
1166 #define TLB_TYPE_F32_COLOR (0 << 6)
1167 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
1168 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
1169 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
1170 #define TLB_F16_SWAP_HI_LO (1 << 1)
1171 #define TLB_VEC_SIZE_4_F16 (1 << 0)
1172 #define TLB_VEC_SIZE_2_F16 (0 << 0)
1173 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
1175 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
1178 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
1179 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
1180 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
1181 #define TLB_V42_DEPTH_TYPE_INVARIANT (0 << 3) /* Unmodified sideband input used */
1182 #define TLB_V42_DEPTH_TYPE_PER_PIXEL (1 << 3) /* QPU result used */
1184 /* Stencil is a single 32-bit write. */
1185 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1188 vir_emit_tlb_color_write(struct v3d_compile
*c
, unsigned rt
)
1190 if (!(c
->fs_key
->cbufs
& (1 << rt
)) || !c
->output_color_var
[rt
])
1193 struct qreg tlb_reg
= vir_magic_reg(V3D_QPU_WADDR_TLB
);
1194 struct qreg tlbu_reg
= vir_magic_reg(V3D_QPU_WADDR_TLBU
);
1196 nir_variable
*var
= c
->output_color_var
[rt
];
1197 int num_components
= glsl_get_vector_elements(var
->type
);
1198 uint32_t conf
= 0xffffff00;
1201 conf
|= c
->msaa_per_sample_output
? TLB_SAMPLE_MODE_PER_SAMPLE
:
1202 TLB_SAMPLE_MODE_PER_PIXEL
;
1203 conf
|= (7 - rt
) << TLB_RENDER_TARGET_SHIFT
;
1205 if (c
->fs_key
->swap_color_rb
& (1 << rt
))
1206 num_components
= MAX2(num_components
, 3);
1207 assert(num_components
!= 0);
1209 enum glsl_base_type type
= glsl_get_base_type(var
->type
);
1210 bool is_int_format
= type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
;
1211 bool is_32b_tlb_format
= is_int_format
||
1212 (c
->fs_key
->f32_color_rb
& (1 << rt
));
1214 if (is_int_format
) {
1215 /* The F32 vs I32 distinction was dropped in 4.2. */
1216 if (c
->devinfo
->ver
< 42)
1217 conf
|= TLB_TYPE_I32_COLOR
;
1219 conf
|= TLB_TYPE_F32_COLOR
;
1220 conf
|= ((num_components
- 1) << TLB_VEC_SIZE_MINUS_1_SHIFT
);
1222 if (c
->fs_key
->f32_color_rb
& (1 << rt
)) {
1223 conf
|= TLB_TYPE_F32_COLOR
;
1224 conf
|= ((num_components
- 1) <<
1225 TLB_VEC_SIZE_MINUS_1_SHIFT
);
1227 conf
|= TLB_TYPE_F16_COLOR
;
1228 conf
|= TLB_F16_SWAP_HI_LO
;
1229 if (num_components
>= 3)
1230 conf
|= TLB_VEC_SIZE_4_F16
;
1232 conf
|= TLB_VEC_SIZE_2_F16
;
1236 int num_samples
= c
->msaa_per_sample_output
? V3D_MAX_SAMPLES
: 1;
1237 for (int i
= 0; i
< num_samples
; i
++) {
1238 struct qreg
*color
= c
->msaa_per_sample_output
?
1239 &c
->sample_colors
[(rt
* V3D_MAX_SAMPLES
+ i
) * 4] :
1240 &c
->outputs
[var
->data
.driver_location
* 4];
1242 struct qreg r
= color
[0];
1243 struct qreg g
= color
[1];
1244 struct qreg b
= color
[2];
1245 struct qreg a
= color
[3];
1247 if (c
->fs_key
->swap_color_rb
& (1 << rt
)) {
1252 if (c
->fs_key
->sample_alpha_to_one
)
1253 a
= vir_uniform_f(c
, 1.0);
1255 if (is_32b_tlb_format
) {
1257 inst
= vir_MOV_dest(c
, tlbu_reg
, r
);
1259 vir_get_uniform_index(c
,
1263 inst
= vir_MOV_dest(c
, tlb_reg
, r
);
1266 if (num_components
>= 2)
1267 vir_MOV_dest(c
, tlb_reg
, g
);
1268 if (num_components
>= 3)
1269 vir_MOV_dest(c
, tlb_reg
, b
);
1270 if (num_components
>= 4)
1271 vir_MOV_dest(c
, tlb_reg
, a
);
1273 inst
= vir_VFPACK_dest(c
, tlb_reg
, r
, g
);
1274 if (conf
!= ~0 && i
== 0) {
1275 inst
->dst
= tlbu_reg
;
1277 vir_get_uniform_index(c
,
1282 if (num_components
>= 3)
1283 inst
= vir_VFPACK_dest(c
, tlb_reg
, b
, a
);
1289 emit_frag_end(struct v3d_compile
*c
)
1292 if (c->output_sample_mask_index != -1) {
1293 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1297 bool has_any_tlb_color_write
= false;
1298 for (int rt
= 0; rt
< V3D_MAX_DRAW_BUFFERS
; rt
++) {
1299 if (c
->fs_key
->cbufs
& (1 << rt
) && c
->output_color_var
[rt
])
1300 has_any_tlb_color_write
= true;
1303 if (c
->fs_key
->sample_alpha_to_coverage
&& c
->output_color_var
[0]) {
1304 struct nir_variable
*var
= c
->output_color_var
[0];
1305 struct qreg
*color
= &c
->outputs
[var
->data
.driver_location
* 4];
1307 vir_SETMSF_dest(c
, vir_nop_reg(),
1310 vir_FTOC(c
, color
[3])));
1313 struct qreg tlbu_reg
= vir_magic_reg(V3D_QPU_WADDR_TLBU
);
1314 if (c
->output_position_index
!= -1) {
1315 struct qinst
*inst
= vir_MOV_dest(c
, tlbu_reg
,
1316 c
->outputs
[c
->output_position_index
]);
1317 uint8_t tlb_specifier
= TLB_TYPE_DEPTH
;
1319 if (c
->devinfo
->ver
>= 42) {
1320 tlb_specifier
|= (TLB_V42_DEPTH_TYPE_PER_PIXEL
|
1321 TLB_SAMPLE_MODE_PER_PIXEL
);
1323 tlb_specifier
|= TLB_DEPTH_TYPE_PER_PIXEL
;
1325 inst
->uniform
= vir_get_uniform_index(c
, QUNIFORM_CONSTANT
,
1329 } else if (c
->s
->info
.fs
.uses_discard
||
1330 !c
->s
->info
.fs
.early_fragment_tests
||
1331 c
->fs_key
->sample_alpha_to_coverage
||
1332 !has_any_tlb_color_write
) {
1333 /* Emit passthrough Z if it needed to be delayed until shader
1334 * end due to potential discards.
1336 * Since (single-threaded) fragment shaders always need a TLB
1337 * write, emit passthrouh Z if we didn't have any color
1338 * buffers and flag us as potentially discarding, so that we
1339 * can use Z as the TLB write.
1341 c
->s
->info
.fs
.uses_discard
= true;
1343 struct qinst
*inst
= vir_MOV_dest(c
, tlbu_reg
,
1345 uint8_t tlb_specifier
= TLB_TYPE_DEPTH
;
1347 if (c
->devinfo
->ver
>= 42) {
1348 /* The spec says the PER_PIXEL flag is ignored for
1349 * invariant writes, but the simulator demands it.
1351 tlb_specifier
|= (TLB_V42_DEPTH_TYPE_INVARIANT
|
1352 TLB_SAMPLE_MODE_PER_PIXEL
);
1354 tlb_specifier
|= TLB_DEPTH_TYPE_INVARIANT
;
1357 inst
->uniform
= vir_get_uniform_index(c
,
1364 /* XXX: Performance improvement: Merge Z write and color writes TLB
1367 for (int rt
= 0; rt
< V3D_MAX_DRAW_BUFFERS
; rt
++)
1368 vir_emit_tlb_color_write(c
, rt
);
1372 vir_VPM_WRITE_indirect(struct v3d_compile
*c
,
1374 struct qreg vpm_index
)
1376 assert(c
->devinfo
->ver
>= 40);
1377 vir_STVPMV(c
, vpm_index
, val
);
1381 vir_VPM_WRITE(struct v3d_compile
*c
, struct qreg val
, uint32_t vpm_index
)
1383 if (c
->devinfo
->ver
>= 40) {
1384 vir_VPM_WRITE_indirect(c
, val
, vir_uniform_ui(c
, vpm_index
));
1386 /* XXX: v3d33_vir_vpm_write_setup(c); */
1387 vir_MOV_dest(c
, vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_VPM
), val
);
1392 emit_vert_end(struct v3d_compile
*c
)
1394 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1396 if (c
->devinfo
->ver
>= 40 && c
->devinfo
->ver
<= 42)
1401 emit_geom_end(struct v3d_compile
*c
)
1403 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1405 if (c
->devinfo
->ver
>= 40 && c
->devinfo
->ver
<= 42)
1410 v3d_optimize_nir(struct nir_shader
*s
)
1413 unsigned lower_flrp
=
1414 (s
->options
->lower_flrp16
? 16 : 0) |
1415 (s
->options
->lower_flrp32
? 32 : 0) |
1416 (s
->options
->lower_flrp64
? 64 : 0);
1421 NIR_PASS_V(s
, nir_lower_vars_to_ssa
);
1422 NIR_PASS(progress
, s
, nir_lower_alu_to_scalar
, NULL
, NULL
);
1423 NIR_PASS(progress
, s
, nir_lower_phis_to_scalar
);
1424 NIR_PASS(progress
, s
, nir_copy_prop
);
1425 NIR_PASS(progress
, s
, nir_opt_remove_phis
);
1426 NIR_PASS(progress
, s
, nir_opt_dce
);
1427 NIR_PASS(progress
, s
, nir_opt_dead_cf
);
1428 NIR_PASS(progress
, s
, nir_opt_cse
);
1429 NIR_PASS(progress
, s
, nir_opt_peephole_select
, 8, true, true);
1430 NIR_PASS(progress
, s
, nir_opt_algebraic
);
1431 NIR_PASS(progress
, s
, nir_opt_constant_folding
);
1433 if (lower_flrp
!= 0) {
1434 bool lower_flrp_progress
= false;
1436 NIR_PASS(lower_flrp_progress
, s
, nir_lower_flrp
,
1438 false /* always_precise */,
1439 s
->options
->lower_ffma
);
1440 if (lower_flrp_progress
) {
1441 NIR_PASS(progress
, s
, nir_opt_constant_folding
);
1445 /* Nothing should rematerialize any flrps, so we only
1446 * need to do this lowering once.
1451 NIR_PASS(progress
, s
, nir_opt_undef
);
1454 NIR_PASS(progress
, s
, nir_opt_move
, nir_move_load_ubo
);
1458 driver_location_compare(const void *in_a
, const void *in_b
)
1460 const nir_variable
*const *a
= in_a
;
1461 const nir_variable
*const *b
= in_b
;
1463 return (*a
)->data
.driver_location
- (*b
)->data
.driver_location
;
1467 ntq_emit_vpm_read(struct v3d_compile
*c
,
1468 uint32_t *num_components_queued
,
1469 uint32_t *remaining
,
1472 struct qreg vpm
= vir_reg(QFILE_VPM
, vpm_index
);
1474 if (c
->devinfo
->ver
>= 40 ) {
1475 return vir_LDVPMV_IN(c
,
1477 (*num_components_queued
)++));
1480 if (*num_components_queued
!= 0) {
1481 (*num_components_queued
)--;
1482 return vir_MOV(c
, vpm
);
1485 uint32_t num_components
= MIN2(*remaining
, 32);
1487 v3d33_vir_vpm_read_setup(c
, num_components
);
1489 *num_components_queued
= num_components
- 1;
1490 *remaining
-= num_components
;
1492 return vir_MOV(c
, vpm
);
1496 ntq_setup_vs_inputs(struct v3d_compile
*c
)
1498 /* Figure out how many components of each vertex attribute the shader
1499 * uses. Each variable should have been split to individual
1500 * components and unused ones DCEed. The vertex fetcher will load
1501 * from the start of the attribute to the number of components we
1502 * declare we need in c->vattr_sizes[].
1504 nir_foreach_variable(var
, &c
->s
->inputs
) {
1505 /* No VS attribute array support. */
1506 assert(MAX2(glsl_get_length(var
->type
), 1) == 1);
1508 unsigned loc
= var
->data
.driver_location
;
1509 int start_component
= var
->data
.location_frac
;
1510 int num_components
= glsl_get_components(var
->type
);
1512 c
->vattr_sizes
[loc
] = MAX2(c
->vattr_sizes
[loc
],
1513 start_component
+ num_components
);
1516 unsigned num_components
= 0;
1517 uint32_t vpm_components_queued
= 0;
1518 bool uses_iid
= c
->s
->info
.system_values_read
&
1519 (1ull << SYSTEM_VALUE_INSTANCE_ID
);
1520 bool uses_vid
= c
->s
->info
.system_values_read
&
1521 (1ull << SYSTEM_VALUE_VERTEX_ID
);
1522 num_components
+= uses_iid
;
1523 num_components
+= uses_vid
;
1525 for (int i
= 0; i
< ARRAY_SIZE(c
->vattr_sizes
); i
++)
1526 num_components
+= c
->vattr_sizes
[i
];
1529 c
->iid
= ntq_emit_vpm_read(c
, &vpm_components_queued
,
1530 &num_components
, ~0);
1534 c
->vid
= ntq_emit_vpm_read(c
, &vpm_components_queued
,
1535 &num_components
, ~0);
1538 /* The actual loads will happen directly in nir_intrinsic_load_input
1539 * on newer versions.
1541 if (c
->devinfo
->ver
>= 40)
1544 for (int loc
= 0; loc
< ARRAY_SIZE(c
->vattr_sizes
); loc
++) {
1545 resize_qreg_array(c
, &c
->inputs
, &c
->inputs_array_size
,
1548 for (int i
= 0; i
< c
->vattr_sizes
[loc
]; i
++) {
1549 c
->inputs
[loc
* 4 + i
] =
1550 ntq_emit_vpm_read(c
,
1551 &vpm_components_queued
,
1558 if (c
->devinfo
->ver
>= 40) {
1559 assert(vpm_components_queued
== num_components
);
1561 assert(vpm_components_queued
== 0);
1562 assert(num_components
== 0);
1567 program_reads_point_coord(struct v3d_compile
*c
)
1569 nir_foreach_variable(var
, &c
->s
->inputs
) {
1570 if (util_varying_is_point_coord(var
->data
.location
,
1571 c
->fs_key
->point_sprite_mask
)) {
1580 get_sorted_input_variables(struct v3d_compile
*c
,
1581 unsigned *num_entries
,
1582 nir_variable
***vars
)
1585 nir_foreach_variable(var
, &c
->s
->inputs
)
1588 *vars
= ralloc_array(c
, nir_variable
*, *num_entries
);
1591 nir_foreach_variable(var
, &c
->s
->inputs
)
1594 /* Sort the variables so that we emit the input setup in
1595 * driver_location order. This is required for VPM reads, whose data
1596 * is fetched into the VPM in driver_location (TGSI register index)
1599 qsort(*vars
, *num_entries
, sizeof(**vars
), driver_location_compare
);
1603 ntq_setup_gs_inputs(struct v3d_compile
*c
)
1605 nir_variable
**vars
;
1606 unsigned num_entries
;
1607 get_sorted_input_variables(c
, &num_entries
, &vars
);
1609 for (unsigned i
= 0; i
< num_entries
; i
++) {
1610 nir_variable
*var
= vars
[i
];
1612 /* All GS inputs are arrays with as many entries as vertices
1613 * in the input primitive, but here we only care about the
1614 * per-vertex input type.
1616 const struct glsl_type
*type
= glsl_without_array(var
->type
);
1617 unsigned array_len
= MAX2(glsl_get_length(type
), 1);
1618 unsigned loc
= var
->data
.driver_location
;
1620 resize_qreg_array(c
, &c
->inputs
, &c
->inputs_array_size
,
1621 (loc
+ array_len
) * 4);
1623 for (unsigned j
= 0; j
< array_len
; j
++) {
1624 unsigned num_elements
= glsl_get_vector_elements(type
);
1625 for (unsigned k
= 0; k
< num_elements
; k
++) {
1626 unsigned chan
= var
->data
.location_frac
+ k
;
1627 unsigned input_idx
= c
->num_inputs
++;
1628 struct v3d_varying_slot slot
=
1629 v3d_slot_from_slot_and_component(var
->data
.location
+ j
, chan
);
1630 c
->input_slots
[input_idx
] = slot
;
1638 ntq_setup_fs_inputs(struct v3d_compile
*c
)
1640 nir_variable
**vars
;
1641 unsigned num_entries
;
1642 get_sorted_input_variables(c
, &num_entries
, &vars
);
1644 for (unsigned i
= 0; i
< num_entries
; i
++) {
1645 nir_variable
*var
= vars
[i
];
1646 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1647 unsigned loc
= var
->data
.driver_location
;
1649 resize_qreg_array(c
, &c
->inputs
, &c
->inputs_array_size
,
1650 (loc
+ array_len
) * 4);
1652 if (var
->data
.location
== VARYING_SLOT_POS
) {
1653 emit_fragcoord_input(c
, loc
);
1654 } else if (util_varying_is_point_coord(var
->data
.location
,
1655 c
->fs_key
->point_sprite_mask
)) {
1656 c
->inputs
[loc
* 4 + 0] = c
->point_x
;
1657 c
->inputs
[loc
* 4 + 1] = c
->point_y
;
1659 for (int j
= 0; j
< array_len
; j
++)
1660 emit_fragment_input(c
, loc
+ j
, var
, j
);
1666 ntq_setup_outputs(struct v3d_compile
*c
)
1668 if (c
->s
->info
.stage
!= MESA_SHADER_FRAGMENT
)
1671 nir_foreach_variable(var
, &c
->s
->outputs
) {
1672 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1673 unsigned loc
= var
->data
.driver_location
* 4;
1675 assert(array_len
== 1);
1678 for (int i
= 0; i
< 4 - var
->data
.location_frac
; i
++) {
1679 add_output(c
, loc
+ var
->data
.location_frac
+ i
,
1681 var
->data
.location_frac
+ i
);
1684 switch (var
->data
.location
) {
1685 case FRAG_RESULT_COLOR
:
1686 c
->output_color_var
[0] = var
;
1687 c
->output_color_var
[1] = var
;
1688 c
->output_color_var
[2] = var
;
1689 c
->output_color_var
[3] = var
;
1691 case FRAG_RESULT_DATA0
:
1692 case FRAG_RESULT_DATA1
:
1693 case FRAG_RESULT_DATA2
:
1694 case FRAG_RESULT_DATA3
:
1695 c
->output_color_var
[var
->data
.location
-
1696 FRAG_RESULT_DATA0
] = var
;
1698 case FRAG_RESULT_DEPTH
:
1699 c
->output_position_index
= loc
;
1701 case FRAG_RESULT_SAMPLE_MASK
:
1702 c
->output_sample_mask_index
= loc
;
1709 * Sets up the mapping from nir_register to struct qreg *.
1711 * Each nir_register gets a struct qreg per 32-bit component being stored.
1714 ntq_setup_registers(struct v3d_compile
*c
, struct exec_list
*list
)
1716 foreach_list_typed(nir_register
, nir_reg
, node
, list
) {
1717 unsigned array_len
= MAX2(nir_reg
->num_array_elems
, 1);
1718 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
1720 nir_reg
->num_components
);
1722 _mesa_hash_table_insert(c
->def_ht
, nir_reg
, qregs
);
1724 for (int i
= 0; i
< array_len
* nir_reg
->num_components
; i
++)
1725 qregs
[i
] = vir_get_temp(c
);
1730 ntq_emit_load_const(struct v3d_compile
*c
, nir_load_const_instr
*instr
)
1732 /* XXX perf: Experiment with using immediate loads to avoid having
1733 * these end up in the uniform stream. Watch out for breaking the
1734 * small immediates optimization in the process!
1736 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1737 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1738 qregs
[i
] = vir_uniform_ui(c
, instr
->value
[i
].u32
);
1740 _mesa_hash_table_insert(c
->def_ht
, &instr
->def
, qregs
);
1744 ntq_emit_ssa_undef(struct v3d_compile
*c
, nir_ssa_undef_instr
*instr
)
1746 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1748 /* VIR needs there to be *some* value, so pick 0 (same as for
1749 * ntq_setup_registers().
1751 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1752 qregs
[i
] = vir_uniform_ui(c
, 0);
1756 ntq_emit_image_size(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
)
1758 unsigned image_index
= nir_src_as_uint(instr
->src
[0]);
1759 bool is_array
= nir_intrinsic_image_array(instr
);
1761 ntq_store_dest(c
, &instr
->dest
, 0,
1762 vir_uniform(c
, QUNIFORM_IMAGE_WIDTH
, image_index
));
1763 if (instr
->num_components
> 1) {
1764 ntq_store_dest(c
, &instr
->dest
, 1,
1765 vir_uniform(c
, QUNIFORM_IMAGE_HEIGHT
,
1768 if (instr
->num_components
> 2) {
1769 ntq_store_dest(c
, &instr
->dest
, 2,
1772 QUNIFORM_IMAGE_ARRAY_SIZE
:
1773 QUNIFORM_IMAGE_DEPTH
,
1779 vir_emit_tlb_color_read(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
)
1781 assert(c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
);
1783 int rt
= nir_src_as_uint(instr
->src
[0]);
1784 assert(rt
< V3D_MAX_DRAW_BUFFERS
);
1786 int sample_index
= nir_intrinsic_base(instr
) ;
1787 assert(sample_index
< V3D_MAX_SAMPLES
);
1789 int component
= nir_intrinsic_component(instr
);
1790 assert(component
< 4);
1792 /* We need to emit our TLB reads after we have acquired the scoreboard
1793 * lock, or the GPU will hang. Usually, we do our scoreboard locking on
1794 * the last thread switch to improve parallelism, however, that is only
1795 * guaranteed to happen before the tlb color writes.
1797 * To fix that, we make sure we always emit a thread switch before the
1798 * first tlb color read. If that happens to be the last thread switch
1799 * we emit, then everything is fine, but otherwsie, if any code after
1800 * this point needs to emit additional thread switches, then we will
1801 * switch the strategy to locking the scoreboard on the first thread
1802 * switch instead -- see vir_emit_thrsw().
1804 if (!c
->emitted_tlb_load
) {
1805 if (!c
->last_thrsw_at_top_level
) {
1806 assert(c
->devinfo
->ver
>= 41);
1810 c
->emitted_tlb_load
= true;
1813 struct qreg
*color_reads_for_sample
=
1814 &c
->color_reads
[(rt
* V3D_MAX_SAMPLES
+ sample_index
) * 4];
1816 if (color_reads_for_sample
[component
].file
== QFILE_NULL
) {
1817 enum pipe_format rt_format
= c
->fs_key
->color_fmt
[rt
].format
;
1818 int num_components
=
1819 util_format_get_nr_components(rt_format
);
1821 const bool swap_rb
= c
->fs_key
->swap_color_rb
& (1 << rt
);
1823 num_components
= MAX2(num_components
, 3);
1825 nir_variable
*var
= c
->output_color_var
[rt
];
1826 enum glsl_base_type type
= glsl_get_base_type(var
->type
);
1828 bool is_int_format
= type
== GLSL_TYPE_INT
||
1829 type
== GLSL_TYPE_UINT
;
1831 bool is_32b_tlb_format
= is_int_format
||
1832 (c
->fs_key
->f32_color_rb
& (1 << rt
));
1834 int num_samples
= c
->fs_key
->msaa
? V3D_MAX_SAMPLES
: 1;
1836 uint32_t conf
= 0xffffff00;
1837 conf
|= c
->fs_key
->msaa
? TLB_SAMPLE_MODE_PER_SAMPLE
:
1838 TLB_SAMPLE_MODE_PER_PIXEL
;
1839 conf
|= (7 - rt
) << TLB_RENDER_TARGET_SHIFT
;
1841 if (is_32b_tlb_format
) {
1842 /* The F32 vs I32 distinction was dropped in 4.2. */
1843 conf
|= (c
->devinfo
->ver
< 42 && is_int_format
) ?
1844 TLB_TYPE_I32_COLOR
: TLB_TYPE_F32_COLOR
;
1846 conf
|= ((num_components
- 1) <<
1847 TLB_VEC_SIZE_MINUS_1_SHIFT
);
1849 conf
|= TLB_TYPE_F16_COLOR
;
1850 conf
|= TLB_F16_SWAP_HI_LO
;
1852 if (num_components
>= 3)
1853 conf
|= TLB_VEC_SIZE_4_F16
;
1855 conf
|= TLB_VEC_SIZE_2_F16
;
1859 for (int i
= 0; i
< num_samples
; i
++) {
1860 struct qreg r
, g
, b
, a
;
1861 if (is_32b_tlb_format
) {
1862 r
= conf
!= 0xffffffff && i
== 0?
1863 vir_TLBU_COLOR_READ(c
, conf
) :
1864 vir_TLB_COLOR_READ(c
);
1865 if (num_components
>= 2)
1866 g
= vir_TLB_COLOR_READ(c
);
1867 if (num_components
>= 3)
1868 b
= vir_TLB_COLOR_READ(c
);
1869 if (num_components
>= 4)
1870 a
= vir_TLB_COLOR_READ(c
);
1872 struct qreg rg
= conf
!= 0xffffffff && i
== 0 ?
1873 vir_TLBU_COLOR_READ(c
, conf
) :
1874 vir_TLB_COLOR_READ(c
);
1875 r
= vir_FMOV(c
, rg
);
1876 vir_set_unpack(c
->defs
[r
.index
], 0,
1878 g
= vir_FMOV(c
, rg
);
1879 vir_set_unpack(c
->defs
[g
.index
], 0,
1882 if (num_components
> 2) {
1883 struct qreg ba
= vir_TLB_COLOR_READ(c
);
1884 b
= vir_FMOV(c
, ba
);
1885 vir_set_unpack(c
->defs
[b
.index
], 0,
1887 a
= vir_FMOV(c
, ba
);
1888 vir_set_unpack(c
->defs
[a
.index
], 0,
1893 struct qreg
*color_reads
=
1894 &c
->color_reads
[(rt
* V3D_MAX_SAMPLES
+ i
) * 4];
1896 color_reads
[0] = swap_rb
? b
: r
;
1897 if (num_components
>= 2)
1899 if (num_components
>= 3)
1900 color_reads
[2] = swap_rb
? r
: b
;
1901 if (num_components
>= 4)
1906 assert(color_reads_for_sample
[component
].file
!= QFILE_NULL
);
1907 ntq_store_dest(c
, &instr
->dest
, 0,
1908 vir_MOV(c
, color_reads_for_sample
[component
]));
1912 ntq_emit_load_uniform(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
)
1914 if (nir_src_is_const(instr
->src
[0])) {
1915 int offset
= (nir_intrinsic_base(instr
) +
1916 nir_src_as_uint(instr
->src
[0]));
1917 assert(offset
% 4 == 0);
1918 /* We need dwords */
1919 offset
= offset
/ 4;
1920 for (int i
= 0; i
< instr
->num_components
; i
++) {
1921 ntq_store_dest(c
, &instr
->dest
, i
,
1922 vir_uniform(c
, QUNIFORM_UNIFORM
,
1926 ntq_emit_tmu_general(c
, instr
, false);
1931 ntq_emit_load_input(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
)
1933 /* XXX: Use ldvpmv (uniform offset) or ldvpmd (non-uniform offset)
1934 * and enable PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR.
1937 nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[0]);
1939 if (c
->s
->info
.stage
!= MESA_SHADER_FRAGMENT
&& c
->devinfo
->ver
>= 40) {
1940 /* Emit the LDVPM directly now, rather than at the top
1941 * of the shader like we did for V3D 3.x (which needs
1942 * vpmsetup when not just taking the next offset).
1944 * Note that delaying like this may introduce stalls,
1945 * as LDVPMV takes a minimum of 1 instruction but may
1946 * be slower if the VPM unit is busy with another QPU.
1949 if (c
->s
->info
.system_values_read
&
1950 (1ull << SYSTEM_VALUE_INSTANCE_ID
)) {
1953 if (c
->s
->info
.system_values_read
&
1954 (1ull << SYSTEM_VALUE_VERTEX_ID
)) {
1957 for (int i
= 0; i
< offset
; i
++)
1958 index
+= c
->vattr_sizes
[i
];
1959 index
+= nir_intrinsic_component(instr
);
1960 for (int i
= 0; i
< instr
->num_components
; i
++) {
1961 struct qreg vpm_offset
= vir_uniform_ui(c
, index
++);
1962 ntq_store_dest(c
, &instr
->dest
, i
,
1963 vir_LDVPMV_IN(c
, vpm_offset
));
1966 for (int i
= 0; i
< instr
->num_components
; i
++) {
1967 int comp
= nir_intrinsic_component(instr
) + i
;
1968 ntq_store_dest(c
, &instr
->dest
, i
,
1969 vir_MOV(c
, c
->inputs
[offset
* 4 + comp
]));
1975 ntq_emit_per_sample_color_write(struct v3d_compile
*c
,
1976 nir_intrinsic_instr
*instr
)
1978 assert(instr
->intrinsic
== nir_intrinsic_store_tlb_sample_color_v3d
);
1980 unsigned rt
= nir_src_as_uint(instr
->src
[1]);
1981 assert(rt
< V3D_MAX_DRAW_BUFFERS
);
1983 unsigned sample_idx
= nir_intrinsic_base(instr
);
1984 assert(sample_idx
< V3D_MAX_SAMPLES
);
1986 unsigned offset
= (rt
* V3D_MAX_SAMPLES
+ sample_idx
) * 4;
1987 for (int i
= 0; i
< instr
->num_components
; i
++) {
1988 c
->sample_colors
[offset
+ i
] =
1989 vir_MOV(c
, ntq_get_src(c
, instr
->src
[0], i
));
1994 ntq_emit_color_write(struct v3d_compile
*c
,
1995 nir_intrinsic_instr
*instr
)
1997 unsigned offset
= (nir_intrinsic_base(instr
) +
1998 nir_src_as_uint(instr
->src
[1])) * 4 +
1999 nir_intrinsic_component(instr
);
2000 for (int i
= 0; i
< instr
->num_components
; i
++) {
2001 c
->outputs
[offset
+ i
] =
2002 vir_MOV(c
, ntq_get_src(c
, instr
->src
[0], i
));
2007 emit_store_output_gs(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
)
2009 assert(instr
->num_components
== 1);
2011 uint32_t base_offset
= nir_intrinsic_base(instr
);
2012 struct qreg src_offset
= ntq_get_src(c
, instr
->src
[1], 0);
2013 struct qreg offset
=
2014 vir_ADD(c
, vir_uniform_ui(c
, base_offset
), src_offset
);
2016 /* Usually, for VS or FS, we only emit outputs once at program end so
2017 * our VPM writes are never in non-uniform control flow, but this
2018 * is not true for GS, where we are emitting multiple vertices.
2020 if (vir_in_nonuniform_control_flow(c
)) {
2021 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
),
2025 struct qreg val
= ntq_get_src(c
, instr
->src
[0], 0);
2027 /* The offset isn’t necessarily dynamically uniform for a geometry
2028 * shader. This can happen if the shader sometimes doesn’t emit one of
2029 * the vertices. In that case subsequent vertices will be written to
2030 * different offsets in the VPM and we need to use the scatter write
2031 * instruction to have a different offset for each lane.
2033 if (nir_src_is_dynamically_uniform(instr
->src
[1]))
2034 vir_VPM_WRITE_indirect(c
, val
, offset
);
2036 vir_STVPMD(c
, offset
, val
);
2038 if (vir_in_nonuniform_control_flow(c
)) {
2039 struct qinst
*last_inst
=
2040 (struct qinst
*)c
->cur_block
->instructions
.prev
;
2041 vir_set_cond(last_inst
, V3D_QPU_COND_IFA
);
2046 ntq_emit_store_output(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
)
2048 /* XXX perf: Use stvpmv with uniform non-constant offsets and
2049 * stvpmd with non-uniform offsets and enable
2050 * PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR.
2052 if (c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
) {
2053 ntq_emit_color_write(c
, instr
);
2054 } else if (c
->s
->info
.stage
== MESA_SHADER_GEOMETRY
) {
2055 emit_store_output_gs(c
, instr
);
2057 assert(c
->s
->info
.stage
== MESA_SHADER_VERTEX
);
2058 assert(instr
->num_components
== 1);
2061 ntq_get_src(c
, instr
->src
[0], 0),
2062 nir_intrinsic_base(instr
));
2067 ntq_emit_intrinsic(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
)
2069 switch (instr
->intrinsic
) {
2070 case nir_intrinsic_load_uniform
:
2071 ntq_emit_load_uniform(c
, instr
);
2074 case nir_intrinsic_load_ubo
:
2075 ntq_emit_tmu_general(c
, instr
, false);
2078 case nir_intrinsic_ssbo_atomic_add
:
2079 case nir_intrinsic_ssbo_atomic_imin
:
2080 case nir_intrinsic_ssbo_atomic_umin
:
2081 case nir_intrinsic_ssbo_atomic_imax
:
2082 case nir_intrinsic_ssbo_atomic_umax
:
2083 case nir_intrinsic_ssbo_atomic_and
:
2084 case nir_intrinsic_ssbo_atomic_or
:
2085 case nir_intrinsic_ssbo_atomic_xor
:
2086 case nir_intrinsic_ssbo_atomic_exchange
:
2087 case nir_intrinsic_ssbo_atomic_comp_swap
:
2088 case nir_intrinsic_load_ssbo
:
2089 case nir_intrinsic_store_ssbo
:
2090 ntq_emit_tmu_general(c
, instr
, false);
2093 case nir_intrinsic_shared_atomic_add
:
2094 case nir_intrinsic_shared_atomic_imin
:
2095 case nir_intrinsic_shared_atomic_umin
:
2096 case nir_intrinsic_shared_atomic_imax
:
2097 case nir_intrinsic_shared_atomic_umax
:
2098 case nir_intrinsic_shared_atomic_and
:
2099 case nir_intrinsic_shared_atomic_or
:
2100 case nir_intrinsic_shared_atomic_xor
:
2101 case nir_intrinsic_shared_atomic_exchange
:
2102 case nir_intrinsic_shared_atomic_comp_swap
:
2103 case nir_intrinsic_load_shared
:
2104 case nir_intrinsic_store_shared
:
2105 case nir_intrinsic_load_scratch
:
2106 case nir_intrinsic_store_scratch
:
2107 ntq_emit_tmu_general(c
, instr
, true);
2110 case nir_intrinsic_image_load
:
2111 case nir_intrinsic_image_store
:
2112 case nir_intrinsic_image_atomic_add
:
2113 case nir_intrinsic_image_atomic_imin
:
2114 case nir_intrinsic_image_atomic_umin
:
2115 case nir_intrinsic_image_atomic_imax
:
2116 case nir_intrinsic_image_atomic_umax
:
2117 case nir_intrinsic_image_atomic_and
:
2118 case nir_intrinsic_image_atomic_or
:
2119 case nir_intrinsic_image_atomic_xor
:
2120 case nir_intrinsic_image_atomic_exchange
:
2121 case nir_intrinsic_image_atomic_comp_swap
:
2122 v3d40_vir_emit_image_load_store(c
, instr
);
2125 case nir_intrinsic_get_buffer_size
:
2126 ntq_store_dest(c
, &instr
->dest
, 0,
2127 vir_uniform(c
, QUNIFORM_GET_BUFFER_SIZE
,
2128 nir_src_as_uint(instr
->src
[0])));
2131 case nir_intrinsic_load_user_clip_plane
:
2132 for (int i
= 0; i
< nir_intrinsic_dest_components(instr
); i
++) {
2133 ntq_store_dest(c
, &instr
->dest
, i
,
2134 vir_uniform(c
, QUNIFORM_USER_CLIP_PLANE
,
2135 nir_intrinsic_ucp_id(instr
) *
2140 case nir_intrinsic_load_viewport_x_scale
:
2141 ntq_store_dest(c
, &instr
->dest
, 0,
2142 vir_uniform(c
, QUNIFORM_VIEWPORT_X_SCALE
, 0));
2145 case nir_intrinsic_load_viewport_y_scale
:
2146 ntq_store_dest(c
, &instr
->dest
, 0,
2147 vir_uniform(c
, QUNIFORM_VIEWPORT_Y_SCALE
, 0));
2150 case nir_intrinsic_load_viewport_z_scale
:
2151 ntq_store_dest(c
, &instr
->dest
, 0,
2152 vir_uniform(c
, QUNIFORM_VIEWPORT_Z_SCALE
, 0));
2155 case nir_intrinsic_load_viewport_z_offset
:
2156 ntq_store_dest(c
, &instr
->dest
, 0,
2157 vir_uniform(c
, QUNIFORM_VIEWPORT_Z_OFFSET
, 0));
2160 case nir_intrinsic_load_alpha_ref_float
:
2161 ntq_store_dest(c
, &instr
->dest
, 0,
2162 vir_uniform(c
, QUNIFORM_ALPHA_REF
, 0));
2165 case nir_intrinsic_load_sample_mask_in
:
2166 ntq_store_dest(c
, &instr
->dest
, 0, vir_MSF(c
));
2169 case nir_intrinsic_load_helper_invocation
:
2170 vir_set_pf(vir_MSF_dest(c
, vir_nop_reg()), V3D_QPU_PF_PUSHZ
);
2171 ntq_store_dest(c
, &instr
->dest
, 0,
2172 vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFA
,
2173 vir_uniform_ui(c
, ~0),
2174 vir_uniform_ui(c
, 0))));
2177 case nir_intrinsic_load_front_face
:
2178 /* The register contains 0 (front) or 1 (back), and we need to
2179 * turn it into a NIR bool where true means front.
2181 ntq_store_dest(c
, &instr
->dest
, 0,
2183 vir_uniform_ui(c
, -1),
2187 case nir_intrinsic_load_instance_id
:
2188 ntq_store_dest(c
, &instr
->dest
, 0, vir_MOV(c
, c
->iid
));
2191 case nir_intrinsic_load_vertex_id
:
2192 ntq_store_dest(c
, &instr
->dest
, 0, vir_MOV(c
, c
->vid
));
2195 case nir_intrinsic_load_tlb_color_v3d
:
2196 vir_emit_tlb_color_read(c
, instr
);
2199 case nir_intrinsic_load_input
:
2200 ntq_emit_load_input(c
, instr
);
2203 case nir_intrinsic_store_tlb_sample_color_v3d
:
2204 ntq_emit_per_sample_color_write(c
, instr
);
2207 case nir_intrinsic_store_output
:
2208 ntq_emit_store_output(c
, instr
);
2211 case nir_intrinsic_image_size
:
2212 ntq_emit_image_size(c
, instr
);
2215 case nir_intrinsic_discard
:
2216 if (vir_in_nonuniform_control_flow(c
)) {
2217 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
),
2219 vir_set_cond(vir_SETMSF_dest(c
, vir_nop_reg(),
2220 vir_uniform_ui(c
, 0)),
2223 vir_SETMSF_dest(c
, vir_nop_reg(),
2224 vir_uniform_ui(c
, 0));
2228 case nir_intrinsic_discard_if
: {
2229 enum v3d_qpu_cond cond
= ntq_emit_bool_to_cond(c
, instr
->src
[0]);
2231 if (vir_in_nonuniform_control_flow(c
)) {
2232 struct qinst
*exec_flag
= vir_MOV_dest(c
, vir_nop_reg(),
2234 if (cond
== V3D_QPU_COND_IFA
) {
2235 vir_set_uf(exec_flag
, V3D_QPU_UF_ANDZ
);
2237 vir_set_uf(exec_flag
, V3D_QPU_UF_NORNZ
);
2238 cond
= V3D_QPU_COND_IFA
;
2242 vir_set_cond(vir_SETMSF_dest(c
, vir_nop_reg(),
2243 vir_uniform_ui(c
, 0)), cond
);
2248 case nir_intrinsic_memory_barrier
:
2249 case nir_intrinsic_memory_barrier_buffer
:
2250 case nir_intrinsic_memory_barrier_image
:
2251 case nir_intrinsic_memory_barrier_shared
:
2252 case nir_intrinsic_memory_barrier_tcs_patch
:
2253 case nir_intrinsic_group_memory_barrier
:
2254 /* We don't do any instruction scheduling of these NIR
2255 * instructions between each other, so we just need to make
2256 * sure that the TMU operations before the barrier are flushed
2257 * before the ones after the barrier. That is currently
2258 * handled by having a THRSW in each of them and a LDTMU
2259 * series or a TMUWT after.
2263 case nir_intrinsic_control_barrier
:
2264 /* Emit a TSY op to get all invocations in the workgroup
2265 * (actually supergroup) to block until the last invocation
2266 * reaches the TSY op.
2268 if (c
->devinfo
->ver
>= 42) {
2269 vir_BARRIERID_dest(c
, vir_reg(QFILE_MAGIC
,
2270 V3D_QPU_WADDR_SYNCB
));
2272 struct qinst
*sync
=
2273 vir_BARRIERID_dest(c
,
2274 vir_reg(QFILE_MAGIC
,
2275 V3D_QPU_WADDR_SYNCU
));
2277 vir_get_uniform_index(c
, QUNIFORM_CONSTANT
,
2279 V3D_TSY_WAIT_INC_CHECK
);
2283 /* The blocking of a TSY op only happens at the next thread
2284 * switch. No texturing may be outstanding at the time of a
2285 * TSY blocking operation.
2290 case nir_intrinsic_load_num_work_groups
:
2291 for (int i
= 0; i
< 3; i
++) {
2292 ntq_store_dest(c
, &instr
->dest
, i
,
2293 vir_uniform(c
, QUNIFORM_NUM_WORK_GROUPS
,
2298 case nir_intrinsic_load_local_invocation_index
:
2299 ntq_store_dest(c
, &instr
->dest
, 0,
2300 vir_SHR(c
, c
->cs_payload
[1],
2301 vir_uniform_ui(c
, 32 - c
->local_invocation_index_bits
)));
2304 case nir_intrinsic_load_work_group_id
:
2305 ntq_store_dest(c
, &instr
->dest
, 0,
2306 vir_AND(c
, c
->cs_payload
[0],
2307 vir_uniform_ui(c
, 0xffff)));
2308 ntq_store_dest(c
, &instr
->dest
, 1,
2309 vir_SHR(c
, c
->cs_payload
[0],
2310 vir_uniform_ui(c
, 16)));
2311 ntq_store_dest(c
, &instr
->dest
, 2,
2312 vir_AND(c
, c
->cs_payload
[1],
2313 vir_uniform_ui(c
, 0xffff)));
2316 case nir_intrinsic_load_subgroup_id
:
2317 ntq_store_dest(c
, &instr
->dest
, 0, vir_EIDX(c
));
2320 case nir_intrinsic_load_per_vertex_input
: {
2321 /* col: vertex index, row = varying index */
2322 struct qreg col
= ntq_get_src(c
, instr
->src
[0], 0);
2323 uint32_t row_idx
= nir_intrinsic_base(instr
) * 4 +
2324 nir_intrinsic_component(instr
);
2325 for (int i
= 0; i
< instr
->num_components
; i
++) {
2326 struct qreg row
= vir_uniform_ui(c
, row_idx
++);
2327 ntq_store_dest(c
, &instr
->dest
, i
,
2328 vir_LDVPMG_IN(c
, row
, col
));
2333 case nir_intrinsic_emit_vertex
:
2334 case nir_intrinsic_end_primitive
:
2335 unreachable("Should have been lowered in v3d_nir_lower_io");
2338 case nir_intrinsic_load_primitive_id
: {
2339 /* gl_PrimitiveIdIn is written by the GBG in the first word of
2340 * VPM output header. According to docs, we should read this
2341 * using ldvpm(v,d)_in (See Table 71).
2343 ntq_store_dest(c
, &instr
->dest
, 0,
2344 vir_LDVPMV_IN(c
, vir_uniform_ui(c
, 0)));
2348 case nir_intrinsic_load_invocation_id
:
2349 ntq_store_dest(c
, &instr
->dest
, 0, vir_IID(c
));
2352 case nir_intrinsic_load_fb_layers_v3d
:
2353 ntq_store_dest(c
, &instr
->dest
, 0,
2354 vir_uniform(c
, QUNIFORM_FB_LAYERS
, 0));
2358 fprintf(stderr
, "Unknown intrinsic: ");
2359 nir_print_instr(&instr
->instr
, stderr
);
2360 fprintf(stderr
, "\n");
2365 /* Clears (activates) the execute flags for any channels whose jump target
2366 * matches this block.
2368 * XXX perf: Could we be using flpush/flpop somehow for our execution channel
2371 * XXX perf: For uniform control flow, we should be able to skip c->execute
2372 * handling entirely.
2375 ntq_activate_execute_for_block(struct v3d_compile
*c
)
2377 vir_set_pf(vir_XOR_dest(c
, vir_nop_reg(),
2378 c
->execute
, vir_uniform_ui(c
, c
->cur_block
->index
)),
2381 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
, vir_uniform_ui(c
, 0));
2385 ntq_emit_uniform_if(struct v3d_compile
*c
, nir_if
*if_stmt
)
2387 nir_block
*nir_else_block
= nir_if_first_else_block(if_stmt
);
2388 bool empty_else_block
=
2389 (nir_else_block
== nir_if_last_else_block(if_stmt
) &&
2390 exec_list_is_empty(&nir_else_block
->instr_list
));
2392 struct qblock
*then_block
= vir_new_block(c
);
2393 struct qblock
*after_block
= vir_new_block(c
);
2394 struct qblock
*else_block
;
2395 if (empty_else_block
)
2396 else_block
= after_block
;
2398 else_block
= vir_new_block(c
);
2400 /* Set up the flags for the IF condition (taking the THEN branch). */
2401 enum v3d_qpu_cond cond
= ntq_emit_bool_to_cond(c
, if_stmt
->condition
);
2404 vir_BRANCH(c
, cond
== V3D_QPU_COND_IFA
?
2405 V3D_QPU_BRANCH_COND_ALLNA
:
2406 V3D_QPU_BRANCH_COND_ALLA
);
2407 vir_link_blocks(c
->cur_block
, else_block
);
2408 vir_link_blocks(c
->cur_block
, then_block
);
2410 /* Process the THEN block. */
2411 vir_set_emit_block(c
, then_block
);
2412 ntq_emit_cf_list(c
, &if_stmt
->then_list
);
2414 if (!empty_else_block
) {
2415 /* At the end of the THEN block, jump to ENDIF */
2416 vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ALWAYS
);
2417 vir_link_blocks(c
->cur_block
, after_block
);
2419 /* Emit the else block. */
2420 vir_set_emit_block(c
, else_block
);
2421 ntq_emit_cf_list(c
, &if_stmt
->else_list
);
2424 vir_link_blocks(c
->cur_block
, after_block
);
2426 vir_set_emit_block(c
, after_block
);
2430 ntq_emit_nonuniform_if(struct v3d_compile
*c
, nir_if
*if_stmt
)
2432 nir_block
*nir_else_block
= nir_if_first_else_block(if_stmt
);
2433 bool empty_else_block
=
2434 (nir_else_block
== nir_if_last_else_block(if_stmt
) &&
2435 exec_list_is_empty(&nir_else_block
->instr_list
));
2437 struct qblock
*then_block
= vir_new_block(c
);
2438 struct qblock
*after_block
= vir_new_block(c
);
2439 struct qblock
*else_block
;
2440 if (empty_else_block
)
2441 else_block
= after_block
;
2443 else_block
= vir_new_block(c
);
2445 bool was_uniform_control_flow
= false;
2446 if (!vir_in_nonuniform_control_flow(c
)) {
2447 c
->execute
= vir_MOV(c
, vir_uniform_ui(c
, 0));
2448 was_uniform_control_flow
= true;
2451 /* Set up the flags for the IF condition (taking the THEN branch). */
2452 enum v3d_qpu_cond cond
= ntq_emit_bool_to_cond(c
, if_stmt
->condition
);
2454 /* Update the flags+cond to mean "Taking the ELSE branch (!cond) and
2455 * was previously active (execute Z) for updating the exec flags.
2457 if (was_uniform_control_flow
) {
2458 cond
= v3d_qpu_cond_invert(cond
);
2460 struct qinst
*inst
= vir_MOV_dest(c
, vir_nop_reg(), c
->execute
);
2461 if (cond
== V3D_QPU_COND_IFA
) {
2462 vir_set_uf(inst
, V3D_QPU_UF_NORNZ
);
2464 vir_set_uf(inst
, V3D_QPU_UF_ANDZ
);
2465 cond
= V3D_QPU_COND_IFA
;
2469 vir_MOV_cond(c
, cond
,
2471 vir_uniform_ui(c
, else_block
->index
));
2473 /* Jump to ELSE if nothing is active for THEN, otherwise fall
2476 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
), V3D_QPU_PF_PUSHZ
);
2477 vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ALLNA
);
2478 vir_link_blocks(c
->cur_block
, else_block
);
2479 vir_link_blocks(c
->cur_block
, then_block
);
2481 /* Process the THEN block. */
2482 vir_set_emit_block(c
, then_block
);
2483 ntq_emit_cf_list(c
, &if_stmt
->then_list
);
2485 if (!empty_else_block
) {
2486 /* Handle the end of the THEN block. First, all currently
2487 * active channels update their execute flags to point to
2490 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
),
2492 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
,
2493 vir_uniform_ui(c
, after_block
->index
));
2495 /* If everything points at ENDIF, then jump there immediately. */
2496 vir_set_pf(vir_XOR_dest(c
, vir_nop_reg(),
2498 vir_uniform_ui(c
, after_block
->index
)),
2500 vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ALLA
);
2501 vir_link_blocks(c
->cur_block
, after_block
);
2502 vir_link_blocks(c
->cur_block
, else_block
);
2504 vir_set_emit_block(c
, else_block
);
2505 ntq_activate_execute_for_block(c
);
2506 ntq_emit_cf_list(c
, &if_stmt
->else_list
);
2509 vir_link_blocks(c
->cur_block
, after_block
);
2511 vir_set_emit_block(c
, after_block
);
2512 if (was_uniform_control_flow
)
2513 c
->execute
= c
->undef
;
2515 ntq_activate_execute_for_block(c
);
2519 ntq_emit_if(struct v3d_compile
*c
, nir_if
*nif
)
2521 bool was_in_control_flow
= c
->in_control_flow
;
2522 c
->in_control_flow
= true;
2523 if (!vir_in_nonuniform_control_flow(c
) &&
2524 nir_src_is_dynamically_uniform(nif
->condition
)) {
2525 ntq_emit_uniform_if(c
, nif
);
2527 ntq_emit_nonuniform_if(c
, nif
);
2529 c
->in_control_flow
= was_in_control_flow
;
2533 ntq_emit_jump(struct v3d_compile
*c
, nir_jump_instr
*jump
)
2535 switch (jump
->type
) {
2536 case nir_jump_break
:
2537 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
),
2539 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
,
2540 vir_uniform_ui(c
, c
->loop_break_block
->index
));
2543 case nir_jump_continue
:
2544 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
),
2546 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
,
2547 vir_uniform_ui(c
, c
->loop_cont_block
->index
));
2550 case nir_jump_return
:
2551 unreachable("All returns shouold be lowered\n");
2556 ntq_emit_instr(struct v3d_compile
*c
, nir_instr
*instr
)
2558 switch (instr
->type
) {
2559 case nir_instr_type_alu
:
2560 ntq_emit_alu(c
, nir_instr_as_alu(instr
));
2563 case nir_instr_type_intrinsic
:
2564 ntq_emit_intrinsic(c
, nir_instr_as_intrinsic(instr
));
2567 case nir_instr_type_load_const
:
2568 ntq_emit_load_const(c
, nir_instr_as_load_const(instr
));
2571 case nir_instr_type_ssa_undef
:
2572 ntq_emit_ssa_undef(c
, nir_instr_as_ssa_undef(instr
));
2575 case nir_instr_type_tex
:
2576 ntq_emit_tex(c
, nir_instr_as_tex(instr
));
2579 case nir_instr_type_jump
:
2580 ntq_emit_jump(c
, nir_instr_as_jump(instr
));
2584 fprintf(stderr
, "Unknown NIR instr type: ");
2585 nir_print_instr(instr
, stderr
);
2586 fprintf(stderr
, "\n");
2592 ntq_emit_block(struct v3d_compile
*c
, nir_block
*block
)
2594 nir_foreach_instr(instr
, block
) {
2595 ntq_emit_instr(c
, instr
);
2599 static void ntq_emit_cf_list(struct v3d_compile
*c
, struct exec_list
*list
);
2602 ntq_emit_loop(struct v3d_compile
*c
, nir_loop
*loop
)
2604 bool was_in_control_flow
= c
->in_control_flow
;
2605 c
->in_control_flow
= true;
2607 bool was_uniform_control_flow
= false;
2608 if (!vir_in_nonuniform_control_flow(c
)) {
2609 c
->execute
= vir_MOV(c
, vir_uniform_ui(c
, 0));
2610 was_uniform_control_flow
= true;
2613 struct qblock
*save_loop_cont_block
= c
->loop_cont_block
;
2614 struct qblock
*save_loop_break_block
= c
->loop_break_block
;
2616 c
->loop_cont_block
= vir_new_block(c
);
2617 c
->loop_break_block
= vir_new_block(c
);
2619 vir_link_blocks(c
->cur_block
, c
->loop_cont_block
);
2620 vir_set_emit_block(c
, c
->loop_cont_block
);
2621 ntq_activate_execute_for_block(c
);
2623 ntq_emit_cf_list(c
, &loop
->body
);
2625 /* Re-enable any previous continues now, so our ANYA check below
2628 * XXX: Use the .ORZ flags update, instead.
2630 vir_set_pf(vir_XOR_dest(c
,
2633 vir_uniform_ui(c
, c
->loop_cont_block
->index
)),
2635 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
, vir_uniform_ui(c
, 0));
2637 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
), V3D_QPU_PF_PUSHZ
);
2639 struct qinst
*branch
= vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ANYA
);
2640 /* Pixels that were not dispatched or have been discarded should not
2641 * contribute to looping again.
2643 branch
->qpu
.branch
.msfign
= V3D_QPU_MSFIGN_P
;
2644 vir_link_blocks(c
->cur_block
, c
->loop_cont_block
);
2645 vir_link_blocks(c
->cur_block
, c
->loop_break_block
);
2647 vir_set_emit_block(c
, c
->loop_break_block
);
2648 if (was_uniform_control_flow
)
2649 c
->execute
= c
->undef
;
2651 ntq_activate_execute_for_block(c
);
2653 c
->loop_break_block
= save_loop_break_block
;
2654 c
->loop_cont_block
= save_loop_cont_block
;
2658 c
->in_control_flow
= was_in_control_flow
;
2662 ntq_emit_function(struct v3d_compile
*c
, nir_function_impl
*func
)
2664 fprintf(stderr
, "FUNCTIONS not handled.\n");
2669 ntq_emit_cf_list(struct v3d_compile
*c
, struct exec_list
*list
)
2671 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2672 switch (node
->type
) {
2673 case nir_cf_node_block
:
2674 ntq_emit_block(c
, nir_cf_node_as_block(node
));
2677 case nir_cf_node_if
:
2678 ntq_emit_if(c
, nir_cf_node_as_if(node
));
2681 case nir_cf_node_loop
:
2682 ntq_emit_loop(c
, nir_cf_node_as_loop(node
));
2685 case nir_cf_node_function
:
2686 ntq_emit_function(c
, nir_cf_node_as_function(node
));
2690 fprintf(stderr
, "Unknown NIR node type\n");
2697 ntq_emit_impl(struct v3d_compile
*c
, nir_function_impl
*impl
)
2699 ntq_setup_registers(c
, &impl
->registers
);
2700 ntq_emit_cf_list(c
, &impl
->body
);
2704 nir_to_vir(struct v3d_compile
*c
)
2706 switch (c
->s
->info
.stage
) {
2707 case MESA_SHADER_FRAGMENT
:
2708 c
->payload_w
= vir_MOV(c
, vir_reg(QFILE_REG
, 0));
2709 c
->payload_w_centroid
= vir_MOV(c
, vir_reg(QFILE_REG
, 1));
2710 c
->payload_z
= vir_MOV(c
, vir_reg(QFILE_REG
, 2));
2712 /* V3D 4.x can disable implicit point coordinate varyings if
2713 * they are not used.
2715 if (c
->fs_key
->is_points
&&
2716 (c
->devinfo
->ver
< 40 || program_reads_point_coord(c
))) {
2717 c
->point_x
= emit_fragment_varying(c
, NULL
, 0, 0);
2718 c
->point_y
= emit_fragment_varying(c
, NULL
, 0, 0);
2719 c
->uses_implicit_point_line_varyings
= true;
2720 } else if (c
->fs_key
->is_lines
&& c
->devinfo
->ver
< 40) {
2721 c
->line_x
= emit_fragment_varying(c
, NULL
, 0, 0);
2722 c
->uses_implicit_point_line_varyings
= true;
2725 case MESA_SHADER_COMPUTE
:
2726 /* Set up the TSO for barriers, assuming we do some. */
2727 if (c
->devinfo
->ver
< 42) {
2728 vir_BARRIERID_dest(c
, vir_reg(QFILE_MAGIC
,
2729 V3D_QPU_WADDR_SYNC
));
2732 c
->cs_payload
[0] = vir_MOV(c
, vir_reg(QFILE_REG
, 0));
2733 c
->cs_payload
[1] = vir_MOV(c
, vir_reg(QFILE_REG
, 2));
2735 /* Set up the division between gl_LocalInvocationIndex and
2736 * wg_in_mem in the payload reg.
2738 int wg_size
= (c
->s
->info
.cs
.local_size
[0] *
2739 c
->s
->info
.cs
.local_size
[1] *
2740 c
->s
->info
.cs
.local_size
[2]);
2741 c
->local_invocation_index_bits
=
2742 ffs(util_next_power_of_two(MAX2(wg_size
, 64))) - 1;
2743 assert(c
->local_invocation_index_bits
<= 8);
2745 if (c
->s
->info
.cs
.shared_size
) {
2746 struct qreg wg_in_mem
= vir_SHR(c
, c
->cs_payload
[1],
2747 vir_uniform_ui(c
, 16));
2748 if (c
->s
->info
.cs
.local_size
[0] != 1 ||
2749 c
->s
->info
.cs
.local_size
[1] != 1 ||
2750 c
->s
->info
.cs
.local_size
[2] != 1) {
2752 c
->local_invocation_index_bits
);
2753 int wg_mask
= (1 << wg_bits
) - 1;
2754 wg_in_mem
= vir_AND(c
, wg_in_mem
,
2755 vir_uniform_ui(c
, wg_mask
));
2757 struct qreg shared_per_wg
=
2758 vir_uniform_ui(c
, c
->s
->info
.cs
.shared_size
);
2760 c
->cs_shared_offset
=
2762 vir_uniform(c
, QUNIFORM_SHARED_OFFSET
,0),
2763 vir_UMUL(c
, wg_in_mem
, shared_per_wg
));
2770 if (c
->s
->scratch_size
) {
2771 v3d_setup_spill_base(c
);
2772 c
->spill_size
+= V3D_CHANNELS
* c
->s
->scratch_size
;
2775 switch (c
->s
->info
.stage
) {
2776 case MESA_SHADER_VERTEX
:
2777 ntq_setup_vs_inputs(c
);
2779 case MESA_SHADER_GEOMETRY
:
2780 ntq_setup_gs_inputs(c
);
2782 case MESA_SHADER_FRAGMENT
:
2783 ntq_setup_fs_inputs(c
);
2785 case MESA_SHADER_COMPUTE
:
2788 unreachable("unsupported shader stage");
2791 ntq_setup_outputs(c
);
2793 /* Find the main function and emit the body. */
2794 nir_foreach_function(function
, c
->s
) {
2795 assert(strcmp(function
->name
, "main") == 0);
2796 assert(function
->impl
);
2797 ntq_emit_impl(c
, function
->impl
);
2801 const nir_shader_compiler_options v3d_nir_options
= {
2802 .lower_all_io_to_temps
= true,
2803 .lower_extract_byte
= true,
2804 .lower_extract_word
= true,
2805 .lower_bitfield_insert_to_shifts
= true,
2806 .lower_bitfield_extract_to_shifts
= true,
2807 .lower_bitfield_reverse
= true,
2808 .lower_bit_count
= true,
2809 .lower_cs_local_id_from_index
= true,
2810 .lower_ffract
= true,
2812 .lower_pack_unorm_2x16
= true,
2813 .lower_pack_snorm_2x16
= true,
2814 .lower_pack_unorm_4x8
= true,
2815 .lower_pack_snorm_4x8
= true,
2816 .lower_unpack_unorm_4x8
= true,
2817 .lower_unpack_snorm_4x8
= true,
2818 .lower_pack_half_2x16
= true,
2819 .lower_unpack_half_2x16
= true,
2821 .lower_find_lsb
= true,
2823 .lower_flrp32
= true,
2826 .lower_fsqrt
= true,
2827 .lower_ifind_msb
= true,
2828 .lower_isign
= true,
2829 .lower_ldexp
= true,
2830 .lower_mul_high
= true,
2831 .lower_wpos_pntc
= true,
2832 .lower_rotate
= true,
2833 .lower_to_scalar
= true,
2837 * When demoting a shader down to single-threaded, removes the THRSW
2838 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
2842 vir_remove_thrsw(struct v3d_compile
*c
)
2844 vir_for_each_block(block
, c
) {
2845 vir_for_each_inst_safe(inst
, block
) {
2846 if (inst
->qpu
.sig
.thrsw
)
2847 vir_remove_instruction(c
, inst
);
2851 c
->last_thrsw
= NULL
;
2855 vir_emit_last_thrsw(struct v3d_compile
*c
)
2857 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
2858 * switching, so disable threads if we didn't do any TMU ops (each of
2859 * which would have emitted a THRSW).
2861 if (!c
->last_thrsw_at_top_level
&& c
->devinfo
->ver
< 41) {
2864 vir_remove_thrsw(c
);
2868 /* If we're threaded and the last THRSW was in conditional code, then
2869 * we need to emit another one so that we can flag it as the last
2872 if (c
->last_thrsw
&& !c
->last_thrsw_at_top_level
) {
2873 assert(c
->devinfo
->ver
>= 41);
2877 /* If we're threaded, then we need to mark the last THRSW instruction
2878 * so we can emit a pair of them at QPU emit time.
2880 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2881 * post-last-THRSW state, so we can skip this.
2883 if (!c
->last_thrsw
&& c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
) {
2884 assert(c
->devinfo
->ver
>= 41);
2889 c
->last_thrsw
->is_last_thrsw
= true;
2892 /* There's a flag in the shader for "center W is needed for reasons other than
2893 * non-centroid varyings", so we just walk the program after VIR optimization
2894 * to see if it's used. It should be harmless to set even if we only use
2895 * center W for varyings.
2898 vir_check_payload_w(struct v3d_compile
*c
)
2900 if (c
->s
->info
.stage
!= MESA_SHADER_FRAGMENT
)
2903 vir_for_each_inst_inorder(inst
, c
) {
2904 for (int i
= 0; i
< vir_get_nsrc(inst
); i
++) {
2905 if (inst
->src
[i
].file
== QFILE_REG
&&
2906 inst
->src
[i
].index
== 0) {
2907 c
->uses_center_w
= true;
2916 v3d_nir_to_vir(struct v3d_compile
*c
)
2918 if (V3D_DEBUG
& (V3D_DEBUG_NIR
|
2919 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
))) {
2920 fprintf(stderr
, "%s prog %d/%d NIR:\n",
2921 vir_get_stage_name(c
),
2922 c
->program_id
, c
->variant_id
);
2923 nir_print_shader(c
->s
, stderr
);
2928 /* Emit the last THRSW before STVPM and TLB writes. */
2929 vir_emit_last_thrsw(c
);
2931 switch (c
->s
->info
.stage
) {
2932 case MESA_SHADER_FRAGMENT
:
2935 case MESA_SHADER_GEOMETRY
:
2938 case MESA_SHADER_VERTEX
:
2941 case MESA_SHADER_COMPUTE
:
2944 unreachable("bad stage");
2947 if (V3D_DEBUG
& (V3D_DEBUG_VIR
|
2948 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
))) {
2949 fprintf(stderr
, "%s prog %d/%d pre-opt VIR:\n",
2950 vir_get_stage_name(c
),
2951 c
->program_id
, c
->variant_id
);
2953 fprintf(stderr
, "\n");
2958 vir_check_payload_w(c
);
2960 /* XXX perf: On VC4, we do a VIR-level instruction scheduling here.
2961 * We used that on that platform to pipeline TMU writes and reduce the
2962 * number of thread switches, as well as try (mostly successfully) to
2963 * reduce maximum register pressure to allow more threads. We should
2964 * do something of that sort for V3D -- either instruction scheduling
2965 * here, or delay the the THRSW and LDTMUs from our texture
2966 * instructions until the results are needed.
2969 if (V3D_DEBUG
& (V3D_DEBUG_VIR
|
2970 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
))) {
2971 fprintf(stderr
, "%s prog %d/%d VIR:\n",
2972 vir_get_stage_name(c
),
2973 c
->program_id
, c
->variant_id
);
2975 fprintf(stderr
, "\n");
2978 /* Attempt to allocate registers for the temporaries. If we fail,
2979 * reduce thread count and try again.
2981 int min_threads
= (c
->devinfo
->ver
>= 41) ? 2 : 1;
2982 struct qpu_reg
*temp_registers
;
2985 temp_registers
= v3d_register_allocate(c
, &spilled
);
2992 if (c
->threads
== min_threads
) {
2993 fprintf(stderr
, "Failed to register allocate at %d threads:\n",
3002 if (c
->threads
== 1)
3003 vir_remove_thrsw(c
);
3007 (V3D_DEBUG
& (V3D_DEBUG_VIR
|
3008 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
)))) {
3009 fprintf(stderr
, "%s prog %d/%d spilled VIR:\n",
3010 vir_get_stage_name(c
),
3011 c
->program_id
, c
->variant_id
);
3013 fprintf(stderr
, "\n");
3016 v3d_vir_to_qpu(c
, temp_registers
);