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11c49f5efa9302f2a8be59c32e647bac926d9719
[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
34
35 #define GENERAL_TMU_LOOKUP_PER_QUAD (0 << 7)
36 #define GENERAL_TMU_LOOKUP_PER_PIXEL (1 << 7)
37 #define GENERAL_TMU_READ_OP_PREFETCH (0 << 3)
38 #define GENERAL_TMU_READ_OP_CACHE_CLEAR (1 << 3)
39 #define GENERAL_TMU_READ_OP_CACHE_FLUSH (3 << 3)
40 #define GENERAL_TMU_READ_OP_CACHE_CLEAN (3 << 3)
41 #define GENERAL_TMU_READ_OP_CACHE_L1T_CLEAR (4 << 3)
42 #define GENERAL_TMU_READ_OP_CACHE_L1T_FLUSH_AGGREGATION (5 << 3)
43 #define GENERAL_TMU_READ_OP_ATOMIC_INC (8 << 3)
44 #define GENERAL_TMU_READ_OP_ATOMIC_DEC (9 << 3)
45 #define GENERAL_TMU_READ_OP_ATOMIC_NOT (10 << 3)
46 #define GENERAL_TMU_READ_OP_READ (15 << 3)
47 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_I (0 << 0)
48 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_I (1 << 0)
49 #define GENERAL_TMU_LOOKUP_TYPE_VEC2 (2 << 0)
50 #define GENERAL_TMU_LOOKUP_TYPE_VEC3 (3 << 0)
51 #define GENERAL_TMU_LOOKUP_TYPE_VEC4 (4 << 0)
52 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_UI (5 << 0)
53 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_UI (6 << 0)
54 #define GENERAL_TMU_LOOKUP_TYPE_32BIT_UI (7 << 0)
55
56 #define GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP (0 << 3)
57 #define GENERAL_TMU_WRITE_OP_ATOMIC_SUB_WRAP (1 << 3)
58 #define GENERAL_TMU_WRITE_OP_ATOMIC_XCHG (2 << 3)
59 #define GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG (3 << 3)
60 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMIN (4 << 3)
61 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMAX (5 << 3)
62 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMIN (6 << 3)
63 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMAX (7 << 3)
64 #define GENERAL_TMU_WRITE_OP_ATOMIC_AND (8 << 3)
65 #define GENERAL_TMU_WRITE_OP_ATOMIC_OR (9 << 3)
66 #define GENERAL_TMU_WRITE_OP_ATOMIC_XOR (10 << 3)
67 #define GENERAL_TMU_WRITE_OP_WRITE (15 << 3)
68
69 #define V3D_TSY_SET_QUORUM 0
70 #define V3D_TSY_INC_WAITERS 1
71 #define V3D_TSY_DEC_WAITERS 2
72 #define V3D_TSY_INC_QUORUM 3
73 #define V3D_TSY_DEC_QUORUM 4
74 #define V3D_TSY_FREE_ALL 5
75 #define V3D_TSY_RELEASE 6
76 #define V3D_TSY_ACQUIRE 7
77 #define V3D_TSY_WAIT 8
78 #define V3D_TSY_WAIT_INC 9
79 #define V3D_TSY_WAIT_CHECK 10
80 #define V3D_TSY_WAIT_INC_CHECK 11
81 #define V3D_TSY_WAIT_CV 12
82 #define V3D_TSY_INC_SEMAPHORE 13
83 #define V3D_TSY_DEC_SEMAPHORE 14
84 #define V3D_TSY_SET_QUORUM_FREE_ALL 15
85
86 static void
87 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
88
89 static void
90 resize_qreg_array(struct v3d_compile *c,
91 struct qreg **regs,
92 uint32_t *size,
93 uint32_t decl_size)
94 {
95 if (*size >= decl_size)
96 return;
97
98 uint32_t old_size = *size;
99 *size = MAX2(*size * 2, decl_size);
100 *regs = reralloc(c, *regs, struct qreg, *size);
101 if (!*regs) {
102 fprintf(stderr, "Malloc failure\n");
103 abort();
104 }
105
106 for (uint32_t i = old_size; i < *size; i++)
107 (*regs)[i] = c->undef;
108 }
109
110 void
111 vir_emit_thrsw(struct v3d_compile *c)
112 {
113 if (c->threads == 1)
114 return;
115
116 /* Always thread switch after each texture operation for now.
117 *
118 * We could do better by batching a bunch of texture fetches up and
119 * then doing one thread switch and collecting all their results
120 * afterward.
121 */
122 c->last_thrsw = vir_NOP(c);
123 c->last_thrsw->qpu.sig.thrsw = true;
124 c->last_thrsw_at_top_level = !c->in_control_flow;
125 }
126
127 static uint32_t
128 v3d_general_tmu_op(nir_intrinsic_instr *instr)
129 {
130 switch (instr->intrinsic) {
131 case nir_intrinsic_load_ssbo:
132 case nir_intrinsic_load_ubo:
133 case nir_intrinsic_load_uniform:
134 case nir_intrinsic_load_shared:
135 case nir_intrinsic_load_scratch:
136 return GENERAL_TMU_READ_OP_READ;
137 case nir_intrinsic_store_ssbo:
138 case nir_intrinsic_store_shared:
139 case nir_intrinsic_store_scratch:
140 return GENERAL_TMU_WRITE_OP_WRITE;
141 case nir_intrinsic_ssbo_atomic_add:
142 case nir_intrinsic_shared_atomic_add:
143 return GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP;
144 case nir_intrinsic_ssbo_atomic_imin:
145 case nir_intrinsic_shared_atomic_imin:
146 return GENERAL_TMU_WRITE_OP_ATOMIC_SMIN;
147 case nir_intrinsic_ssbo_atomic_umin:
148 case nir_intrinsic_shared_atomic_umin:
149 return GENERAL_TMU_WRITE_OP_ATOMIC_UMIN;
150 case nir_intrinsic_ssbo_atomic_imax:
151 case nir_intrinsic_shared_atomic_imax:
152 return GENERAL_TMU_WRITE_OP_ATOMIC_SMAX;
153 case nir_intrinsic_ssbo_atomic_umax:
154 case nir_intrinsic_shared_atomic_umax:
155 return GENERAL_TMU_WRITE_OP_ATOMIC_UMAX;
156 case nir_intrinsic_ssbo_atomic_and:
157 case nir_intrinsic_shared_atomic_and:
158 return GENERAL_TMU_WRITE_OP_ATOMIC_AND;
159 case nir_intrinsic_ssbo_atomic_or:
160 case nir_intrinsic_shared_atomic_or:
161 return GENERAL_TMU_WRITE_OP_ATOMIC_OR;
162 case nir_intrinsic_ssbo_atomic_xor:
163 case nir_intrinsic_shared_atomic_xor:
164 return GENERAL_TMU_WRITE_OP_ATOMIC_XOR;
165 case nir_intrinsic_ssbo_atomic_exchange:
166 case nir_intrinsic_shared_atomic_exchange:
167 return GENERAL_TMU_WRITE_OP_ATOMIC_XCHG;
168 case nir_intrinsic_ssbo_atomic_comp_swap:
169 case nir_intrinsic_shared_atomic_comp_swap:
170 return GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG;
171 default:
172 unreachable("unknown intrinsic op");
173 }
174 }
175
176 /**
177 * Implements indirect uniform loads and SSBO accesses through the TMU general
178 * memory access interface.
179 */
180 static void
181 ntq_emit_tmu_general(struct v3d_compile *c, nir_intrinsic_instr *instr,
182 bool is_shared_or_scratch)
183 {
184 /* XXX perf: We should turn add/sub of 1 to inc/dec. Perhaps NIR
185 * wants to have support for inc/dec?
186 */
187
188 uint32_t tmu_op = v3d_general_tmu_op(instr);
189 bool is_store = (instr->intrinsic == nir_intrinsic_store_ssbo ||
190 instr->intrinsic == nir_intrinsic_store_scratch ||
191 instr->intrinsic == nir_intrinsic_store_shared);
192 bool has_index = !is_shared_or_scratch;
193
194 int offset_src;
195 int tmu_writes = 1; /* address */
196 if (instr->intrinsic == nir_intrinsic_load_uniform) {
197 offset_src = 0;
198 } else if (instr->intrinsic == nir_intrinsic_load_ssbo ||
199 instr->intrinsic == nir_intrinsic_load_ubo ||
200 instr->intrinsic == nir_intrinsic_load_scratch ||
201 instr->intrinsic == nir_intrinsic_load_shared) {
202 offset_src = 0 + has_index;
203 } else if (is_store) {
204 offset_src = 1 + has_index;
205 for (int i = 0; i < instr->num_components; i++) {
206 vir_MOV_dest(c,
207 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
208 ntq_get_src(c, instr->src[0], i));
209 tmu_writes++;
210 }
211 } else {
212 offset_src = 0 + has_index;
213 vir_MOV_dest(c,
214 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
215 ntq_get_src(c, instr->src[1 + has_index], 0));
216 tmu_writes++;
217 if (tmu_op == GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG) {
218 vir_MOV_dest(c,
219 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
220 ntq_get_src(c, instr->src[2 + has_index],
221 0));
222 tmu_writes++;
223 }
224 }
225
226 bool dynamic_src = !nir_src_is_const(instr->src[offset_src]);
227 uint32_t const_offset = 0;
228 if (!dynamic_src)
229 const_offset = nir_src_as_uint(instr->src[offset_src]);
230
231 /* Make sure we won't exceed the 16-entry TMU fifo if each thread is
232 * storing at the same time.
233 */
234 while (tmu_writes > 16 / c->threads)
235 c->threads /= 2;
236
237 struct qreg offset;
238 if (instr->intrinsic == nir_intrinsic_load_uniform) {
239 const_offset += nir_intrinsic_base(instr);
240 offset = vir_uniform(c, QUNIFORM_UBO_ADDR,
241 v3d_unit_data_create(0, const_offset));
242 const_offset = 0;
243 } else if (instr->intrinsic == nir_intrinsic_load_ubo) {
244 uint32_t index = nir_src_as_uint(instr->src[0]) + 1;
245 /* Note that QUNIFORM_UBO_ADDR takes a UBO index shifted up by
246 * 1 (0 is gallium's constant buffer 0).
247 */
248 offset = vir_uniform(c, QUNIFORM_UBO_ADDR,
249 v3d_unit_data_create(index, const_offset));
250 const_offset = 0;
251 } else if (is_shared_or_scratch) {
252 /* Shared and scratch variables have no buffer index, and all
253 * start from a common base that we set up at the start of
254 * dispatch.
255 */
256 if (instr->intrinsic == nir_intrinsic_load_scratch ||
257 instr->intrinsic == nir_intrinsic_store_scratch) {
258 offset = c->spill_base;
259 } else {
260 offset = c->cs_shared_offset;
261 const_offset += nir_intrinsic_base(instr);
262 }
263 } else {
264 offset = vir_uniform(c, QUNIFORM_SSBO_OFFSET,
265 nir_src_as_uint(instr->src[is_store ?
266 1 : 0]));
267 }
268
269 uint32_t config = (0xffffff00 |
270 tmu_op |
271 GENERAL_TMU_LOOKUP_PER_PIXEL);
272 if (instr->num_components == 1) {
273 config |= GENERAL_TMU_LOOKUP_TYPE_32BIT_UI;
274 } else {
275 config |= (GENERAL_TMU_LOOKUP_TYPE_VEC2 +
276 instr->num_components - 2);
277 }
278
279 if (vir_in_nonuniform_control_flow(c)) {
280 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
281 V3D_QPU_PF_PUSHZ);
282 }
283
284 struct qreg tmua;
285 if (config == ~0)
286 tmua = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA);
287 else
288 tmua = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUAU);
289
290 struct qinst *tmu;
291 if (dynamic_src) {
292 if (const_offset != 0) {
293 offset = vir_ADD(c, offset,
294 vir_uniform_ui(c, const_offset));
295 }
296 tmu = vir_ADD_dest(c, tmua, offset,
297 ntq_get_src(c, instr->src[offset_src], 0));
298 } else {
299 if (const_offset != 0) {
300 tmu = vir_ADD_dest(c, tmua, offset,
301 vir_uniform_ui(c, const_offset));
302 } else {
303 tmu = vir_MOV_dest(c, tmua, offset);
304 }
305 }
306
307 if (config != ~0) {
308 tmu->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT,
309 config);
310 }
311
312 if (vir_in_nonuniform_control_flow(c))
313 vir_set_cond(tmu, V3D_QPU_COND_IFA);
314
315 vir_emit_thrsw(c);
316
317 /* Read the result, or wait for the TMU op to complete. */
318 for (int i = 0; i < nir_intrinsic_dest_components(instr); i++)
319 ntq_store_dest(c, &instr->dest, i, vir_MOV(c, vir_LDTMU(c)));
320
321 if (nir_intrinsic_dest_components(instr) == 0)
322 vir_TMUWT(c);
323 }
324
325 static struct qreg *
326 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
327 {
328 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
329 def->num_components);
330 _mesa_hash_table_insert(c->def_ht, def, qregs);
331 return qregs;
332 }
333
334 /**
335 * This function is responsible for getting VIR results into the associated
336 * storage for a NIR instruction.
337 *
338 * If it's a NIR SSA def, then we just set the associated hash table entry to
339 * the new result.
340 *
341 * If it's a NIR reg, then we need to update the existing qreg assigned to the
342 * NIR destination with the incoming value. To do that without introducing
343 * new MOVs, we require that the incoming qreg either be a uniform, or be
344 * SSA-defined by the previous VIR instruction in the block and rewritable by
345 * this function. That lets us sneak ahead and insert the SF flag beforehand
346 * (knowing that the previous instruction doesn't depend on flags) and rewrite
347 * its destination to be the NIR reg's destination
348 */
349 void
350 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
351 struct qreg result)
352 {
353 struct qinst *last_inst = NULL;
354 if (!list_empty(&c->cur_block->instructions))
355 last_inst = (struct qinst *)c->cur_block->instructions.prev;
356
357 assert((result.file == QFILE_TEMP &&
358 last_inst && last_inst == c->defs[result.index]));
359
360 if (dest->is_ssa) {
361 assert(chan < dest->ssa.num_components);
362
363 struct qreg *qregs;
364 struct hash_entry *entry =
365 _mesa_hash_table_search(c->def_ht, &dest->ssa);
366
367 if (entry)
368 qregs = entry->data;
369 else
370 qregs = ntq_init_ssa_def(c, &dest->ssa);
371
372 qregs[chan] = result;
373 } else {
374 nir_register *reg = dest->reg.reg;
375 assert(dest->reg.base_offset == 0);
376 assert(reg->num_array_elems == 0);
377 struct hash_entry *entry =
378 _mesa_hash_table_search(c->def_ht, reg);
379 struct qreg *qregs = entry->data;
380
381 /* Insert a MOV if the source wasn't an SSA def in the
382 * previous instruction.
383 */
384 if ((vir_in_nonuniform_control_flow(c) &&
385 c->defs[last_inst->dst.index]->qpu.sig.ldunif)) {
386 result = vir_MOV(c, result);
387 last_inst = c->defs[result.index];
388 }
389
390 /* We know they're both temps, so just rewrite index. */
391 c->defs[last_inst->dst.index] = NULL;
392 last_inst->dst.index = qregs[chan].index;
393
394 /* If we're in control flow, then make this update of the reg
395 * conditional on the execution mask.
396 */
397 if (vir_in_nonuniform_control_flow(c)) {
398 last_inst->dst.index = qregs[chan].index;
399
400 /* Set the flags to the current exec mask.
401 */
402 c->cursor = vir_before_inst(last_inst);
403 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
404 V3D_QPU_PF_PUSHZ);
405 c->cursor = vir_after_inst(last_inst);
406
407 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
408 }
409 }
410 }
411
412 struct qreg
413 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
414 {
415 struct hash_entry *entry;
416 if (src.is_ssa) {
417 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
418 assert(i < src.ssa->num_components);
419 } else {
420 nir_register *reg = src.reg.reg;
421 entry = _mesa_hash_table_search(c->def_ht, reg);
422 assert(reg->num_array_elems == 0);
423 assert(src.reg.base_offset == 0);
424 assert(i < reg->num_components);
425 }
426
427 struct qreg *qregs = entry->data;
428 return qregs[i];
429 }
430
431 static struct qreg
432 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
433 unsigned src)
434 {
435 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
436 unsigned chan = ffs(instr->dest.write_mask) - 1;
437 struct qreg r = ntq_get_src(c, instr->src[src].src,
438 instr->src[src].swizzle[chan]);
439
440 assert(!instr->src[src].abs);
441 assert(!instr->src[src].negate);
442
443 return r;
444 };
445
446 static struct qreg
447 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
448 {
449 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
450 }
451
452 static void
453 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
454 {
455 unsigned unit = instr->texture_index;
456 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
457 int dest_size = nir_tex_instr_dest_size(instr);
458
459 struct qreg lod = c->undef;
460 if (lod_index != -1)
461 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
462
463 for (int i = 0; i < dest_size; i++) {
464 assert(i < 3);
465 enum quniform_contents contents;
466
467 if (instr->is_array && i == dest_size - 1)
468 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
469 else
470 contents = QUNIFORM_TEXTURE_WIDTH + i;
471
472 struct qreg size = vir_uniform(c, contents, unit);
473
474 switch (instr->sampler_dim) {
475 case GLSL_SAMPLER_DIM_1D:
476 case GLSL_SAMPLER_DIM_2D:
477 case GLSL_SAMPLER_DIM_MS:
478 case GLSL_SAMPLER_DIM_3D:
479 case GLSL_SAMPLER_DIM_CUBE:
480 /* Don't minify the array size. */
481 if (!(instr->is_array && i == dest_size - 1)) {
482 size = ntq_minify(c, size, lod);
483 }
484 break;
485
486 case GLSL_SAMPLER_DIM_RECT:
487 /* There's no LOD field for rects */
488 break;
489
490 default:
491 unreachable("Bad sampler type");
492 }
493
494 ntq_store_dest(c, &instr->dest, i, size);
495 }
496 }
497
498 static void
499 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
500 {
501 unsigned unit = instr->texture_index;
502
503 /* Since each texture sampling op requires uploading uniforms to
504 * reference the texture, there's no HW support for texture size and
505 * you just upload uniforms containing the size.
506 */
507 switch (instr->op) {
508 case nir_texop_query_levels:
509 ntq_store_dest(c, &instr->dest, 0,
510 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
511 return;
512 case nir_texop_txs:
513 ntq_emit_txs(c, instr);
514 return;
515 default:
516 break;
517 }
518
519 if (c->devinfo->ver >= 40)
520 v3d40_vir_emit_tex(c, instr);
521 else
522 v3d33_vir_emit_tex(c, instr);
523 }
524
525 static struct qreg
526 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
527 {
528 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
529 if (is_cos)
530 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
531
532 struct qreg periods = vir_FROUND(c, input);
533 struct qreg sin_output = vir_SIN(c, vir_FSUB(c, input, periods));
534 return vir_XOR(c, sin_output, vir_SHL(c,
535 vir_FTOIN(c, periods),
536 vir_uniform_ui(c, -1)));
537 }
538
539 static struct qreg
540 ntq_fsign(struct v3d_compile *c, struct qreg src)
541 {
542 struct qreg t = vir_get_temp(c);
543
544 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
545 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHZ);
546 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
547 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHN);
548 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
549 return vir_MOV(c, t);
550 }
551
552 static void
553 emit_fragcoord_input(struct v3d_compile *c, int attr)
554 {
555 c->inputs[attr * 4 + 0] = vir_FXCD(c);
556 c->inputs[attr * 4 + 1] = vir_FYCD(c);
557 c->inputs[attr * 4 + 2] = c->payload_z;
558 c->inputs[attr * 4 + 3] = vir_RECIP(c, c->payload_w);
559 }
560
561 static struct qreg
562 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
563 uint8_t swizzle, int array_index)
564 {
565 struct qreg r3 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R3);
566 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
567
568 struct qreg vary;
569 if (c->devinfo->ver >= 41) {
570 struct qinst *ldvary = vir_add_inst(V3D_QPU_A_NOP, c->undef,
571 c->undef, c->undef);
572 ldvary->qpu.sig.ldvary = true;
573 vary = vir_emit_def(c, ldvary);
574 } else {
575 vir_NOP(c)->qpu.sig.ldvary = true;
576 vary = r3;
577 }
578
579 /* For gl_PointCoord input or distance along a line, we'll be called
580 * with no nir_variable, and we don't count toward VPM size so we
581 * don't track an input slot.
582 */
583 if (!var) {
584 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
585 }
586
587 int i = c->num_inputs++;
588 c->input_slots[i] =
589 v3d_slot_from_slot_and_component(var->data.location +
590 array_index, swizzle);
591
592 switch (var->data.interpolation) {
593 case INTERP_MODE_NONE:
594 /* If a gl_FrontColor or gl_BackColor input has no interp
595 * qualifier, then if we're using glShadeModel(GL_FLAT) it
596 * needs to be flat shaded.
597 */
598 switch (var->data.location + array_index) {
599 case VARYING_SLOT_COL0:
600 case VARYING_SLOT_COL1:
601 case VARYING_SLOT_BFC0:
602 case VARYING_SLOT_BFC1:
603 if (c->fs_key->shade_model_flat) {
604 BITSET_SET(c->flat_shade_flags, i);
605 vir_MOV_dest(c, c->undef, vary);
606 return vir_MOV(c, r5);
607 } else {
608 return vir_FADD(c, vir_FMUL(c, vary,
609 c->payload_w), r5);
610 }
611 default:
612 break;
613 }
614 /* FALLTHROUGH */
615 case INTERP_MODE_SMOOTH:
616 if (var->data.centroid) {
617 BITSET_SET(c->centroid_flags, i);
618 return vir_FADD(c, vir_FMUL(c, vary,
619 c->payload_w_centroid), r5);
620 } else {
621 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
622 }
623 case INTERP_MODE_NOPERSPECTIVE:
624 BITSET_SET(c->noperspective_flags, i);
625 return vir_FADD(c, vir_MOV(c, vary), r5);
626 case INTERP_MODE_FLAT:
627 BITSET_SET(c->flat_shade_flags, i);
628 vir_MOV_dest(c, c->undef, vary);
629 return vir_MOV(c, r5);
630 default:
631 unreachable("Bad interp mode");
632 }
633 }
634
635 static void
636 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var,
637 int array_index)
638 {
639 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
640 int chan = var->data.location_frac + i;
641 c->inputs[attr * 4 + chan] =
642 emit_fragment_varying(c, var, chan, array_index);
643 }
644 }
645
646 static void
647 add_output(struct v3d_compile *c,
648 uint32_t decl_offset,
649 uint8_t slot,
650 uint8_t swizzle)
651 {
652 uint32_t old_array_size = c->outputs_array_size;
653 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
654 decl_offset + 1);
655
656 if (old_array_size != c->outputs_array_size) {
657 c->output_slots = reralloc(c,
658 c->output_slots,
659 struct v3d_varying_slot,
660 c->outputs_array_size);
661 }
662
663 c->output_slots[decl_offset] =
664 v3d_slot_from_slot_and_component(slot, swizzle);
665 }
666
667 /**
668 * If compare_instr is a valid comparison instruction, emits the
669 * compare_instr's comparison and returns the sel_instr's return value based
670 * on the compare_instr's result.
671 */
672 static bool
673 ntq_emit_comparison(struct v3d_compile *c,
674 nir_alu_instr *compare_instr,
675 enum v3d_qpu_cond *out_cond)
676 {
677 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
678 struct qreg src1;
679 if (nir_op_infos[compare_instr->op].num_inputs > 1)
680 src1 = ntq_get_alu_src(c, compare_instr, 1);
681 bool cond_invert = false;
682 struct qreg nop = vir_nop_reg();
683
684 switch (compare_instr->op) {
685 case nir_op_feq32:
686 case nir_op_seq:
687 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
688 break;
689 case nir_op_ieq32:
690 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
691 break;
692
693 case nir_op_fne32:
694 case nir_op_sne:
695 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
696 cond_invert = true;
697 break;
698 case nir_op_ine32:
699 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
700 cond_invert = true;
701 break;
702
703 case nir_op_fge32:
704 case nir_op_sge:
705 vir_set_pf(vir_FCMP_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
706 break;
707 case nir_op_ige32:
708 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
709 cond_invert = true;
710 break;
711 case nir_op_uge32:
712 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
713 cond_invert = true;
714 break;
715
716 case nir_op_slt:
717 case nir_op_flt32:
718 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHN);
719 break;
720 case nir_op_ilt32:
721 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
722 break;
723 case nir_op_ult32:
724 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
725 break;
726
727 case nir_op_i2b32:
728 vir_set_pf(vir_MOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ);
729 cond_invert = true;
730 break;
731
732 case nir_op_f2b32:
733 vir_set_pf(vir_FMOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ);
734 cond_invert = true;
735 break;
736
737 default:
738 return false;
739 }
740
741 *out_cond = cond_invert ? V3D_QPU_COND_IFNA : V3D_QPU_COND_IFA;
742
743 return true;
744 }
745
746 /* Finds an ALU instruction that generates our src value that could
747 * (potentially) be greedily emitted in the consuming instruction.
748 */
749 static struct nir_alu_instr *
750 ntq_get_alu_parent(nir_src src)
751 {
752 if (!src.is_ssa || src.ssa->parent_instr->type != nir_instr_type_alu)
753 return NULL;
754 nir_alu_instr *instr = nir_instr_as_alu(src.ssa->parent_instr);
755 if (!instr)
756 return NULL;
757
758 /* If the ALU instr's srcs are non-SSA, then we would have to avoid
759 * moving emission of the ALU instr down past another write of the
760 * src.
761 */
762 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
763 if (!instr->src[i].src.is_ssa)
764 return NULL;
765 }
766
767 return instr;
768 }
769
770 /* Turns a NIR bool into a condition code to predicate on. */
771 static enum v3d_qpu_cond
772 ntq_emit_bool_to_cond(struct v3d_compile *c, nir_src src)
773 {
774 nir_alu_instr *compare = ntq_get_alu_parent(src);
775 if (!compare)
776 goto out;
777
778 enum v3d_qpu_cond cond;
779 if (ntq_emit_comparison(c, compare, &cond))
780 return cond;
781
782 out:
783 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), ntq_get_src(c, src, 0)),
784 V3D_QPU_PF_PUSHZ);
785 return V3D_QPU_COND_IFNA;
786 }
787
788 static void
789 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
790 {
791 /* This should always be lowered to ALU operations for V3D. */
792 assert(!instr->dest.saturate);
793
794 /* Vectors are special in that they have non-scalarized writemasks,
795 * and just take the first swizzle channel for each argument in order
796 * into each writemask channel.
797 */
798 if (instr->op == nir_op_vec2 ||
799 instr->op == nir_op_vec3 ||
800 instr->op == nir_op_vec4) {
801 struct qreg srcs[4];
802 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
803 srcs[i] = ntq_get_src(c, instr->src[i].src,
804 instr->src[i].swizzle[0]);
805 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
806 ntq_store_dest(c, &instr->dest.dest, i,
807 vir_MOV(c, srcs[i]));
808 return;
809 }
810
811 /* General case: We can just grab the one used channel per src. */
812 struct qreg src[nir_op_infos[instr->op].num_inputs];
813 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
814 src[i] = ntq_get_alu_src(c, instr, i);
815 }
816
817 struct qreg result;
818
819 switch (instr->op) {
820 case nir_op_fmov:
821 case nir_op_imov:
822 result = vir_MOV(c, src[0]);
823 break;
824
825 case nir_op_fneg:
826 result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
827 break;
828 case nir_op_ineg:
829 result = vir_NEG(c, src[0]);
830 break;
831
832 case nir_op_fmul:
833 result = vir_FMUL(c, src[0], src[1]);
834 break;
835 case nir_op_fadd:
836 result = vir_FADD(c, src[0], src[1]);
837 break;
838 case nir_op_fsub:
839 result = vir_FSUB(c, src[0], src[1]);
840 break;
841 case nir_op_fmin:
842 result = vir_FMIN(c, src[0], src[1]);
843 break;
844 case nir_op_fmax:
845 result = vir_FMAX(c, src[0], src[1]);
846 break;
847
848 case nir_op_f2i32: {
849 nir_alu_instr *src0_alu = ntq_get_alu_parent(instr->src[0].src);
850 if (src0_alu && src0_alu->op == nir_op_fround_even) {
851 result = vir_FTOIN(c, ntq_get_alu_src(c, src0_alu, 0));
852 } else {
853 result = vir_FTOIZ(c, src[0]);
854 }
855 break;
856 }
857
858 case nir_op_f2u32:
859 result = vir_FTOUZ(c, src[0]);
860 break;
861 case nir_op_i2f32:
862 result = vir_ITOF(c, src[0]);
863 break;
864 case nir_op_u2f32:
865 result = vir_UTOF(c, src[0]);
866 break;
867 case nir_op_b2f32:
868 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
869 break;
870 case nir_op_b2i32:
871 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
872 break;
873
874 case nir_op_iadd:
875 result = vir_ADD(c, src[0], src[1]);
876 break;
877 case nir_op_ushr:
878 result = vir_SHR(c, src[0], src[1]);
879 break;
880 case nir_op_isub:
881 result = vir_SUB(c, src[0], src[1]);
882 break;
883 case nir_op_ishr:
884 result = vir_ASR(c, src[0], src[1]);
885 break;
886 case nir_op_ishl:
887 result = vir_SHL(c, src[0], src[1]);
888 break;
889 case nir_op_imin:
890 result = vir_MIN(c, src[0], src[1]);
891 break;
892 case nir_op_umin:
893 result = vir_UMIN(c, src[0], src[1]);
894 break;
895 case nir_op_imax:
896 result = vir_MAX(c, src[0], src[1]);
897 break;
898 case nir_op_umax:
899 result = vir_UMAX(c, src[0], src[1]);
900 break;
901 case nir_op_iand:
902 result = vir_AND(c, src[0], src[1]);
903 break;
904 case nir_op_ior:
905 result = vir_OR(c, src[0], src[1]);
906 break;
907 case nir_op_ixor:
908 result = vir_XOR(c, src[0], src[1]);
909 break;
910 case nir_op_inot:
911 result = vir_NOT(c, src[0]);
912 break;
913
914 case nir_op_ufind_msb:
915 result = vir_SUB(c, vir_uniform_ui(c, 31), vir_CLZ(c, src[0]));
916 break;
917
918 case nir_op_imul:
919 result = vir_UMUL(c, src[0], src[1]);
920 break;
921
922 case nir_op_seq:
923 case nir_op_sne:
924 case nir_op_sge:
925 case nir_op_slt: {
926 enum v3d_qpu_cond cond;
927 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
928 assert(ok);
929 result = vir_MOV(c, vir_SEL(c, cond,
930 vir_uniform_f(c, 1.0),
931 vir_uniform_f(c, 0.0)));
932 break;
933 }
934
935 case nir_op_i2b32:
936 case nir_op_f2b32:
937 case nir_op_feq32:
938 case nir_op_fne32:
939 case nir_op_fge32:
940 case nir_op_flt32:
941 case nir_op_ieq32:
942 case nir_op_ine32:
943 case nir_op_ige32:
944 case nir_op_uge32:
945 case nir_op_ilt32:
946 case nir_op_ult32: {
947 enum v3d_qpu_cond cond;
948 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
949 assert(ok);
950 result = vir_MOV(c, vir_SEL(c, cond,
951 vir_uniform_ui(c, ~0),
952 vir_uniform_ui(c, 0)));
953 break;
954 }
955
956 case nir_op_b32csel:
957 result = vir_MOV(c,
958 vir_SEL(c,
959 ntq_emit_bool_to_cond(c, instr->src[0].src),
960 src[1], src[2]));
961 break;
962
963 case nir_op_fcsel:
964 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), src[0]),
965 V3D_QPU_PF_PUSHZ);
966 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
967 src[1], src[2]));
968 break;
969
970 case nir_op_frcp:
971 result = vir_RECIP(c, src[0]);
972 break;
973 case nir_op_frsq:
974 result = vir_RSQRT(c, src[0]);
975 break;
976 case nir_op_fexp2:
977 result = vir_EXP(c, src[0]);
978 break;
979 case nir_op_flog2:
980 result = vir_LOG(c, src[0]);
981 break;
982
983 case nir_op_fceil:
984 result = vir_FCEIL(c, src[0]);
985 break;
986 case nir_op_ffloor:
987 result = vir_FFLOOR(c, src[0]);
988 break;
989 case nir_op_fround_even:
990 result = vir_FROUND(c, src[0]);
991 break;
992 case nir_op_ftrunc:
993 result = vir_FTRUNC(c, src[0]);
994 break;
995
996 case nir_op_fsin:
997 result = ntq_fsincos(c, src[0], false);
998 break;
999 case nir_op_fcos:
1000 result = ntq_fsincos(c, src[0], true);
1001 break;
1002
1003 case nir_op_fsign:
1004 result = ntq_fsign(c, src[0]);
1005 break;
1006
1007 case nir_op_fabs: {
1008 result = vir_FMOV(c, src[0]);
1009 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
1010 break;
1011 }
1012
1013 case nir_op_iabs:
1014 result = vir_MAX(c, src[0], vir_NEG(c, src[0]));
1015 break;
1016
1017 case nir_op_fddx:
1018 case nir_op_fddx_coarse:
1019 case nir_op_fddx_fine:
1020 result = vir_FDX(c, src[0]);
1021 break;
1022
1023 case nir_op_fddy:
1024 case nir_op_fddy_coarse:
1025 case nir_op_fddy_fine:
1026 result = vir_FDY(c, src[0]);
1027 break;
1028
1029 case nir_op_uadd_carry:
1030 vir_set_pf(vir_ADD_dest(c, vir_nop_reg(), src[0], src[1]),
1031 V3D_QPU_PF_PUSHC);
1032 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1033 vir_uniform_ui(c, ~0),
1034 vir_uniform_ui(c, 0)));
1035 break;
1036
1037 case nir_op_pack_half_2x16_split:
1038 result = vir_VFPACK(c, src[0], src[1]);
1039 break;
1040
1041 case nir_op_unpack_half_2x16_split_x:
1042 result = vir_FMOV(c, src[0]);
1043 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_L);
1044 break;
1045
1046 case nir_op_unpack_half_2x16_split_y:
1047 result = vir_FMOV(c, src[0]);
1048 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_H);
1049 break;
1050
1051 default:
1052 fprintf(stderr, "unknown NIR ALU inst: ");
1053 nir_print_instr(&instr->instr, stderr);
1054 fprintf(stderr, "\n");
1055 abort();
1056 }
1057
1058 /* We have a scalar result, so the instruction should only have a
1059 * single channel written to.
1060 */
1061 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
1062 ntq_store_dest(c, &instr->dest.dest,
1063 ffs(instr->dest.write_mask) - 1, result);
1064 }
1065
1066 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
1067 * specifier. They come from a register that's preloaded with 0xffffffff
1068 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
1069 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
1070 */
1071 #define TLB_TYPE_F16_COLOR (3 << 6)
1072 #define TLB_TYPE_I32_COLOR (1 << 6)
1073 #define TLB_TYPE_F32_COLOR (0 << 6)
1074 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
1075 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
1076 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
1077 #define TLB_F16_SWAP_HI_LO (1 << 1)
1078 #define TLB_VEC_SIZE_4_F16 (1 << 0)
1079 #define TLB_VEC_SIZE_2_F16 (0 << 0)
1080 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
1081
1082 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
1083 * flag is set.
1084 */
1085 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
1086 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
1087 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
1088 #define TLB_V42_DEPTH_TYPE_INVARIANT (0 << 3) /* Unmodified sideband input used */
1089 #define TLB_V42_DEPTH_TYPE_PER_PIXEL (1 << 3) /* QPU result used */
1090
1091 /* Stencil is a single 32-bit write. */
1092 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1093
1094 static void
1095 emit_frag_end(struct v3d_compile *c)
1096 {
1097 /* XXX
1098 if (c->output_sample_mask_index != -1) {
1099 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1100 }
1101 */
1102
1103 bool has_any_tlb_color_write = false;
1104 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1105 if (c->fs_key->cbufs & (1 << rt) && c->output_color_var[rt])
1106 has_any_tlb_color_write = true;
1107 }
1108
1109 if (c->fs_key->sample_alpha_to_coverage && c->output_color_var[0]) {
1110 struct nir_variable *var = c->output_color_var[0];
1111 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1112
1113 vir_SETMSF_dest(c, vir_nop_reg(),
1114 vir_AND(c,
1115 vir_MSF(c),
1116 vir_FTOC(c, color[3])));
1117 }
1118
1119 struct qreg tlb_reg = vir_magic_reg(V3D_QPU_WADDR_TLB);
1120 struct qreg tlbu_reg = vir_magic_reg(V3D_QPU_WADDR_TLBU);
1121 if (c->output_position_index != -1) {
1122 struct qinst *inst = vir_MOV_dest(c, tlbu_reg,
1123 c->outputs[c->output_position_index]);
1124 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1125
1126 if (c->devinfo->ver >= 42) {
1127 tlb_specifier |= (TLB_V42_DEPTH_TYPE_PER_PIXEL |
1128 TLB_SAMPLE_MODE_PER_PIXEL);
1129 } else
1130 tlb_specifier |= TLB_DEPTH_TYPE_PER_PIXEL;
1131
1132 inst->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT,
1133 tlb_specifier |
1134 0xffffff00);
1135 c->writes_z = true;
1136 } else if (c->s->info.fs.uses_discard ||
1137 !c->s->info.fs.early_fragment_tests ||
1138 c->fs_key->sample_alpha_to_coverage ||
1139 !has_any_tlb_color_write) {
1140 /* Emit passthrough Z if it needed to be delayed until shader
1141 * end due to potential discards.
1142 *
1143 * Since (single-threaded) fragment shaders always need a TLB
1144 * write, emit passthrouh Z if we didn't have any color
1145 * buffers and flag us as potentially discarding, so that we
1146 * can use Z as the TLB write.
1147 */
1148 c->s->info.fs.uses_discard = true;
1149
1150 struct qinst *inst = vir_MOV_dest(c, tlbu_reg,
1151 vir_nop_reg());
1152 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1153
1154 if (c->devinfo->ver >= 42) {
1155 /* The spec says the PER_PIXEL flag is ignored for
1156 * invariant writes, but the simulator demands it.
1157 */
1158 tlb_specifier |= (TLB_V42_DEPTH_TYPE_INVARIANT |
1159 TLB_SAMPLE_MODE_PER_PIXEL);
1160 } else {
1161 tlb_specifier |= TLB_DEPTH_TYPE_INVARIANT;
1162 }
1163
1164 inst->uniform = vir_get_uniform_index(c,
1165 QUNIFORM_CONSTANT,
1166 tlb_specifier |
1167 0xffffff00);
1168 c->writes_z = true;
1169 }
1170
1171 /* XXX: Performance improvement: Merge Z write and color writes TLB
1172 * uniform setup
1173 */
1174
1175 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1176 if (!(c->fs_key->cbufs & (1 << rt)) || !c->output_color_var[rt])
1177 continue;
1178
1179 nir_variable *var = c->output_color_var[rt];
1180 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1181 int num_components = glsl_get_vector_elements(var->type);
1182 uint32_t conf = 0xffffff00;
1183 struct qinst *inst;
1184
1185 conf |= TLB_SAMPLE_MODE_PER_PIXEL;
1186 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1187
1188 if (c->fs_key->swap_color_rb & (1 << rt))
1189 num_components = MAX2(num_components, 3);
1190
1191 assert(num_components != 0);
1192 switch (glsl_get_base_type(var->type)) {
1193 case GLSL_TYPE_UINT:
1194 case GLSL_TYPE_INT:
1195 /* The F32 vs I32 distinction was dropped in 4.2. */
1196 if (c->devinfo->ver < 42)
1197 conf |= TLB_TYPE_I32_COLOR;
1198 else
1199 conf |= TLB_TYPE_F32_COLOR;
1200 conf |= ((num_components - 1) <<
1201 TLB_VEC_SIZE_MINUS_1_SHIFT);
1202
1203 inst = vir_MOV_dest(c, tlbu_reg, color[0]);
1204 inst->uniform = vir_get_uniform_index(c,
1205 QUNIFORM_CONSTANT,
1206 conf);
1207
1208 for (int i = 1; i < num_components; i++) {
1209 inst = vir_MOV_dest(c, tlb_reg, color[i]);
1210 }
1211 break;
1212
1213 default: {
1214 struct qreg r = color[0];
1215 struct qreg g = color[1];
1216 struct qreg b = color[2];
1217 struct qreg a = color[3];
1218
1219 if (c->fs_key->f32_color_rb & (1 << rt)) {
1220 conf |= TLB_TYPE_F32_COLOR;
1221 conf |= ((num_components - 1) <<
1222 TLB_VEC_SIZE_MINUS_1_SHIFT);
1223 } else {
1224 conf |= TLB_TYPE_F16_COLOR;
1225 conf |= TLB_F16_SWAP_HI_LO;
1226 if (num_components >= 3)
1227 conf |= TLB_VEC_SIZE_4_F16;
1228 else
1229 conf |= TLB_VEC_SIZE_2_F16;
1230 }
1231
1232 if (c->fs_key->swap_color_rb & (1 << rt)) {
1233 r = color[2];
1234 b = color[0];
1235 }
1236
1237 if (c->fs_key->sample_alpha_to_one)
1238 a = vir_uniform_f(c, 1.0);
1239
1240 if (c->fs_key->f32_color_rb & (1 << rt)) {
1241 inst = vir_MOV_dest(c, tlbu_reg, r);
1242 inst->uniform = vir_get_uniform_index(c,
1243 QUNIFORM_CONSTANT,
1244 conf);
1245
1246 if (num_components >= 2)
1247 vir_MOV_dest(c, tlb_reg, g);
1248 if (num_components >= 3)
1249 vir_MOV_dest(c, tlb_reg, b);
1250 if (num_components >= 4)
1251 vir_MOV_dest(c, tlb_reg, a);
1252 } else {
1253 inst = vir_VFPACK_dest(c, tlb_reg, r, g);
1254 if (conf != ~0) {
1255 inst->dst = tlbu_reg;
1256 inst->uniform = vir_get_uniform_index(c,
1257 QUNIFORM_CONSTANT,
1258 conf);
1259 }
1260
1261 if (num_components >= 3)
1262 inst = vir_VFPACK_dest(c, tlb_reg, b, a);
1263 }
1264 break;
1265 }
1266 }
1267 }
1268 }
1269
1270 static void
1271 vir_VPM_WRITE(struct v3d_compile *c, struct qreg val, uint32_t vpm_index)
1272 {
1273 if (c->devinfo->ver >= 40) {
1274 vir_STVPMV(c, vir_uniform_ui(c, vpm_index), val);
1275 } else {
1276 /* XXX: v3d33_vir_vpm_write_setup(c); */
1277 vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM), val);
1278 }
1279 }
1280
1281 static void
1282 emit_vert_end(struct v3d_compile *c)
1283 {
1284 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1285 */
1286 if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
1287 vir_VPMWT(c);
1288 }
1289
1290 void
1291 v3d_optimize_nir(struct nir_shader *s)
1292 {
1293 bool progress;
1294
1295 do {
1296 progress = false;
1297
1298 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1299 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1300 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1301 NIR_PASS(progress, s, nir_copy_prop);
1302 NIR_PASS(progress, s, nir_opt_remove_phis);
1303 NIR_PASS(progress, s, nir_opt_dce);
1304 NIR_PASS(progress, s, nir_opt_dead_cf);
1305 NIR_PASS(progress, s, nir_opt_cse);
1306 NIR_PASS(progress, s, nir_opt_peephole_select, 8, true, true);
1307 NIR_PASS(progress, s, nir_opt_algebraic);
1308 NIR_PASS(progress, s, nir_opt_constant_folding);
1309 NIR_PASS(progress, s, nir_opt_undef);
1310 } while (progress);
1311
1312 NIR_PASS(progress, s, nir_opt_move_load_ubo);
1313 }
1314
1315 static int
1316 driver_location_compare(const void *in_a, const void *in_b)
1317 {
1318 const nir_variable *const *a = in_a;
1319 const nir_variable *const *b = in_b;
1320
1321 return (*a)->data.driver_location - (*b)->data.driver_location;
1322 }
1323
1324 static struct qreg
1325 ntq_emit_vpm_read(struct v3d_compile *c,
1326 uint32_t *num_components_queued,
1327 uint32_t *remaining,
1328 uint32_t vpm_index)
1329 {
1330 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1331
1332 if (c->devinfo->ver >= 40 ) {
1333 return vir_LDVPMV_IN(c,
1334 vir_uniform_ui(c,
1335 (*num_components_queued)++));
1336 }
1337
1338 if (*num_components_queued != 0) {
1339 (*num_components_queued)--;
1340 return vir_MOV(c, vpm);
1341 }
1342
1343 uint32_t num_components = MIN2(*remaining, 32);
1344
1345 v3d33_vir_vpm_read_setup(c, num_components);
1346
1347 *num_components_queued = num_components - 1;
1348 *remaining -= num_components;
1349
1350 return vir_MOV(c, vpm);
1351 }
1352
1353 static void
1354 ntq_setup_vpm_inputs(struct v3d_compile *c)
1355 {
1356 /* Figure out how many components of each vertex attribute the shader
1357 * uses. Each variable should have been split to individual
1358 * components and unused ones DCEed. The vertex fetcher will load
1359 * from the start of the attribute to the number of components we
1360 * declare we need in c->vattr_sizes[].
1361 */
1362 nir_foreach_variable(var, &c->s->inputs) {
1363 /* No VS attribute array support. */
1364 assert(MAX2(glsl_get_length(var->type), 1) == 1);
1365
1366 unsigned loc = var->data.driver_location;
1367 int start_component = var->data.location_frac;
1368 int num_components = glsl_get_components(var->type);
1369
1370 c->vattr_sizes[loc] = MAX2(c->vattr_sizes[loc],
1371 start_component + num_components);
1372 }
1373
1374 unsigned num_components = 0;
1375 uint32_t vpm_components_queued = 0;
1376 bool uses_iid = c->s->info.system_values_read &
1377 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1378 bool uses_vid = c->s->info.system_values_read &
1379 (1ull << SYSTEM_VALUE_VERTEX_ID);
1380 num_components += uses_iid;
1381 num_components += uses_vid;
1382
1383 for (int i = 0; i < ARRAY_SIZE(c->vattr_sizes); i++)
1384 num_components += c->vattr_sizes[i];
1385
1386 if (uses_iid) {
1387 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1388 &num_components, ~0);
1389 }
1390
1391 if (uses_vid) {
1392 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1393 &num_components, ~0);
1394 }
1395
1396 /* The actual loads will happen directly in nir_intrinsic_load_input
1397 * on newer versions.
1398 */
1399 if (c->devinfo->ver >= 40)
1400 return;
1401
1402 for (int loc = 0; loc < ARRAY_SIZE(c->vattr_sizes); loc++) {
1403 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1404 (loc + 1) * 4);
1405
1406 for (int i = 0; i < c->vattr_sizes[loc]; i++) {
1407 c->inputs[loc * 4 + i] =
1408 ntq_emit_vpm_read(c,
1409 &vpm_components_queued,
1410 &num_components,
1411 loc * 4 + i);
1412
1413 }
1414 }
1415
1416 if (c->devinfo->ver >= 40) {
1417 assert(vpm_components_queued == num_components);
1418 } else {
1419 assert(vpm_components_queued == 0);
1420 assert(num_components == 0);
1421 }
1422 }
1423
1424 static void
1425 ntq_setup_fs_inputs(struct v3d_compile *c)
1426 {
1427 unsigned num_entries = 0;
1428 unsigned num_components = 0;
1429 nir_foreach_variable(var, &c->s->inputs) {
1430 num_entries++;
1431 num_components += glsl_get_components(var->type);
1432 }
1433
1434 nir_variable *vars[num_entries];
1435
1436 unsigned i = 0;
1437 nir_foreach_variable(var, &c->s->inputs)
1438 vars[i++] = var;
1439
1440 /* Sort the variables so that we emit the input setup in
1441 * driver_location order. This is required for VPM reads, whose data
1442 * is fetched into the VPM in driver_location (TGSI register index)
1443 * order.
1444 */
1445 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1446
1447 for (unsigned i = 0; i < num_entries; i++) {
1448 nir_variable *var = vars[i];
1449 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1450 unsigned loc = var->data.driver_location;
1451
1452 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1453 (loc + array_len) * 4);
1454
1455 if (var->data.location == VARYING_SLOT_POS) {
1456 emit_fragcoord_input(c, loc);
1457 } else if (var->data.location == VARYING_SLOT_PNTC ||
1458 (var->data.location >= VARYING_SLOT_VAR0 &&
1459 (c->fs_key->point_sprite_mask &
1460 (1 << (var->data.location -
1461 VARYING_SLOT_VAR0))))) {
1462 c->inputs[loc * 4 + 0] = c->point_x;
1463 c->inputs[loc * 4 + 1] = c->point_y;
1464 } else {
1465 for (int j = 0; j < array_len; j++)
1466 emit_fragment_input(c, loc + j, var, j);
1467 }
1468 }
1469 }
1470
1471 static void
1472 ntq_setup_outputs(struct v3d_compile *c)
1473 {
1474 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
1475 return;
1476
1477 nir_foreach_variable(var, &c->s->outputs) {
1478 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1479 unsigned loc = var->data.driver_location * 4;
1480
1481 assert(array_len == 1);
1482 (void)array_len;
1483
1484 for (int i = 0; i < 4 - var->data.location_frac; i++) {
1485 add_output(c, loc + var->data.location_frac + i,
1486 var->data.location,
1487 var->data.location_frac + i);
1488 }
1489
1490 switch (var->data.location) {
1491 case FRAG_RESULT_COLOR:
1492 c->output_color_var[0] = var;
1493 c->output_color_var[1] = var;
1494 c->output_color_var[2] = var;
1495 c->output_color_var[3] = var;
1496 break;
1497 case FRAG_RESULT_DATA0:
1498 case FRAG_RESULT_DATA1:
1499 case FRAG_RESULT_DATA2:
1500 case FRAG_RESULT_DATA3:
1501 c->output_color_var[var->data.location -
1502 FRAG_RESULT_DATA0] = var;
1503 break;
1504 case FRAG_RESULT_DEPTH:
1505 c->output_position_index = loc;
1506 break;
1507 case FRAG_RESULT_SAMPLE_MASK:
1508 c->output_sample_mask_index = loc;
1509 break;
1510 }
1511 }
1512 }
1513
1514 /**
1515 * Sets up the mapping from nir_register to struct qreg *.
1516 *
1517 * Each nir_register gets a struct qreg per 32-bit component being stored.
1518 */
1519 static void
1520 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1521 {
1522 foreach_list_typed(nir_register, nir_reg, node, list) {
1523 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1524 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1525 array_len *
1526 nir_reg->num_components);
1527
1528 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1529
1530 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1531 qregs[i] = vir_get_temp(c);
1532 }
1533 }
1534
1535 static void
1536 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1537 {
1538 /* XXX perf: Experiment with using immediate loads to avoid having
1539 * these end up in the uniform stream. Watch out for breaking the
1540 * small immediates optimization in the process!
1541 */
1542 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1543 for (int i = 0; i < instr->def.num_components; i++)
1544 qregs[i] = vir_uniform_ui(c, instr->value.u32[i]);
1545
1546 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1547 }
1548
1549 static void
1550 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1551 {
1552 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1553
1554 /* VIR needs there to be *some* value, so pick 0 (same as for
1555 * ntq_setup_registers().
1556 */
1557 for (int i = 0; i < instr->def.num_components; i++)
1558 qregs[i] = vir_uniform_ui(c, 0);
1559 }
1560
1561 static void
1562 ntq_emit_image_size(struct v3d_compile *c, nir_intrinsic_instr *instr)
1563 {
1564 assert(instr->intrinsic == nir_intrinsic_image_deref_size);
1565 nir_variable *var = nir_intrinsic_get_var(instr, 0);
1566 unsigned image_index = var->data.driver_location;
1567 const struct glsl_type *sampler_type = glsl_without_array(var->type);
1568 bool is_array = glsl_sampler_type_is_array(sampler_type);
1569
1570 ntq_store_dest(c, &instr->dest, 0,
1571 vir_uniform(c, QUNIFORM_IMAGE_WIDTH, image_index));
1572 if (instr->num_components > 1) {
1573 ntq_store_dest(c, &instr->dest, 1,
1574 vir_uniform(c, QUNIFORM_IMAGE_HEIGHT,
1575 image_index));
1576 }
1577 if (instr->num_components > 2) {
1578 ntq_store_dest(c, &instr->dest, 2,
1579 vir_uniform(c,
1580 is_array ?
1581 QUNIFORM_IMAGE_ARRAY_SIZE :
1582 QUNIFORM_IMAGE_DEPTH,
1583 image_index));
1584 }
1585 }
1586
1587 static void
1588 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
1589 {
1590 unsigned offset;
1591
1592 switch (instr->intrinsic) {
1593 case nir_intrinsic_load_uniform:
1594 if (nir_src_is_const(instr->src[0])) {
1595 int offset = (nir_intrinsic_base(instr) +
1596 nir_src_as_uint(instr->src[0]));
1597 assert(offset % 4 == 0);
1598 /* We need dwords */
1599 offset = offset / 4;
1600 for (int i = 0; i < instr->num_components; i++) {
1601 ntq_store_dest(c, &instr->dest, i,
1602 vir_uniform(c, QUNIFORM_UNIFORM,
1603 offset + i));
1604 }
1605 } else {
1606 ntq_emit_tmu_general(c, instr, false);
1607 }
1608 break;
1609
1610 case nir_intrinsic_load_ubo:
1611 ntq_emit_tmu_general(c, instr, false);
1612 break;
1613
1614 case nir_intrinsic_ssbo_atomic_add:
1615 case nir_intrinsic_ssbo_atomic_imin:
1616 case nir_intrinsic_ssbo_atomic_umin:
1617 case nir_intrinsic_ssbo_atomic_imax:
1618 case nir_intrinsic_ssbo_atomic_umax:
1619 case nir_intrinsic_ssbo_atomic_and:
1620 case nir_intrinsic_ssbo_atomic_or:
1621 case nir_intrinsic_ssbo_atomic_xor:
1622 case nir_intrinsic_ssbo_atomic_exchange:
1623 case nir_intrinsic_ssbo_atomic_comp_swap:
1624 case nir_intrinsic_load_ssbo:
1625 case nir_intrinsic_store_ssbo:
1626 ntq_emit_tmu_general(c, instr, false);
1627 break;
1628
1629 case nir_intrinsic_shared_atomic_add:
1630 case nir_intrinsic_shared_atomic_imin:
1631 case nir_intrinsic_shared_atomic_umin:
1632 case nir_intrinsic_shared_atomic_imax:
1633 case nir_intrinsic_shared_atomic_umax:
1634 case nir_intrinsic_shared_atomic_and:
1635 case nir_intrinsic_shared_atomic_or:
1636 case nir_intrinsic_shared_atomic_xor:
1637 case nir_intrinsic_shared_atomic_exchange:
1638 case nir_intrinsic_shared_atomic_comp_swap:
1639 case nir_intrinsic_load_shared:
1640 case nir_intrinsic_store_shared:
1641 case nir_intrinsic_load_scratch:
1642 case nir_intrinsic_store_scratch:
1643 ntq_emit_tmu_general(c, instr, true);
1644 break;
1645
1646 case nir_intrinsic_image_deref_load:
1647 case nir_intrinsic_image_deref_store:
1648 case nir_intrinsic_image_deref_atomic_add:
1649 case nir_intrinsic_image_deref_atomic_min:
1650 case nir_intrinsic_image_deref_atomic_max:
1651 case nir_intrinsic_image_deref_atomic_and:
1652 case nir_intrinsic_image_deref_atomic_or:
1653 case nir_intrinsic_image_deref_atomic_xor:
1654 case nir_intrinsic_image_deref_atomic_exchange:
1655 case nir_intrinsic_image_deref_atomic_comp_swap:
1656 v3d40_vir_emit_image_load_store(c, instr);
1657 break;
1658
1659 case nir_intrinsic_get_buffer_size:
1660 ntq_store_dest(c, &instr->dest, 0,
1661 vir_uniform(c, QUNIFORM_GET_BUFFER_SIZE,
1662 nir_src_as_uint(instr->src[0])));
1663 break;
1664
1665 case nir_intrinsic_load_user_clip_plane:
1666 for (int i = 0; i < instr->num_components; i++) {
1667 ntq_store_dest(c, &instr->dest, i,
1668 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1669 nir_intrinsic_ucp_id(instr) *
1670 4 + i));
1671 }
1672 break;
1673
1674 case nir_intrinsic_load_viewport_x_scale:
1675 ntq_store_dest(c, &instr->dest, 0,
1676 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE, 0));
1677 break;
1678
1679 case nir_intrinsic_load_viewport_y_scale:
1680 ntq_store_dest(c, &instr->dest, 0,
1681 vir_uniform(c, QUNIFORM_VIEWPORT_Y_SCALE, 0));
1682 break;
1683
1684 case nir_intrinsic_load_viewport_z_scale:
1685 ntq_store_dest(c, &instr->dest, 0,
1686 vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0));
1687 break;
1688
1689 case nir_intrinsic_load_viewport_z_offset:
1690 ntq_store_dest(c, &instr->dest, 0,
1691 vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0));
1692 break;
1693
1694 case nir_intrinsic_load_alpha_ref_float:
1695 ntq_store_dest(c, &instr->dest, 0,
1696 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1697 break;
1698
1699 case nir_intrinsic_load_sample_mask_in:
1700 ntq_store_dest(c, &instr->dest, 0, vir_MSF(c));
1701 break;
1702
1703 case nir_intrinsic_load_helper_invocation:
1704 vir_set_pf(vir_MSF_dest(c, vir_nop_reg()), V3D_QPU_PF_PUSHZ);
1705 ntq_store_dest(c, &instr->dest, 0,
1706 vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1707 vir_uniform_ui(c, ~0),
1708 vir_uniform_ui(c, 0))));
1709 break;
1710
1711 case nir_intrinsic_load_front_face:
1712 /* The register contains 0 (front) or 1 (back), and we need to
1713 * turn it into a NIR bool where true means front.
1714 */
1715 ntq_store_dest(c, &instr->dest, 0,
1716 vir_ADD(c,
1717 vir_uniform_ui(c, -1),
1718 vir_REVF(c)));
1719 break;
1720
1721 case nir_intrinsic_load_instance_id:
1722 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
1723 break;
1724
1725 case nir_intrinsic_load_vertex_id:
1726 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
1727 break;
1728
1729 case nir_intrinsic_load_input:
1730 offset = (nir_intrinsic_base(instr) +
1731 nir_src_as_uint(instr->src[0]));
1732 if (c->s->info.stage != MESA_SHADER_FRAGMENT &&
1733 c->devinfo->ver >= 40) {
1734 /* Emit the LDVPM directly now, rather than at the top
1735 * of the shader like we did for V3D 3.x (which needs
1736 * vpmsetup when not just taking the next offset).
1737 *
1738 * Note that delaying like this may introduce stalls,
1739 * as LDVPMV takes a minimum of 1 instruction but may
1740 * be slower if the VPM unit is busy with another QPU.
1741 */
1742 int index = 0;
1743 if (c->s->info.system_values_read &
1744 (1ull << SYSTEM_VALUE_INSTANCE_ID)) {
1745 index++;
1746 }
1747 if (c->s->info.system_values_read &
1748 (1ull << SYSTEM_VALUE_VERTEX_ID)) {
1749 index++;
1750 }
1751 for (int i = 0; i < offset; i++)
1752 index += c->vattr_sizes[i];
1753 index += nir_intrinsic_component(instr);
1754 for (int i = 0; i < instr->num_components; i++) {
1755 struct qreg vpm_offset =
1756 vir_uniform_ui(c, index++);
1757 ntq_store_dest(c, &instr->dest, i,
1758 vir_LDVPMV_IN(c, vpm_offset));
1759 }
1760 } else {
1761 for (int i = 0; i < instr->num_components; i++) {
1762 int comp = nir_intrinsic_component(instr) + i;
1763 ntq_store_dest(c, &instr->dest, i,
1764 vir_MOV(c, c->inputs[offset * 4 +
1765 comp]));
1766 }
1767 }
1768 break;
1769
1770 case nir_intrinsic_store_output:
1771 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1772 offset = ((nir_intrinsic_base(instr) +
1773 nir_src_as_uint(instr->src[1])) * 4 +
1774 nir_intrinsic_component(instr));
1775 for (int i = 0; i < instr->num_components; i++) {
1776 c->outputs[offset + i] =
1777 vir_MOV(c,
1778 ntq_get_src(c,
1779 instr->src[0], i));
1780 }
1781 } else {
1782 assert(instr->num_components == 1);
1783
1784 vir_VPM_WRITE(c,
1785 ntq_get_src(c, instr->src[0], 0),
1786 nir_intrinsic_base(instr));
1787 }
1788 break;
1789
1790 case nir_intrinsic_image_deref_size:
1791 ntq_emit_image_size(c, instr);
1792 break;
1793
1794 case nir_intrinsic_discard:
1795 if (vir_in_nonuniform_control_flow(c)) {
1796 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
1797 V3D_QPU_PF_PUSHZ);
1798 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
1799 vir_uniform_ui(c, 0)),
1800 V3D_QPU_COND_IFA);
1801 } else {
1802 vir_SETMSF_dest(c, vir_nop_reg(),
1803 vir_uniform_ui(c, 0));
1804 }
1805 break;
1806
1807 case nir_intrinsic_discard_if: {
1808 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, instr->src[0]);
1809
1810 if (vir_in_nonuniform_control_flow(c)) {
1811 struct qinst *exec_flag = vir_MOV_dest(c, vir_nop_reg(),
1812 c->execute);
1813 if (cond == V3D_QPU_COND_IFA) {
1814 vir_set_uf(exec_flag, V3D_QPU_UF_ANDZ);
1815 } else {
1816 vir_set_uf(exec_flag, V3D_QPU_UF_NORNZ);
1817 cond = V3D_QPU_COND_IFA;
1818 }
1819 }
1820
1821 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
1822 vir_uniform_ui(c, 0)), cond);
1823
1824 break;
1825 }
1826
1827 case nir_intrinsic_memory_barrier:
1828 case nir_intrinsic_memory_barrier_atomic_counter:
1829 case nir_intrinsic_memory_barrier_buffer:
1830 case nir_intrinsic_memory_barrier_image:
1831 case nir_intrinsic_group_memory_barrier:
1832 /* We don't do any instruction scheduling of these NIR
1833 * instructions between each other, so we just need to make
1834 * sure that the TMU operations before the barrier are flushed
1835 * before the ones after the barrier. That is currently
1836 * handled by having a THRSW in each of them and a LDTMU
1837 * series or a TMUWT after.
1838 */
1839 break;
1840
1841 case nir_intrinsic_barrier:
1842 /* Emit a TSY op to get all invocations in the workgroup
1843 * (actually supergroup) to block until the last invocation
1844 * reaches the TSY op.
1845 */
1846 if (c->devinfo->ver >= 42) {
1847 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
1848 V3D_QPU_WADDR_SYNCB));
1849 } else {
1850 struct qinst *sync =
1851 vir_BARRIERID_dest(c,
1852 vir_reg(QFILE_MAGIC,
1853 V3D_QPU_WADDR_SYNCU));
1854 sync->uniform =
1855 vir_get_uniform_index(c, QUNIFORM_CONSTANT,
1856 0xffffff00 |
1857 V3D_TSY_WAIT_INC_CHECK);
1858
1859 }
1860
1861 /* The blocking of a TSY op only happens at the next thread
1862 * switch. No texturing may be outstanding at the time of a
1863 * TSY blocking operation.
1864 */
1865 vir_emit_thrsw(c);
1866 break;
1867
1868 case nir_intrinsic_load_num_work_groups:
1869 for (int i = 0; i < 3; i++) {
1870 ntq_store_dest(c, &instr->dest, i,
1871 vir_uniform(c, QUNIFORM_NUM_WORK_GROUPS,
1872 i));
1873 }
1874 break;
1875
1876 case nir_intrinsic_load_local_invocation_index:
1877 ntq_store_dest(c, &instr->dest, 0,
1878 vir_SHR(c, c->cs_payload[1],
1879 vir_uniform_ui(c, 32 - c->local_invocation_index_bits)));
1880 break;
1881
1882 case nir_intrinsic_load_work_group_id:
1883 ntq_store_dest(c, &instr->dest, 0,
1884 vir_AND(c, c->cs_payload[0],
1885 vir_uniform_ui(c, 0xffff)));
1886 ntq_store_dest(c, &instr->dest, 1,
1887 vir_SHR(c, c->cs_payload[0],
1888 vir_uniform_ui(c, 16)));
1889 ntq_store_dest(c, &instr->dest, 2,
1890 vir_AND(c, c->cs_payload[1],
1891 vir_uniform_ui(c, 0xffff)));
1892 break;
1893
1894 case nir_intrinsic_load_subgroup_id:
1895 ntq_store_dest(c, &instr->dest, 0, vir_EIDX(c));
1896 break;
1897
1898 default:
1899 fprintf(stderr, "Unknown intrinsic: ");
1900 nir_print_instr(&instr->instr, stderr);
1901 fprintf(stderr, "\n");
1902 break;
1903 }
1904 }
1905
1906 /* Clears (activates) the execute flags for any channels whose jump target
1907 * matches this block.
1908 *
1909 * XXX perf: Could we be using flpush/flpop somehow for our execution channel
1910 * enabling?
1911 *
1912 * XXX perf: For uniform control flow, we should be able to skip c->execute
1913 * handling entirely.
1914 */
1915 static void
1916 ntq_activate_execute_for_block(struct v3d_compile *c)
1917 {
1918 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
1919 c->execute, vir_uniform_ui(c, c->cur_block->index)),
1920 V3D_QPU_PF_PUSHZ);
1921
1922 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
1923 }
1924
1925 static void
1926 ntq_emit_uniform_if(struct v3d_compile *c, nir_if *if_stmt)
1927 {
1928 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
1929 bool empty_else_block =
1930 (nir_else_block == nir_if_last_else_block(if_stmt) &&
1931 exec_list_is_empty(&nir_else_block->instr_list));
1932
1933 struct qblock *then_block = vir_new_block(c);
1934 struct qblock *after_block = vir_new_block(c);
1935 struct qblock *else_block;
1936 if (empty_else_block)
1937 else_block = after_block;
1938 else
1939 else_block = vir_new_block(c);
1940
1941 /* Set up the flags for the IF condition (taking the THEN branch). */
1942 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
1943
1944 /* Jump to ELSE. */
1945 vir_BRANCH(c, cond == V3D_QPU_COND_IFA ?
1946 V3D_QPU_BRANCH_COND_ALLNA :
1947 V3D_QPU_BRANCH_COND_ALLA);
1948 vir_link_blocks(c->cur_block, else_block);
1949 vir_link_blocks(c->cur_block, then_block);
1950
1951 /* Process the THEN block. */
1952 vir_set_emit_block(c, then_block);
1953 ntq_emit_cf_list(c, &if_stmt->then_list);
1954
1955 if (!empty_else_block) {
1956 /* At the end of the THEN block, jump to ENDIF */
1957 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALWAYS);
1958 vir_link_blocks(c->cur_block, after_block);
1959
1960 /* Emit the else block. */
1961 vir_set_emit_block(c, else_block);
1962 ntq_activate_execute_for_block(c);
1963 ntq_emit_cf_list(c, &if_stmt->else_list);
1964 }
1965
1966 vir_link_blocks(c->cur_block, after_block);
1967
1968 vir_set_emit_block(c, after_block);
1969 }
1970
1971 static void
1972 ntq_emit_nonuniform_if(struct v3d_compile *c, nir_if *if_stmt)
1973 {
1974 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
1975 bool empty_else_block =
1976 (nir_else_block == nir_if_last_else_block(if_stmt) &&
1977 exec_list_is_empty(&nir_else_block->instr_list));
1978
1979 struct qblock *then_block = vir_new_block(c);
1980 struct qblock *after_block = vir_new_block(c);
1981 struct qblock *else_block;
1982 if (empty_else_block)
1983 else_block = after_block;
1984 else
1985 else_block = vir_new_block(c);
1986
1987 bool was_uniform_control_flow = false;
1988 if (!vir_in_nonuniform_control_flow(c)) {
1989 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
1990 was_uniform_control_flow = true;
1991 }
1992
1993 /* Set up the flags for the IF condition (taking the THEN branch). */
1994 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
1995
1996 /* Update the flags+cond to mean "Taking the ELSE branch (!cond) and
1997 * was previously active (execute Z) for updating the exec flags.
1998 */
1999 if (was_uniform_control_flow) {
2000 cond = v3d_qpu_cond_invert(cond);
2001 } else {
2002 struct qinst *inst = vir_MOV_dest(c, vir_nop_reg(), c->execute);
2003 if (cond == V3D_QPU_COND_IFA) {
2004 vir_set_uf(inst, V3D_QPU_UF_NORNZ);
2005 } else {
2006 vir_set_uf(inst, V3D_QPU_UF_ANDZ);
2007 cond = V3D_QPU_COND_IFA;
2008 }
2009 }
2010
2011 vir_MOV_cond(c, cond,
2012 c->execute,
2013 vir_uniform_ui(c, else_block->index));
2014
2015 /* Jump to ELSE if nothing is active for THEN, otherwise fall
2016 * through.
2017 */
2018 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ);
2019 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
2020 vir_link_blocks(c->cur_block, else_block);
2021 vir_link_blocks(c->cur_block, then_block);
2022
2023 /* Process the THEN block. */
2024 vir_set_emit_block(c, then_block);
2025 ntq_emit_cf_list(c, &if_stmt->then_list);
2026
2027 if (!empty_else_block) {
2028 /* Handle the end of the THEN block. First, all currently
2029 * active channels update their execute flags to point to
2030 * ENDIF
2031 */
2032 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2033 V3D_QPU_PF_PUSHZ);
2034 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2035 vir_uniform_ui(c, after_block->index));
2036
2037 /* If everything points at ENDIF, then jump there immediately. */
2038 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
2039 c->execute,
2040 vir_uniform_ui(c, after_block->index)),
2041 V3D_QPU_PF_PUSHZ);
2042 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
2043 vir_link_blocks(c->cur_block, after_block);
2044 vir_link_blocks(c->cur_block, else_block);
2045
2046 vir_set_emit_block(c, else_block);
2047 ntq_activate_execute_for_block(c);
2048 ntq_emit_cf_list(c, &if_stmt->else_list);
2049 }
2050
2051 vir_link_blocks(c->cur_block, after_block);
2052
2053 vir_set_emit_block(c, after_block);
2054 if (was_uniform_control_flow)
2055 c->execute = c->undef;
2056 else
2057 ntq_activate_execute_for_block(c);
2058 }
2059
2060 static void
2061 ntq_emit_if(struct v3d_compile *c, nir_if *nif)
2062 {
2063 bool was_in_control_flow = c->in_control_flow;
2064 c->in_control_flow = true;
2065 if (!vir_in_nonuniform_control_flow(c) &&
2066 nir_src_is_dynamically_uniform(nif->condition)) {
2067 ntq_emit_uniform_if(c, nif);
2068 } else {
2069 ntq_emit_nonuniform_if(c, nif);
2070 }
2071 c->in_control_flow = was_in_control_flow;
2072 }
2073
2074 static void
2075 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
2076 {
2077 switch (jump->type) {
2078 case nir_jump_break:
2079 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2080 V3D_QPU_PF_PUSHZ);
2081 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2082 vir_uniform_ui(c, c->loop_break_block->index));
2083 break;
2084
2085 case nir_jump_continue:
2086 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2087 V3D_QPU_PF_PUSHZ);
2088 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2089 vir_uniform_ui(c, c->loop_cont_block->index));
2090 break;
2091
2092 case nir_jump_return:
2093 unreachable("All returns shouold be lowered\n");
2094 }
2095 }
2096
2097 static void
2098 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
2099 {
2100 switch (instr->type) {
2101 case nir_instr_type_deref:
2102 /* ignored, will be walked by the intrinsic using it. */
2103 break;
2104
2105 case nir_instr_type_alu:
2106 ntq_emit_alu(c, nir_instr_as_alu(instr));
2107 break;
2108
2109 case nir_instr_type_intrinsic:
2110 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
2111 break;
2112
2113 case nir_instr_type_load_const:
2114 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
2115 break;
2116
2117 case nir_instr_type_ssa_undef:
2118 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
2119 break;
2120
2121 case nir_instr_type_tex:
2122 ntq_emit_tex(c, nir_instr_as_tex(instr));
2123 break;
2124
2125 case nir_instr_type_jump:
2126 ntq_emit_jump(c, nir_instr_as_jump(instr));
2127 break;
2128
2129 default:
2130 fprintf(stderr, "Unknown NIR instr type: ");
2131 nir_print_instr(instr, stderr);
2132 fprintf(stderr, "\n");
2133 abort();
2134 }
2135 }
2136
2137 static void
2138 ntq_emit_block(struct v3d_compile *c, nir_block *block)
2139 {
2140 nir_foreach_instr(instr, block) {
2141 ntq_emit_instr(c, instr);
2142 }
2143 }
2144
2145 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
2146
2147 static void
2148 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
2149 {
2150 bool was_in_control_flow = c->in_control_flow;
2151 c->in_control_flow = true;
2152
2153 bool was_uniform_control_flow = false;
2154 if (!vir_in_nonuniform_control_flow(c)) {
2155 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2156 was_uniform_control_flow = true;
2157 }
2158
2159 struct qblock *save_loop_cont_block = c->loop_cont_block;
2160 struct qblock *save_loop_break_block = c->loop_break_block;
2161
2162 c->loop_cont_block = vir_new_block(c);
2163 c->loop_break_block = vir_new_block(c);
2164
2165 vir_link_blocks(c->cur_block, c->loop_cont_block);
2166 vir_set_emit_block(c, c->loop_cont_block);
2167 ntq_activate_execute_for_block(c);
2168
2169 ntq_emit_cf_list(c, &loop->body);
2170
2171 /* Re-enable any previous continues now, so our ANYA check below
2172 * works.
2173 *
2174 * XXX: Use the .ORZ flags update, instead.
2175 */
2176 vir_set_pf(vir_XOR_dest(c,
2177 vir_nop_reg(),
2178 c->execute,
2179 vir_uniform_ui(c, c->loop_cont_block->index)),
2180 V3D_QPU_PF_PUSHZ);
2181 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2182
2183 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ);
2184
2185 struct qinst *branch = vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
2186 /* Pixels that were not dispatched or have been discarded should not
2187 * contribute to looping again.
2188 */
2189 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P;
2190 vir_link_blocks(c->cur_block, c->loop_cont_block);
2191 vir_link_blocks(c->cur_block, c->loop_break_block);
2192
2193 vir_set_emit_block(c, c->loop_break_block);
2194 if (was_uniform_control_flow)
2195 c->execute = c->undef;
2196 else
2197 ntq_activate_execute_for_block(c);
2198
2199 c->loop_break_block = save_loop_break_block;
2200 c->loop_cont_block = save_loop_cont_block;
2201
2202 c->loops++;
2203
2204 c->in_control_flow = was_in_control_flow;
2205 }
2206
2207 static void
2208 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
2209 {
2210 fprintf(stderr, "FUNCTIONS not handled.\n");
2211 abort();
2212 }
2213
2214 static void
2215 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
2216 {
2217 foreach_list_typed(nir_cf_node, node, node, list) {
2218 switch (node->type) {
2219 case nir_cf_node_block:
2220 ntq_emit_block(c, nir_cf_node_as_block(node));
2221 break;
2222
2223 case nir_cf_node_if:
2224 ntq_emit_if(c, nir_cf_node_as_if(node));
2225 break;
2226
2227 case nir_cf_node_loop:
2228 ntq_emit_loop(c, nir_cf_node_as_loop(node));
2229 break;
2230
2231 case nir_cf_node_function:
2232 ntq_emit_function(c, nir_cf_node_as_function(node));
2233 break;
2234
2235 default:
2236 fprintf(stderr, "Unknown NIR node type\n");
2237 abort();
2238 }
2239 }
2240 }
2241
2242 static void
2243 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
2244 {
2245 ntq_setup_registers(c, &impl->registers);
2246 ntq_emit_cf_list(c, &impl->body);
2247 }
2248
2249 static void
2250 nir_to_vir(struct v3d_compile *c)
2251 {
2252 switch (c->s->info.stage) {
2253 case MESA_SHADER_FRAGMENT:
2254 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
2255 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
2256 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
2257
2258 /* XXX perf: We could set the "disable implicit point/line
2259 * varyings" field in the shader record and not emit these, if
2260 * they're not going to be used.
2261 */
2262 if (c->fs_key->is_points) {
2263 c->point_x = emit_fragment_varying(c, NULL, 0, 0);
2264 c->point_y = emit_fragment_varying(c, NULL, 0, 0);
2265 } else if (c->fs_key->is_lines) {
2266 c->line_x = emit_fragment_varying(c, NULL, 0, 0);
2267 }
2268 break;
2269 case MESA_SHADER_COMPUTE:
2270 /* Set up the TSO for barriers, assuming we do some. */
2271 if (c->devinfo->ver < 42) {
2272 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
2273 V3D_QPU_WADDR_SYNC));
2274 }
2275
2276 if (c->s->info.system_values_read &
2277 ((1ull << SYSTEM_VALUE_LOCAL_INVOCATION_INDEX) |
2278 (1ull << SYSTEM_VALUE_WORK_GROUP_ID))) {
2279 c->cs_payload[0] = vir_MOV(c, vir_reg(QFILE_REG, 0));
2280 }
2281 if ((c->s->info.system_values_read &
2282 ((1ull << SYSTEM_VALUE_WORK_GROUP_ID))) ||
2283 c->s->info.cs.shared_size) {
2284 c->cs_payload[1] = vir_MOV(c, vir_reg(QFILE_REG, 2));
2285 }
2286
2287 /* Set up the division between gl_LocalInvocationIndex and
2288 * wg_in_mem in the payload reg.
2289 */
2290 int wg_size = (c->s->info.cs.local_size[0] *
2291 c->s->info.cs.local_size[1] *
2292 c->s->info.cs.local_size[2]);
2293 c->local_invocation_index_bits =
2294 ffs(util_next_power_of_two(MAX2(wg_size, 64))) - 1;
2295 assert(c->local_invocation_index_bits <= 8);
2296
2297 if (c->s->info.cs.shared_size) {
2298 struct qreg wg_in_mem = vir_SHR(c, c->cs_payload[1],
2299 vir_uniform_ui(c, 16));
2300 if (c->s->info.cs.local_size[0] != 1 ||
2301 c->s->info.cs.local_size[1] != 1 ||
2302 c->s->info.cs.local_size[2] != 1) {
2303 int wg_bits = (16 -
2304 c->local_invocation_index_bits);
2305 int wg_mask = (1 << wg_bits) - 1;
2306 wg_in_mem = vir_AND(c, wg_in_mem,
2307 vir_uniform_ui(c, wg_mask));
2308 }
2309 struct qreg shared_per_wg =
2310 vir_uniform_ui(c, c->s->info.cs.shared_size);
2311
2312 c->cs_shared_offset =
2313 vir_ADD(c,
2314 vir_uniform(c, QUNIFORM_SHARED_OFFSET,0),
2315 vir_UMUL(c, wg_in_mem, shared_per_wg));
2316 }
2317 break;
2318 default:
2319 break;
2320 }
2321
2322 if (c->s->scratch_size) {
2323 v3d_setup_spill_base(c);
2324 c->spill_size += V3D_CHANNELS * c->s->scratch_size;
2325 }
2326
2327 if (c->s->info.stage == MESA_SHADER_FRAGMENT)
2328 ntq_setup_fs_inputs(c);
2329 else
2330 ntq_setup_vpm_inputs(c);
2331
2332 ntq_setup_outputs(c);
2333
2334 /* Find the main function and emit the body. */
2335 nir_foreach_function(function, c->s) {
2336 assert(strcmp(function->name, "main") == 0);
2337 assert(function->impl);
2338 ntq_emit_impl(c, function->impl);
2339 }
2340 }
2341
2342 const nir_shader_compiler_options v3d_nir_options = {
2343 .lower_all_io_to_temps = true,
2344 .lower_extract_byte = true,
2345 .lower_extract_word = true,
2346 .lower_bfm = true,
2347 .lower_bitfield_insert_to_shifts = true,
2348 .lower_bitfield_extract_to_shifts = true,
2349 .lower_bitfield_reverse = true,
2350 .lower_bit_count = true,
2351 .lower_cs_local_id_from_index = true,
2352 .lower_ffract = true,
2353 .lower_pack_unorm_2x16 = true,
2354 .lower_pack_snorm_2x16 = true,
2355 .lower_pack_unorm_4x8 = true,
2356 .lower_pack_snorm_4x8 = true,
2357 .lower_unpack_unorm_4x8 = true,
2358 .lower_unpack_snorm_4x8 = true,
2359 .lower_pack_half_2x16 = true,
2360 .lower_unpack_half_2x16 = true,
2361 .lower_fdiv = true,
2362 .lower_find_lsb = true,
2363 .lower_ffma = true,
2364 .lower_flrp32 = true,
2365 .lower_fpow = true,
2366 .lower_fsat = true,
2367 .lower_fsqrt = true,
2368 .lower_ifind_msb = true,
2369 .lower_isign = true,
2370 .lower_ldexp = true,
2371 .lower_mul_high = true,
2372 .lower_wpos_pntc = true,
2373 .native_integers = true,
2374 };
2375
2376 /**
2377 * When demoting a shader down to single-threaded, removes the THRSW
2378 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
2379 * program end).
2380 */
2381 static void
2382 vir_remove_thrsw(struct v3d_compile *c)
2383 {
2384 vir_for_each_block(block, c) {
2385 vir_for_each_inst_safe(inst, block) {
2386 if (inst->qpu.sig.thrsw)
2387 vir_remove_instruction(c, inst);
2388 }
2389 }
2390
2391 c->last_thrsw = NULL;
2392 }
2393
2394 void
2395 vir_emit_last_thrsw(struct v3d_compile *c)
2396 {
2397 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
2398 * switching, so disable threads if we didn't do any TMU ops (each of
2399 * which would have emitted a THRSW).
2400 */
2401 if (!c->last_thrsw_at_top_level && c->devinfo->ver < 41) {
2402 c->threads = 1;
2403 if (c->last_thrsw)
2404 vir_remove_thrsw(c);
2405 return;
2406 }
2407
2408 /* If we're threaded and the last THRSW was in conditional code, then
2409 * we need to emit another one so that we can flag it as the last
2410 * thrsw.
2411 */
2412 if (c->last_thrsw && !c->last_thrsw_at_top_level) {
2413 assert(c->devinfo->ver >= 41);
2414 vir_emit_thrsw(c);
2415 }
2416
2417 /* If we're threaded, then we need to mark the last THRSW instruction
2418 * so we can emit a pair of them at QPU emit time.
2419 *
2420 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2421 * post-last-THRSW state, so we can skip this.
2422 */
2423 if (!c->last_thrsw && c->s->info.stage == MESA_SHADER_FRAGMENT) {
2424 assert(c->devinfo->ver >= 41);
2425 vir_emit_thrsw(c);
2426 }
2427
2428 if (c->last_thrsw)
2429 c->last_thrsw->is_last_thrsw = true;
2430 }
2431
2432 /* There's a flag in the shader for "center W is needed for reasons other than
2433 * non-centroid varyings", so we just walk the program after VIR optimization
2434 * to see if it's used. It should be harmless to set even if we only use
2435 * center W for varyings.
2436 */
2437 static void
2438 vir_check_payload_w(struct v3d_compile *c)
2439 {
2440 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
2441 return;
2442
2443 vir_for_each_inst_inorder(inst, c) {
2444 for (int i = 0; i < vir_get_nsrc(inst); i++) {
2445 if (inst->src[i].file == QFILE_REG &&
2446 inst->src[i].index == 0) {
2447 c->uses_center_w = true;
2448 return;
2449 }
2450 }
2451 }
2452
2453 }
2454
2455 void
2456 v3d_nir_to_vir(struct v3d_compile *c)
2457 {
2458 if (V3D_DEBUG & (V3D_DEBUG_NIR |
2459 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2460 fprintf(stderr, "%s prog %d/%d NIR:\n",
2461 vir_get_stage_name(c),
2462 c->program_id, c->variant_id);
2463 nir_print_shader(c->s, stderr);
2464 }
2465
2466 nir_to_vir(c);
2467
2468 /* Emit the last THRSW before STVPM and TLB writes. */
2469 vir_emit_last_thrsw(c);
2470
2471 switch (c->s->info.stage) {
2472 case MESA_SHADER_FRAGMENT:
2473 emit_frag_end(c);
2474 break;
2475 case MESA_SHADER_VERTEX:
2476 emit_vert_end(c);
2477 break;
2478 case MESA_SHADER_COMPUTE:
2479 break;
2480 default:
2481 unreachable("bad stage");
2482 }
2483
2484 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2485 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2486 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
2487 vir_get_stage_name(c),
2488 c->program_id, c->variant_id);
2489 vir_dump(c);
2490 fprintf(stderr, "\n");
2491 }
2492
2493 vir_optimize(c);
2494
2495 vir_check_payload_w(c);
2496
2497 /* XXX perf: On VC4, we do a VIR-level instruction scheduling here.
2498 * We used that on that platform to pipeline TMU writes and reduce the
2499 * number of thread switches, as well as try (mostly successfully) to
2500 * reduce maximum register pressure to allow more threads. We should
2501 * do something of that sort for V3D -- either instruction scheduling
2502 * here, or delay the the THRSW and LDTMUs from our texture
2503 * instructions until the results are needed.
2504 */
2505
2506 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2507 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2508 fprintf(stderr, "%s prog %d/%d VIR:\n",
2509 vir_get_stage_name(c),
2510 c->program_id, c->variant_id);
2511 vir_dump(c);
2512 fprintf(stderr, "\n");
2513 }
2514
2515 /* Attempt to allocate registers for the temporaries. If we fail,
2516 * reduce thread count and try again.
2517 */
2518 int min_threads = (c->devinfo->ver >= 41) ? 2 : 1;
2519 struct qpu_reg *temp_registers;
2520 while (true) {
2521 bool spilled;
2522 temp_registers = v3d_register_allocate(c, &spilled);
2523 if (spilled)
2524 continue;
2525
2526 if (temp_registers)
2527 break;
2528
2529 if (c->threads == min_threads) {
2530 fprintf(stderr, "Failed to register allocate at %d threads:\n",
2531 c->threads);
2532 vir_dump(c);
2533 c->failed = true;
2534 return;
2535 }
2536
2537 c->threads /= 2;
2538
2539 if (c->threads == 1)
2540 vir_remove_thrsw(c);
2541 }
2542
2543 if (c->spills &&
2544 (V3D_DEBUG & (V3D_DEBUG_VIR |
2545 v3d_debug_flag_for_shader_stage(c->s->info.stage)))) {
2546 fprintf(stderr, "%s prog %d/%d spilled VIR:\n",
2547 vir_get_stage_name(c),
2548 c->program_id, c->variant_id);
2549 vir_dump(c);
2550 fprintf(stderr, "\n");
2551 }
2552
2553 v3d_vir_to_qpu(c, temp_registers);
2554 }