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[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
34
35 #define GENERAL_TMU_LOOKUP_PER_QUAD (0 << 7)
36 #define GENERAL_TMU_LOOKUP_PER_PIXEL (1 << 7)
37 #define GENERAL_TMU_READ_OP_PREFETCH (0 << 3)
38 #define GENERAL_TMU_READ_OP_CACHE_CLEAR (1 << 3)
39 #define GENERAL_TMU_READ_OP_CACHE_FLUSH (3 << 3)
40 #define GENERAL_TMU_READ_OP_CACHE_CLEAN (3 << 3)
41 #define GENERAL_TMU_READ_OP_CACHE_L1T_CLEAR (4 << 3)
42 #define GENERAL_TMU_READ_OP_CACHE_L1T_FLUSH_AGGREGATION (5 << 3)
43 #define GENERAL_TMU_READ_OP_ATOMIC_INC (8 << 3)
44 #define GENERAL_TMU_READ_OP_ATOMIC_DEC (9 << 3)
45 #define GENERAL_TMU_READ_OP_ATOMIC_NOT (10 << 3)
46 #define GENERAL_TMU_READ_OP_READ (15 << 3)
47 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_I (0 << 0)
48 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_I (1 << 0)
49 #define GENERAL_TMU_LOOKUP_TYPE_VEC2 (2 << 0)
50 #define GENERAL_TMU_LOOKUP_TYPE_VEC3 (3 << 0)
51 #define GENERAL_TMU_LOOKUP_TYPE_VEC4 (4 << 0)
52 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_UI (5 << 0)
53 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_UI (6 << 0)
54 #define GENERAL_TMU_LOOKUP_TYPE_32BIT_UI (7 << 0)
55
56 #define GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP (0 << 3)
57 #define GENERAL_TMU_WRITE_OP_ATOMIC_SUB_WRAP (1 << 3)
58 #define GENERAL_TMU_WRITE_OP_ATOMIC_XCHG (2 << 3)
59 #define GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG (3 << 3)
60 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMIN (4 << 3)
61 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMAX (5 << 3)
62 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMIN (6 << 3)
63 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMAX (7 << 3)
64 #define GENERAL_TMU_WRITE_OP_ATOMIC_AND (8 << 3)
65 #define GENERAL_TMU_WRITE_OP_ATOMIC_OR (9 << 3)
66 #define GENERAL_TMU_WRITE_OP_ATOMIC_XOR (10 << 3)
67 #define GENERAL_TMU_WRITE_OP_WRITE (15 << 3)
68
69 #define V3D_TSY_SET_QUORUM 0
70 #define V3D_TSY_INC_WAITERS 1
71 #define V3D_TSY_DEC_WAITERS 2
72 #define V3D_TSY_INC_QUORUM 3
73 #define V3D_TSY_DEC_QUORUM 4
74 #define V3D_TSY_FREE_ALL 5
75 #define V3D_TSY_RELEASE 6
76 #define V3D_TSY_ACQUIRE 7
77 #define V3D_TSY_WAIT 8
78 #define V3D_TSY_WAIT_INC 9
79 #define V3D_TSY_WAIT_CHECK 10
80 #define V3D_TSY_WAIT_INC_CHECK 11
81 #define V3D_TSY_WAIT_CV 12
82 #define V3D_TSY_INC_SEMAPHORE 13
83 #define V3D_TSY_DEC_SEMAPHORE 14
84 #define V3D_TSY_SET_QUORUM_FREE_ALL 15
85
86 static void
87 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
88
89 static void
90 resize_qreg_array(struct v3d_compile *c,
91 struct qreg **regs,
92 uint32_t *size,
93 uint32_t decl_size)
94 {
95 if (*size >= decl_size)
96 return;
97
98 uint32_t old_size = *size;
99 *size = MAX2(*size * 2, decl_size);
100 *regs = reralloc(c, *regs, struct qreg, *size);
101 if (!*regs) {
102 fprintf(stderr, "Malloc failure\n");
103 abort();
104 }
105
106 for (uint32_t i = old_size; i < *size; i++)
107 (*regs)[i] = c->undef;
108 }
109
110 void
111 vir_emit_thrsw(struct v3d_compile *c)
112 {
113 if (c->threads == 1)
114 return;
115
116 /* Always thread switch after each texture operation for now.
117 *
118 * We could do better by batching a bunch of texture fetches up and
119 * then doing one thread switch and collecting all their results
120 * afterward.
121 */
122 c->last_thrsw = vir_NOP(c);
123 c->last_thrsw->qpu.sig.thrsw = true;
124 c->last_thrsw_at_top_level = !c->in_control_flow;
125 }
126
127 static uint32_t
128 v3d_general_tmu_op(nir_intrinsic_instr *instr)
129 {
130 switch (instr->intrinsic) {
131 case nir_intrinsic_load_ssbo:
132 case nir_intrinsic_load_ubo:
133 case nir_intrinsic_load_uniform:
134 case nir_intrinsic_load_shared:
135 case nir_intrinsic_load_scratch:
136 return GENERAL_TMU_READ_OP_READ;
137 case nir_intrinsic_store_ssbo:
138 case nir_intrinsic_store_shared:
139 case nir_intrinsic_store_scratch:
140 return GENERAL_TMU_WRITE_OP_WRITE;
141 case nir_intrinsic_ssbo_atomic_add:
142 case nir_intrinsic_shared_atomic_add:
143 return GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP;
144 case nir_intrinsic_ssbo_atomic_imin:
145 case nir_intrinsic_shared_atomic_imin:
146 return GENERAL_TMU_WRITE_OP_ATOMIC_SMIN;
147 case nir_intrinsic_ssbo_atomic_umin:
148 case nir_intrinsic_shared_atomic_umin:
149 return GENERAL_TMU_WRITE_OP_ATOMIC_UMIN;
150 case nir_intrinsic_ssbo_atomic_imax:
151 case nir_intrinsic_shared_atomic_imax:
152 return GENERAL_TMU_WRITE_OP_ATOMIC_SMAX;
153 case nir_intrinsic_ssbo_atomic_umax:
154 case nir_intrinsic_shared_atomic_umax:
155 return GENERAL_TMU_WRITE_OP_ATOMIC_UMAX;
156 case nir_intrinsic_ssbo_atomic_and:
157 case nir_intrinsic_shared_atomic_and:
158 return GENERAL_TMU_WRITE_OP_ATOMIC_AND;
159 case nir_intrinsic_ssbo_atomic_or:
160 case nir_intrinsic_shared_atomic_or:
161 return GENERAL_TMU_WRITE_OP_ATOMIC_OR;
162 case nir_intrinsic_ssbo_atomic_xor:
163 case nir_intrinsic_shared_atomic_xor:
164 return GENERAL_TMU_WRITE_OP_ATOMIC_XOR;
165 case nir_intrinsic_ssbo_atomic_exchange:
166 case nir_intrinsic_shared_atomic_exchange:
167 return GENERAL_TMU_WRITE_OP_ATOMIC_XCHG;
168 case nir_intrinsic_ssbo_atomic_comp_swap:
169 case nir_intrinsic_shared_atomic_comp_swap:
170 return GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG;
171 default:
172 unreachable("unknown intrinsic op");
173 }
174 }
175
176 /**
177 * Implements indirect uniform loads and SSBO accesses through the TMU general
178 * memory access interface.
179 */
180 static void
181 ntq_emit_tmu_general(struct v3d_compile *c, nir_intrinsic_instr *instr,
182 bool is_shared_or_scratch)
183 {
184 /* XXX perf: We should turn add/sub of 1 to inc/dec. Perhaps NIR
185 * wants to have support for inc/dec?
186 */
187
188 uint32_t tmu_op = v3d_general_tmu_op(instr);
189 bool is_store = (instr->intrinsic == nir_intrinsic_store_ssbo ||
190 instr->intrinsic == nir_intrinsic_store_scratch ||
191 instr->intrinsic == nir_intrinsic_store_shared);
192 bool has_index = !is_shared_or_scratch;
193
194 int offset_src;
195 int tmu_writes = 1; /* address */
196 if (instr->intrinsic == nir_intrinsic_load_uniform) {
197 offset_src = 0;
198 } else if (instr->intrinsic == nir_intrinsic_load_ssbo ||
199 instr->intrinsic == nir_intrinsic_load_ubo ||
200 instr->intrinsic == nir_intrinsic_load_scratch ||
201 instr->intrinsic == nir_intrinsic_load_shared) {
202 offset_src = 0 + has_index;
203 } else if (is_store) {
204 offset_src = 1 + has_index;
205 for (int i = 0; i < instr->num_components; i++) {
206 vir_MOV_dest(c,
207 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
208 ntq_get_src(c, instr->src[0], i));
209 tmu_writes++;
210 }
211 } else {
212 offset_src = 0 + has_index;
213 vir_MOV_dest(c,
214 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
215 ntq_get_src(c, instr->src[1 + has_index], 0));
216 tmu_writes++;
217 if (tmu_op == GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG) {
218 vir_MOV_dest(c,
219 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
220 ntq_get_src(c, instr->src[2 + has_index],
221 0));
222 tmu_writes++;
223 }
224 }
225
226 bool dynamic_src = !nir_src_is_const(instr->src[offset_src]);
227 uint32_t const_offset = 0;
228 if (!dynamic_src)
229 const_offset = nir_src_as_uint(instr->src[offset_src]);
230
231 /* Make sure we won't exceed the 16-entry TMU fifo if each thread is
232 * storing at the same time.
233 */
234 while (tmu_writes > 16 / c->threads)
235 c->threads /= 2;
236
237 struct qreg offset;
238 if (instr->intrinsic == nir_intrinsic_load_uniform) {
239 const_offset += nir_intrinsic_base(instr);
240 offset = vir_uniform(c, QUNIFORM_UBO_ADDR,
241 v3d_unit_data_create(0, const_offset));
242 const_offset = 0;
243 } else if (instr->intrinsic == nir_intrinsic_load_ubo) {
244 uint32_t index = nir_src_as_uint(instr->src[0]) + 1;
245 /* Note that QUNIFORM_UBO_ADDR takes a UBO index shifted up by
246 * 1 (0 is gallium's constant buffer 0).
247 */
248 offset = vir_uniform(c, QUNIFORM_UBO_ADDR,
249 v3d_unit_data_create(index, const_offset));
250 const_offset = 0;
251 } else if (is_shared_or_scratch) {
252 /* Shared and scratch variables have no buffer index, and all
253 * start from a common base that we set up at the start of
254 * dispatch.
255 */
256 if (instr->intrinsic == nir_intrinsic_load_scratch ||
257 instr->intrinsic == nir_intrinsic_store_scratch) {
258 offset = c->spill_base;
259 } else {
260 offset = c->cs_shared_offset;
261 const_offset += nir_intrinsic_base(instr);
262 }
263 } else {
264 offset = vir_uniform(c, QUNIFORM_SSBO_OFFSET,
265 nir_src_as_uint(instr->src[is_store ?
266 1 : 0]));
267 }
268
269 /* The spec says that for atomics, the TYPE field is ignored, but that
270 * doesn't seem to be the case for CMPXCHG. Just use the number of
271 * tmud writes we did to decide the type (or choose "32bit" for atomic
272 * reads, which has been fine).
273 */
274 int num_components;
275 if (tmu_op == GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG)
276 num_components = 2;
277 else
278 num_components = instr->num_components;
279
280 uint32_t config = (0xffffff00 |
281 tmu_op |
282 GENERAL_TMU_LOOKUP_PER_PIXEL);
283 if (num_components == 1) {
284 config |= GENERAL_TMU_LOOKUP_TYPE_32BIT_UI;
285 } else {
286 config |= GENERAL_TMU_LOOKUP_TYPE_VEC2 + num_components - 2;
287 }
288
289 if (vir_in_nonuniform_control_flow(c)) {
290 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
291 V3D_QPU_PF_PUSHZ);
292 }
293
294 struct qreg tmua;
295 if (config == ~0)
296 tmua = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA);
297 else
298 tmua = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUAU);
299
300 struct qinst *tmu;
301 if (dynamic_src) {
302 if (const_offset != 0) {
303 offset = vir_ADD(c, offset,
304 vir_uniform_ui(c, const_offset));
305 }
306 tmu = vir_ADD_dest(c, tmua, offset,
307 ntq_get_src(c, instr->src[offset_src], 0));
308 } else {
309 if (const_offset != 0) {
310 tmu = vir_ADD_dest(c, tmua, offset,
311 vir_uniform_ui(c, const_offset));
312 } else {
313 tmu = vir_MOV_dest(c, tmua, offset);
314 }
315 }
316
317 if (config != ~0) {
318 tmu->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT,
319 config);
320 }
321
322 if (vir_in_nonuniform_control_flow(c))
323 vir_set_cond(tmu, V3D_QPU_COND_IFA);
324
325 vir_emit_thrsw(c);
326
327 /* Read the result, or wait for the TMU op to complete. */
328 for (int i = 0; i < nir_intrinsic_dest_components(instr); i++)
329 ntq_store_dest(c, &instr->dest, i, vir_MOV(c, vir_LDTMU(c)));
330
331 if (nir_intrinsic_dest_components(instr) == 0)
332 vir_TMUWT(c);
333 }
334
335 static struct qreg *
336 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
337 {
338 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
339 def->num_components);
340 _mesa_hash_table_insert(c->def_ht, def, qregs);
341 return qregs;
342 }
343
344 /**
345 * This function is responsible for getting VIR results into the associated
346 * storage for a NIR instruction.
347 *
348 * If it's a NIR SSA def, then we just set the associated hash table entry to
349 * the new result.
350 *
351 * If it's a NIR reg, then we need to update the existing qreg assigned to the
352 * NIR destination with the incoming value. To do that without introducing
353 * new MOVs, we require that the incoming qreg either be a uniform, or be
354 * SSA-defined by the previous VIR instruction in the block and rewritable by
355 * this function. That lets us sneak ahead and insert the SF flag beforehand
356 * (knowing that the previous instruction doesn't depend on flags) and rewrite
357 * its destination to be the NIR reg's destination
358 */
359 void
360 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
361 struct qreg result)
362 {
363 struct qinst *last_inst = NULL;
364 if (!list_empty(&c->cur_block->instructions))
365 last_inst = (struct qinst *)c->cur_block->instructions.prev;
366
367 assert((result.file == QFILE_TEMP &&
368 last_inst && last_inst == c->defs[result.index]));
369
370 if (dest->is_ssa) {
371 assert(chan < dest->ssa.num_components);
372
373 struct qreg *qregs;
374 struct hash_entry *entry =
375 _mesa_hash_table_search(c->def_ht, &dest->ssa);
376
377 if (entry)
378 qregs = entry->data;
379 else
380 qregs = ntq_init_ssa_def(c, &dest->ssa);
381
382 qregs[chan] = result;
383 } else {
384 nir_register *reg = dest->reg.reg;
385 assert(dest->reg.base_offset == 0);
386 assert(reg->num_array_elems == 0);
387 struct hash_entry *entry =
388 _mesa_hash_table_search(c->def_ht, reg);
389 struct qreg *qregs = entry->data;
390
391 /* Insert a MOV if the source wasn't an SSA def in the
392 * previous instruction.
393 */
394 if ((vir_in_nonuniform_control_flow(c) &&
395 c->defs[last_inst->dst.index]->qpu.sig.ldunif)) {
396 result = vir_MOV(c, result);
397 last_inst = c->defs[result.index];
398 }
399
400 /* We know they're both temps, so just rewrite index. */
401 c->defs[last_inst->dst.index] = NULL;
402 last_inst->dst.index = qregs[chan].index;
403
404 /* If we're in control flow, then make this update of the reg
405 * conditional on the execution mask.
406 */
407 if (vir_in_nonuniform_control_flow(c)) {
408 last_inst->dst.index = qregs[chan].index;
409
410 /* Set the flags to the current exec mask.
411 */
412 c->cursor = vir_before_inst(last_inst);
413 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
414 V3D_QPU_PF_PUSHZ);
415 c->cursor = vir_after_inst(last_inst);
416
417 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
418 }
419 }
420 }
421
422 struct qreg
423 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
424 {
425 struct hash_entry *entry;
426 if (src.is_ssa) {
427 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
428 assert(i < src.ssa->num_components);
429 } else {
430 nir_register *reg = src.reg.reg;
431 entry = _mesa_hash_table_search(c->def_ht, reg);
432 assert(reg->num_array_elems == 0);
433 assert(src.reg.base_offset == 0);
434 assert(i < reg->num_components);
435 }
436
437 struct qreg *qregs = entry->data;
438 return qregs[i];
439 }
440
441 static struct qreg
442 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
443 unsigned src)
444 {
445 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
446 unsigned chan = ffs(instr->dest.write_mask) - 1;
447 struct qreg r = ntq_get_src(c, instr->src[src].src,
448 instr->src[src].swizzle[chan]);
449
450 assert(!instr->src[src].abs);
451 assert(!instr->src[src].negate);
452
453 return r;
454 };
455
456 static struct qreg
457 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
458 {
459 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
460 }
461
462 static void
463 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
464 {
465 unsigned unit = instr->texture_index;
466 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
467 int dest_size = nir_tex_instr_dest_size(instr);
468
469 struct qreg lod = c->undef;
470 if (lod_index != -1)
471 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
472
473 for (int i = 0; i < dest_size; i++) {
474 assert(i < 3);
475 enum quniform_contents contents;
476
477 if (instr->is_array && i == dest_size - 1)
478 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
479 else
480 contents = QUNIFORM_TEXTURE_WIDTH + i;
481
482 struct qreg size = vir_uniform(c, contents, unit);
483
484 switch (instr->sampler_dim) {
485 case GLSL_SAMPLER_DIM_1D:
486 case GLSL_SAMPLER_DIM_2D:
487 case GLSL_SAMPLER_DIM_MS:
488 case GLSL_SAMPLER_DIM_3D:
489 case GLSL_SAMPLER_DIM_CUBE:
490 /* Don't minify the array size. */
491 if (!(instr->is_array && i == dest_size - 1)) {
492 size = ntq_minify(c, size, lod);
493 }
494 break;
495
496 case GLSL_SAMPLER_DIM_RECT:
497 /* There's no LOD field for rects */
498 break;
499
500 default:
501 unreachable("Bad sampler type");
502 }
503
504 ntq_store_dest(c, &instr->dest, i, size);
505 }
506 }
507
508 static void
509 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
510 {
511 unsigned unit = instr->texture_index;
512
513 /* Since each texture sampling op requires uploading uniforms to
514 * reference the texture, there's no HW support for texture size and
515 * you just upload uniforms containing the size.
516 */
517 switch (instr->op) {
518 case nir_texop_query_levels:
519 ntq_store_dest(c, &instr->dest, 0,
520 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
521 return;
522 case nir_texop_txs:
523 ntq_emit_txs(c, instr);
524 return;
525 default:
526 break;
527 }
528
529 if (c->devinfo->ver >= 40)
530 v3d40_vir_emit_tex(c, instr);
531 else
532 v3d33_vir_emit_tex(c, instr);
533 }
534
535 static struct qreg
536 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
537 {
538 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
539 if (is_cos)
540 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
541
542 struct qreg periods = vir_FROUND(c, input);
543 struct qreg sin_output = vir_SIN(c, vir_FSUB(c, input, periods));
544 return vir_XOR(c, sin_output, vir_SHL(c,
545 vir_FTOIN(c, periods),
546 vir_uniform_ui(c, -1)));
547 }
548
549 static struct qreg
550 ntq_fsign(struct v3d_compile *c, struct qreg src)
551 {
552 struct qreg t = vir_get_temp(c);
553
554 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
555 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHZ);
556 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
557 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHN);
558 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
559 return vir_MOV(c, t);
560 }
561
562 static void
563 emit_fragcoord_input(struct v3d_compile *c, int attr)
564 {
565 c->inputs[attr * 4 + 0] = vir_FXCD(c);
566 c->inputs[attr * 4 + 1] = vir_FYCD(c);
567 c->inputs[attr * 4 + 2] = c->payload_z;
568 c->inputs[attr * 4 + 3] = vir_RECIP(c, c->payload_w);
569 }
570
571 static struct qreg
572 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
573 uint8_t swizzle, int array_index)
574 {
575 struct qreg r3 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R3);
576 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
577
578 struct qreg vary;
579 if (c->devinfo->ver >= 41) {
580 struct qinst *ldvary = vir_add_inst(V3D_QPU_A_NOP, c->undef,
581 c->undef, c->undef);
582 ldvary->qpu.sig.ldvary = true;
583 vary = vir_emit_def(c, ldvary);
584 } else {
585 vir_NOP(c)->qpu.sig.ldvary = true;
586 vary = r3;
587 }
588
589 /* For gl_PointCoord input or distance along a line, we'll be called
590 * with no nir_variable, and we don't count toward VPM size so we
591 * don't track an input slot.
592 */
593 if (!var) {
594 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
595 }
596
597 int i = c->num_inputs++;
598 c->input_slots[i] =
599 v3d_slot_from_slot_and_component(var->data.location +
600 array_index, swizzle);
601
602 switch (var->data.interpolation) {
603 case INTERP_MODE_NONE:
604 /* If a gl_FrontColor or gl_BackColor input has no interp
605 * qualifier, then if we're using glShadeModel(GL_FLAT) it
606 * needs to be flat shaded.
607 */
608 switch (var->data.location + array_index) {
609 case VARYING_SLOT_COL0:
610 case VARYING_SLOT_COL1:
611 case VARYING_SLOT_BFC0:
612 case VARYING_SLOT_BFC1:
613 if (c->fs_key->shade_model_flat) {
614 BITSET_SET(c->flat_shade_flags, i);
615 vir_MOV_dest(c, c->undef, vary);
616 return vir_MOV(c, r5);
617 } else {
618 return vir_FADD(c, vir_FMUL(c, vary,
619 c->payload_w), r5);
620 }
621 default:
622 break;
623 }
624 /* FALLTHROUGH */
625 case INTERP_MODE_SMOOTH:
626 if (var->data.centroid) {
627 BITSET_SET(c->centroid_flags, i);
628 return vir_FADD(c, vir_FMUL(c, vary,
629 c->payload_w_centroid), r5);
630 } else {
631 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
632 }
633 case INTERP_MODE_NOPERSPECTIVE:
634 BITSET_SET(c->noperspective_flags, i);
635 return vir_FADD(c, vir_MOV(c, vary), r5);
636 case INTERP_MODE_FLAT:
637 BITSET_SET(c->flat_shade_flags, i);
638 vir_MOV_dest(c, c->undef, vary);
639 return vir_MOV(c, r5);
640 default:
641 unreachable("Bad interp mode");
642 }
643 }
644
645 static void
646 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var,
647 int array_index)
648 {
649 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
650 int chan = var->data.location_frac + i;
651 c->inputs[attr * 4 + chan] =
652 emit_fragment_varying(c, var, chan, array_index);
653 }
654 }
655
656 static void
657 add_output(struct v3d_compile *c,
658 uint32_t decl_offset,
659 uint8_t slot,
660 uint8_t swizzle)
661 {
662 uint32_t old_array_size = c->outputs_array_size;
663 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
664 decl_offset + 1);
665
666 if (old_array_size != c->outputs_array_size) {
667 c->output_slots = reralloc(c,
668 c->output_slots,
669 struct v3d_varying_slot,
670 c->outputs_array_size);
671 }
672
673 c->output_slots[decl_offset] =
674 v3d_slot_from_slot_and_component(slot, swizzle);
675 }
676
677 /**
678 * If compare_instr is a valid comparison instruction, emits the
679 * compare_instr's comparison and returns the sel_instr's return value based
680 * on the compare_instr's result.
681 */
682 static bool
683 ntq_emit_comparison(struct v3d_compile *c,
684 nir_alu_instr *compare_instr,
685 enum v3d_qpu_cond *out_cond)
686 {
687 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
688 struct qreg src1;
689 if (nir_op_infos[compare_instr->op].num_inputs > 1)
690 src1 = ntq_get_alu_src(c, compare_instr, 1);
691 bool cond_invert = false;
692 struct qreg nop = vir_nop_reg();
693
694 switch (compare_instr->op) {
695 case nir_op_feq32:
696 case nir_op_seq:
697 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
698 break;
699 case nir_op_ieq32:
700 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
701 break;
702
703 case nir_op_fne32:
704 case nir_op_sne:
705 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
706 cond_invert = true;
707 break;
708 case nir_op_ine32:
709 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
710 cond_invert = true;
711 break;
712
713 case nir_op_fge32:
714 case nir_op_sge:
715 vir_set_pf(vir_FCMP_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
716 break;
717 case nir_op_ige32:
718 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
719 cond_invert = true;
720 break;
721 case nir_op_uge32:
722 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
723 cond_invert = true;
724 break;
725
726 case nir_op_slt:
727 case nir_op_flt32:
728 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHN);
729 break;
730 case nir_op_ilt32:
731 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
732 break;
733 case nir_op_ult32:
734 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
735 break;
736
737 case nir_op_i2b32:
738 vir_set_pf(vir_MOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ);
739 cond_invert = true;
740 break;
741
742 case nir_op_f2b32:
743 vir_set_pf(vir_FMOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ);
744 cond_invert = true;
745 break;
746
747 default:
748 return false;
749 }
750
751 *out_cond = cond_invert ? V3D_QPU_COND_IFNA : V3D_QPU_COND_IFA;
752
753 return true;
754 }
755
756 /* Finds an ALU instruction that generates our src value that could
757 * (potentially) be greedily emitted in the consuming instruction.
758 */
759 static struct nir_alu_instr *
760 ntq_get_alu_parent(nir_src src)
761 {
762 if (!src.is_ssa || src.ssa->parent_instr->type != nir_instr_type_alu)
763 return NULL;
764 nir_alu_instr *instr = nir_instr_as_alu(src.ssa->parent_instr);
765 if (!instr)
766 return NULL;
767
768 /* If the ALU instr's srcs are non-SSA, then we would have to avoid
769 * moving emission of the ALU instr down past another write of the
770 * src.
771 */
772 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
773 if (!instr->src[i].src.is_ssa)
774 return NULL;
775 }
776
777 return instr;
778 }
779
780 /* Turns a NIR bool into a condition code to predicate on. */
781 static enum v3d_qpu_cond
782 ntq_emit_bool_to_cond(struct v3d_compile *c, nir_src src)
783 {
784 nir_alu_instr *compare = ntq_get_alu_parent(src);
785 if (!compare)
786 goto out;
787
788 enum v3d_qpu_cond cond;
789 if (ntq_emit_comparison(c, compare, &cond))
790 return cond;
791
792 out:
793 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), ntq_get_src(c, src, 0)),
794 V3D_QPU_PF_PUSHZ);
795 return V3D_QPU_COND_IFNA;
796 }
797
798 static void
799 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
800 {
801 /* This should always be lowered to ALU operations for V3D. */
802 assert(!instr->dest.saturate);
803
804 /* Vectors are special in that they have non-scalarized writemasks,
805 * and just take the first swizzle channel for each argument in order
806 * into each writemask channel.
807 */
808 if (instr->op == nir_op_vec2 ||
809 instr->op == nir_op_vec3 ||
810 instr->op == nir_op_vec4) {
811 struct qreg srcs[4];
812 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
813 srcs[i] = ntq_get_src(c, instr->src[i].src,
814 instr->src[i].swizzle[0]);
815 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
816 ntq_store_dest(c, &instr->dest.dest, i,
817 vir_MOV(c, srcs[i]));
818 return;
819 }
820
821 /* General case: We can just grab the one used channel per src. */
822 struct qreg src[nir_op_infos[instr->op].num_inputs];
823 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
824 src[i] = ntq_get_alu_src(c, instr, i);
825 }
826
827 struct qreg result;
828
829 switch (instr->op) {
830 case nir_op_mov:
831 result = vir_MOV(c, src[0]);
832 break;
833
834 case nir_op_fneg:
835 result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
836 break;
837 case nir_op_ineg:
838 result = vir_NEG(c, src[0]);
839 break;
840
841 case nir_op_fmul:
842 result = vir_FMUL(c, src[0], src[1]);
843 break;
844 case nir_op_fadd:
845 result = vir_FADD(c, src[0], src[1]);
846 break;
847 case nir_op_fsub:
848 result = vir_FSUB(c, src[0], src[1]);
849 break;
850 case nir_op_fmin:
851 result = vir_FMIN(c, src[0], src[1]);
852 break;
853 case nir_op_fmax:
854 result = vir_FMAX(c, src[0], src[1]);
855 break;
856
857 case nir_op_f2i32: {
858 nir_alu_instr *src0_alu = ntq_get_alu_parent(instr->src[0].src);
859 if (src0_alu && src0_alu->op == nir_op_fround_even) {
860 result = vir_FTOIN(c, ntq_get_alu_src(c, src0_alu, 0));
861 } else {
862 result = vir_FTOIZ(c, src[0]);
863 }
864 break;
865 }
866
867 case nir_op_f2u32:
868 result = vir_FTOUZ(c, src[0]);
869 break;
870 case nir_op_i2f32:
871 result = vir_ITOF(c, src[0]);
872 break;
873 case nir_op_u2f32:
874 result = vir_UTOF(c, src[0]);
875 break;
876 case nir_op_b2f32:
877 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
878 break;
879 case nir_op_b2i32:
880 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
881 break;
882
883 case nir_op_iadd:
884 result = vir_ADD(c, src[0], src[1]);
885 break;
886 case nir_op_ushr:
887 result = vir_SHR(c, src[0], src[1]);
888 break;
889 case nir_op_isub:
890 result = vir_SUB(c, src[0], src[1]);
891 break;
892 case nir_op_ishr:
893 result = vir_ASR(c, src[0], src[1]);
894 break;
895 case nir_op_ishl:
896 result = vir_SHL(c, src[0], src[1]);
897 break;
898 case nir_op_imin:
899 result = vir_MIN(c, src[0], src[1]);
900 break;
901 case nir_op_umin:
902 result = vir_UMIN(c, src[0], src[1]);
903 break;
904 case nir_op_imax:
905 result = vir_MAX(c, src[0], src[1]);
906 break;
907 case nir_op_umax:
908 result = vir_UMAX(c, src[0], src[1]);
909 break;
910 case nir_op_iand:
911 result = vir_AND(c, src[0], src[1]);
912 break;
913 case nir_op_ior:
914 result = vir_OR(c, src[0], src[1]);
915 break;
916 case nir_op_ixor:
917 result = vir_XOR(c, src[0], src[1]);
918 break;
919 case nir_op_inot:
920 result = vir_NOT(c, src[0]);
921 break;
922
923 case nir_op_ufind_msb:
924 result = vir_SUB(c, vir_uniform_ui(c, 31), vir_CLZ(c, src[0]));
925 break;
926
927 case nir_op_imul:
928 result = vir_UMUL(c, src[0], src[1]);
929 break;
930
931 case nir_op_seq:
932 case nir_op_sne:
933 case nir_op_sge:
934 case nir_op_slt: {
935 enum v3d_qpu_cond cond;
936 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
937 assert(ok);
938 result = vir_MOV(c, vir_SEL(c, cond,
939 vir_uniform_f(c, 1.0),
940 vir_uniform_f(c, 0.0)));
941 break;
942 }
943
944 case nir_op_i2b32:
945 case nir_op_f2b32:
946 case nir_op_feq32:
947 case nir_op_fne32:
948 case nir_op_fge32:
949 case nir_op_flt32:
950 case nir_op_ieq32:
951 case nir_op_ine32:
952 case nir_op_ige32:
953 case nir_op_uge32:
954 case nir_op_ilt32:
955 case nir_op_ult32: {
956 enum v3d_qpu_cond cond;
957 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
958 assert(ok);
959 result = vir_MOV(c, vir_SEL(c, cond,
960 vir_uniform_ui(c, ~0),
961 vir_uniform_ui(c, 0)));
962 break;
963 }
964
965 case nir_op_b32csel:
966 result = vir_MOV(c,
967 vir_SEL(c,
968 ntq_emit_bool_to_cond(c, instr->src[0].src),
969 src[1], src[2]));
970 break;
971
972 case nir_op_fcsel:
973 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), src[0]),
974 V3D_QPU_PF_PUSHZ);
975 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
976 src[1], src[2]));
977 break;
978
979 case nir_op_frcp:
980 result = vir_RECIP(c, src[0]);
981 break;
982 case nir_op_frsq:
983 result = vir_RSQRT(c, src[0]);
984 break;
985 case nir_op_fexp2:
986 result = vir_EXP(c, src[0]);
987 break;
988 case nir_op_flog2:
989 result = vir_LOG(c, src[0]);
990 break;
991
992 case nir_op_fceil:
993 result = vir_FCEIL(c, src[0]);
994 break;
995 case nir_op_ffloor:
996 result = vir_FFLOOR(c, src[0]);
997 break;
998 case nir_op_fround_even:
999 result = vir_FROUND(c, src[0]);
1000 break;
1001 case nir_op_ftrunc:
1002 result = vir_FTRUNC(c, src[0]);
1003 break;
1004
1005 case nir_op_fsin:
1006 result = ntq_fsincos(c, src[0], false);
1007 break;
1008 case nir_op_fcos:
1009 result = ntq_fsincos(c, src[0], true);
1010 break;
1011
1012 case nir_op_fsign:
1013 result = ntq_fsign(c, src[0]);
1014 break;
1015
1016 case nir_op_fabs: {
1017 result = vir_FMOV(c, src[0]);
1018 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
1019 break;
1020 }
1021
1022 case nir_op_iabs:
1023 result = vir_MAX(c, src[0], vir_NEG(c, src[0]));
1024 break;
1025
1026 case nir_op_fddx:
1027 case nir_op_fddx_coarse:
1028 case nir_op_fddx_fine:
1029 result = vir_FDX(c, src[0]);
1030 break;
1031
1032 case nir_op_fddy:
1033 case nir_op_fddy_coarse:
1034 case nir_op_fddy_fine:
1035 result = vir_FDY(c, src[0]);
1036 break;
1037
1038 case nir_op_uadd_carry:
1039 vir_set_pf(vir_ADD_dest(c, vir_nop_reg(), src[0], src[1]),
1040 V3D_QPU_PF_PUSHC);
1041 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1042 vir_uniform_ui(c, ~0),
1043 vir_uniform_ui(c, 0)));
1044 break;
1045
1046 case nir_op_pack_half_2x16_split:
1047 result = vir_VFPACK(c, src[0], src[1]);
1048 break;
1049
1050 case nir_op_unpack_half_2x16_split_x:
1051 result = vir_FMOV(c, src[0]);
1052 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_L);
1053 break;
1054
1055 case nir_op_unpack_half_2x16_split_y:
1056 result = vir_FMOV(c, src[0]);
1057 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_H);
1058 break;
1059
1060 default:
1061 fprintf(stderr, "unknown NIR ALU inst: ");
1062 nir_print_instr(&instr->instr, stderr);
1063 fprintf(stderr, "\n");
1064 abort();
1065 }
1066
1067 /* We have a scalar result, so the instruction should only have a
1068 * single channel written to.
1069 */
1070 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
1071 ntq_store_dest(c, &instr->dest.dest,
1072 ffs(instr->dest.write_mask) - 1, result);
1073 }
1074
1075 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
1076 * specifier. They come from a register that's preloaded with 0xffffffff
1077 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
1078 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
1079 */
1080 #define TLB_TYPE_F16_COLOR (3 << 6)
1081 #define TLB_TYPE_I32_COLOR (1 << 6)
1082 #define TLB_TYPE_F32_COLOR (0 << 6)
1083 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
1084 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
1085 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
1086 #define TLB_F16_SWAP_HI_LO (1 << 1)
1087 #define TLB_VEC_SIZE_4_F16 (1 << 0)
1088 #define TLB_VEC_SIZE_2_F16 (0 << 0)
1089 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
1090
1091 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
1092 * flag is set.
1093 */
1094 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
1095 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
1096 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
1097 #define TLB_V42_DEPTH_TYPE_INVARIANT (0 << 3) /* Unmodified sideband input used */
1098 #define TLB_V42_DEPTH_TYPE_PER_PIXEL (1 << 3) /* QPU result used */
1099
1100 /* Stencil is a single 32-bit write. */
1101 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1102
1103 static void
1104 emit_frag_end(struct v3d_compile *c)
1105 {
1106 /* XXX
1107 if (c->output_sample_mask_index != -1) {
1108 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1109 }
1110 */
1111
1112 bool has_any_tlb_color_write = false;
1113 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1114 if (c->fs_key->cbufs & (1 << rt) && c->output_color_var[rt])
1115 has_any_tlb_color_write = true;
1116 }
1117
1118 if (c->fs_key->sample_alpha_to_coverage && c->output_color_var[0]) {
1119 struct nir_variable *var = c->output_color_var[0];
1120 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1121
1122 vir_SETMSF_dest(c, vir_nop_reg(),
1123 vir_AND(c,
1124 vir_MSF(c),
1125 vir_FTOC(c, color[3])));
1126 }
1127
1128 struct qreg tlb_reg = vir_magic_reg(V3D_QPU_WADDR_TLB);
1129 struct qreg tlbu_reg = vir_magic_reg(V3D_QPU_WADDR_TLBU);
1130 if (c->output_position_index != -1) {
1131 struct qinst *inst = vir_MOV_dest(c, tlbu_reg,
1132 c->outputs[c->output_position_index]);
1133 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1134
1135 if (c->devinfo->ver >= 42) {
1136 tlb_specifier |= (TLB_V42_DEPTH_TYPE_PER_PIXEL |
1137 TLB_SAMPLE_MODE_PER_PIXEL);
1138 } else
1139 tlb_specifier |= TLB_DEPTH_TYPE_PER_PIXEL;
1140
1141 inst->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT,
1142 tlb_specifier |
1143 0xffffff00);
1144 c->writes_z = true;
1145 } else if (c->s->info.fs.uses_discard ||
1146 !c->s->info.fs.early_fragment_tests ||
1147 c->fs_key->sample_alpha_to_coverage ||
1148 !has_any_tlb_color_write) {
1149 /* Emit passthrough Z if it needed to be delayed until shader
1150 * end due to potential discards.
1151 *
1152 * Since (single-threaded) fragment shaders always need a TLB
1153 * write, emit passthrouh Z if we didn't have any color
1154 * buffers and flag us as potentially discarding, so that we
1155 * can use Z as the TLB write.
1156 */
1157 c->s->info.fs.uses_discard = true;
1158
1159 struct qinst *inst = vir_MOV_dest(c, tlbu_reg,
1160 vir_nop_reg());
1161 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1162
1163 if (c->devinfo->ver >= 42) {
1164 /* The spec says the PER_PIXEL flag is ignored for
1165 * invariant writes, but the simulator demands it.
1166 */
1167 tlb_specifier |= (TLB_V42_DEPTH_TYPE_INVARIANT |
1168 TLB_SAMPLE_MODE_PER_PIXEL);
1169 } else {
1170 tlb_specifier |= TLB_DEPTH_TYPE_INVARIANT;
1171 }
1172
1173 inst->uniform = vir_get_uniform_index(c,
1174 QUNIFORM_CONSTANT,
1175 tlb_specifier |
1176 0xffffff00);
1177 c->writes_z = true;
1178 }
1179
1180 /* XXX: Performance improvement: Merge Z write and color writes TLB
1181 * uniform setup
1182 */
1183
1184 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1185 if (!(c->fs_key->cbufs & (1 << rt)) || !c->output_color_var[rt])
1186 continue;
1187
1188 nir_variable *var = c->output_color_var[rt];
1189 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1190 int num_components = glsl_get_vector_elements(var->type);
1191 uint32_t conf = 0xffffff00;
1192 struct qinst *inst;
1193
1194 conf |= TLB_SAMPLE_MODE_PER_PIXEL;
1195 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1196
1197 if (c->fs_key->swap_color_rb & (1 << rt))
1198 num_components = MAX2(num_components, 3);
1199
1200 assert(num_components != 0);
1201 switch (glsl_get_base_type(var->type)) {
1202 case GLSL_TYPE_UINT:
1203 case GLSL_TYPE_INT:
1204 /* The F32 vs I32 distinction was dropped in 4.2. */
1205 if (c->devinfo->ver < 42)
1206 conf |= TLB_TYPE_I32_COLOR;
1207 else
1208 conf |= TLB_TYPE_F32_COLOR;
1209 conf |= ((num_components - 1) <<
1210 TLB_VEC_SIZE_MINUS_1_SHIFT);
1211
1212 inst = vir_MOV_dest(c, tlbu_reg, color[0]);
1213 inst->uniform = vir_get_uniform_index(c,
1214 QUNIFORM_CONSTANT,
1215 conf);
1216
1217 for (int i = 1; i < num_components; i++) {
1218 inst = vir_MOV_dest(c, tlb_reg, color[i]);
1219 }
1220 break;
1221
1222 default: {
1223 struct qreg r = color[0];
1224 struct qreg g = color[1];
1225 struct qreg b = color[2];
1226 struct qreg a = color[3];
1227
1228 if (c->fs_key->f32_color_rb & (1 << rt)) {
1229 conf |= TLB_TYPE_F32_COLOR;
1230 conf |= ((num_components - 1) <<
1231 TLB_VEC_SIZE_MINUS_1_SHIFT);
1232 } else {
1233 conf |= TLB_TYPE_F16_COLOR;
1234 conf |= TLB_F16_SWAP_HI_LO;
1235 if (num_components >= 3)
1236 conf |= TLB_VEC_SIZE_4_F16;
1237 else
1238 conf |= TLB_VEC_SIZE_2_F16;
1239 }
1240
1241 if (c->fs_key->swap_color_rb & (1 << rt)) {
1242 r = color[2];
1243 b = color[0];
1244 }
1245
1246 if (c->fs_key->sample_alpha_to_one)
1247 a = vir_uniform_f(c, 1.0);
1248
1249 if (c->fs_key->f32_color_rb & (1 << rt)) {
1250 inst = vir_MOV_dest(c, tlbu_reg, r);
1251 inst->uniform = vir_get_uniform_index(c,
1252 QUNIFORM_CONSTANT,
1253 conf);
1254
1255 if (num_components >= 2)
1256 vir_MOV_dest(c, tlb_reg, g);
1257 if (num_components >= 3)
1258 vir_MOV_dest(c, tlb_reg, b);
1259 if (num_components >= 4)
1260 vir_MOV_dest(c, tlb_reg, a);
1261 } else {
1262 inst = vir_VFPACK_dest(c, tlb_reg, r, g);
1263 if (conf != ~0) {
1264 inst->dst = tlbu_reg;
1265 inst->uniform = vir_get_uniform_index(c,
1266 QUNIFORM_CONSTANT,
1267 conf);
1268 }
1269
1270 if (num_components >= 3)
1271 inst = vir_VFPACK_dest(c, tlb_reg, b, a);
1272 }
1273 break;
1274 }
1275 }
1276 }
1277 }
1278
1279 static void
1280 vir_VPM_WRITE(struct v3d_compile *c, struct qreg val, uint32_t vpm_index)
1281 {
1282 if (c->devinfo->ver >= 40) {
1283 vir_STVPMV(c, vir_uniform_ui(c, vpm_index), val);
1284 } else {
1285 /* XXX: v3d33_vir_vpm_write_setup(c); */
1286 vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM), val);
1287 }
1288 }
1289
1290 static void
1291 emit_vert_end(struct v3d_compile *c)
1292 {
1293 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1294 */
1295 if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
1296 vir_VPMWT(c);
1297 }
1298
1299 void
1300 v3d_optimize_nir(struct nir_shader *s)
1301 {
1302 bool progress;
1303 unsigned lower_flrp =
1304 (s->options->lower_flrp16 ? 16 : 0) |
1305 (s->options->lower_flrp32 ? 32 : 0) |
1306 (s->options->lower_flrp64 ? 64 : 0);
1307
1308 do {
1309 progress = false;
1310
1311 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1312 NIR_PASS(progress, s, nir_lower_alu_to_scalar, NULL);
1313 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1314 NIR_PASS(progress, s, nir_copy_prop);
1315 NIR_PASS(progress, s, nir_opt_remove_phis);
1316 NIR_PASS(progress, s, nir_opt_dce);
1317 NIR_PASS(progress, s, nir_opt_dead_cf);
1318 NIR_PASS(progress, s, nir_opt_cse);
1319 NIR_PASS(progress, s, nir_opt_peephole_select, 8, true, true);
1320 NIR_PASS(progress, s, nir_opt_algebraic);
1321 NIR_PASS(progress, s, nir_opt_constant_folding);
1322
1323 if (lower_flrp != 0) {
1324 bool lower_flrp_progress = false;
1325
1326 NIR_PASS(lower_flrp_progress, s, nir_lower_flrp,
1327 lower_flrp,
1328 false /* always_precise */,
1329 s->options->lower_ffma);
1330 if (lower_flrp_progress) {
1331 NIR_PASS(progress, s, nir_opt_constant_folding);
1332 progress = true;
1333 }
1334
1335 /* Nothing should rematerialize any flrps, so we only
1336 * need to do this lowering once.
1337 */
1338 lower_flrp = 0;
1339 }
1340
1341 NIR_PASS(progress, s, nir_opt_undef);
1342 } while (progress);
1343
1344 NIR_PASS(progress, s, nir_opt_move_load_ubo);
1345 }
1346
1347 static int
1348 driver_location_compare(const void *in_a, const void *in_b)
1349 {
1350 const nir_variable *const *a = in_a;
1351 const nir_variable *const *b = in_b;
1352
1353 return (*a)->data.driver_location - (*b)->data.driver_location;
1354 }
1355
1356 static struct qreg
1357 ntq_emit_vpm_read(struct v3d_compile *c,
1358 uint32_t *num_components_queued,
1359 uint32_t *remaining,
1360 uint32_t vpm_index)
1361 {
1362 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1363
1364 if (c->devinfo->ver >= 40 ) {
1365 return vir_LDVPMV_IN(c,
1366 vir_uniform_ui(c,
1367 (*num_components_queued)++));
1368 }
1369
1370 if (*num_components_queued != 0) {
1371 (*num_components_queued)--;
1372 return vir_MOV(c, vpm);
1373 }
1374
1375 uint32_t num_components = MIN2(*remaining, 32);
1376
1377 v3d33_vir_vpm_read_setup(c, num_components);
1378
1379 *num_components_queued = num_components - 1;
1380 *remaining -= num_components;
1381
1382 return vir_MOV(c, vpm);
1383 }
1384
1385 static void
1386 ntq_setup_vpm_inputs(struct v3d_compile *c)
1387 {
1388 /* Figure out how many components of each vertex attribute the shader
1389 * uses. Each variable should have been split to individual
1390 * components and unused ones DCEed. The vertex fetcher will load
1391 * from the start of the attribute to the number of components we
1392 * declare we need in c->vattr_sizes[].
1393 */
1394 nir_foreach_variable(var, &c->s->inputs) {
1395 /* No VS attribute array support. */
1396 assert(MAX2(glsl_get_length(var->type), 1) == 1);
1397
1398 unsigned loc = var->data.driver_location;
1399 int start_component = var->data.location_frac;
1400 int num_components = glsl_get_components(var->type);
1401
1402 c->vattr_sizes[loc] = MAX2(c->vattr_sizes[loc],
1403 start_component + num_components);
1404 }
1405
1406 unsigned num_components = 0;
1407 uint32_t vpm_components_queued = 0;
1408 bool uses_iid = c->s->info.system_values_read &
1409 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1410 bool uses_vid = c->s->info.system_values_read &
1411 (1ull << SYSTEM_VALUE_VERTEX_ID);
1412 num_components += uses_iid;
1413 num_components += uses_vid;
1414
1415 for (int i = 0; i < ARRAY_SIZE(c->vattr_sizes); i++)
1416 num_components += c->vattr_sizes[i];
1417
1418 if (uses_iid) {
1419 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1420 &num_components, ~0);
1421 }
1422
1423 if (uses_vid) {
1424 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1425 &num_components, ~0);
1426 }
1427
1428 /* The actual loads will happen directly in nir_intrinsic_load_input
1429 * on newer versions.
1430 */
1431 if (c->devinfo->ver >= 40)
1432 return;
1433
1434 for (int loc = 0; loc < ARRAY_SIZE(c->vattr_sizes); loc++) {
1435 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1436 (loc + 1) * 4);
1437
1438 for (int i = 0; i < c->vattr_sizes[loc]; i++) {
1439 c->inputs[loc * 4 + i] =
1440 ntq_emit_vpm_read(c,
1441 &vpm_components_queued,
1442 &num_components,
1443 loc * 4 + i);
1444
1445 }
1446 }
1447
1448 if (c->devinfo->ver >= 40) {
1449 assert(vpm_components_queued == num_components);
1450 } else {
1451 assert(vpm_components_queued == 0);
1452 assert(num_components == 0);
1453 }
1454 }
1455
1456 static bool
1457 var_needs_point_coord(struct v3d_compile *c, nir_variable *var)
1458 {
1459 return (var->data.location == VARYING_SLOT_PNTC ||
1460 (var->data.location >= VARYING_SLOT_VAR0 &&
1461 (c->fs_key->point_sprite_mask &
1462 (1 << (var->data.location - VARYING_SLOT_VAR0)))));
1463 }
1464
1465 static void
1466 ntq_setup_fs_inputs(struct v3d_compile *c)
1467 {
1468 unsigned num_entries = 0;
1469 unsigned num_components = 0;
1470 nir_foreach_variable(var, &c->s->inputs) {
1471 num_entries++;
1472 num_components += glsl_get_components(var->type);
1473 }
1474
1475 nir_variable *vars[num_entries];
1476
1477 unsigned i = 0;
1478 nir_foreach_variable(var, &c->s->inputs)
1479 vars[i++] = var;
1480
1481 /* Sort the variables so that we emit the input setup in
1482 * driver_location order. This is required for VPM reads, whose data
1483 * is fetched into the VPM in driver_location (TGSI register index)
1484 * order.
1485 */
1486 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1487
1488 for (unsigned i = 0; i < num_entries; i++) {
1489 nir_variable *var = vars[i];
1490 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1491 unsigned loc = var->data.driver_location;
1492
1493 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1494 (loc + array_len) * 4);
1495
1496 if (var->data.location == VARYING_SLOT_POS) {
1497 emit_fragcoord_input(c, loc);
1498 } else if (var_needs_point_coord(c, var)) {
1499 c->inputs[loc * 4 + 0] = c->point_x;
1500 c->inputs[loc * 4 + 1] = c->point_y;
1501 } else {
1502 for (int j = 0; j < array_len; j++)
1503 emit_fragment_input(c, loc + j, var, j);
1504 }
1505 }
1506 }
1507
1508 static void
1509 ntq_setup_outputs(struct v3d_compile *c)
1510 {
1511 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
1512 return;
1513
1514 nir_foreach_variable(var, &c->s->outputs) {
1515 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1516 unsigned loc = var->data.driver_location * 4;
1517
1518 assert(array_len == 1);
1519 (void)array_len;
1520
1521 for (int i = 0; i < 4 - var->data.location_frac; i++) {
1522 add_output(c, loc + var->data.location_frac + i,
1523 var->data.location,
1524 var->data.location_frac + i);
1525 }
1526
1527 switch (var->data.location) {
1528 case FRAG_RESULT_COLOR:
1529 c->output_color_var[0] = var;
1530 c->output_color_var[1] = var;
1531 c->output_color_var[2] = var;
1532 c->output_color_var[3] = var;
1533 break;
1534 case FRAG_RESULT_DATA0:
1535 case FRAG_RESULT_DATA1:
1536 case FRAG_RESULT_DATA2:
1537 case FRAG_RESULT_DATA3:
1538 c->output_color_var[var->data.location -
1539 FRAG_RESULT_DATA0] = var;
1540 break;
1541 case FRAG_RESULT_DEPTH:
1542 c->output_position_index = loc;
1543 break;
1544 case FRAG_RESULT_SAMPLE_MASK:
1545 c->output_sample_mask_index = loc;
1546 break;
1547 }
1548 }
1549 }
1550
1551 /**
1552 * Sets up the mapping from nir_register to struct qreg *.
1553 *
1554 * Each nir_register gets a struct qreg per 32-bit component being stored.
1555 */
1556 static void
1557 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1558 {
1559 foreach_list_typed(nir_register, nir_reg, node, list) {
1560 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1561 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1562 array_len *
1563 nir_reg->num_components);
1564
1565 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1566
1567 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1568 qregs[i] = vir_get_temp(c);
1569 }
1570 }
1571
1572 static void
1573 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1574 {
1575 /* XXX perf: Experiment with using immediate loads to avoid having
1576 * these end up in the uniform stream. Watch out for breaking the
1577 * small immediates optimization in the process!
1578 */
1579 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1580 for (int i = 0; i < instr->def.num_components; i++)
1581 qregs[i] = vir_uniform_ui(c, instr->value[i].u32);
1582
1583 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1584 }
1585
1586 static void
1587 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1588 {
1589 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1590
1591 /* VIR needs there to be *some* value, so pick 0 (same as for
1592 * ntq_setup_registers().
1593 */
1594 for (int i = 0; i < instr->def.num_components; i++)
1595 qregs[i] = vir_uniform_ui(c, 0);
1596 }
1597
1598 static void
1599 ntq_emit_image_size(struct v3d_compile *c, nir_intrinsic_instr *instr)
1600 {
1601 assert(instr->intrinsic == nir_intrinsic_image_deref_size);
1602 nir_variable *var = nir_intrinsic_get_var(instr, 0);
1603 unsigned image_index = var->data.driver_location;
1604 const struct glsl_type *sampler_type = glsl_without_array(var->type);
1605 bool is_array = glsl_sampler_type_is_array(sampler_type);
1606
1607 ntq_store_dest(c, &instr->dest, 0,
1608 vir_uniform(c, QUNIFORM_IMAGE_WIDTH, image_index));
1609 if (instr->num_components > 1) {
1610 ntq_store_dest(c, &instr->dest, 1,
1611 vir_uniform(c, QUNIFORM_IMAGE_HEIGHT,
1612 image_index));
1613 }
1614 if (instr->num_components > 2) {
1615 ntq_store_dest(c, &instr->dest, 2,
1616 vir_uniform(c,
1617 is_array ?
1618 QUNIFORM_IMAGE_ARRAY_SIZE :
1619 QUNIFORM_IMAGE_DEPTH,
1620 image_index));
1621 }
1622 }
1623
1624 static void
1625 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
1626 {
1627 unsigned offset;
1628
1629 switch (instr->intrinsic) {
1630 case nir_intrinsic_load_uniform:
1631 if (nir_src_is_const(instr->src[0])) {
1632 int offset = (nir_intrinsic_base(instr) +
1633 nir_src_as_uint(instr->src[0]));
1634 assert(offset % 4 == 0);
1635 /* We need dwords */
1636 offset = offset / 4;
1637 for (int i = 0; i < instr->num_components; i++) {
1638 ntq_store_dest(c, &instr->dest, i,
1639 vir_uniform(c, QUNIFORM_UNIFORM,
1640 offset + i));
1641 }
1642 } else {
1643 ntq_emit_tmu_general(c, instr, false);
1644 }
1645 break;
1646
1647 case nir_intrinsic_load_ubo:
1648 ntq_emit_tmu_general(c, instr, false);
1649 break;
1650
1651 case nir_intrinsic_ssbo_atomic_add:
1652 case nir_intrinsic_ssbo_atomic_imin:
1653 case nir_intrinsic_ssbo_atomic_umin:
1654 case nir_intrinsic_ssbo_atomic_imax:
1655 case nir_intrinsic_ssbo_atomic_umax:
1656 case nir_intrinsic_ssbo_atomic_and:
1657 case nir_intrinsic_ssbo_atomic_or:
1658 case nir_intrinsic_ssbo_atomic_xor:
1659 case nir_intrinsic_ssbo_atomic_exchange:
1660 case nir_intrinsic_ssbo_atomic_comp_swap:
1661 case nir_intrinsic_load_ssbo:
1662 case nir_intrinsic_store_ssbo:
1663 ntq_emit_tmu_general(c, instr, false);
1664 break;
1665
1666 case nir_intrinsic_shared_atomic_add:
1667 case nir_intrinsic_shared_atomic_imin:
1668 case nir_intrinsic_shared_atomic_umin:
1669 case nir_intrinsic_shared_atomic_imax:
1670 case nir_intrinsic_shared_atomic_umax:
1671 case nir_intrinsic_shared_atomic_and:
1672 case nir_intrinsic_shared_atomic_or:
1673 case nir_intrinsic_shared_atomic_xor:
1674 case nir_intrinsic_shared_atomic_exchange:
1675 case nir_intrinsic_shared_atomic_comp_swap:
1676 case nir_intrinsic_load_shared:
1677 case nir_intrinsic_store_shared:
1678 case nir_intrinsic_load_scratch:
1679 case nir_intrinsic_store_scratch:
1680 ntq_emit_tmu_general(c, instr, true);
1681 break;
1682
1683 case nir_intrinsic_image_deref_load:
1684 case nir_intrinsic_image_deref_store:
1685 case nir_intrinsic_image_deref_atomic_add:
1686 case nir_intrinsic_image_deref_atomic_min:
1687 case nir_intrinsic_image_deref_atomic_max:
1688 case nir_intrinsic_image_deref_atomic_and:
1689 case nir_intrinsic_image_deref_atomic_or:
1690 case nir_intrinsic_image_deref_atomic_xor:
1691 case nir_intrinsic_image_deref_atomic_exchange:
1692 case nir_intrinsic_image_deref_atomic_comp_swap:
1693 v3d40_vir_emit_image_load_store(c, instr);
1694 break;
1695
1696 case nir_intrinsic_get_buffer_size:
1697 ntq_store_dest(c, &instr->dest, 0,
1698 vir_uniform(c, QUNIFORM_GET_BUFFER_SIZE,
1699 nir_src_as_uint(instr->src[0])));
1700 break;
1701
1702 case nir_intrinsic_load_user_clip_plane:
1703 for (int i = 0; i < instr->num_components; i++) {
1704 ntq_store_dest(c, &instr->dest, i,
1705 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1706 nir_intrinsic_ucp_id(instr) *
1707 4 + i));
1708 }
1709 break;
1710
1711 case nir_intrinsic_load_viewport_x_scale:
1712 ntq_store_dest(c, &instr->dest, 0,
1713 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE, 0));
1714 break;
1715
1716 case nir_intrinsic_load_viewport_y_scale:
1717 ntq_store_dest(c, &instr->dest, 0,
1718 vir_uniform(c, QUNIFORM_VIEWPORT_Y_SCALE, 0));
1719 break;
1720
1721 case nir_intrinsic_load_viewport_z_scale:
1722 ntq_store_dest(c, &instr->dest, 0,
1723 vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0));
1724 break;
1725
1726 case nir_intrinsic_load_viewport_z_offset:
1727 ntq_store_dest(c, &instr->dest, 0,
1728 vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0));
1729 break;
1730
1731 case nir_intrinsic_load_alpha_ref_float:
1732 ntq_store_dest(c, &instr->dest, 0,
1733 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1734 break;
1735
1736 case nir_intrinsic_load_sample_mask_in:
1737 ntq_store_dest(c, &instr->dest, 0, vir_MSF(c));
1738 break;
1739
1740 case nir_intrinsic_load_helper_invocation:
1741 vir_set_pf(vir_MSF_dest(c, vir_nop_reg()), V3D_QPU_PF_PUSHZ);
1742 ntq_store_dest(c, &instr->dest, 0,
1743 vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1744 vir_uniform_ui(c, ~0),
1745 vir_uniform_ui(c, 0))));
1746 break;
1747
1748 case nir_intrinsic_load_front_face:
1749 /* The register contains 0 (front) or 1 (back), and we need to
1750 * turn it into a NIR bool where true means front.
1751 */
1752 ntq_store_dest(c, &instr->dest, 0,
1753 vir_ADD(c,
1754 vir_uniform_ui(c, -1),
1755 vir_REVF(c)));
1756 break;
1757
1758 case nir_intrinsic_load_instance_id:
1759 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
1760 break;
1761
1762 case nir_intrinsic_load_vertex_id:
1763 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
1764 break;
1765
1766 case nir_intrinsic_load_input:
1767 /* Use ldvpmv (uniform offset) or ldvpmd (non-uniform offset)
1768 * and enable PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR.
1769 */
1770 offset = (nir_intrinsic_base(instr) +
1771 nir_src_as_uint(instr->src[0]));
1772 if (c->s->info.stage != MESA_SHADER_FRAGMENT &&
1773 c->devinfo->ver >= 40) {
1774 /* Emit the LDVPM directly now, rather than at the top
1775 * of the shader like we did for V3D 3.x (which needs
1776 * vpmsetup when not just taking the next offset).
1777 *
1778 * Note that delaying like this may introduce stalls,
1779 * as LDVPMV takes a minimum of 1 instruction but may
1780 * be slower if the VPM unit is busy with another QPU.
1781 */
1782 int index = 0;
1783 if (c->s->info.system_values_read &
1784 (1ull << SYSTEM_VALUE_INSTANCE_ID)) {
1785 index++;
1786 }
1787 if (c->s->info.system_values_read &
1788 (1ull << SYSTEM_VALUE_VERTEX_ID)) {
1789 index++;
1790 }
1791 for (int i = 0; i < offset; i++)
1792 index += c->vattr_sizes[i];
1793 index += nir_intrinsic_component(instr);
1794 for (int i = 0; i < instr->num_components; i++) {
1795 struct qreg vpm_offset =
1796 vir_uniform_ui(c, index++);
1797 ntq_store_dest(c, &instr->dest, i,
1798 vir_LDVPMV_IN(c, vpm_offset));
1799 }
1800 } else {
1801 for (int i = 0; i < instr->num_components; i++) {
1802 int comp = nir_intrinsic_component(instr) + i;
1803 ntq_store_dest(c, &instr->dest, i,
1804 vir_MOV(c, c->inputs[offset * 4 +
1805 comp]));
1806 }
1807 }
1808 break;
1809
1810 case nir_intrinsic_store_output:
1811 /* XXX perf: Use stvpmv with uniform non-constant offsets and
1812 * stvpmd with non-uniform offsets and enable
1813 * PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR.
1814 */
1815 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1816 offset = ((nir_intrinsic_base(instr) +
1817 nir_src_as_uint(instr->src[1])) * 4 +
1818 nir_intrinsic_component(instr));
1819 for (int i = 0; i < instr->num_components; i++) {
1820 c->outputs[offset + i] =
1821 vir_MOV(c,
1822 ntq_get_src(c,
1823 instr->src[0], i));
1824 }
1825 } else {
1826 assert(instr->num_components == 1);
1827
1828 vir_VPM_WRITE(c,
1829 ntq_get_src(c, instr->src[0], 0),
1830 nir_intrinsic_base(instr));
1831 }
1832 break;
1833
1834 case nir_intrinsic_image_deref_size:
1835 ntq_emit_image_size(c, instr);
1836 break;
1837
1838 case nir_intrinsic_discard:
1839 if (vir_in_nonuniform_control_flow(c)) {
1840 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
1841 V3D_QPU_PF_PUSHZ);
1842 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
1843 vir_uniform_ui(c, 0)),
1844 V3D_QPU_COND_IFA);
1845 } else {
1846 vir_SETMSF_dest(c, vir_nop_reg(),
1847 vir_uniform_ui(c, 0));
1848 }
1849 break;
1850
1851 case nir_intrinsic_discard_if: {
1852 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, instr->src[0]);
1853
1854 if (vir_in_nonuniform_control_flow(c)) {
1855 struct qinst *exec_flag = vir_MOV_dest(c, vir_nop_reg(),
1856 c->execute);
1857 if (cond == V3D_QPU_COND_IFA) {
1858 vir_set_uf(exec_flag, V3D_QPU_UF_ANDZ);
1859 } else {
1860 vir_set_uf(exec_flag, V3D_QPU_UF_NORNZ);
1861 cond = V3D_QPU_COND_IFA;
1862 }
1863 }
1864
1865 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
1866 vir_uniform_ui(c, 0)), cond);
1867
1868 break;
1869 }
1870
1871 case nir_intrinsic_memory_barrier:
1872 case nir_intrinsic_memory_barrier_atomic_counter:
1873 case nir_intrinsic_memory_barrier_buffer:
1874 case nir_intrinsic_memory_barrier_image:
1875 case nir_intrinsic_memory_barrier_shared:
1876 case nir_intrinsic_group_memory_barrier:
1877 /* We don't do any instruction scheduling of these NIR
1878 * instructions between each other, so we just need to make
1879 * sure that the TMU operations before the barrier are flushed
1880 * before the ones after the barrier. That is currently
1881 * handled by having a THRSW in each of them and a LDTMU
1882 * series or a TMUWT after.
1883 */
1884 break;
1885
1886 case nir_intrinsic_barrier:
1887 /* Emit a TSY op to get all invocations in the workgroup
1888 * (actually supergroup) to block until the last invocation
1889 * reaches the TSY op.
1890 */
1891 if (c->devinfo->ver >= 42) {
1892 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
1893 V3D_QPU_WADDR_SYNCB));
1894 } else {
1895 struct qinst *sync =
1896 vir_BARRIERID_dest(c,
1897 vir_reg(QFILE_MAGIC,
1898 V3D_QPU_WADDR_SYNCU));
1899 sync->uniform =
1900 vir_get_uniform_index(c, QUNIFORM_CONSTANT,
1901 0xffffff00 |
1902 V3D_TSY_WAIT_INC_CHECK);
1903
1904 }
1905
1906 /* The blocking of a TSY op only happens at the next thread
1907 * switch. No texturing may be outstanding at the time of a
1908 * TSY blocking operation.
1909 */
1910 vir_emit_thrsw(c);
1911 break;
1912
1913 case nir_intrinsic_load_num_work_groups:
1914 for (int i = 0; i < 3; i++) {
1915 ntq_store_dest(c, &instr->dest, i,
1916 vir_uniform(c, QUNIFORM_NUM_WORK_GROUPS,
1917 i));
1918 }
1919 break;
1920
1921 case nir_intrinsic_load_local_invocation_index:
1922 ntq_store_dest(c, &instr->dest, 0,
1923 vir_SHR(c, c->cs_payload[1],
1924 vir_uniform_ui(c, 32 - c->local_invocation_index_bits)));
1925 break;
1926
1927 case nir_intrinsic_load_work_group_id:
1928 ntq_store_dest(c, &instr->dest, 0,
1929 vir_AND(c, c->cs_payload[0],
1930 vir_uniform_ui(c, 0xffff)));
1931 ntq_store_dest(c, &instr->dest, 1,
1932 vir_SHR(c, c->cs_payload[0],
1933 vir_uniform_ui(c, 16)));
1934 ntq_store_dest(c, &instr->dest, 2,
1935 vir_AND(c, c->cs_payload[1],
1936 vir_uniform_ui(c, 0xffff)));
1937 break;
1938
1939 case nir_intrinsic_load_subgroup_id:
1940 ntq_store_dest(c, &instr->dest, 0, vir_EIDX(c));
1941 break;
1942
1943 default:
1944 fprintf(stderr, "Unknown intrinsic: ");
1945 nir_print_instr(&instr->instr, stderr);
1946 fprintf(stderr, "\n");
1947 break;
1948 }
1949 }
1950
1951 /* Clears (activates) the execute flags for any channels whose jump target
1952 * matches this block.
1953 *
1954 * XXX perf: Could we be using flpush/flpop somehow for our execution channel
1955 * enabling?
1956 *
1957 * XXX perf: For uniform control flow, we should be able to skip c->execute
1958 * handling entirely.
1959 */
1960 static void
1961 ntq_activate_execute_for_block(struct v3d_compile *c)
1962 {
1963 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
1964 c->execute, vir_uniform_ui(c, c->cur_block->index)),
1965 V3D_QPU_PF_PUSHZ);
1966
1967 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
1968 }
1969
1970 static void
1971 ntq_emit_uniform_if(struct v3d_compile *c, nir_if *if_stmt)
1972 {
1973 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
1974 bool empty_else_block =
1975 (nir_else_block == nir_if_last_else_block(if_stmt) &&
1976 exec_list_is_empty(&nir_else_block->instr_list));
1977
1978 struct qblock *then_block = vir_new_block(c);
1979 struct qblock *after_block = vir_new_block(c);
1980 struct qblock *else_block;
1981 if (empty_else_block)
1982 else_block = after_block;
1983 else
1984 else_block = vir_new_block(c);
1985
1986 /* Set up the flags for the IF condition (taking the THEN branch). */
1987 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
1988
1989 /* Jump to ELSE. */
1990 vir_BRANCH(c, cond == V3D_QPU_COND_IFA ?
1991 V3D_QPU_BRANCH_COND_ALLNA :
1992 V3D_QPU_BRANCH_COND_ALLA);
1993 vir_link_blocks(c->cur_block, else_block);
1994 vir_link_blocks(c->cur_block, then_block);
1995
1996 /* Process the THEN block. */
1997 vir_set_emit_block(c, then_block);
1998 ntq_emit_cf_list(c, &if_stmt->then_list);
1999
2000 if (!empty_else_block) {
2001 /* At the end of the THEN block, jump to ENDIF */
2002 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALWAYS);
2003 vir_link_blocks(c->cur_block, after_block);
2004
2005 /* Emit the else block. */
2006 vir_set_emit_block(c, else_block);
2007 ntq_activate_execute_for_block(c);
2008 ntq_emit_cf_list(c, &if_stmt->else_list);
2009 }
2010
2011 vir_link_blocks(c->cur_block, after_block);
2012
2013 vir_set_emit_block(c, after_block);
2014 }
2015
2016 static void
2017 ntq_emit_nonuniform_if(struct v3d_compile *c, nir_if *if_stmt)
2018 {
2019 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2020 bool empty_else_block =
2021 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2022 exec_list_is_empty(&nir_else_block->instr_list));
2023
2024 struct qblock *then_block = vir_new_block(c);
2025 struct qblock *after_block = vir_new_block(c);
2026 struct qblock *else_block;
2027 if (empty_else_block)
2028 else_block = after_block;
2029 else
2030 else_block = vir_new_block(c);
2031
2032 bool was_uniform_control_flow = false;
2033 if (!vir_in_nonuniform_control_flow(c)) {
2034 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2035 was_uniform_control_flow = true;
2036 }
2037
2038 /* Set up the flags for the IF condition (taking the THEN branch). */
2039 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
2040
2041 /* Update the flags+cond to mean "Taking the ELSE branch (!cond) and
2042 * was previously active (execute Z) for updating the exec flags.
2043 */
2044 if (was_uniform_control_flow) {
2045 cond = v3d_qpu_cond_invert(cond);
2046 } else {
2047 struct qinst *inst = vir_MOV_dest(c, vir_nop_reg(), c->execute);
2048 if (cond == V3D_QPU_COND_IFA) {
2049 vir_set_uf(inst, V3D_QPU_UF_NORNZ);
2050 } else {
2051 vir_set_uf(inst, V3D_QPU_UF_ANDZ);
2052 cond = V3D_QPU_COND_IFA;
2053 }
2054 }
2055
2056 vir_MOV_cond(c, cond,
2057 c->execute,
2058 vir_uniform_ui(c, else_block->index));
2059
2060 /* Jump to ELSE if nothing is active for THEN, otherwise fall
2061 * through.
2062 */
2063 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ);
2064 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
2065 vir_link_blocks(c->cur_block, else_block);
2066 vir_link_blocks(c->cur_block, then_block);
2067
2068 /* Process the THEN block. */
2069 vir_set_emit_block(c, then_block);
2070 ntq_emit_cf_list(c, &if_stmt->then_list);
2071
2072 if (!empty_else_block) {
2073 /* Handle the end of the THEN block. First, all currently
2074 * active channels update their execute flags to point to
2075 * ENDIF
2076 */
2077 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2078 V3D_QPU_PF_PUSHZ);
2079 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2080 vir_uniform_ui(c, after_block->index));
2081
2082 /* If everything points at ENDIF, then jump there immediately. */
2083 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
2084 c->execute,
2085 vir_uniform_ui(c, after_block->index)),
2086 V3D_QPU_PF_PUSHZ);
2087 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
2088 vir_link_blocks(c->cur_block, after_block);
2089 vir_link_blocks(c->cur_block, else_block);
2090
2091 vir_set_emit_block(c, else_block);
2092 ntq_activate_execute_for_block(c);
2093 ntq_emit_cf_list(c, &if_stmt->else_list);
2094 }
2095
2096 vir_link_blocks(c->cur_block, after_block);
2097
2098 vir_set_emit_block(c, after_block);
2099 if (was_uniform_control_flow)
2100 c->execute = c->undef;
2101 else
2102 ntq_activate_execute_for_block(c);
2103 }
2104
2105 static void
2106 ntq_emit_if(struct v3d_compile *c, nir_if *nif)
2107 {
2108 bool was_in_control_flow = c->in_control_flow;
2109 c->in_control_flow = true;
2110 if (!vir_in_nonuniform_control_flow(c) &&
2111 nir_src_is_dynamically_uniform(nif->condition)) {
2112 ntq_emit_uniform_if(c, nif);
2113 } else {
2114 ntq_emit_nonuniform_if(c, nif);
2115 }
2116 c->in_control_flow = was_in_control_flow;
2117 }
2118
2119 static void
2120 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
2121 {
2122 switch (jump->type) {
2123 case nir_jump_break:
2124 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2125 V3D_QPU_PF_PUSHZ);
2126 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2127 vir_uniform_ui(c, c->loop_break_block->index));
2128 break;
2129
2130 case nir_jump_continue:
2131 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2132 V3D_QPU_PF_PUSHZ);
2133 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2134 vir_uniform_ui(c, c->loop_cont_block->index));
2135 break;
2136
2137 case nir_jump_return:
2138 unreachable("All returns shouold be lowered\n");
2139 }
2140 }
2141
2142 static void
2143 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
2144 {
2145 switch (instr->type) {
2146 case nir_instr_type_deref:
2147 /* ignored, will be walked by the intrinsic using it. */
2148 break;
2149
2150 case nir_instr_type_alu:
2151 ntq_emit_alu(c, nir_instr_as_alu(instr));
2152 break;
2153
2154 case nir_instr_type_intrinsic:
2155 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
2156 break;
2157
2158 case nir_instr_type_load_const:
2159 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
2160 break;
2161
2162 case nir_instr_type_ssa_undef:
2163 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
2164 break;
2165
2166 case nir_instr_type_tex:
2167 ntq_emit_tex(c, nir_instr_as_tex(instr));
2168 break;
2169
2170 case nir_instr_type_jump:
2171 ntq_emit_jump(c, nir_instr_as_jump(instr));
2172 break;
2173
2174 default:
2175 fprintf(stderr, "Unknown NIR instr type: ");
2176 nir_print_instr(instr, stderr);
2177 fprintf(stderr, "\n");
2178 abort();
2179 }
2180 }
2181
2182 static void
2183 ntq_emit_block(struct v3d_compile *c, nir_block *block)
2184 {
2185 nir_foreach_instr(instr, block) {
2186 ntq_emit_instr(c, instr);
2187 }
2188 }
2189
2190 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
2191
2192 static void
2193 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
2194 {
2195 bool was_in_control_flow = c->in_control_flow;
2196 c->in_control_flow = true;
2197
2198 bool was_uniform_control_flow = false;
2199 if (!vir_in_nonuniform_control_flow(c)) {
2200 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2201 was_uniform_control_flow = true;
2202 }
2203
2204 struct qblock *save_loop_cont_block = c->loop_cont_block;
2205 struct qblock *save_loop_break_block = c->loop_break_block;
2206
2207 c->loop_cont_block = vir_new_block(c);
2208 c->loop_break_block = vir_new_block(c);
2209
2210 vir_link_blocks(c->cur_block, c->loop_cont_block);
2211 vir_set_emit_block(c, c->loop_cont_block);
2212 ntq_activate_execute_for_block(c);
2213
2214 ntq_emit_cf_list(c, &loop->body);
2215
2216 /* Re-enable any previous continues now, so our ANYA check below
2217 * works.
2218 *
2219 * XXX: Use the .ORZ flags update, instead.
2220 */
2221 vir_set_pf(vir_XOR_dest(c,
2222 vir_nop_reg(),
2223 c->execute,
2224 vir_uniform_ui(c, c->loop_cont_block->index)),
2225 V3D_QPU_PF_PUSHZ);
2226 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2227
2228 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ);
2229
2230 struct qinst *branch = vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
2231 /* Pixels that were not dispatched or have been discarded should not
2232 * contribute to looping again.
2233 */
2234 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P;
2235 vir_link_blocks(c->cur_block, c->loop_cont_block);
2236 vir_link_blocks(c->cur_block, c->loop_break_block);
2237
2238 vir_set_emit_block(c, c->loop_break_block);
2239 if (was_uniform_control_flow)
2240 c->execute = c->undef;
2241 else
2242 ntq_activate_execute_for_block(c);
2243
2244 c->loop_break_block = save_loop_break_block;
2245 c->loop_cont_block = save_loop_cont_block;
2246
2247 c->loops++;
2248
2249 c->in_control_flow = was_in_control_flow;
2250 }
2251
2252 static void
2253 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
2254 {
2255 fprintf(stderr, "FUNCTIONS not handled.\n");
2256 abort();
2257 }
2258
2259 static void
2260 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
2261 {
2262 foreach_list_typed(nir_cf_node, node, node, list) {
2263 switch (node->type) {
2264 case nir_cf_node_block:
2265 ntq_emit_block(c, nir_cf_node_as_block(node));
2266 break;
2267
2268 case nir_cf_node_if:
2269 ntq_emit_if(c, nir_cf_node_as_if(node));
2270 break;
2271
2272 case nir_cf_node_loop:
2273 ntq_emit_loop(c, nir_cf_node_as_loop(node));
2274 break;
2275
2276 case nir_cf_node_function:
2277 ntq_emit_function(c, nir_cf_node_as_function(node));
2278 break;
2279
2280 default:
2281 fprintf(stderr, "Unknown NIR node type\n");
2282 abort();
2283 }
2284 }
2285 }
2286
2287 static void
2288 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
2289 {
2290 ntq_setup_registers(c, &impl->registers);
2291 ntq_emit_cf_list(c, &impl->body);
2292 }
2293
2294 static void
2295 nir_to_vir(struct v3d_compile *c)
2296 {
2297 switch (c->s->info.stage) {
2298 case MESA_SHADER_FRAGMENT:
2299 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
2300 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
2301 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
2302
2303 /* XXX perf: We could set the "disable implicit point/line
2304 * varyings" field in the shader record and not emit these, if
2305 * they're not going to be used.
2306 */
2307 if (c->fs_key->is_points) {
2308 c->point_x = emit_fragment_varying(c, NULL, 0, 0);
2309 c->point_y = emit_fragment_varying(c, NULL, 0, 0);
2310 } else if (c->fs_key->is_lines) {
2311 c->line_x = emit_fragment_varying(c, NULL, 0, 0);
2312 }
2313 break;
2314 case MESA_SHADER_COMPUTE:
2315 /* Set up the TSO for barriers, assuming we do some. */
2316 if (c->devinfo->ver < 42) {
2317 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
2318 V3D_QPU_WADDR_SYNC));
2319 }
2320
2321 c->cs_payload[0] = vir_MOV(c, vir_reg(QFILE_REG, 0));
2322 c->cs_payload[1] = vir_MOV(c, vir_reg(QFILE_REG, 2));
2323
2324 /* Set up the division between gl_LocalInvocationIndex and
2325 * wg_in_mem in the payload reg.
2326 */
2327 int wg_size = (c->s->info.cs.local_size[0] *
2328 c->s->info.cs.local_size[1] *
2329 c->s->info.cs.local_size[2]);
2330 c->local_invocation_index_bits =
2331 ffs(util_next_power_of_two(MAX2(wg_size, 64))) - 1;
2332 assert(c->local_invocation_index_bits <= 8);
2333
2334 if (c->s->info.cs.shared_size) {
2335 struct qreg wg_in_mem = vir_SHR(c, c->cs_payload[1],
2336 vir_uniform_ui(c, 16));
2337 if (c->s->info.cs.local_size[0] != 1 ||
2338 c->s->info.cs.local_size[1] != 1 ||
2339 c->s->info.cs.local_size[2] != 1) {
2340 int wg_bits = (16 -
2341 c->local_invocation_index_bits);
2342 int wg_mask = (1 << wg_bits) - 1;
2343 wg_in_mem = vir_AND(c, wg_in_mem,
2344 vir_uniform_ui(c, wg_mask));
2345 }
2346 struct qreg shared_per_wg =
2347 vir_uniform_ui(c, c->s->info.cs.shared_size);
2348
2349 c->cs_shared_offset =
2350 vir_ADD(c,
2351 vir_uniform(c, QUNIFORM_SHARED_OFFSET,0),
2352 vir_UMUL(c, wg_in_mem, shared_per_wg));
2353 }
2354 break;
2355 default:
2356 break;
2357 }
2358
2359 if (c->s->scratch_size) {
2360 v3d_setup_spill_base(c);
2361 c->spill_size += V3D_CHANNELS * c->s->scratch_size;
2362 }
2363
2364 if (c->s->info.stage == MESA_SHADER_FRAGMENT)
2365 ntq_setup_fs_inputs(c);
2366 else
2367 ntq_setup_vpm_inputs(c);
2368
2369 ntq_setup_outputs(c);
2370
2371 /* Find the main function and emit the body. */
2372 nir_foreach_function(function, c->s) {
2373 assert(strcmp(function->name, "main") == 0);
2374 assert(function->impl);
2375 ntq_emit_impl(c, function->impl);
2376 }
2377 }
2378
2379 const nir_shader_compiler_options v3d_nir_options = {
2380 .lower_all_io_to_temps = true,
2381 .lower_extract_byte = true,
2382 .lower_extract_word = true,
2383 .lower_bfm = true,
2384 .lower_bitfield_insert_to_shifts = true,
2385 .lower_bitfield_extract_to_shifts = true,
2386 .lower_bitfield_reverse = true,
2387 .lower_bit_count = true,
2388 .lower_cs_local_id_from_index = true,
2389 .lower_ffract = true,
2390 .lower_fmod = true,
2391 .lower_pack_unorm_2x16 = true,
2392 .lower_pack_snorm_2x16 = true,
2393 .lower_pack_unorm_4x8 = true,
2394 .lower_pack_snorm_4x8 = true,
2395 .lower_unpack_unorm_4x8 = true,
2396 .lower_unpack_snorm_4x8 = true,
2397 .lower_pack_half_2x16 = true,
2398 .lower_unpack_half_2x16 = true,
2399 .lower_fdiv = true,
2400 .lower_find_lsb = true,
2401 .lower_ffma = true,
2402 .lower_flrp32 = true,
2403 .lower_fpow = true,
2404 .lower_fsat = true,
2405 .lower_fsqrt = true,
2406 .lower_ifind_msb = true,
2407 .lower_isign = true,
2408 .lower_ldexp = true,
2409 .lower_mul_high = true,
2410 .lower_wpos_pntc = true,
2411 };
2412
2413 /**
2414 * When demoting a shader down to single-threaded, removes the THRSW
2415 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
2416 * program end).
2417 */
2418 static void
2419 vir_remove_thrsw(struct v3d_compile *c)
2420 {
2421 vir_for_each_block(block, c) {
2422 vir_for_each_inst_safe(inst, block) {
2423 if (inst->qpu.sig.thrsw)
2424 vir_remove_instruction(c, inst);
2425 }
2426 }
2427
2428 c->last_thrsw = NULL;
2429 }
2430
2431 void
2432 vir_emit_last_thrsw(struct v3d_compile *c)
2433 {
2434 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
2435 * switching, so disable threads if we didn't do any TMU ops (each of
2436 * which would have emitted a THRSW).
2437 */
2438 if (!c->last_thrsw_at_top_level && c->devinfo->ver < 41) {
2439 c->threads = 1;
2440 if (c->last_thrsw)
2441 vir_remove_thrsw(c);
2442 return;
2443 }
2444
2445 /* If we're threaded and the last THRSW was in conditional code, then
2446 * we need to emit another one so that we can flag it as the last
2447 * thrsw.
2448 */
2449 if (c->last_thrsw && !c->last_thrsw_at_top_level) {
2450 assert(c->devinfo->ver >= 41);
2451 vir_emit_thrsw(c);
2452 }
2453
2454 /* If we're threaded, then we need to mark the last THRSW instruction
2455 * so we can emit a pair of them at QPU emit time.
2456 *
2457 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2458 * post-last-THRSW state, so we can skip this.
2459 */
2460 if (!c->last_thrsw && c->s->info.stage == MESA_SHADER_FRAGMENT) {
2461 assert(c->devinfo->ver >= 41);
2462 vir_emit_thrsw(c);
2463 }
2464
2465 if (c->last_thrsw)
2466 c->last_thrsw->is_last_thrsw = true;
2467 }
2468
2469 /* There's a flag in the shader for "center W is needed for reasons other than
2470 * non-centroid varyings", so we just walk the program after VIR optimization
2471 * to see if it's used. It should be harmless to set even if we only use
2472 * center W for varyings.
2473 */
2474 static void
2475 vir_check_payload_w(struct v3d_compile *c)
2476 {
2477 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
2478 return;
2479
2480 vir_for_each_inst_inorder(inst, c) {
2481 for (int i = 0; i < vir_get_nsrc(inst); i++) {
2482 if (inst->src[i].file == QFILE_REG &&
2483 inst->src[i].index == 0) {
2484 c->uses_center_w = true;
2485 return;
2486 }
2487 }
2488 }
2489
2490 }
2491
2492 void
2493 v3d_nir_to_vir(struct v3d_compile *c)
2494 {
2495 if (V3D_DEBUG & (V3D_DEBUG_NIR |
2496 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2497 fprintf(stderr, "%s prog %d/%d NIR:\n",
2498 vir_get_stage_name(c),
2499 c->program_id, c->variant_id);
2500 nir_print_shader(c->s, stderr);
2501 }
2502
2503 nir_to_vir(c);
2504
2505 /* Emit the last THRSW before STVPM and TLB writes. */
2506 vir_emit_last_thrsw(c);
2507
2508 switch (c->s->info.stage) {
2509 case MESA_SHADER_FRAGMENT:
2510 emit_frag_end(c);
2511 break;
2512 case MESA_SHADER_VERTEX:
2513 emit_vert_end(c);
2514 break;
2515 case MESA_SHADER_COMPUTE:
2516 break;
2517 default:
2518 unreachable("bad stage");
2519 }
2520
2521 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2522 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2523 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
2524 vir_get_stage_name(c),
2525 c->program_id, c->variant_id);
2526 vir_dump(c);
2527 fprintf(stderr, "\n");
2528 }
2529
2530 vir_optimize(c);
2531
2532 vir_check_payload_w(c);
2533
2534 /* XXX perf: On VC4, we do a VIR-level instruction scheduling here.
2535 * We used that on that platform to pipeline TMU writes and reduce the
2536 * number of thread switches, as well as try (mostly successfully) to
2537 * reduce maximum register pressure to allow more threads. We should
2538 * do something of that sort for V3D -- either instruction scheduling
2539 * here, or delay the the THRSW and LDTMUs from our texture
2540 * instructions until the results are needed.
2541 */
2542
2543 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2544 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2545 fprintf(stderr, "%s prog %d/%d VIR:\n",
2546 vir_get_stage_name(c),
2547 c->program_id, c->variant_id);
2548 vir_dump(c);
2549 fprintf(stderr, "\n");
2550 }
2551
2552 /* Attempt to allocate registers for the temporaries. If we fail,
2553 * reduce thread count and try again.
2554 */
2555 int min_threads = (c->devinfo->ver >= 41) ? 2 : 1;
2556 struct qpu_reg *temp_registers;
2557 while (true) {
2558 bool spilled;
2559 temp_registers = v3d_register_allocate(c, &spilled);
2560 if (spilled)
2561 continue;
2562
2563 if (temp_registers)
2564 break;
2565
2566 if (c->threads == min_threads) {
2567 fprintf(stderr, "Failed to register allocate at %d threads:\n",
2568 c->threads);
2569 vir_dump(c);
2570 c->failed = true;
2571 return;
2572 }
2573
2574 c->threads /= 2;
2575
2576 if (c->threads == 1)
2577 vir_remove_thrsw(c);
2578 }
2579
2580 if (c->spills &&
2581 (V3D_DEBUG & (V3D_DEBUG_VIR |
2582 v3d_debug_flag_for_shader_stage(c->s->info.stage)))) {
2583 fprintf(stderr, "%s prog %d/%d spilled VIR:\n",
2584 vir_get_stage_name(c),
2585 c->program_id, c->variant_id);
2586 vir_dump(c);
2587 fprintf(stderr, "\n");
2588 }
2589
2590 v3d_vir_to_qpu(c, temp_registers);
2591 }