2 * Copyright © 2016 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
35 /* We don't do any address packing. */
36 #define __gen_user_data void
37 #define __gen_address_type uint32_t
38 #define __gen_address_offset(reloc) (*reloc)
39 #define __gen_emit_reloc(cl, reloc)
40 #include "cle/v3d_packet_v41_pack.h"
42 #define GENERAL_TMU_LOOKUP_PER_QUAD (0 << 7)
43 #define GENERAL_TMU_LOOKUP_PER_PIXEL (1 << 7)
44 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_I (0 << 0)
45 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_I (1 << 0)
46 #define GENERAL_TMU_LOOKUP_TYPE_VEC2 (2 << 0)
47 #define GENERAL_TMU_LOOKUP_TYPE_VEC3 (3 << 0)
48 #define GENERAL_TMU_LOOKUP_TYPE_VEC4 (4 << 0)
49 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_UI (5 << 0)
50 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_UI (6 << 0)
51 #define GENERAL_TMU_LOOKUP_TYPE_32BIT_UI (7 << 0)
53 #define V3D_TSY_SET_QUORUM 0
54 #define V3D_TSY_INC_WAITERS 1
55 #define V3D_TSY_DEC_WAITERS 2
56 #define V3D_TSY_INC_QUORUM 3
57 #define V3D_TSY_DEC_QUORUM 4
58 #define V3D_TSY_FREE_ALL 5
59 #define V3D_TSY_RELEASE 6
60 #define V3D_TSY_ACQUIRE 7
61 #define V3D_TSY_WAIT 8
62 #define V3D_TSY_WAIT_INC 9
63 #define V3D_TSY_WAIT_CHECK 10
64 #define V3D_TSY_WAIT_INC_CHECK 11
65 #define V3D_TSY_WAIT_CV 12
66 #define V3D_TSY_INC_SEMAPHORE 13
67 #define V3D_TSY_DEC_SEMAPHORE 14
68 #define V3D_TSY_SET_QUORUM_FREE_ALL 15
71 ntq_emit_cf_list(struct v3d_compile
*c
, struct exec_list
*list
);
74 resize_qreg_array(struct v3d_compile
*c
,
79 if (*size
>= decl_size
)
82 uint32_t old_size
= *size
;
83 *size
= MAX2(*size
* 2, decl_size
);
84 *regs
= reralloc(c
, *regs
, struct qreg
, *size
);
86 fprintf(stderr
, "Malloc failure\n");
90 for (uint32_t i
= old_size
; i
< *size
; i
++)
91 (*regs
)[i
] = c
->undef
;
95 vir_emit_thrsw(struct v3d_compile
*c
)
100 /* Always thread switch after each texture operation for now.
102 * We could do better by batching a bunch of texture fetches up and
103 * then doing one thread switch and collecting all their results
106 c
->last_thrsw
= vir_NOP(c
);
107 c
->last_thrsw
->qpu
.sig
.thrsw
= true;
108 c
->last_thrsw_at_top_level
= !c
->in_control_flow
;
110 /* We need to lock the scoreboard before any tlb acess happens. If this
111 * thread switch comes after we have emitted a tlb load, then it means
112 * that we can't lock on the last thread switch any more.
114 if (c
->emitted_tlb_load
)
115 c
->lock_scoreboard_on_first_thrsw
= true;
119 v3d_get_op_for_atomic_add(nir_intrinsic_instr
*instr
, unsigned src
)
121 if (nir_src_is_const(instr
->src
[src
])) {
122 int64_t add_val
= nir_src_as_int(instr
->src
[src
]);
124 return V3D_TMU_OP_WRITE_AND_READ_INC
;
125 else if (add_val
== -1)
126 return V3D_TMU_OP_WRITE_OR_READ_DEC
;
129 return V3D_TMU_OP_WRITE_ADD_READ_PREFETCH
;
133 v3d_general_tmu_op(nir_intrinsic_instr
*instr
)
135 switch (instr
->intrinsic
) {
136 case nir_intrinsic_load_ssbo
:
137 case nir_intrinsic_load_ubo
:
138 case nir_intrinsic_load_uniform
:
139 case nir_intrinsic_load_shared
:
140 case nir_intrinsic_load_scratch
:
141 case nir_intrinsic_store_ssbo
:
142 case nir_intrinsic_store_shared
:
143 case nir_intrinsic_store_scratch
:
144 return V3D_TMU_OP_REGULAR
;
145 case nir_intrinsic_ssbo_atomic_add
:
146 return v3d_get_op_for_atomic_add(instr
, 2);
147 case nir_intrinsic_shared_atomic_add
:
148 return v3d_get_op_for_atomic_add(instr
, 1);
149 case nir_intrinsic_ssbo_atomic_imin
:
150 case nir_intrinsic_shared_atomic_imin
:
151 return V3D_TMU_OP_WRITE_SMIN
;
152 case nir_intrinsic_ssbo_atomic_umin
:
153 case nir_intrinsic_shared_atomic_umin
:
154 return V3D_TMU_OP_WRITE_UMIN_FULL_L1_CLEAR
;
155 case nir_intrinsic_ssbo_atomic_imax
:
156 case nir_intrinsic_shared_atomic_imax
:
157 return V3D_TMU_OP_WRITE_SMAX
;
158 case nir_intrinsic_ssbo_atomic_umax
:
159 case nir_intrinsic_shared_atomic_umax
:
160 return V3D_TMU_OP_WRITE_UMAX
;
161 case nir_intrinsic_ssbo_atomic_and
:
162 case nir_intrinsic_shared_atomic_and
:
163 return V3D_TMU_OP_WRITE_AND_READ_INC
;
164 case nir_intrinsic_ssbo_atomic_or
:
165 case nir_intrinsic_shared_atomic_or
:
166 return V3D_TMU_OP_WRITE_OR_READ_DEC
;
167 case nir_intrinsic_ssbo_atomic_xor
:
168 case nir_intrinsic_shared_atomic_xor
:
169 return V3D_TMU_OP_WRITE_XOR_READ_NOT
;
170 case nir_intrinsic_ssbo_atomic_exchange
:
171 case nir_intrinsic_shared_atomic_exchange
:
172 return V3D_TMU_OP_WRITE_XCHG_READ_FLUSH
;
173 case nir_intrinsic_ssbo_atomic_comp_swap
:
174 case nir_intrinsic_shared_atomic_comp_swap
:
175 return V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH
;
177 unreachable("unknown intrinsic op");
182 * Implements indirect uniform loads and SSBO accesses through the TMU general
183 * memory access interface.
186 ntq_emit_tmu_general(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
,
187 bool is_shared_or_scratch
)
189 uint32_t tmu_op
= v3d_general_tmu_op(instr
);
191 /* If we were able to replace atomic_add for an inc/dec, then we
192 * need/can to do things slightly different, like not loading the
193 * amount to add/sub, as that is implicit.
195 bool atomic_add_replaced
= ((instr
->intrinsic
== nir_intrinsic_ssbo_atomic_add
||
196 instr
->intrinsic
== nir_intrinsic_shared_atomic_add
) &&
197 (tmu_op
== V3D_TMU_OP_WRITE_AND_READ_INC
||
198 tmu_op
== V3D_TMU_OP_WRITE_OR_READ_DEC
));
199 bool is_store
= (instr
->intrinsic
== nir_intrinsic_store_ssbo
||
200 instr
->intrinsic
== nir_intrinsic_store_scratch
||
201 instr
->intrinsic
== nir_intrinsic_store_shared
);
202 bool has_index
= !is_shared_or_scratch
;
205 int tmu_writes
= 1; /* address */
206 if (instr
->intrinsic
== nir_intrinsic_load_uniform
) {
208 } else if (instr
->intrinsic
== nir_intrinsic_load_ssbo
||
209 instr
->intrinsic
== nir_intrinsic_load_ubo
||
210 instr
->intrinsic
== nir_intrinsic_load_scratch
||
211 instr
->intrinsic
== nir_intrinsic_load_shared
||
212 atomic_add_replaced
) {
213 offset_src
= 0 + has_index
;
214 } else if (is_store
) {
215 offset_src
= 1 + has_index
;
216 for (int i
= 0; i
< instr
->num_components
; i
++) {
218 vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_TMUD
),
219 ntq_get_src(c
, instr
->src
[0], i
));
223 offset_src
= 0 + has_index
;
225 vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_TMUD
),
226 ntq_get_src(c
, instr
->src
[1 + has_index
], 0));
228 if (tmu_op
== V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH
) {
230 vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_TMUD
),
231 ntq_get_src(c
, instr
->src
[2 + has_index
],
237 bool dynamic_src
= !nir_src_is_const(instr
->src
[offset_src
]);
238 uint32_t const_offset
= 0;
240 const_offset
= nir_src_as_uint(instr
->src
[offset_src
]);
242 /* Make sure we won't exceed the 16-entry TMU fifo if each thread is
243 * storing at the same time.
245 while (tmu_writes
> 16 / c
->threads
)
249 if (instr
->intrinsic
== nir_intrinsic_load_uniform
) {
250 const_offset
+= nir_intrinsic_base(instr
);
251 offset
= vir_uniform(c
, QUNIFORM_UBO_ADDR
,
252 v3d_unit_data_create(0, const_offset
));
254 } else if (instr
->intrinsic
== nir_intrinsic_load_ubo
) {
255 uint32_t index
= nir_src_as_uint(instr
->src
[0]) + 1;
256 /* Note that QUNIFORM_UBO_ADDR takes a UBO index shifted up by
257 * 1 (0 is gallium's constant buffer 0).
259 offset
= vir_uniform(c
, QUNIFORM_UBO_ADDR
,
260 v3d_unit_data_create(index
, const_offset
));
262 } else if (is_shared_or_scratch
) {
263 /* Shared and scratch variables have no buffer index, and all
264 * start from a common base that we set up at the start of
267 if (instr
->intrinsic
== nir_intrinsic_load_scratch
||
268 instr
->intrinsic
== nir_intrinsic_store_scratch
) {
269 offset
= c
->spill_base
;
271 offset
= c
->cs_shared_offset
;
272 const_offset
+= nir_intrinsic_base(instr
);
275 offset
= vir_uniform(c
, QUNIFORM_SSBO_OFFSET
,
276 nir_src_as_uint(instr
->src
[is_store
?
280 /* The spec says that for atomics, the TYPE field is ignored, but that
281 * doesn't seem to be the case for CMPXCHG. Just use the number of
282 * tmud writes we did to decide the type (or choose "32bit" for atomic
283 * reads, which has been fine).
286 if (tmu_op
== V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH
)
289 num_components
= instr
->num_components
;
291 uint32_t config
= (0xffffff00 |
293 GENERAL_TMU_LOOKUP_PER_PIXEL
);
294 if (num_components
== 1) {
295 config
|= GENERAL_TMU_LOOKUP_TYPE_32BIT_UI
;
297 config
|= GENERAL_TMU_LOOKUP_TYPE_VEC2
+ num_components
- 2;
300 if (vir_in_nonuniform_control_flow(c
)) {
301 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
),
307 tmua
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_TMUA
);
309 tmua
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_TMUAU
);
313 if (const_offset
!= 0) {
314 offset
= vir_ADD(c
, offset
,
315 vir_uniform_ui(c
, const_offset
));
317 tmu
= vir_ADD_dest(c
, tmua
, offset
,
318 ntq_get_src(c
, instr
->src
[offset_src
], 0));
320 if (const_offset
!= 0) {
321 tmu
= vir_ADD_dest(c
, tmua
, offset
,
322 vir_uniform_ui(c
, const_offset
));
324 tmu
= vir_MOV_dest(c
, tmua
, offset
);
329 tmu
->uniform
= vir_get_uniform_index(c
, QUNIFORM_CONSTANT
,
333 if (vir_in_nonuniform_control_flow(c
))
334 vir_set_cond(tmu
, V3D_QPU_COND_IFA
);
338 /* Read the result, or wait for the TMU op to complete. */
339 for (int i
= 0; i
< nir_intrinsic_dest_components(instr
); i
++)
340 ntq_store_dest(c
, &instr
->dest
, i
, vir_MOV(c
, vir_LDTMU(c
)));
342 if (nir_intrinsic_dest_components(instr
) == 0)
347 ntq_init_ssa_def(struct v3d_compile
*c
, nir_ssa_def
*def
)
349 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
350 def
->num_components
);
351 _mesa_hash_table_insert(c
->def_ht
, def
, qregs
);
356 * This function is responsible for getting VIR results into the associated
357 * storage for a NIR instruction.
359 * If it's a NIR SSA def, then we just set the associated hash table entry to
362 * If it's a NIR reg, then we need to update the existing qreg assigned to the
363 * NIR destination with the incoming value. To do that without introducing
364 * new MOVs, we require that the incoming qreg either be a uniform, or be
365 * SSA-defined by the previous VIR instruction in the block and rewritable by
366 * this function. That lets us sneak ahead and insert the SF flag beforehand
367 * (knowing that the previous instruction doesn't depend on flags) and rewrite
368 * its destination to be the NIR reg's destination
371 ntq_store_dest(struct v3d_compile
*c
, nir_dest
*dest
, int chan
,
374 struct qinst
*last_inst
= NULL
;
375 if (!list_empty(&c
->cur_block
->instructions
))
376 last_inst
= (struct qinst
*)c
->cur_block
->instructions
.prev
;
378 assert((result
.file
== QFILE_TEMP
&&
379 last_inst
&& last_inst
== c
->defs
[result
.index
]));
382 assert(chan
< dest
->ssa
.num_components
);
385 struct hash_entry
*entry
=
386 _mesa_hash_table_search(c
->def_ht
, &dest
->ssa
);
391 qregs
= ntq_init_ssa_def(c
, &dest
->ssa
);
393 qregs
[chan
] = result
;
395 nir_register
*reg
= dest
->reg
.reg
;
396 assert(dest
->reg
.base_offset
== 0);
397 assert(reg
->num_array_elems
== 0);
398 struct hash_entry
*entry
=
399 _mesa_hash_table_search(c
->def_ht
, reg
);
400 struct qreg
*qregs
= entry
->data
;
402 /* Insert a MOV if the source wasn't an SSA def in the
403 * previous instruction.
405 if ((vir_in_nonuniform_control_flow(c
) &&
406 c
->defs
[last_inst
->dst
.index
]->qpu
.sig
.ldunif
)) {
407 result
= vir_MOV(c
, result
);
408 last_inst
= c
->defs
[result
.index
];
411 /* We know they're both temps, so just rewrite index. */
412 c
->defs
[last_inst
->dst
.index
] = NULL
;
413 last_inst
->dst
.index
= qregs
[chan
].index
;
415 /* If we're in control flow, then make this update of the reg
416 * conditional on the execution mask.
418 if (vir_in_nonuniform_control_flow(c
)) {
419 last_inst
->dst
.index
= qregs
[chan
].index
;
421 /* Set the flags to the current exec mask.
423 c
->cursor
= vir_before_inst(last_inst
);
424 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
),
426 c
->cursor
= vir_after_inst(last_inst
);
428 vir_set_cond(last_inst
, V3D_QPU_COND_IFA
);
434 ntq_get_src(struct v3d_compile
*c
, nir_src src
, int i
)
436 struct hash_entry
*entry
;
438 entry
= _mesa_hash_table_search(c
->def_ht
, src
.ssa
);
439 assert(i
< src
.ssa
->num_components
);
441 nir_register
*reg
= src
.reg
.reg
;
442 entry
= _mesa_hash_table_search(c
->def_ht
, reg
);
443 assert(reg
->num_array_elems
== 0);
444 assert(src
.reg
.base_offset
== 0);
445 assert(i
< reg
->num_components
);
448 struct qreg
*qregs
= entry
->data
;
453 ntq_get_alu_src(struct v3d_compile
*c
, nir_alu_instr
*instr
,
456 assert(util_is_power_of_two_or_zero(instr
->dest
.write_mask
));
457 unsigned chan
= ffs(instr
->dest
.write_mask
) - 1;
458 struct qreg r
= ntq_get_src(c
, instr
->src
[src
].src
,
459 instr
->src
[src
].swizzle
[chan
]);
461 assert(!instr
->src
[src
].abs
);
462 assert(!instr
->src
[src
].negate
);
468 ntq_minify(struct v3d_compile
*c
, struct qreg size
, struct qreg level
)
470 return vir_MAX(c
, vir_SHR(c
, size
, level
), vir_uniform_ui(c
, 1));
474 ntq_emit_txs(struct v3d_compile
*c
, nir_tex_instr
*instr
)
476 unsigned unit
= instr
->texture_index
;
477 int lod_index
= nir_tex_instr_src_index(instr
, nir_tex_src_lod
);
478 int dest_size
= nir_tex_instr_dest_size(instr
);
480 struct qreg lod
= c
->undef
;
482 lod
= ntq_get_src(c
, instr
->src
[lod_index
].src
, 0);
484 for (int i
= 0; i
< dest_size
; i
++) {
486 enum quniform_contents contents
;
488 if (instr
->is_array
&& i
== dest_size
- 1)
489 contents
= QUNIFORM_TEXTURE_ARRAY_SIZE
;
491 contents
= QUNIFORM_TEXTURE_WIDTH
+ i
;
493 struct qreg size
= vir_uniform(c
, contents
, unit
);
495 switch (instr
->sampler_dim
) {
496 case GLSL_SAMPLER_DIM_1D
:
497 case GLSL_SAMPLER_DIM_2D
:
498 case GLSL_SAMPLER_DIM_MS
:
499 case GLSL_SAMPLER_DIM_3D
:
500 case GLSL_SAMPLER_DIM_CUBE
:
501 /* Don't minify the array size. */
502 if (!(instr
->is_array
&& i
== dest_size
- 1)) {
503 size
= ntq_minify(c
, size
, lod
);
507 case GLSL_SAMPLER_DIM_RECT
:
508 /* There's no LOD field for rects */
512 unreachable("Bad sampler type");
515 ntq_store_dest(c
, &instr
->dest
, i
, size
);
520 ntq_emit_tex(struct v3d_compile
*c
, nir_tex_instr
*instr
)
522 unsigned unit
= instr
->texture_index
;
524 /* Since each texture sampling op requires uploading uniforms to
525 * reference the texture, there's no HW support for texture size and
526 * you just upload uniforms containing the size.
529 case nir_texop_query_levels
:
530 ntq_store_dest(c
, &instr
->dest
, 0,
531 vir_uniform(c
, QUNIFORM_TEXTURE_LEVELS
, unit
));
534 ntq_emit_txs(c
, instr
);
540 if (c
->devinfo
->ver
>= 40)
541 v3d40_vir_emit_tex(c
, instr
);
543 v3d33_vir_emit_tex(c
, instr
);
547 ntq_fsincos(struct v3d_compile
*c
, struct qreg src
, bool is_cos
)
549 struct qreg input
= vir_FMUL(c
, src
, vir_uniform_f(c
, 1.0f
/ M_PI
));
551 input
= vir_FADD(c
, input
, vir_uniform_f(c
, 0.5));
553 struct qreg periods
= vir_FROUND(c
, input
);
554 struct qreg sin_output
= vir_SIN(c
, vir_FSUB(c
, input
, periods
));
555 return vir_XOR(c
, sin_output
, vir_SHL(c
,
556 vir_FTOIN(c
, periods
),
557 vir_uniform_ui(c
, -1)));
561 ntq_fsign(struct v3d_compile
*c
, struct qreg src
)
563 struct qreg t
= vir_get_temp(c
);
565 vir_MOV_dest(c
, t
, vir_uniform_f(c
, 0.0));
566 vir_set_pf(vir_FMOV_dest(c
, vir_nop_reg(), src
), V3D_QPU_PF_PUSHZ
);
567 vir_MOV_cond(c
, V3D_QPU_COND_IFNA
, t
, vir_uniform_f(c
, 1.0));
568 vir_set_pf(vir_FMOV_dest(c
, vir_nop_reg(), src
), V3D_QPU_PF_PUSHN
);
569 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, t
, vir_uniform_f(c
, -1.0));
570 return vir_MOV(c
, t
);
574 emit_fragcoord_input(struct v3d_compile
*c
, int attr
)
576 c
->inputs
[attr
* 4 + 0] = vir_FXCD(c
);
577 c
->inputs
[attr
* 4 + 1] = vir_FYCD(c
);
578 c
->inputs
[attr
* 4 + 2] = c
->payload_z
;
579 c
->inputs
[attr
* 4 + 3] = vir_RECIP(c
, c
->payload_w
);
583 emit_fragment_varying(struct v3d_compile
*c
, nir_variable
*var
,
584 uint8_t swizzle
, int array_index
)
586 struct qreg r3
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_R3
);
587 struct qreg r5
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_R5
);
590 if (c
->devinfo
->ver
>= 41) {
591 struct qinst
*ldvary
= vir_add_inst(V3D_QPU_A_NOP
, c
->undef
,
593 ldvary
->qpu
.sig
.ldvary
= true;
594 vary
= vir_emit_def(c
, ldvary
);
596 vir_NOP(c
)->qpu
.sig
.ldvary
= true;
600 /* For gl_PointCoord input or distance along a line, we'll be called
601 * with no nir_variable, and we don't count toward VPM size so we
602 * don't track an input slot.
605 return vir_FADD(c
, vir_FMUL(c
, vary
, c
->payload_w
), r5
);
608 int i
= c
->num_inputs
++;
610 v3d_slot_from_slot_and_component(var
->data
.location
+
611 array_index
, swizzle
);
613 switch (var
->data
.interpolation
) {
614 case INTERP_MODE_NONE
:
615 /* If a gl_FrontColor or gl_BackColor input has no interp
616 * qualifier, then if we're using glShadeModel(GL_FLAT) it
617 * needs to be flat shaded.
619 switch (var
->data
.location
+ array_index
) {
620 case VARYING_SLOT_COL0
:
621 case VARYING_SLOT_COL1
:
622 case VARYING_SLOT_BFC0
:
623 case VARYING_SLOT_BFC1
:
624 if (c
->fs_key
->shade_model_flat
) {
625 BITSET_SET(c
->flat_shade_flags
, i
);
626 vir_MOV_dest(c
, c
->undef
, vary
);
627 return vir_MOV(c
, r5
);
629 return vir_FADD(c
, vir_FMUL(c
, vary
,
636 case INTERP_MODE_SMOOTH
:
637 if (var
->data
.centroid
) {
638 BITSET_SET(c
->centroid_flags
, i
);
639 return vir_FADD(c
, vir_FMUL(c
, vary
,
640 c
->payload_w_centroid
), r5
);
642 return vir_FADD(c
, vir_FMUL(c
, vary
, c
->payload_w
), r5
);
644 case INTERP_MODE_NOPERSPECTIVE
:
645 BITSET_SET(c
->noperspective_flags
, i
);
646 return vir_FADD(c
, vir_MOV(c
, vary
), r5
);
647 case INTERP_MODE_FLAT
:
648 BITSET_SET(c
->flat_shade_flags
, i
);
649 vir_MOV_dest(c
, c
->undef
, vary
);
650 return vir_MOV(c
, r5
);
652 unreachable("Bad interp mode");
657 emit_fragment_input(struct v3d_compile
*c
, int attr
, nir_variable
*var
,
660 for (int i
= 0; i
< glsl_get_vector_elements(var
->type
); i
++) {
661 int chan
= var
->data
.location_frac
+ i
;
662 c
->inputs
[attr
* 4 + chan
] =
663 emit_fragment_varying(c
, var
, chan
, array_index
);
668 add_output(struct v3d_compile
*c
,
669 uint32_t decl_offset
,
673 uint32_t old_array_size
= c
->outputs_array_size
;
674 resize_qreg_array(c
, &c
->outputs
, &c
->outputs_array_size
,
677 if (old_array_size
!= c
->outputs_array_size
) {
678 c
->output_slots
= reralloc(c
,
680 struct v3d_varying_slot
,
681 c
->outputs_array_size
);
684 c
->output_slots
[decl_offset
] =
685 v3d_slot_from_slot_and_component(slot
, swizzle
);
689 * If compare_instr is a valid comparison instruction, emits the
690 * compare_instr's comparison and returns the sel_instr's return value based
691 * on the compare_instr's result.
694 ntq_emit_comparison(struct v3d_compile
*c
,
695 nir_alu_instr
*compare_instr
,
696 enum v3d_qpu_cond
*out_cond
)
698 struct qreg src0
= ntq_get_alu_src(c
, compare_instr
, 0);
700 if (nir_op_infos
[compare_instr
->op
].num_inputs
> 1)
701 src1
= ntq_get_alu_src(c
, compare_instr
, 1);
702 bool cond_invert
= false;
703 struct qreg nop
= vir_nop_reg();
705 switch (compare_instr
->op
) {
708 vir_set_pf(vir_FCMP_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
711 vir_set_pf(vir_XOR_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
716 vir_set_pf(vir_FCMP_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
720 vir_set_pf(vir_XOR_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
726 vir_set_pf(vir_FCMP_dest(c
, nop
, src1
, src0
), V3D_QPU_PF_PUSHC
);
729 vir_set_pf(vir_MIN_dest(c
, nop
, src1
, src0
), V3D_QPU_PF_PUSHC
);
733 vir_set_pf(vir_SUB_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHC
);
739 vir_set_pf(vir_FCMP_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHN
);
742 vir_set_pf(vir_MIN_dest(c
, nop
, src1
, src0
), V3D_QPU_PF_PUSHC
);
745 vir_set_pf(vir_SUB_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHC
);
749 vir_set_pf(vir_MOV_dest(c
, nop
, src0
), V3D_QPU_PF_PUSHZ
);
754 vir_set_pf(vir_FMOV_dest(c
, nop
, src0
), V3D_QPU_PF_PUSHZ
);
762 *out_cond
= cond_invert
? V3D_QPU_COND_IFNA
: V3D_QPU_COND_IFA
;
767 /* Finds an ALU instruction that generates our src value that could
768 * (potentially) be greedily emitted in the consuming instruction.
770 static struct nir_alu_instr
*
771 ntq_get_alu_parent(nir_src src
)
773 if (!src
.is_ssa
|| src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
775 nir_alu_instr
*instr
= nir_instr_as_alu(src
.ssa
->parent_instr
);
779 /* If the ALU instr's srcs are non-SSA, then we would have to avoid
780 * moving emission of the ALU instr down past another write of the
783 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
784 if (!instr
->src
[i
].src
.is_ssa
)
791 /* Turns a NIR bool into a condition code to predicate on. */
792 static enum v3d_qpu_cond
793 ntq_emit_bool_to_cond(struct v3d_compile
*c
, nir_src src
)
795 nir_alu_instr
*compare
= ntq_get_alu_parent(src
);
799 enum v3d_qpu_cond cond
;
800 if (ntq_emit_comparison(c
, compare
, &cond
))
804 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), ntq_get_src(c
, src
, 0)),
806 return V3D_QPU_COND_IFNA
;
810 ntq_emit_alu(struct v3d_compile
*c
, nir_alu_instr
*instr
)
812 /* This should always be lowered to ALU operations for V3D. */
813 assert(!instr
->dest
.saturate
);
815 /* Vectors are special in that they have non-scalarized writemasks,
816 * and just take the first swizzle channel for each argument in order
817 * into each writemask channel.
819 if (instr
->op
== nir_op_vec2
||
820 instr
->op
== nir_op_vec3
||
821 instr
->op
== nir_op_vec4
) {
823 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
824 srcs
[i
] = ntq_get_src(c
, instr
->src
[i
].src
,
825 instr
->src
[i
].swizzle
[0]);
826 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
827 ntq_store_dest(c
, &instr
->dest
.dest
, i
,
828 vir_MOV(c
, srcs
[i
]));
832 /* General case: We can just grab the one used channel per src. */
833 struct qreg src
[nir_op_infos
[instr
->op
].num_inputs
];
834 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
835 src
[i
] = ntq_get_alu_src(c
, instr
, i
);
842 result
= vir_MOV(c
, src
[0]);
846 result
= vir_XOR(c
, src
[0], vir_uniform_ui(c
, 1 << 31));
849 result
= vir_NEG(c
, src
[0]);
853 result
= vir_FMUL(c
, src
[0], src
[1]);
856 result
= vir_FADD(c
, src
[0], src
[1]);
859 result
= vir_FSUB(c
, src
[0], src
[1]);
862 result
= vir_FMIN(c
, src
[0], src
[1]);
865 result
= vir_FMAX(c
, src
[0], src
[1]);
869 nir_alu_instr
*src0_alu
= ntq_get_alu_parent(instr
->src
[0].src
);
870 if (src0_alu
&& src0_alu
->op
== nir_op_fround_even
) {
871 result
= vir_FTOIN(c
, ntq_get_alu_src(c
, src0_alu
, 0));
873 result
= vir_FTOIZ(c
, src
[0]);
879 result
= vir_FTOUZ(c
, src
[0]);
882 result
= vir_ITOF(c
, src
[0]);
885 result
= vir_UTOF(c
, src
[0]);
888 result
= vir_AND(c
, src
[0], vir_uniform_f(c
, 1.0));
891 result
= vir_AND(c
, src
[0], vir_uniform_ui(c
, 1));
895 result
= vir_ADD(c
, src
[0], src
[1]);
898 result
= vir_SHR(c
, src
[0], src
[1]);
901 result
= vir_SUB(c
, src
[0], src
[1]);
904 result
= vir_ASR(c
, src
[0], src
[1]);
907 result
= vir_SHL(c
, src
[0], src
[1]);
910 result
= vir_MIN(c
, src
[0], src
[1]);
913 result
= vir_UMIN(c
, src
[0], src
[1]);
916 result
= vir_MAX(c
, src
[0], src
[1]);
919 result
= vir_UMAX(c
, src
[0], src
[1]);
922 result
= vir_AND(c
, src
[0], src
[1]);
925 result
= vir_OR(c
, src
[0], src
[1]);
928 result
= vir_XOR(c
, src
[0], src
[1]);
931 result
= vir_NOT(c
, src
[0]);
934 case nir_op_ufind_msb
:
935 result
= vir_SUB(c
, vir_uniform_ui(c
, 31), vir_CLZ(c
, src
[0]));
939 result
= vir_UMUL(c
, src
[0], src
[1]);
946 enum v3d_qpu_cond cond
;
947 MAYBE_UNUSED
bool ok
= ntq_emit_comparison(c
, instr
, &cond
);
949 result
= vir_MOV(c
, vir_SEL(c
, cond
,
950 vir_uniform_f(c
, 1.0),
951 vir_uniform_f(c
, 0.0)));
967 enum v3d_qpu_cond cond
;
968 MAYBE_UNUSED
bool ok
= ntq_emit_comparison(c
, instr
, &cond
);
970 result
= vir_MOV(c
, vir_SEL(c
, cond
,
971 vir_uniform_ui(c
, ~0),
972 vir_uniform_ui(c
, 0)));
979 ntq_emit_bool_to_cond(c
, instr
->src
[0].src
),
984 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), src
[0]),
986 result
= vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFNA
,
991 result
= vir_RECIP(c
, src
[0]);
994 result
= vir_RSQRT(c
, src
[0]);
997 result
= vir_EXP(c
, src
[0]);
1000 result
= vir_LOG(c
, src
[0]);
1004 result
= vir_FCEIL(c
, src
[0]);
1007 result
= vir_FFLOOR(c
, src
[0]);
1009 case nir_op_fround_even
:
1010 result
= vir_FROUND(c
, src
[0]);
1013 result
= vir_FTRUNC(c
, src
[0]);
1017 result
= ntq_fsincos(c
, src
[0], false);
1020 result
= ntq_fsincos(c
, src
[0], true);
1024 result
= ntq_fsign(c
, src
[0]);
1028 result
= vir_FMOV(c
, src
[0]);
1029 vir_set_unpack(c
->defs
[result
.index
], 0, V3D_QPU_UNPACK_ABS
);
1034 result
= vir_MAX(c
, src
[0], vir_NEG(c
, src
[0]));
1038 case nir_op_fddx_coarse
:
1039 case nir_op_fddx_fine
:
1040 result
= vir_FDX(c
, src
[0]);
1044 case nir_op_fddy_coarse
:
1045 case nir_op_fddy_fine
:
1046 result
= vir_FDY(c
, src
[0]);
1049 case nir_op_uadd_carry
:
1050 vir_set_pf(vir_ADD_dest(c
, vir_nop_reg(), src
[0], src
[1]),
1052 result
= vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFA
,
1053 vir_uniform_ui(c
, ~0),
1054 vir_uniform_ui(c
, 0)));
1057 case nir_op_pack_half_2x16_split
:
1058 result
= vir_VFPACK(c
, src
[0], src
[1]);
1061 case nir_op_unpack_half_2x16_split_x
:
1062 result
= vir_FMOV(c
, src
[0]);
1063 vir_set_unpack(c
->defs
[result
.index
], 0, V3D_QPU_UNPACK_L
);
1066 case nir_op_unpack_half_2x16_split_y
:
1067 result
= vir_FMOV(c
, src
[0]);
1068 vir_set_unpack(c
->defs
[result
.index
], 0, V3D_QPU_UNPACK_H
);
1072 fprintf(stderr
, "unknown NIR ALU inst: ");
1073 nir_print_instr(&instr
->instr
, stderr
);
1074 fprintf(stderr
, "\n");
1078 /* We have a scalar result, so the instruction should only have a
1079 * single channel written to.
1081 assert(util_is_power_of_two_or_zero(instr
->dest
.write_mask
));
1082 ntq_store_dest(c
, &instr
->dest
.dest
,
1083 ffs(instr
->dest
.write_mask
) - 1, result
);
1086 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
1087 * specifier. They come from a register that's preloaded with 0xffffffff
1088 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
1089 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
1091 #define TLB_TYPE_F16_COLOR (3 << 6)
1092 #define TLB_TYPE_I32_COLOR (1 << 6)
1093 #define TLB_TYPE_F32_COLOR (0 << 6)
1094 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
1095 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
1096 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
1097 #define TLB_F16_SWAP_HI_LO (1 << 1)
1098 #define TLB_VEC_SIZE_4_F16 (1 << 0)
1099 #define TLB_VEC_SIZE_2_F16 (0 << 0)
1100 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
1102 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
1105 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
1106 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
1107 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
1108 #define TLB_V42_DEPTH_TYPE_INVARIANT (0 << 3) /* Unmodified sideband input used */
1109 #define TLB_V42_DEPTH_TYPE_PER_PIXEL (1 << 3) /* QPU result used */
1111 /* Stencil is a single 32-bit write. */
1112 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1115 emit_frag_end(struct v3d_compile
*c
)
1118 if (c->output_sample_mask_index != -1) {
1119 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1123 bool has_any_tlb_color_write
= false;
1124 for (int rt
= 0; rt
< V3D_MAX_DRAW_BUFFERS
; rt
++) {
1125 if (c
->fs_key
->cbufs
& (1 << rt
) && c
->output_color_var
[rt
])
1126 has_any_tlb_color_write
= true;
1129 if (c
->fs_key
->sample_alpha_to_coverage
&& c
->output_color_var
[0]) {
1130 struct nir_variable
*var
= c
->output_color_var
[0];
1131 struct qreg
*color
= &c
->outputs
[var
->data
.driver_location
* 4];
1133 vir_SETMSF_dest(c
, vir_nop_reg(),
1136 vir_FTOC(c
, color
[3])));
1139 struct qreg tlb_reg
= vir_magic_reg(V3D_QPU_WADDR_TLB
);
1140 struct qreg tlbu_reg
= vir_magic_reg(V3D_QPU_WADDR_TLBU
);
1141 if (c
->output_position_index
!= -1) {
1142 struct qinst
*inst
= vir_MOV_dest(c
, tlbu_reg
,
1143 c
->outputs
[c
->output_position_index
]);
1144 uint8_t tlb_specifier
= TLB_TYPE_DEPTH
;
1146 if (c
->devinfo
->ver
>= 42) {
1147 tlb_specifier
|= (TLB_V42_DEPTH_TYPE_PER_PIXEL
|
1148 TLB_SAMPLE_MODE_PER_PIXEL
);
1150 tlb_specifier
|= TLB_DEPTH_TYPE_PER_PIXEL
;
1152 inst
->uniform
= vir_get_uniform_index(c
, QUNIFORM_CONSTANT
,
1156 } else if (c
->s
->info
.fs
.uses_discard
||
1157 !c
->s
->info
.fs
.early_fragment_tests
||
1158 c
->fs_key
->sample_alpha_to_coverage
||
1159 !has_any_tlb_color_write
) {
1160 /* Emit passthrough Z if it needed to be delayed until shader
1161 * end due to potential discards.
1163 * Since (single-threaded) fragment shaders always need a TLB
1164 * write, emit passthrouh Z if we didn't have any color
1165 * buffers and flag us as potentially discarding, so that we
1166 * can use Z as the TLB write.
1168 c
->s
->info
.fs
.uses_discard
= true;
1170 struct qinst
*inst
= vir_MOV_dest(c
, tlbu_reg
,
1172 uint8_t tlb_specifier
= TLB_TYPE_DEPTH
;
1174 if (c
->devinfo
->ver
>= 42) {
1175 /* The spec says the PER_PIXEL flag is ignored for
1176 * invariant writes, but the simulator demands it.
1178 tlb_specifier
|= (TLB_V42_DEPTH_TYPE_INVARIANT
|
1179 TLB_SAMPLE_MODE_PER_PIXEL
);
1181 tlb_specifier
|= TLB_DEPTH_TYPE_INVARIANT
;
1184 inst
->uniform
= vir_get_uniform_index(c
,
1191 /* XXX: Performance improvement: Merge Z write and color writes TLB
1195 for (int rt
= 0; rt
< V3D_MAX_DRAW_BUFFERS
; rt
++) {
1196 if (!(c
->fs_key
->cbufs
& (1 << rt
)) || !c
->output_color_var
[rt
])
1199 nir_variable
*var
= c
->output_color_var
[rt
];
1200 struct qreg
*color
= &c
->outputs
[var
->data
.driver_location
* 4];
1201 int num_components
= glsl_get_vector_elements(var
->type
);
1202 uint32_t conf
= 0xffffff00;
1205 conf
|= TLB_SAMPLE_MODE_PER_PIXEL
;
1206 conf
|= (7 - rt
) << TLB_RENDER_TARGET_SHIFT
;
1208 if (c
->fs_key
->swap_color_rb
& (1 << rt
))
1209 num_components
= MAX2(num_components
, 3);
1211 assert(num_components
!= 0);
1212 switch (glsl_get_base_type(var
->type
)) {
1213 case GLSL_TYPE_UINT
:
1215 /* The F32 vs I32 distinction was dropped in 4.2. */
1216 if (c
->devinfo
->ver
< 42)
1217 conf
|= TLB_TYPE_I32_COLOR
;
1219 conf
|= TLB_TYPE_F32_COLOR
;
1220 conf
|= ((num_components
- 1) <<
1221 TLB_VEC_SIZE_MINUS_1_SHIFT
);
1223 inst
= vir_MOV_dest(c
, tlbu_reg
, color
[0]);
1224 inst
->uniform
= vir_get_uniform_index(c
,
1228 for (int i
= 1; i
< num_components
; i
++) {
1229 inst
= vir_MOV_dest(c
, tlb_reg
, color
[i
]);
1234 struct qreg r
= color
[0];
1235 struct qreg g
= color
[1];
1236 struct qreg b
= color
[2];
1237 struct qreg a
= color
[3];
1239 if (c
->fs_key
->f32_color_rb
& (1 << rt
)) {
1240 conf
|= TLB_TYPE_F32_COLOR
;
1241 conf
|= ((num_components
- 1) <<
1242 TLB_VEC_SIZE_MINUS_1_SHIFT
);
1244 conf
|= TLB_TYPE_F16_COLOR
;
1245 conf
|= TLB_F16_SWAP_HI_LO
;
1246 if (num_components
>= 3)
1247 conf
|= TLB_VEC_SIZE_4_F16
;
1249 conf
|= TLB_VEC_SIZE_2_F16
;
1252 if (c
->fs_key
->swap_color_rb
& (1 << rt
)) {
1257 if (c
->fs_key
->sample_alpha_to_one
)
1258 a
= vir_uniform_f(c
, 1.0);
1260 if (c
->fs_key
->f32_color_rb
& (1 << rt
)) {
1261 inst
= vir_MOV_dest(c
, tlbu_reg
, r
);
1262 inst
->uniform
= vir_get_uniform_index(c
,
1266 if (num_components
>= 2)
1267 vir_MOV_dest(c
, tlb_reg
, g
);
1268 if (num_components
>= 3)
1269 vir_MOV_dest(c
, tlb_reg
, b
);
1270 if (num_components
>= 4)
1271 vir_MOV_dest(c
, tlb_reg
, a
);
1273 inst
= vir_VFPACK_dest(c
, tlb_reg
, r
, g
);
1275 inst
->dst
= tlbu_reg
;
1276 inst
->uniform
= vir_get_uniform_index(c
,
1281 if (num_components
>= 3)
1282 inst
= vir_VFPACK_dest(c
, tlb_reg
, b
, a
);
1291 vir_VPM_WRITE(struct v3d_compile
*c
, struct qreg val
, uint32_t vpm_index
)
1293 if (c
->devinfo
->ver
>= 40) {
1294 vir_STVPMV(c
, vir_uniform_ui(c
, vpm_index
), val
);
1296 /* XXX: v3d33_vir_vpm_write_setup(c); */
1297 vir_MOV_dest(c
, vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_VPM
), val
);
1302 emit_vert_end(struct v3d_compile
*c
)
1304 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1306 if (c
->devinfo
->ver
>= 40 && c
->devinfo
->ver
<= 42)
1311 v3d_optimize_nir(struct nir_shader
*s
)
1314 unsigned lower_flrp
=
1315 (s
->options
->lower_flrp16
? 16 : 0) |
1316 (s
->options
->lower_flrp32
? 32 : 0) |
1317 (s
->options
->lower_flrp64
? 64 : 0);
1322 NIR_PASS_V(s
, nir_lower_vars_to_ssa
);
1323 NIR_PASS(progress
, s
, nir_lower_alu_to_scalar
, NULL
);
1324 NIR_PASS(progress
, s
, nir_lower_phis_to_scalar
);
1325 NIR_PASS(progress
, s
, nir_copy_prop
);
1326 NIR_PASS(progress
, s
, nir_opt_remove_phis
);
1327 NIR_PASS(progress
, s
, nir_opt_dce
);
1328 NIR_PASS(progress
, s
, nir_opt_dead_cf
);
1329 NIR_PASS(progress
, s
, nir_opt_cse
);
1330 NIR_PASS(progress
, s
, nir_opt_peephole_select
, 8, true, true);
1331 NIR_PASS(progress
, s
, nir_opt_algebraic
);
1332 NIR_PASS(progress
, s
, nir_opt_constant_folding
);
1334 if (lower_flrp
!= 0) {
1335 bool lower_flrp_progress
= false;
1337 NIR_PASS(lower_flrp_progress
, s
, nir_lower_flrp
,
1339 false /* always_precise */,
1340 s
->options
->lower_ffma
);
1341 if (lower_flrp_progress
) {
1342 NIR_PASS(progress
, s
, nir_opt_constant_folding
);
1346 /* Nothing should rematerialize any flrps, so we only
1347 * need to do this lowering once.
1352 NIR_PASS(progress
, s
, nir_opt_undef
);
1355 NIR_PASS(progress
, s
, nir_opt_move_load_ubo
);
1359 driver_location_compare(const void *in_a
, const void *in_b
)
1361 const nir_variable
*const *a
= in_a
;
1362 const nir_variable
*const *b
= in_b
;
1364 return (*a
)->data
.driver_location
- (*b
)->data
.driver_location
;
1368 ntq_emit_vpm_read(struct v3d_compile
*c
,
1369 uint32_t *num_components_queued
,
1370 uint32_t *remaining
,
1373 struct qreg vpm
= vir_reg(QFILE_VPM
, vpm_index
);
1375 if (c
->devinfo
->ver
>= 40 ) {
1376 return vir_LDVPMV_IN(c
,
1378 (*num_components_queued
)++));
1381 if (*num_components_queued
!= 0) {
1382 (*num_components_queued
)--;
1383 return vir_MOV(c
, vpm
);
1386 uint32_t num_components
= MIN2(*remaining
, 32);
1388 v3d33_vir_vpm_read_setup(c
, num_components
);
1390 *num_components_queued
= num_components
- 1;
1391 *remaining
-= num_components
;
1393 return vir_MOV(c
, vpm
);
1397 ntq_setup_vpm_inputs(struct v3d_compile
*c
)
1399 /* Figure out how many components of each vertex attribute the shader
1400 * uses. Each variable should have been split to individual
1401 * components and unused ones DCEed. The vertex fetcher will load
1402 * from the start of the attribute to the number of components we
1403 * declare we need in c->vattr_sizes[].
1405 nir_foreach_variable(var
, &c
->s
->inputs
) {
1406 /* No VS attribute array support. */
1407 assert(MAX2(glsl_get_length(var
->type
), 1) == 1);
1409 unsigned loc
= var
->data
.driver_location
;
1410 int start_component
= var
->data
.location_frac
;
1411 int num_components
= glsl_get_components(var
->type
);
1413 c
->vattr_sizes
[loc
] = MAX2(c
->vattr_sizes
[loc
],
1414 start_component
+ num_components
);
1417 unsigned num_components
= 0;
1418 uint32_t vpm_components_queued
= 0;
1419 bool uses_iid
= c
->s
->info
.system_values_read
&
1420 (1ull << SYSTEM_VALUE_INSTANCE_ID
);
1421 bool uses_vid
= c
->s
->info
.system_values_read
&
1422 (1ull << SYSTEM_VALUE_VERTEX_ID
);
1423 num_components
+= uses_iid
;
1424 num_components
+= uses_vid
;
1426 for (int i
= 0; i
< ARRAY_SIZE(c
->vattr_sizes
); i
++)
1427 num_components
+= c
->vattr_sizes
[i
];
1430 c
->iid
= ntq_emit_vpm_read(c
, &vpm_components_queued
,
1431 &num_components
, ~0);
1435 c
->vid
= ntq_emit_vpm_read(c
, &vpm_components_queued
,
1436 &num_components
, ~0);
1439 /* The actual loads will happen directly in nir_intrinsic_load_input
1440 * on newer versions.
1442 if (c
->devinfo
->ver
>= 40)
1445 for (int loc
= 0; loc
< ARRAY_SIZE(c
->vattr_sizes
); loc
++) {
1446 resize_qreg_array(c
, &c
->inputs
, &c
->inputs_array_size
,
1449 for (int i
= 0; i
< c
->vattr_sizes
[loc
]; i
++) {
1450 c
->inputs
[loc
* 4 + i
] =
1451 ntq_emit_vpm_read(c
,
1452 &vpm_components_queued
,
1459 if (c
->devinfo
->ver
>= 40) {
1460 assert(vpm_components_queued
== num_components
);
1462 assert(vpm_components_queued
== 0);
1463 assert(num_components
== 0);
1468 var_needs_point_coord(struct v3d_compile
*c
, nir_variable
*var
)
1470 return (var
->data
.location
== VARYING_SLOT_PNTC
||
1471 (var
->data
.location
>= VARYING_SLOT_VAR0
&&
1472 (c
->fs_key
->point_sprite_mask
&
1473 (1 << (var
->data
.location
- VARYING_SLOT_VAR0
)))));
1477 program_reads_point_coord(struct v3d_compile
*c
)
1479 nir_foreach_variable(var
, &c
->s
->inputs
) {
1480 if (var_needs_point_coord(c
, var
))
1488 ntq_setup_fs_inputs(struct v3d_compile
*c
)
1490 unsigned num_entries
= 0;
1491 unsigned num_components
= 0;
1492 nir_foreach_variable(var
, &c
->s
->inputs
) {
1494 num_components
+= glsl_get_components(var
->type
);
1497 nir_variable
*vars
[num_entries
];
1500 nir_foreach_variable(var
, &c
->s
->inputs
)
1503 /* Sort the variables so that we emit the input setup in
1504 * driver_location order. This is required for VPM reads, whose data
1505 * is fetched into the VPM in driver_location (TGSI register index)
1508 qsort(&vars
, num_entries
, sizeof(*vars
), driver_location_compare
);
1510 for (unsigned i
= 0; i
< num_entries
; i
++) {
1511 nir_variable
*var
= vars
[i
];
1512 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1513 unsigned loc
= var
->data
.driver_location
;
1515 resize_qreg_array(c
, &c
->inputs
, &c
->inputs_array_size
,
1516 (loc
+ array_len
) * 4);
1518 if (var
->data
.location
== VARYING_SLOT_POS
) {
1519 emit_fragcoord_input(c
, loc
);
1520 } else if (var_needs_point_coord(c
, var
)) {
1521 c
->inputs
[loc
* 4 + 0] = c
->point_x
;
1522 c
->inputs
[loc
* 4 + 1] = c
->point_y
;
1524 for (int j
= 0; j
< array_len
; j
++)
1525 emit_fragment_input(c
, loc
+ j
, var
, j
);
1531 ntq_setup_outputs(struct v3d_compile
*c
)
1533 if (c
->s
->info
.stage
!= MESA_SHADER_FRAGMENT
)
1536 nir_foreach_variable(var
, &c
->s
->outputs
) {
1537 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1538 unsigned loc
= var
->data
.driver_location
* 4;
1540 assert(array_len
== 1);
1543 for (int i
= 0; i
< 4 - var
->data
.location_frac
; i
++) {
1544 add_output(c
, loc
+ var
->data
.location_frac
+ i
,
1546 var
->data
.location_frac
+ i
);
1549 switch (var
->data
.location
) {
1550 case FRAG_RESULT_COLOR
:
1551 c
->output_color_var
[0] = var
;
1552 c
->output_color_var
[1] = var
;
1553 c
->output_color_var
[2] = var
;
1554 c
->output_color_var
[3] = var
;
1556 case FRAG_RESULT_DATA0
:
1557 case FRAG_RESULT_DATA1
:
1558 case FRAG_RESULT_DATA2
:
1559 case FRAG_RESULT_DATA3
:
1560 c
->output_color_var
[var
->data
.location
-
1561 FRAG_RESULT_DATA0
] = var
;
1563 case FRAG_RESULT_DEPTH
:
1564 c
->output_position_index
= loc
;
1566 case FRAG_RESULT_SAMPLE_MASK
:
1567 c
->output_sample_mask_index
= loc
;
1574 * Sets up the mapping from nir_register to struct qreg *.
1576 * Each nir_register gets a struct qreg per 32-bit component being stored.
1579 ntq_setup_registers(struct v3d_compile
*c
, struct exec_list
*list
)
1581 foreach_list_typed(nir_register
, nir_reg
, node
, list
) {
1582 unsigned array_len
= MAX2(nir_reg
->num_array_elems
, 1);
1583 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
1585 nir_reg
->num_components
);
1587 _mesa_hash_table_insert(c
->def_ht
, nir_reg
, qregs
);
1589 for (int i
= 0; i
< array_len
* nir_reg
->num_components
; i
++)
1590 qregs
[i
] = vir_get_temp(c
);
1595 ntq_emit_load_const(struct v3d_compile
*c
, nir_load_const_instr
*instr
)
1597 /* XXX perf: Experiment with using immediate loads to avoid having
1598 * these end up in the uniform stream. Watch out for breaking the
1599 * small immediates optimization in the process!
1601 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1602 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1603 qregs
[i
] = vir_uniform_ui(c
, instr
->value
[i
].u32
);
1605 _mesa_hash_table_insert(c
->def_ht
, &instr
->def
, qregs
);
1609 ntq_emit_ssa_undef(struct v3d_compile
*c
, nir_ssa_undef_instr
*instr
)
1611 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1613 /* VIR needs there to be *some* value, so pick 0 (same as for
1614 * ntq_setup_registers().
1616 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1617 qregs
[i
] = vir_uniform_ui(c
, 0);
1621 ntq_emit_image_size(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
)
1623 assert(instr
->intrinsic
== nir_intrinsic_image_deref_size
);
1624 nir_variable
*var
= nir_intrinsic_get_var(instr
, 0);
1625 unsigned image_index
= var
->data
.driver_location
;
1626 const struct glsl_type
*sampler_type
= glsl_without_array(var
->type
);
1627 bool is_array
= glsl_sampler_type_is_array(sampler_type
);
1629 ntq_store_dest(c
, &instr
->dest
, 0,
1630 vir_uniform(c
, QUNIFORM_IMAGE_WIDTH
, image_index
));
1631 if (instr
->num_components
> 1) {
1632 ntq_store_dest(c
, &instr
->dest
, 1,
1633 vir_uniform(c
, QUNIFORM_IMAGE_HEIGHT
,
1636 if (instr
->num_components
> 2) {
1637 ntq_store_dest(c
, &instr
->dest
, 2,
1640 QUNIFORM_IMAGE_ARRAY_SIZE
:
1641 QUNIFORM_IMAGE_DEPTH
,
1647 vir_emit_tlb_color_read(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
)
1649 assert(c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
);
1651 int rt
= nir_src_as_uint(instr
->src
[0]);
1652 assert(rt
< V3D_MAX_DRAW_BUFFERS
);
1654 int sample_index
= nir_intrinsic_base(instr
) ;
1655 assert(sample_index
< V3D_MAX_SAMPLES
);
1657 int component
= nir_intrinsic_component(instr
);
1658 assert(component
< 4);
1660 /* We need to emit our TLB reads after we have acquired the scoreboard
1661 * lock, or the GPU will hang. Usually, we do our scoreboard locking on
1662 * the last thread switch to improve parallelism, however, that is only
1663 * guaranteed to happen before the tlb color writes.
1665 * To fix that, we make sure we always emit a thread switch before the
1666 * first tlb color read. If that happens to be the last thread switch
1667 * we emit, then everything is fine, but otherwsie, if any code after
1668 * this point needs to emit additional thread switches, then we will
1669 * switch the strategy to locking the scoreboard on the first thread
1670 * switch instead -- see vir_emit_thrsw().
1672 if (!c
->emitted_tlb_load
) {
1673 if (!c
->last_thrsw_at_top_level
) {
1674 assert(c
->devinfo
->ver
>= 41);
1678 c
->emitted_tlb_load
= true;
1681 struct qreg
*color_reads_for_sample
=
1682 &c
->color_reads
[(rt
* V3D_MAX_SAMPLES
+ sample_index
) * 4];
1684 if (color_reads_for_sample
[component
].file
== QFILE_NULL
) {
1685 enum pipe_format rt_format
= c
->fs_key
->color_fmt
[rt
].format
;
1686 int num_components
=
1687 util_format_get_nr_components(rt_format
);
1689 const bool swap_rb
= c
->fs_key
->swap_color_rb
& (1 << rt
);
1691 num_components
= MAX2(num_components
, 3);
1693 nir_variable
*var
= c
->output_color_var
[rt
];
1694 enum glsl_base_type type
= glsl_get_base_type(var
->type
);
1696 bool is_int_format
= type
== GLSL_TYPE_INT
||
1697 type
== GLSL_TYPE_UINT
;
1699 bool is_32b_tlb_format
= is_int_format
||
1700 (c
->fs_key
->f32_color_rb
& (1 << rt
));
1702 int num_samples
= c
->fs_key
->msaa
? V3D_MAX_SAMPLES
: 1;
1704 uint32_t conf
= 0xffffff00;
1705 conf
|= c
->fs_key
->msaa
? TLB_SAMPLE_MODE_PER_SAMPLE
:
1706 TLB_SAMPLE_MODE_PER_PIXEL
;
1707 conf
|= (7 - rt
) << TLB_RENDER_TARGET_SHIFT
;
1709 if (is_32b_tlb_format
) {
1710 /* The F32 vs I32 distinction was dropped in 4.2. */
1711 conf
|= (c
->devinfo
->ver
< 42 && is_int_format
) ?
1712 TLB_TYPE_I32_COLOR
: TLB_TYPE_F32_COLOR
;
1714 conf
|= ((num_components
- 1) <<
1715 TLB_VEC_SIZE_MINUS_1_SHIFT
);
1717 conf
|= TLB_TYPE_F16_COLOR
;
1718 conf
|= TLB_F16_SWAP_HI_LO
;
1720 if (num_components
>= 3)
1721 conf
|= TLB_VEC_SIZE_4_F16
;
1723 conf
|= TLB_VEC_SIZE_2_F16
;
1727 for (int i
= 0; i
< num_samples
; i
++) {
1728 struct qreg r
, g
, b
, a
;
1729 if (is_32b_tlb_format
) {
1730 r
= conf
!= 0xffffffff && i
== 0?
1731 vir_TLBU_COLOR_READ(c
, conf
) :
1732 vir_TLB_COLOR_READ(c
);
1733 if (num_components
>= 2)
1734 g
= vir_TLB_COLOR_READ(c
);
1735 if (num_components
>= 3)
1736 b
= vir_TLB_COLOR_READ(c
);
1737 if (num_components
>= 4)
1738 a
= vir_TLB_COLOR_READ(c
);
1740 struct qreg rg
= conf
!= 0xffffffff && i
== 0 ?
1741 vir_TLBU_COLOR_READ(c
, conf
) :
1742 vir_TLB_COLOR_READ(c
);
1743 r
= vir_FMOV(c
, rg
);
1744 vir_set_unpack(c
->defs
[r
.index
], 0,
1746 g
= vir_FMOV(c
, rg
);
1747 vir_set_unpack(c
->defs
[g
.index
], 0,
1750 if (num_components
> 2) {
1751 struct qreg ba
= vir_TLB_COLOR_READ(c
);
1752 b
= vir_FMOV(c
, ba
);
1753 vir_set_unpack(c
->defs
[b
.index
], 0,
1755 a
= vir_FMOV(c
, ba
);
1756 vir_set_unpack(c
->defs
[a
.index
], 0,
1761 struct qreg
*color_reads
=
1762 &c
->color_reads
[(rt
* V3D_MAX_SAMPLES
+ i
) * 4];
1764 color_reads
[0] = swap_rb
? b
: r
;
1765 if (num_components
>= 2)
1767 if (num_components
>= 3)
1768 color_reads
[2] = swap_rb
? r
: b
;
1769 if (num_components
>= 4)
1774 assert(color_reads_for_sample
[component
].file
!= QFILE_NULL
);
1775 ntq_store_dest(c
, &instr
->dest
, 0,
1776 vir_MOV(c
, color_reads_for_sample
[component
]));
1780 ntq_emit_load_uniform(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
)
1782 if (nir_src_is_const(instr
->src
[0])) {
1783 int offset
= (nir_intrinsic_base(instr
) +
1784 nir_src_as_uint(instr
->src
[0]));
1785 assert(offset
% 4 == 0);
1786 /* We need dwords */
1787 offset
= offset
/ 4;
1788 for (int i
= 0; i
< instr
->num_components
; i
++) {
1789 ntq_store_dest(c
, &instr
->dest
, i
,
1790 vir_uniform(c
, QUNIFORM_UNIFORM
,
1794 ntq_emit_tmu_general(c
, instr
, false);
1799 ntq_emit_load_input(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
)
1801 /* XXX: Use ldvpmv (uniform offset) or ldvpmd (non-uniform offset)
1802 * and enable PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR.
1805 nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[0]);
1807 if (c
->s
->info
.stage
!= MESA_SHADER_FRAGMENT
&& c
->devinfo
->ver
>= 40) {
1808 /* Emit the LDVPM directly now, rather than at the top
1809 * of the shader like we did for V3D 3.x (which needs
1810 * vpmsetup when not just taking the next offset).
1812 * Note that delaying like this may introduce stalls,
1813 * as LDVPMV takes a minimum of 1 instruction but may
1814 * be slower if the VPM unit is busy with another QPU.
1817 if (c
->s
->info
.system_values_read
&
1818 (1ull << SYSTEM_VALUE_INSTANCE_ID
)) {
1821 if (c
->s
->info
.system_values_read
&
1822 (1ull << SYSTEM_VALUE_VERTEX_ID
)) {
1825 for (int i
= 0; i
< offset
; i
++)
1826 index
+= c
->vattr_sizes
[i
];
1827 index
+= nir_intrinsic_component(instr
);
1828 for (int i
= 0; i
< instr
->num_components
; i
++) {
1829 struct qreg vpm_offset
= vir_uniform_ui(c
, index
++);
1830 ntq_store_dest(c
, &instr
->dest
, i
,
1831 vir_LDVPMV_IN(c
, vpm_offset
));
1834 for (int i
= 0; i
< instr
->num_components
; i
++) {
1835 int comp
= nir_intrinsic_component(instr
) + i
;
1836 ntq_store_dest(c
, &instr
->dest
, i
,
1837 vir_MOV(c
, c
->inputs
[offset
* 4 + comp
]));
1843 ntq_emit_store_output(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
)
1845 /* XXX perf: Use stvpmv with uniform non-constant offsets and
1846 * stvpmd with non-uniform offsets and enable
1847 * PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR.
1849 if (c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
) {
1850 unsigned offset
= ((nir_intrinsic_base(instr
) +
1851 nir_src_as_uint(instr
->src
[1])) * 4 +
1852 nir_intrinsic_component(instr
));
1853 for (int i
= 0; i
< instr
->num_components
; i
++) {
1854 c
->outputs
[offset
+ i
] =
1855 vir_MOV(c
, ntq_get_src(c
, instr
->src
[0], i
));
1858 assert(instr
->num_components
== 1);
1861 ntq_get_src(c
, instr
->src
[0], 0),
1862 nir_intrinsic_base(instr
));
1867 ntq_emit_intrinsic(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
)
1869 switch (instr
->intrinsic
) {
1870 case nir_intrinsic_load_uniform
:
1871 ntq_emit_load_uniform(c
, instr
);
1874 case nir_intrinsic_load_ubo
:
1875 ntq_emit_tmu_general(c
, instr
, false);
1878 case nir_intrinsic_ssbo_atomic_add
:
1879 case nir_intrinsic_ssbo_atomic_imin
:
1880 case nir_intrinsic_ssbo_atomic_umin
:
1881 case nir_intrinsic_ssbo_atomic_imax
:
1882 case nir_intrinsic_ssbo_atomic_umax
:
1883 case nir_intrinsic_ssbo_atomic_and
:
1884 case nir_intrinsic_ssbo_atomic_or
:
1885 case nir_intrinsic_ssbo_atomic_xor
:
1886 case nir_intrinsic_ssbo_atomic_exchange
:
1887 case nir_intrinsic_ssbo_atomic_comp_swap
:
1888 case nir_intrinsic_load_ssbo
:
1889 case nir_intrinsic_store_ssbo
:
1890 ntq_emit_tmu_general(c
, instr
, false);
1893 case nir_intrinsic_shared_atomic_add
:
1894 case nir_intrinsic_shared_atomic_imin
:
1895 case nir_intrinsic_shared_atomic_umin
:
1896 case nir_intrinsic_shared_atomic_imax
:
1897 case nir_intrinsic_shared_atomic_umax
:
1898 case nir_intrinsic_shared_atomic_and
:
1899 case nir_intrinsic_shared_atomic_or
:
1900 case nir_intrinsic_shared_atomic_xor
:
1901 case nir_intrinsic_shared_atomic_exchange
:
1902 case nir_intrinsic_shared_atomic_comp_swap
:
1903 case nir_intrinsic_load_shared
:
1904 case nir_intrinsic_store_shared
:
1905 case nir_intrinsic_load_scratch
:
1906 case nir_intrinsic_store_scratch
:
1907 ntq_emit_tmu_general(c
, instr
, true);
1910 case nir_intrinsic_image_deref_load
:
1911 case nir_intrinsic_image_deref_store
:
1912 case nir_intrinsic_image_deref_atomic_add
:
1913 case nir_intrinsic_image_deref_atomic_min
:
1914 case nir_intrinsic_image_deref_atomic_max
:
1915 case nir_intrinsic_image_deref_atomic_and
:
1916 case nir_intrinsic_image_deref_atomic_or
:
1917 case nir_intrinsic_image_deref_atomic_xor
:
1918 case nir_intrinsic_image_deref_atomic_exchange
:
1919 case nir_intrinsic_image_deref_atomic_comp_swap
:
1920 v3d40_vir_emit_image_load_store(c
, instr
);
1923 case nir_intrinsic_get_buffer_size
:
1924 ntq_store_dest(c
, &instr
->dest
, 0,
1925 vir_uniform(c
, QUNIFORM_GET_BUFFER_SIZE
,
1926 nir_src_as_uint(instr
->src
[0])));
1929 case nir_intrinsic_load_user_clip_plane
:
1930 for (int i
= 0; i
< instr
->num_components
; i
++) {
1931 ntq_store_dest(c
, &instr
->dest
, i
,
1932 vir_uniform(c
, QUNIFORM_USER_CLIP_PLANE
,
1933 nir_intrinsic_ucp_id(instr
) *
1938 case nir_intrinsic_load_viewport_x_scale
:
1939 ntq_store_dest(c
, &instr
->dest
, 0,
1940 vir_uniform(c
, QUNIFORM_VIEWPORT_X_SCALE
, 0));
1943 case nir_intrinsic_load_viewport_y_scale
:
1944 ntq_store_dest(c
, &instr
->dest
, 0,
1945 vir_uniform(c
, QUNIFORM_VIEWPORT_Y_SCALE
, 0));
1948 case nir_intrinsic_load_viewport_z_scale
:
1949 ntq_store_dest(c
, &instr
->dest
, 0,
1950 vir_uniform(c
, QUNIFORM_VIEWPORT_Z_SCALE
, 0));
1953 case nir_intrinsic_load_viewport_z_offset
:
1954 ntq_store_dest(c
, &instr
->dest
, 0,
1955 vir_uniform(c
, QUNIFORM_VIEWPORT_Z_OFFSET
, 0));
1958 case nir_intrinsic_load_alpha_ref_float
:
1959 ntq_store_dest(c
, &instr
->dest
, 0,
1960 vir_uniform(c
, QUNIFORM_ALPHA_REF
, 0));
1963 case nir_intrinsic_load_sample_mask_in
:
1964 ntq_store_dest(c
, &instr
->dest
, 0, vir_MSF(c
));
1967 case nir_intrinsic_load_helper_invocation
:
1968 vir_set_pf(vir_MSF_dest(c
, vir_nop_reg()), V3D_QPU_PF_PUSHZ
);
1969 ntq_store_dest(c
, &instr
->dest
, 0,
1970 vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFA
,
1971 vir_uniform_ui(c
, ~0),
1972 vir_uniform_ui(c
, 0))));
1975 case nir_intrinsic_load_front_face
:
1976 /* The register contains 0 (front) or 1 (back), and we need to
1977 * turn it into a NIR bool where true means front.
1979 ntq_store_dest(c
, &instr
->dest
, 0,
1981 vir_uniform_ui(c
, -1),
1985 case nir_intrinsic_load_instance_id
:
1986 ntq_store_dest(c
, &instr
->dest
, 0, vir_MOV(c
, c
->iid
));
1989 case nir_intrinsic_load_vertex_id
:
1990 ntq_store_dest(c
, &instr
->dest
, 0, vir_MOV(c
, c
->vid
));
1993 case nir_intrinsic_load_tlb_color_v3d
:
1994 vir_emit_tlb_color_read(c
, instr
);
1997 case nir_intrinsic_load_input
:
1998 ntq_emit_load_input(c
, instr
);
2001 case nir_intrinsic_store_output
:
2002 ntq_emit_store_output(c
, instr
);
2005 case nir_intrinsic_image_deref_size
:
2006 ntq_emit_image_size(c
, instr
);
2009 case nir_intrinsic_discard
:
2010 if (vir_in_nonuniform_control_flow(c
)) {
2011 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
),
2013 vir_set_cond(vir_SETMSF_dest(c
, vir_nop_reg(),
2014 vir_uniform_ui(c
, 0)),
2017 vir_SETMSF_dest(c
, vir_nop_reg(),
2018 vir_uniform_ui(c
, 0));
2022 case nir_intrinsic_discard_if
: {
2023 enum v3d_qpu_cond cond
= ntq_emit_bool_to_cond(c
, instr
->src
[0]);
2025 if (vir_in_nonuniform_control_flow(c
)) {
2026 struct qinst
*exec_flag
= vir_MOV_dest(c
, vir_nop_reg(),
2028 if (cond
== V3D_QPU_COND_IFA
) {
2029 vir_set_uf(exec_flag
, V3D_QPU_UF_ANDZ
);
2031 vir_set_uf(exec_flag
, V3D_QPU_UF_NORNZ
);
2032 cond
= V3D_QPU_COND_IFA
;
2036 vir_set_cond(vir_SETMSF_dest(c
, vir_nop_reg(),
2037 vir_uniform_ui(c
, 0)), cond
);
2042 case nir_intrinsic_memory_barrier
:
2043 case nir_intrinsic_memory_barrier_atomic_counter
:
2044 case nir_intrinsic_memory_barrier_buffer
:
2045 case nir_intrinsic_memory_barrier_image
:
2046 case nir_intrinsic_memory_barrier_shared
:
2047 case nir_intrinsic_group_memory_barrier
:
2048 /* We don't do any instruction scheduling of these NIR
2049 * instructions between each other, so we just need to make
2050 * sure that the TMU operations before the barrier are flushed
2051 * before the ones after the barrier. That is currently
2052 * handled by having a THRSW in each of them and a LDTMU
2053 * series or a TMUWT after.
2057 case nir_intrinsic_barrier
:
2058 /* Emit a TSY op to get all invocations in the workgroup
2059 * (actually supergroup) to block until the last invocation
2060 * reaches the TSY op.
2062 if (c
->devinfo
->ver
>= 42) {
2063 vir_BARRIERID_dest(c
, vir_reg(QFILE_MAGIC
,
2064 V3D_QPU_WADDR_SYNCB
));
2066 struct qinst
*sync
=
2067 vir_BARRIERID_dest(c
,
2068 vir_reg(QFILE_MAGIC
,
2069 V3D_QPU_WADDR_SYNCU
));
2071 vir_get_uniform_index(c
, QUNIFORM_CONSTANT
,
2073 V3D_TSY_WAIT_INC_CHECK
);
2077 /* The blocking of a TSY op only happens at the next thread
2078 * switch. No texturing may be outstanding at the time of a
2079 * TSY blocking operation.
2084 case nir_intrinsic_load_num_work_groups
:
2085 for (int i
= 0; i
< 3; i
++) {
2086 ntq_store_dest(c
, &instr
->dest
, i
,
2087 vir_uniform(c
, QUNIFORM_NUM_WORK_GROUPS
,
2092 case nir_intrinsic_load_local_invocation_index
:
2093 ntq_store_dest(c
, &instr
->dest
, 0,
2094 vir_SHR(c
, c
->cs_payload
[1],
2095 vir_uniform_ui(c
, 32 - c
->local_invocation_index_bits
)));
2098 case nir_intrinsic_load_work_group_id
:
2099 ntq_store_dest(c
, &instr
->dest
, 0,
2100 vir_AND(c
, c
->cs_payload
[0],
2101 vir_uniform_ui(c
, 0xffff)));
2102 ntq_store_dest(c
, &instr
->dest
, 1,
2103 vir_SHR(c
, c
->cs_payload
[0],
2104 vir_uniform_ui(c
, 16)));
2105 ntq_store_dest(c
, &instr
->dest
, 2,
2106 vir_AND(c
, c
->cs_payload
[1],
2107 vir_uniform_ui(c
, 0xffff)));
2110 case nir_intrinsic_load_subgroup_id
:
2111 ntq_store_dest(c
, &instr
->dest
, 0, vir_EIDX(c
));
2115 fprintf(stderr
, "Unknown intrinsic: ");
2116 nir_print_instr(&instr
->instr
, stderr
);
2117 fprintf(stderr
, "\n");
2122 /* Clears (activates) the execute flags for any channels whose jump target
2123 * matches this block.
2125 * XXX perf: Could we be using flpush/flpop somehow for our execution channel
2128 * XXX perf: For uniform control flow, we should be able to skip c->execute
2129 * handling entirely.
2132 ntq_activate_execute_for_block(struct v3d_compile
*c
)
2134 vir_set_pf(vir_XOR_dest(c
, vir_nop_reg(),
2135 c
->execute
, vir_uniform_ui(c
, c
->cur_block
->index
)),
2138 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
, vir_uniform_ui(c
, 0));
2142 ntq_emit_uniform_if(struct v3d_compile
*c
, nir_if
*if_stmt
)
2144 nir_block
*nir_else_block
= nir_if_first_else_block(if_stmt
);
2145 bool empty_else_block
=
2146 (nir_else_block
== nir_if_last_else_block(if_stmt
) &&
2147 exec_list_is_empty(&nir_else_block
->instr_list
));
2149 struct qblock
*then_block
= vir_new_block(c
);
2150 struct qblock
*after_block
= vir_new_block(c
);
2151 struct qblock
*else_block
;
2152 if (empty_else_block
)
2153 else_block
= after_block
;
2155 else_block
= vir_new_block(c
);
2157 /* Set up the flags for the IF condition (taking the THEN branch). */
2158 enum v3d_qpu_cond cond
= ntq_emit_bool_to_cond(c
, if_stmt
->condition
);
2161 vir_BRANCH(c
, cond
== V3D_QPU_COND_IFA
?
2162 V3D_QPU_BRANCH_COND_ALLNA
:
2163 V3D_QPU_BRANCH_COND_ALLA
);
2164 vir_link_blocks(c
->cur_block
, else_block
);
2165 vir_link_blocks(c
->cur_block
, then_block
);
2167 /* Process the THEN block. */
2168 vir_set_emit_block(c
, then_block
);
2169 ntq_emit_cf_list(c
, &if_stmt
->then_list
);
2171 if (!empty_else_block
) {
2172 /* At the end of the THEN block, jump to ENDIF */
2173 vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ALWAYS
);
2174 vir_link_blocks(c
->cur_block
, after_block
);
2176 /* Emit the else block. */
2177 vir_set_emit_block(c
, else_block
);
2178 ntq_emit_cf_list(c
, &if_stmt
->else_list
);
2181 vir_link_blocks(c
->cur_block
, after_block
);
2183 vir_set_emit_block(c
, after_block
);
2187 ntq_emit_nonuniform_if(struct v3d_compile
*c
, nir_if
*if_stmt
)
2189 nir_block
*nir_else_block
= nir_if_first_else_block(if_stmt
);
2190 bool empty_else_block
=
2191 (nir_else_block
== nir_if_last_else_block(if_stmt
) &&
2192 exec_list_is_empty(&nir_else_block
->instr_list
));
2194 struct qblock
*then_block
= vir_new_block(c
);
2195 struct qblock
*after_block
= vir_new_block(c
);
2196 struct qblock
*else_block
;
2197 if (empty_else_block
)
2198 else_block
= after_block
;
2200 else_block
= vir_new_block(c
);
2202 bool was_uniform_control_flow
= false;
2203 if (!vir_in_nonuniform_control_flow(c
)) {
2204 c
->execute
= vir_MOV(c
, vir_uniform_ui(c
, 0));
2205 was_uniform_control_flow
= true;
2208 /* Set up the flags for the IF condition (taking the THEN branch). */
2209 enum v3d_qpu_cond cond
= ntq_emit_bool_to_cond(c
, if_stmt
->condition
);
2211 /* Update the flags+cond to mean "Taking the ELSE branch (!cond) and
2212 * was previously active (execute Z) for updating the exec flags.
2214 if (was_uniform_control_flow
) {
2215 cond
= v3d_qpu_cond_invert(cond
);
2217 struct qinst
*inst
= vir_MOV_dest(c
, vir_nop_reg(), c
->execute
);
2218 if (cond
== V3D_QPU_COND_IFA
) {
2219 vir_set_uf(inst
, V3D_QPU_UF_NORNZ
);
2221 vir_set_uf(inst
, V3D_QPU_UF_ANDZ
);
2222 cond
= V3D_QPU_COND_IFA
;
2226 vir_MOV_cond(c
, cond
,
2228 vir_uniform_ui(c
, else_block
->index
));
2230 /* Jump to ELSE if nothing is active for THEN, otherwise fall
2233 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
), V3D_QPU_PF_PUSHZ
);
2234 vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ALLNA
);
2235 vir_link_blocks(c
->cur_block
, else_block
);
2236 vir_link_blocks(c
->cur_block
, then_block
);
2238 /* Process the THEN block. */
2239 vir_set_emit_block(c
, then_block
);
2240 ntq_emit_cf_list(c
, &if_stmt
->then_list
);
2242 if (!empty_else_block
) {
2243 /* Handle the end of the THEN block. First, all currently
2244 * active channels update their execute flags to point to
2247 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
),
2249 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
,
2250 vir_uniform_ui(c
, after_block
->index
));
2252 /* If everything points at ENDIF, then jump there immediately. */
2253 vir_set_pf(vir_XOR_dest(c
, vir_nop_reg(),
2255 vir_uniform_ui(c
, after_block
->index
)),
2257 vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ALLA
);
2258 vir_link_blocks(c
->cur_block
, after_block
);
2259 vir_link_blocks(c
->cur_block
, else_block
);
2261 vir_set_emit_block(c
, else_block
);
2262 ntq_activate_execute_for_block(c
);
2263 ntq_emit_cf_list(c
, &if_stmt
->else_list
);
2266 vir_link_blocks(c
->cur_block
, after_block
);
2268 vir_set_emit_block(c
, after_block
);
2269 if (was_uniform_control_flow
)
2270 c
->execute
= c
->undef
;
2272 ntq_activate_execute_for_block(c
);
2276 ntq_emit_if(struct v3d_compile
*c
, nir_if
*nif
)
2278 bool was_in_control_flow
= c
->in_control_flow
;
2279 c
->in_control_flow
= true;
2280 if (!vir_in_nonuniform_control_flow(c
) &&
2281 nir_src_is_dynamically_uniform(nif
->condition
)) {
2282 ntq_emit_uniform_if(c
, nif
);
2284 ntq_emit_nonuniform_if(c
, nif
);
2286 c
->in_control_flow
= was_in_control_flow
;
2290 ntq_emit_jump(struct v3d_compile
*c
, nir_jump_instr
*jump
)
2292 switch (jump
->type
) {
2293 case nir_jump_break
:
2294 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
),
2296 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
,
2297 vir_uniform_ui(c
, c
->loop_break_block
->index
));
2300 case nir_jump_continue
:
2301 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
),
2303 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
,
2304 vir_uniform_ui(c
, c
->loop_cont_block
->index
));
2307 case nir_jump_return
:
2308 unreachable("All returns shouold be lowered\n");
2313 ntq_emit_instr(struct v3d_compile
*c
, nir_instr
*instr
)
2315 switch (instr
->type
) {
2316 case nir_instr_type_deref
:
2317 /* ignored, will be walked by the intrinsic using it. */
2320 case nir_instr_type_alu
:
2321 ntq_emit_alu(c
, nir_instr_as_alu(instr
));
2324 case nir_instr_type_intrinsic
:
2325 ntq_emit_intrinsic(c
, nir_instr_as_intrinsic(instr
));
2328 case nir_instr_type_load_const
:
2329 ntq_emit_load_const(c
, nir_instr_as_load_const(instr
));
2332 case nir_instr_type_ssa_undef
:
2333 ntq_emit_ssa_undef(c
, nir_instr_as_ssa_undef(instr
));
2336 case nir_instr_type_tex
:
2337 ntq_emit_tex(c
, nir_instr_as_tex(instr
));
2340 case nir_instr_type_jump
:
2341 ntq_emit_jump(c
, nir_instr_as_jump(instr
));
2345 fprintf(stderr
, "Unknown NIR instr type: ");
2346 nir_print_instr(instr
, stderr
);
2347 fprintf(stderr
, "\n");
2353 ntq_emit_block(struct v3d_compile
*c
, nir_block
*block
)
2355 nir_foreach_instr(instr
, block
) {
2356 ntq_emit_instr(c
, instr
);
2360 static void ntq_emit_cf_list(struct v3d_compile
*c
, struct exec_list
*list
);
2363 ntq_emit_loop(struct v3d_compile
*c
, nir_loop
*loop
)
2365 bool was_in_control_flow
= c
->in_control_flow
;
2366 c
->in_control_flow
= true;
2368 bool was_uniform_control_flow
= false;
2369 if (!vir_in_nonuniform_control_flow(c
)) {
2370 c
->execute
= vir_MOV(c
, vir_uniform_ui(c
, 0));
2371 was_uniform_control_flow
= true;
2374 struct qblock
*save_loop_cont_block
= c
->loop_cont_block
;
2375 struct qblock
*save_loop_break_block
= c
->loop_break_block
;
2377 c
->loop_cont_block
= vir_new_block(c
);
2378 c
->loop_break_block
= vir_new_block(c
);
2380 vir_link_blocks(c
->cur_block
, c
->loop_cont_block
);
2381 vir_set_emit_block(c
, c
->loop_cont_block
);
2382 ntq_activate_execute_for_block(c
);
2384 ntq_emit_cf_list(c
, &loop
->body
);
2386 /* Re-enable any previous continues now, so our ANYA check below
2389 * XXX: Use the .ORZ flags update, instead.
2391 vir_set_pf(vir_XOR_dest(c
,
2394 vir_uniform_ui(c
, c
->loop_cont_block
->index
)),
2396 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
, vir_uniform_ui(c
, 0));
2398 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
), V3D_QPU_PF_PUSHZ
);
2400 struct qinst
*branch
= vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ANYA
);
2401 /* Pixels that were not dispatched or have been discarded should not
2402 * contribute to looping again.
2404 branch
->qpu
.branch
.msfign
= V3D_QPU_MSFIGN_P
;
2405 vir_link_blocks(c
->cur_block
, c
->loop_cont_block
);
2406 vir_link_blocks(c
->cur_block
, c
->loop_break_block
);
2408 vir_set_emit_block(c
, c
->loop_break_block
);
2409 if (was_uniform_control_flow
)
2410 c
->execute
= c
->undef
;
2412 ntq_activate_execute_for_block(c
);
2414 c
->loop_break_block
= save_loop_break_block
;
2415 c
->loop_cont_block
= save_loop_cont_block
;
2419 c
->in_control_flow
= was_in_control_flow
;
2423 ntq_emit_function(struct v3d_compile
*c
, nir_function_impl
*func
)
2425 fprintf(stderr
, "FUNCTIONS not handled.\n");
2430 ntq_emit_cf_list(struct v3d_compile
*c
, struct exec_list
*list
)
2432 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2433 switch (node
->type
) {
2434 case nir_cf_node_block
:
2435 ntq_emit_block(c
, nir_cf_node_as_block(node
));
2438 case nir_cf_node_if
:
2439 ntq_emit_if(c
, nir_cf_node_as_if(node
));
2442 case nir_cf_node_loop
:
2443 ntq_emit_loop(c
, nir_cf_node_as_loop(node
));
2446 case nir_cf_node_function
:
2447 ntq_emit_function(c
, nir_cf_node_as_function(node
));
2451 fprintf(stderr
, "Unknown NIR node type\n");
2458 ntq_emit_impl(struct v3d_compile
*c
, nir_function_impl
*impl
)
2460 ntq_setup_registers(c
, &impl
->registers
);
2461 ntq_emit_cf_list(c
, &impl
->body
);
2465 nir_to_vir(struct v3d_compile
*c
)
2467 switch (c
->s
->info
.stage
) {
2468 case MESA_SHADER_FRAGMENT
:
2469 c
->payload_w
= vir_MOV(c
, vir_reg(QFILE_REG
, 0));
2470 c
->payload_w_centroid
= vir_MOV(c
, vir_reg(QFILE_REG
, 1));
2471 c
->payload_z
= vir_MOV(c
, vir_reg(QFILE_REG
, 2));
2473 /* V3D 4.x can disable implicit point coordinate varyings if
2474 * they are not used.
2476 if (c
->fs_key
->is_points
&&
2477 (c
->devinfo
->ver
< 40 || program_reads_point_coord(c
))) {
2478 c
->point_x
= emit_fragment_varying(c
, NULL
, 0, 0);
2479 c
->point_y
= emit_fragment_varying(c
, NULL
, 0, 0);
2480 c
->uses_implicit_point_line_varyings
= true;
2481 } else if (c
->fs_key
->is_lines
&& c
->devinfo
->ver
< 40) {
2482 c
->line_x
= emit_fragment_varying(c
, NULL
, 0, 0);
2483 c
->uses_implicit_point_line_varyings
= true;
2486 case MESA_SHADER_COMPUTE
:
2487 /* Set up the TSO for barriers, assuming we do some. */
2488 if (c
->devinfo
->ver
< 42) {
2489 vir_BARRIERID_dest(c
, vir_reg(QFILE_MAGIC
,
2490 V3D_QPU_WADDR_SYNC
));
2493 c
->cs_payload
[0] = vir_MOV(c
, vir_reg(QFILE_REG
, 0));
2494 c
->cs_payload
[1] = vir_MOV(c
, vir_reg(QFILE_REG
, 2));
2496 /* Set up the division between gl_LocalInvocationIndex and
2497 * wg_in_mem in the payload reg.
2499 int wg_size
= (c
->s
->info
.cs
.local_size
[0] *
2500 c
->s
->info
.cs
.local_size
[1] *
2501 c
->s
->info
.cs
.local_size
[2]);
2502 c
->local_invocation_index_bits
=
2503 ffs(util_next_power_of_two(MAX2(wg_size
, 64))) - 1;
2504 assert(c
->local_invocation_index_bits
<= 8);
2506 if (c
->s
->info
.cs
.shared_size
) {
2507 struct qreg wg_in_mem
= vir_SHR(c
, c
->cs_payload
[1],
2508 vir_uniform_ui(c
, 16));
2509 if (c
->s
->info
.cs
.local_size
[0] != 1 ||
2510 c
->s
->info
.cs
.local_size
[1] != 1 ||
2511 c
->s
->info
.cs
.local_size
[2] != 1) {
2513 c
->local_invocation_index_bits
);
2514 int wg_mask
= (1 << wg_bits
) - 1;
2515 wg_in_mem
= vir_AND(c
, wg_in_mem
,
2516 vir_uniform_ui(c
, wg_mask
));
2518 struct qreg shared_per_wg
=
2519 vir_uniform_ui(c
, c
->s
->info
.cs
.shared_size
);
2521 c
->cs_shared_offset
=
2523 vir_uniform(c
, QUNIFORM_SHARED_OFFSET
,0),
2524 vir_UMUL(c
, wg_in_mem
, shared_per_wg
));
2531 if (c
->s
->scratch_size
) {
2532 v3d_setup_spill_base(c
);
2533 c
->spill_size
+= V3D_CHANNELS
* c
->s
->scratch_size
;
2536 if (c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
)
2537 ntq_setup_fs_inputs(c
);
2539 ntq_setup_vpm_inputs(c
);
2541 ntq_setup_outputs(c
);
2543 /* Find the main function and emit the body. */
2544 nir_foreach_function(function
, c
->s
) {
2545 assert(strcmp(function
->name
, "main") == 0);
2546 assert(function
->impl
);
2547 ntq_emit_impl(c
, function
->impl
);
2551 const nir_shader_compiler_options v3d_nir_options
= {
2552 .lower_all_io_to_temps
= true,
2553 .lower_extract_byte
= true,
2554 .lower_extract_word
= true,
2555 .lower_bitfield_insert_to_shifts
= true,
2556 .lower_bitfield_extract_to_shifts
= true,
2557 .lower_bitfield_reverse
= true,
2558 .lower_bit_count
= true,
2559 .lower_cs_local_id_from_index
= true,
2560 .lower_ffract
= true,
2562 .lower_pack_unorm_2x16
= true,
2563 .lower_pack_snorm_2x16
= true,
2564 .lower_pack_unorm_4x8
= true,
2565 .lower_pack_snorm_4x8
= true,
2566 .lower_unpack_unorm_4x8
= true,
2567 .lower_unpack_snorm_4x8
= true,
2568 .lower_pack_half_2x16
= true,
2569 .lower_unpack_half_2x16
= true,
2571 .lower_find_lsb
= true,
2573 .lower_flrp32
= true,
2576 .lower_fsqrt
= true,
2577 .lower_ifind_msb
= true,
2578 .lower_isign
= true,
2579 .lower_ldexp
= true,
2580 .lower_mul_high
= true,
2581 .lower_wpos_pntc
= true,
2582 .lower_rotate
= true,
2586 * When demoting a shader down to single-threaded, removes the THRSW
2587 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
2591 vir_remove_thrsw(struct v3d_compile
*c
)
2593 vir_for_each_block(block
, c
) {
2594 vir_for_each_inst_safe(inst
, block
) {
2595 if (inst
->qpu
.sig
.thrsw
)
2596 vir_remove_instruction(c
, inst
);
2600 c
->last_thrsw
= NULL
;
2604 vir_emit_last_thrsw(struct v3d_compile
*c
)
2606 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
2607 * switching, so disable threads if we didn't do any TMU ops (each of
2608 * which would have emitted a THRSW).
2610 if (!c
->last_thrsw_at_top_level
&& c
->devinfo
->ver
< 41) {
2613 vir_remove_thrsw(c
);
2617 /* If we're threaded and the last THRSW was in conditional code, then
2618 * we need to emit another one so that we can flag it as the last
2621 if (c
->last_thrsw
&& !c
->last_thrsw_at_top_level
) {
2622 assert(c
->devinfo
->ver
>= 41);
2626 /* If we're threaded, then we need to mark the last THRSW instruction
2627 * so we can emit a pair of them at QPU emit time.
2629 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2630 * post-last-THRSW state, so we can skip this.
2632 if (!c
->last_thrsw
&& c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
) {
2633 assert(c
->devinfo
->ver
>= 41);
2638 c
->last_thrsw
->is_last_thrsw
= true;
2641 /* There's a flag in the shader for "center W is needed for reasons other than
2642 * non-centroid varyings", so we just walk the program after VIR optimization
2643 * to see if it's used. It should be harmless to set even if we only use
2644 * center W for varyings.
2647 vir_check_payload_w(struct v3d_compile
*c
)
2649 if (c
->s
->info
.stage
!= MESA_SHADER_FRAGMENT
)
2652 vir_for_each_inst_inorder(inst
, c
) {
2653 for (int i
= 0; i
< vir_get_nsrc(inst
); i
++) {
2654 if (inst
->src
[i
].file
== QFILE_REG
&&
2655 inst
->src
[i
].index
== 0) {
2656 c
->uses_center_w
= true;
2665 v3d_nir_to_vir(struct v3d_compile
*c
)
2667 if (V3D_DEBUG
& (V3D_DEBUG_NIR
|
2668 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
))) {
2669 fprintf(stderr
, "%s prog %d/%d NIR:\n",
2670 vir_get_stage_name(c
),
2671 c
->program_id
, c
->variant_id
);
2672 nir_print_shader(c
->s
, stderr
);
2677 /* Emit the last THRSW before STVPM and TLB writes. */
2678 vir_emit_last_thrsw(c
);
2680 switch (c
->s
->info
.stage
) {
2681 case MESA_SHADER_FRAGMENT
:
2684 case MESA_SHADER_VERTEX
:
2687 case MESA_SHADER_COMPUTE
:
2690 unreachable("bad stage");
2693 if (V3D_DEBUG
& (V3D_DEBUG_VIR
|
2694 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
))) {
2695 fprintf(stderr
, "%s prog %d/%d pre-opt VIR:\n",
2696 vir_get_stage_name(c
),
2697 c
->program_id
, c
->variant_id
);
2699 fprintf(stderr
, "\n");
2704 vir_check_payload_w(c
);
2706 /* XXX perf: On VC4, we do a VIR-level instruction scheduling here.
2707 * We used that on that platform to pipeline TMU writes and reduce the
2708 * number of thread switches, as well as try (mostly successfully) to
2709 * reduce maximum register pressure to allow more threads. We should
2710 * do something of that sort for V3D -- either instruction scheduling
2711 * here, or delay the the THRSW and LDTMUs from our texture
2712 * instructions until the results are needed.
2715 if (V3D_DEBUG
& (V3D_DEBUG_VIR
|
2716 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
))) {
2717 fprintf(stderr
, "%s prog %d/%d VIR:\n",
2718 vir_get_stage_name(c
),
2719 c
->program_id
, c
->variant_id
);
2721 fprintf(stderr
, "\n");
2724 /* Attempt to allocate registers for the temporaries. If we fail,
2725 * reduce thread count and try again.
2727 int min_threads
= (c
->devinfo
->ver
>= 41) ? 2 : 1;
2728 struct qpu_reg
*temp_registers
;
2731 temp_registers
= v3d_register_allocate(c
, &spilled
);
2738 if (c
->threads
== min_threads
) {
2739 fprintf(stderr
, "Failed to register allocate at %d threads:\n",
2748 if (c
->threads
== 1)
2749 vir_remove_thrsw(c
);
2753 (V3D_DEBUG
& (V3D_DEBUG_VIR
|
2754 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
)))) {
2755 fprintf(stderr
, "%s prog %d/%d spilled VIR:\n",
2756 vir_get_stage_name(c
),
2757 c
->program_id
, c
->variant_id
);
2759 fprintf(stderr
, "\n");
2762 v3d_vir_to_qpu(c
, temp_registers
);