nir: Add goto_if jump instruction
[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/format/u_format.h"
26 #include "util/u_helpers.h"
27 #include "util/u_math.h"
28 #include "util/u_memory.h"
29 #include "util/ralloc.h"
30 #include "util/hash_table.h"
31 #include "compiler/nir/nir.h"
32 #include "compiler/nir/nir_builder.h"
33 #include "common/v3d_device_info.h"
34 #include "v3d_compiler.h"
35
36 /* We don't do any address packing. */
37 #define __gen_user_data void
38 #define __gen_address_type uint32_t
39 #define __gen_address_offset(reloc) (*reloc)
40 #define __gen_emit_reloc(cl, reloc)
41 #include "cle/v3d_packet_v41_pack.h"
42
43 #define GENERAL_TMU_LOOKUP_PER_QUAD (0 << 7)
44 #define GENERAL_TMU_LOOKUP_PER_PIXEL (1 << 7)
45 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_I (0 << 0)
46 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_I (1 << 0)
47 #define GENERAL_TMU_LOOKUP_TYPE_VEC2 (2 << 0)
48 #define GENERAL_TMU_LOOKUP_TYPE_VEC3 (3 << 0)
49 #define GENERAL_TMU_LOOKUP_TYPE_VEC4 (4 << 0)
50 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_UI (5 << 0)
51 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_UI (6 << 0)
52 #define GENERAL_TMU_LOOKUP_TYPE_32BIT_UI (7 << 0)
53
54 #define V3D_TSY_SET_QUORUM 0
55 #define V3D_TSY_INC_WAITERS 1
56 #define V3D_TSY_DEC_WAITERS 2
57 #define V3D_TSY_INC_QUORUM 3
58 #define V3D_TSY_DEC_QUORUM 4
59 #define V3D_TSY_FREE_ALL 5
60 #define V3D_TSY_RELEASE 6
61 #define V3D_TSY_ACQUIRE 7
62 #define V3D_TSY_WAIT 8
63 #define V3D_TSY_WAIT_INC 9
64 #define V3D_TSY_WAIT_CHECK 10
65 #define V3D_TSY_WAIT_INC_CHECK 11
66 #define V3D_TSY_WAIT_CV 12
67 #define V3D_TSY_INC_SEMAPHORE 13
68 #define V3D_TSY_DEC_SEMAPHORE 14
69 #define V3D_TSY_SET_QUORUM_FREE_ALL 15
70
71 static void
72 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
73
74 static void
75 resize_qreg_array(struct v3d_compile *c,
76 struct qreg **regs,
77 uint32_t *size,
78 uint32_t decl_size)
79 {
80 if (*size >= decl_size)
81 return;
82
83 uint32_t old_size = *size;
84 *size = MAX2(*size * 2, decl_size);
85 *regs = reralloc(c, *regs, struct qreg, *size);
86 if (!*regs) {
87 fprintf(stderr, "Malloc failure\n");
88 abort();
89 }
90
91 for (uint32_t i = old_size; i < *size; i++)
92 (*regs)[i] = c->undef;
93 }
94
95 void
96 vir_emit_thrsw(struct v3d_compile *c)
97 {
98 if (c->threads == 1)
99 return;
100
101 /* Always thread switch after each texture operation for now.
102 *
103 * We could do better by batching a bunch of texture fetches up and
104 * then doing one thread switch and collecting all their results
105 * afterward.
106 */
107 c->last_thrsw = vir_NOP(c);
108 c->last_thrsw->qpu.sig.thrsw = true;
109 c->last_thrsw_at_top_level = !c->in_control_flow;
110
111 /* We need to lock the scoreboard before any tlb acess happens. If this
112 * thread switch comes after we have emitted a tlb load, then it means
113 * that we can't lock on the last thread switch any more.
114 */
115 if (c->emitted_tlb_load)
116 c->lock_scoreboard_on_first_thrsw = true;
117 }
118
119 uint32_t
120 v3d_get_op_for_atomic_add(nir_intrinsic_instr *instr, unsigned src)
121 {
122 if (nir_src_is_const(instr->src[src])) {
123 int64_t add_val = nir_src_as_int(instr->src[src]);
124 if (add_val == 1)
125 return V3D_TMU_OP_WRITE_AND_READ_INC;
126 else if (add_val == -1)
127 return V3D_TMU_OP_WRITE_OR_READ_DEC;
128 }
129
130 return V3D_TMU_OP_WRITE_ADD_READ_PREFETCH;
131 }
132
133 static uint32_t
134 v3d_general_tmu_op(nir_intrinsic_instr *instr)
135 {
136 switch (instr->intrinsic) {
137 case nir_intrinsic_load_ssbo:
138 case nir_intrinsic_load_ubo:
139 case nir_intrinsic_load_uniform:
140 case nir_intrinsic_load_shared:
141 case nir_intrinsic_load_scratch:
142 case nir_intrinsic_store_ssbo:
143 case nir_intrinsic_store_shared:
144 case nir_intrinsic_store_scratch:
145 return V3D_TMU_OP_REGULAR;
146 case nir_intrinsic_ssbo_atomic_add:
147 return v3d_get_op_for_atomic_add(instr, 2);
148 case nir_intrinsic_shared_atomic_add:
149 return v3d_get_op_for_atomic_add(instr, 1);
150 case nir_intrinsic_ssbo_atomic_imin:
151 case nir_intrinsic_shared_atomic_imin:
152 return V3D_TMU_OP_WRITE_SMIN;
153 case nir_intrinsic_ssbo_atomic_umin:
154 case nir_intrinsic_shared_atomic_umin:
155 return V3D_TMU_OP_WRITE_UMIN_FULL_L1_CLEAR;
156 case nir_intrinsic_ssbo_atomic_imax:
157 case nir_intrinsic_shared_atomic_imax:
158 return V3D_TMU_OP_WRITE_SMAX;
159 case nir_intrinsic_ssbo_atomic_umax:
160 case nir_intrinsic_shared_atomic_umax:
161 return V3D_TMU_OP_WRITE_UMAX;
162 case nir_intrinsic_ssbo_atomic_and:
163 case nir_intrinsic_shared_atomic_and:
164 return V3D_TMU_OP_WRITE_AND_READ_INC;
165 case nir_intrinsic_ssbo_atomic_or:
166 case nir_intrinsic_shared_atomic_or:
167 return V3D_TMU_OP_WRITE_OR_READ_DEC;
168 case nir_intrinsic_ssbo_atomic_xor:
169 case nir_intrinsic_shared_atomic_xor:
170 return V3D_TMU_OP_WRITE_XOR_READ_NOT;
171 case nir_intrinsic_ssbo_atomic_exchange:
172 case nir_intrinsic_shared_atomic_exchange:
173 return V3D_TMU_OP_WRITE_XCHG_READ_FLUSH;
174 case nir_intrinsic_ssbo_atomic_comp_swap:
175 case nir_intrinsic_shared_atomic_comp_swap:
176 return V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH;
177 default:
178 unreachable("unknown intrinsic op");
179 }
180 }
181
182 /**
183 * Implements indirect uniform loads and SSBO accesses through the TMU general
184 * memory access interface.
185 */
186 static void
187 ntq_emit_tmu_general(struct v3d_compile *c, nir_intrinsic_instr *instr,
188 bool is_shared_or_scratch)
189 {
190 uint32_t tmu_op = v3d_general_tmu_op(instr);
191
192 /* If we were able to replace atomic_add for an inc/dec, then we
193 * need/can to do things slightly different, like not loading the
194 * amount to add/sub, as that is implicit.
195 */
196 bool atomic_add_replaced =
197 ((instr->intrinsic == nir_intrinsic_ssbo_atomic_add ||
198 instr->intrinsic == nir_intrinsic_shared_atomic_add) &&
199 (tmu_op == V3D_TMU_OP_WRITE_AND_READ_INC ||
200 tmu_op == V3D_TMU_OP_WRITE_OR_READ_DEC));
201
202 bool is_store = (instr->intrinsic == nir_intrinsic_store_ssbo ||
203 instr->intrinsic == nir_intrinsic_store_scratch ||
204 instr->intrinsic == nir_intrinsic_store_shared);
205
206 bool is_load = (instr->intrinsic == nir_intrinsic_load_uniform ||
207 instr->intrinsic == nir_intrinsic_load_ubo ||
208 instr->intrinsic == nir_intrinsic_load_ssbo ||
209 instr->intrinsic == nir_intrinsic_load_scratch ||
210 instr->intrinsic == nir_intrinsic_load_shared);
211
212 if (!is_load)
213 c->tmu_dirty_rcl = true;
214
215 bool has_index = !is_shared_or_scratch;
216
217 int offset_src;
218 if (instr->intrinsic == nir_intrinsic_load_uniform) {
219 offset_src = 0;
220 } else if (instr->intrinsic == nir_intrinsic_load_ssbo ||
221 instr->intrinsic == nir_intrinsic_load_ubo ||
222 instr->intrinsic == nir_intrinsic_load_scratch ||
223 instr->intrinsic == nir_intrinsic_load_shared ||
224 atomic_add_replaced) {
225 offset_src = 0 + has_index;
226 } else if (is_store) {
227 offset_src = 1 + has_index;
228 } else {
229 offset_src = 0 + has_index;
230 }
231
232 bool dynamic_src = !nir_src_is_const(instr->src[offset_src]);
233 uint32_t const_offset = 0;
234 if (!dynamic_src)
235 const_offset = nir_src_as_uint(instr->src[offset_src]);
236
237 struct qreg base_offset;
238 if (instr->intrinsic == nir_intrinsic_load_uniform) {
239 const_offset += nir_intrinsic_base(instr);
240 base_offset = vir_uniform(c, QUNIFORM_UBO_ADDR,
241 v3d_unit_data_create(0, const_offset));
242 const_offset = 0;
243 } else if (instr->intrinsic == nir_intrinsic_load_ubo) {
244 uint32_t index = nir_src_as_uint(instr->src[0]) + 1;
245 /* Note that QUNIFORM_UBO_ADDR takes a UBO index shifted up by
246 * 1 (0 is gallium's constant buffer 0).
247 */
248 base_offset =
249 vir_uniform(c, QUNIFORM_UBO_ADDR,
250 v3d_unit_data_create(index, const_offset));
251 const_offset = 0;
252 } else if (is_shared_or_scratch) {
253 /* Shared and scratch variables have no buffer index, and all
254 * start from a common base that we set up at the start of
255 * dispatch.
256 */
257 if (instr->intrinsic == nir_intrinsic_load_scratch ||
258 instr->intrinsic == nir_intrinsic_store_scratch) {
259 base_offset = c->spill_base;
260 } else {
261 base_offset = c->cs_shared_offset;
262 const_offset += nir_intrinsic_base(instr);
263 }
264 } else {
265 base_offset = vir_uniform(c, QUNIFORM_SSBO_OFFSET,
266 nir_src_as_uint(instr->src[is_store ?
267 1 : 0]));
268 }
269
270 struct qreg tmud = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD);
271 unsigned writemask = is_store ? nir_intrinsic_write_mask(instr) : 0;
272 uint32_t base_const_offset = const_offset;
273 int first_component = -1;
274 int last_component = -1;
275 do {
276 int tmu_writes = 1; /* address */
277
278 if (is_store) {
279 /* Find the first set of consecutive components that
280 * are enabled in the writemask and emit the TMUD
281 * instructions for them.
282 */
283 first_component = ffs(writemask) - 1;
284 last_component = first_component;
285 while (writemask & BITFIELD_BIT(last_component + 1))
286 last_component++;
287
288 assert(first_component >= 0 &&
289 first_component <= last_component &&
290 last_component < instr->num_components);
291
292 struct qreg tmud = vir_reg(QFILE_MAGIC,
293 V3D_QPU_WADDR_TMUD);
294 for (int i = first_component; i <= last_component; i++) {
295 struct qreg data =
296 ntq_get_src(c, instr->src[0], i);
297 vir_MOV_dest(c, tmud, data);
298 tmu_writes++;
299 }
300
301 /* Update the offset for the TMU write based on the
302 * the first component we are writing.
303 */
304 const_offset = base_const_offset + first_component * 4;
305
306 /* Clear these components from the writemask */
307 uint32_t written_mask =
308 BITFIELD_RANGE(first_component, tmu_writes - 1);
309 writemask &= ~written_mask;
310 } else if (!is_load && !atomic_add_replaced) {
311 struct qreg data =
312 ntq_get_src(c, instr->src[1 + has_index], 0);
313 vir_MOV_dest(c, tmud, data);
314 tmu_writes++;
315 if (tmu_op == V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH) {
316 data = ntq_get_src(c, instr->src[2 + has_index],
317 0);
318 vir_MOV_dest(c, tmud, data);
319 tmu_writes++;
320 }
321 }
322
323 /* Make sure we won't exceed the 16-entry TMU fifo if each
324 * thread is storing at the same time.
325 */
326 while (tmu_writes > 16 / c->threads)
327 c->threads /= 2;
328
329 /* The spec says that for atomics, the TYPE field is ignored,
330 * but that doesn't seem to be the case for CMPXCHG. Just use
331 * the number of tmud writes we did to decide the type (or
332 * choose "32bit" for atomic reads, which has been fine).
333 */
334 uint32_t num_components;
335 if (is_load || atomic_add_replaced) {
336 num_components = instr->num_components;
337 } else {
338 assert(tmu_writes > 1);
339 num_components = tmu_writes - 1;
340 }
341
342 uint32_t config = (0xffffff00 |
343 tmu_op << 3|
344 GENERAL_TMU_LOOKUP_PER_PIXEL);
345 if (num_components == 1) {
346 config |= GENERAL_TMU_LOOKUP_TYPE_32BIT_UI;
347 } else {
348 config |= GENERAL_TMU_LOOKUP_TYPE_VEC2 +
349 num_components - 2;
350 }
351
352 if (vir_in_nonuniform_control_flow(c)) {
353 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
354 V3D_QPU_PF_PUSHZ);
355 }
356
357 struct qreg tmua;
358 if (config == ~0)
359 tmua = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA);
360 else
361 tmua = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUAU);
362
363 struct qinst *tmu;
364 if (dynamic_src) {
365 struct qreg offset = base_offset;
366 if (const_offset != 0) {
367 offset = vir_ADD(c, offset,
368 vir_uniform_ui(c, const_offset));
369 }
370 struct qreg data =
371 ntq_get_src(c, instr->src[offset_src], 0);
372 tmu = vir_ADD_dest(c, tmua, offset, data);
373 } else {
374 if (const_offset != 0) {
375 tmu = vir_ADD_dest(c, tmua, base_offset,
376 vir_uniform_ui(c, const_offset));
377 } else {
378 tmu = vir_MOV_dest(c, tmua, base_offset);
379 }
380 }
381
382 if (config != ~0) {
383 tmu->uniform =
384 vir_get_uniform_index(c, QUNIFORM_CONSTANT,
385 config);
386 }
387
388 if (vir_in_nonuniform_control_flow(c))
389 vir_set_cond(tmu, V3D_QPU_COND_IFA);
390
391 vir_emit_thrsw(c);
392
393 /* Read the result, or wait for the TMU op to complete. */
394 for (int i = 0; i < nir_intrinsic_dest_components(instr); i++) {
395 ntq_store_dest(c, &instr->dest, i,
396 vir_MOV(c, vir_LDTMU(c)));
397 }
398
399 if (nir_intrinsic_dest_components(instr) == 0)
400 vir_TMUWT(c);
401 } while (is_store && writemask != 0);
402 }
403
404 static struct qreg *
405 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
406 {
407 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
408 def->num_components);
409 _mesa_hash_table_insert(c->def_ht, def, qregs);
410 return qregs;
411 }
412
413 static bool
414 is_ld_signal(const struct v3d_qpu_sig *sig)
415 {
416 return (sig->ldunif ||
417 sig->ldunifa ||
418 sig->ldunifrf ||
419 sig->ldunifarf ||
420 sig->ldtmu ||
421 sig->ldvary ||
422 sig->ldvpm ||
423 sig->ldtlb ||
424 sig->ldtlbu);
425 }
426
427 /**
428 * This function is responsible for getting VIR results into the associated
429 * storage for a NIR instruction.
430 *
431 * If it's a NIR SSA def, then we just set the associated hash table entry to
432 * the new result.
433 *
434 * If it's a NIR reg, then we need to update the existing qreg assigned to the
435 * NIR destination with the incoming value. To do that without introducing
436 * new MOVs, we require that the incoming qreg either be a uniform, or be
437 * SSA-defined by the previous VIR instruction in the block and rewritable by
438 * this function. That lets us sneak ahead and insert the SF flag beforehand
439 * (knowing that the previous instruction doesn't depend on flags) and rewrite
440 * its destination to be the NIR reg's destination
441 */
442 void
443 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
444 struct qreg result)
445 {
446 struct qinst *last_inst = NULL;
447 if (!list_is_empty(&c->cur_block->instructions))
448 last_inst = (struct qinst *)c->cur_block->instructions.prev;
449
450 assert((result.file == QFILE_TEMP &&
451 last_inst && last_inst == c->defs[result.index]));
452
453 if (dest->is_ssa) {
454 assert(chan < dest->ssa.num_components);
455
456 struct qreg *qregs;
457 struct hash_entry *entry =
458 _mesa_hash_table_search(c->def_ht, &dest->ssa);
459
460 if (entry)
461 qregs = entry->data;
462 else
463 qregs = ntq_init_ssa_def(c, &dest->ssa);
464
465 qregs[chan] = result;
466 } else {
467 nir_register *reg = dest->reg.reg;
468 assert(dest->reg.base_offset == 0);
469 assert(reg->num_array_elems == 0);
470 struct hash_entry *entry =
471 _mesa_hash_table_search(c->def_ht, reg);
472 struct qreg *qregs = entry->data;
473
474 /* If the previous instruction can't be predicated for
475 * the store into the nir_register, then emit a MOV
476 * that can be.
477 */
478 if (vir_in_nonuniform_control_flow(c) &&
479 is_ld_signal(&c->defs[last_inst->dst.index]->qpu.sig)) {
480 result = vir_MOV(c, result);
481 last_inst = c->defs[result.index];
482 }
483
484 /* We know they're both temps, so just rewrite index. */
485 c->defs[last_inst->dst.index] = NULL;
486 last_inst->dst.index = qregs[chan].index;
487
488 /* If we're in control flow, then make this update of the reg
489 * conditional on the execution mask.
490 */
491 if (vir_in_nonuniform_control_flow(c)) {
492 last_inst->dst.index = qregs[chan].index;
493
494 /* Set the flags to the current exec mask.
495 */
496 c->cursor = vir_before_inst(last_inst);
497 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
498 V3D_QPU_PF_PUSHZ);
499 c->cursor = vir_after_inst(last_inst);
500
501 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
502 }
503 }
504 }
505
506 struct qreg
507 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
508 {
509 struct hash_entry *entry;
510 if (src.is_ssa) {
511 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
512 assert(i < src.ssa->num_components);
513 } else {
514 nir_register *reg = src.reg.reg;
515 entry = _mesa_hash_table_search(c->def_ht, reg);
516 assert(reg->num_array_elems == 0);
517 assert(src.reg.base_offset == 0);
518 assert(i < reg->num_components);
519 }
520
521 struct qreg *qregs = entry->data;
522 return qregs[i];
523 }
524
525 static struct qreg
526 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
527 unsigned src)
528 {
529 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
530 unsigned chan = ffs(instr->dest.write_mask) - 1;
531 struct qreg r = ntq_get_src(c, instr->src[src].src,
532 instr->src[src].swizzle[chan]);
533
534 assert(!instr->src[src].abs);
535 assert(!instr->src[src].negate);
536
537 return r;
538 };
539
540 static struct qreg
541 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
542 {
543 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
544 }
545
546 static void
547 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
548 {
549 unsigned unit = instr->texture_index;
550 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
551 int dest_size = nir_tex_instr_dest_size(instr);
552
553 struct qreg lod = c->undef;
554 if (lod_index != -1)
555 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
556
557 for (int i = 0; i < dest_size; i++) {
558 assert(i < 3);
559 enum quniform_contents contents;
560
561 if (instr->is_array && i == dest_size - 1)
562 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
563 else
564 contents = QUNIFORM_TEXTURE_WIDTH + i;
565
566 struct qreg size = vir_uniform(c, contents, unit);
567
568 switch (instr->sampler_dim) {
569 case GLSL_SAMPLER_DIM_1D:
570 case GLSL_SAMPLER_DIM_2D:
571 case GLSL_SAMPLER_DIM_MS:
572 case GLSL_SAMPLER_DIM_3D:
573 case GLSL_SAMPLER_DIM_CUBE:
574 /* Don't minify the array size. */
575 if (!(instr->is_array && i == dest_size - 1)) {
576 size = ntq_minify(c, size, lod);
577 }
578 break;
579
580 case GLSL_SAMPLER_DIM_RECT:
581 /* There's no LOD field for rects */
582 break;
583
584 default:
585 unreachable("Bad sampler type");
586 }
587
588 ntq_store_dest(c, &instr->dest, i, size);
589 }
590 }
591
592 static void
593 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
594 {
595 unsigned unit = instr->texture_index;
596
597 /* Since each texture sampling op requires uploading uniforms to
598 * reference the texture, there's no HW support for texture size and
599 * you just upload uniforms containing the size.
600 */
601 switch (instr->op) {
602 case nir_texop_query_levels:
603 ntq_store_dest(c, &instr->dest, 0,
604 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
605 return;
606 case nir_texop_txs:
607 ntq_emit_txs(c, instr);
608 return;
609 default:
610 break;
611 }
612
613 if (c->devinfo->ver >= 40)
614 v3d40_vir_emit_tex(c, instr);
615 else
616 v3d33_vir_emit_tex(c, instr);
617 }
618
619 static struct qreg
620 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
621 {
622 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
623 if (is_cos)
624 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
625
626 struct qreg periods = vir_FROUND(c, input);
627 struct qreg sin_output = vir_SIN(c, vir_FSUB(c, input, periods));
628 return vir_XOR(c, sin_output, vir_SHL(c,
629 vir_FTOIN(c, periods),
630 vir_uniform_ui(c, -1)));
631 }
632
633 static struct qreg
634 ntq_fsign(struct v3d_compile *c, struct qreg src)
635 {
636 struct qreg t = vir_get_temp(c);
637
638 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
639 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHZ);
640 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
641 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHN);
642 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
643 return vir_MOV(c, t);
644 }
645
646 static void
647 emit_fragcoord_input(struct v3d_compile *c, int attr)
648 {
649 c->inputs[attr * 4 + 0] = vir_FXCD(c);
650 c->inputs[attr * 4 + 1] = vir_FYCD(c);
651 c->inputs[attr * 4 + 2] = c->payload_z;
652 c->inputs[attr * 4 + 3] = vir_RECIP(c, c->payload_w);
653 }
654
655 static struct qreg
656 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
657 uint8_t swizzle, int array_index)
658 {
659 struct qreg r3 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R3);
660 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
661
662 struct qreg vary;
663 if (c->devinfo->ver >= 41) {
664 struct qinst *ldvary = vir_add_inst(V3D_QPU_A_NOP, c->undef,
665 c->undef, c->undef);
666 ldvary->qpu.sig.ldvary = true;
667 vary = vir_emit_def(c, ldvary);
668 } else {
669 vir_NOP(c)->qpu.sig.ldvary = true;
670 vary = r3;
671 }
672
673 /* For gl_PointCoord input or distance along a line, we'll be called
674 * with no nir_variable, and we don't count toward VPM size so we
675 * don't track an input slot.
676 */
677 if (!var) {
678 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
679 }
680
681 int i = c->num_inputs++;
682 c->input_slots[i] =
683 v3d_slot_from_slot_and_component(var->data.location +
684 array_index, swizzle);
685
686 switch (var->data.interpolation) {
687 case INTERP_MODE_NONE:
688 /* If a gl_FrontColor or gl_BackColor input has no interp
689 * qualifier, then if we're using glShadeModel(GL_FLAT) it
690 * needs to be flat shaded.
691 */
692 switch (var->data.location + array_index) {
693 case VARYING_SLOT_COL0:
694 case VARYING_SLOT_COL1:
695 case VARYING_SLOT_BFC0:
696 case VARYING_SLOT_BFC1:
697 if (c->fs_key->shade_model_flat) {
698 BITSET_SET(c->flat_shade_flags, i);
699 vir_MOV_dest(c, c->undef, vary);
700 return vir_MOV(c, r5);
701 } else {
702 return vir_FADD(c, vir_FMUL(c, vary,
703 c->payload_w), r5);
704 }
705 default:
706 break;
707 }
708 /* FALLTHROUGH */
709 case INTERP_MODE_SMOOTH:
710 if (var->data.centroid) {
711 BITSET_SET(c->centroid_flags, i);
712 return vir_FADD(c, vir_FMUL(c, vary,
713 c->payload_w_centroid), r5);
714 } else {
715 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
716 }
717 case INTERP_MODE_NOPERSPECTIVE:
718 BITSET_SET(c->noperspective_flags, i);
719 return vir_FADD(c, vir_MOV(c, vary), r5);
720 case INTERP_MODE_FLAT:
721 BITSET_SET(c->flat_shade_flags, i);
722 vir_MOV_dest(c, c->undef, vary);
723 return vir_MOV(c, r5);
724 default:
725 unreachable("Bad interp mode");
726 }
727 }
728
729 static void
730 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var,
731 int array_index)
732 {
733 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
734 int chan = var->data.location_frac + i;
735 c->inputs[attr * 4 + chan] =
736 emit_fragment_varying(c, var, chan, array_index);
737 }
738 }
739
740 static void
741 emit_compact_fragment_input(struct v3d_compile *c, int attr, nir_variable *var,
742 int array_index)
743 {
744 /* Compact variables are scalar arrays where each set of 4 elements
745 * consumes a single location.
746 */
747 int loc_offset = array_index / 4;
748 int chan = var->data.location_frac + array_index % 4;
749 c->inputs[(attr + loc_offset) * 4 + chan] =
750 emit_fragment_varying(c, var, chan, loc_offset);
751 }
752
753 static void
754 add_output(struct v3d_compile *c,
755 uint32_t decl_offset,
756 uint8_t slot,
757 uint8_t swizzle)
758 {
759 uint32_t old_array_size = c->outputs_array_size;
760 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
761 decl_offset + 1);
762
763 if (old_array_size != c->outputs_array_size) {
764 c->output_slots = reralloc(c,
765 c->output_slots,
766 struct v3d_varying_slot,
767 c->outputs_array_size);
768 }
769
770 c->output_slots[decl_offset] =
771 v3d_slot_from_slot_and_component(slot, swizzle);
772 }
773
774 /**
775 * If compare_instr is a valid comparison instruction, emits the
776 * compare_instr's comparison and returns the sel_instr's return value based
777 * on the compare_instr's result.
778 */
779 static bool
780 ntq_emit_comparison(struct v3d_compile *c,
781 nir_alu_instr *compare_instr,
782 enum v3d_qpu_cond *out_cond)
783 {
784 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
785 struct qreg src1;
786 if (nir_op_infos[compare_instr->op].num_inputs > 1)
787 src1 = ntq_get_alu_src(c, compare_instr, 1);
788 bool cond_invert = false;
789 struct qreg nop = vir_nop_reg();
790
791 switch (compare_instr->op) {
792 case nir_op_feq32:
793 case nir_op_seq:
794 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
795 break;
796 case nir_op_ieq32:
797 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
798 break;
799
800 case nir_op_fne32:
801 case nir_op_sne:
802 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
803 cond_invert = true;
804 break;
805 case nir_op_ine32:
806 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
807 cond_invert = true;
808 break;
809
810 case nir_op_fge32:
811 case nir_op_sge:
812 vir_set_pf(vir_FCMP_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
813 break;
814 case nir_op_ige32:
815 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
816 cond_invert = true;
817 break;
818 case nir_op_uge32:
819 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
820 cond_invert = true;
821 break;
822
823 case nir_op_slt:
824 case nir_op_flt32:
825 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHN);
826 break;
827 case nir_op_ilt32:
828 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
829 break;
830 case nir_op_ult32:
831 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
832 break;
833
834 case nir_op_i2b32:
835 vir_set_pf(vir_MOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ);
836 cond_invert = true;
837 break;
838
839 case nir_op_f2b32:
840 vir_set_pf(vir_FMOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ);
841 cond_invert = true;
842 break;
843
844 default:
845 return false;
846 }
847
848 *out_cond = cond_invert ? V3D_QPU_COND_IFNA : V3D_QPU_COND_IFA;
849
850 return true;
851 }
852
853 /* Finds an ALU instruction that generates our src value that could
854 * (potentially) be greedily emitted in the consuming instruction.
855 */
856 static struct nir_alu_instr *
857 ntq_get_alu_parent(nir_src src)
858 {
859 if (!src.is_ssa || src.ssa->parent_instr->type != nir_instr_type_alu)
860 return NULL;
861 nir_alu_instr *instr = nir_instr_as_alu(src.ssa->parent_instr);
862 if (!instr)
863 return NULL;
864
865 /* If the ALU instr's srcs are non-SSA, then we would have to avoid
866 * moving emission of the ALU instr down past another write of the
867 * src.
868 */
869 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
870 if (!instr->src[i].src.is_ssa)
871 return NULL;
872 }
873
874 return instr;
875 }
876
877 /* Turns a NIR bool into a condition code to predicate on. */
878 static enum v3d_qpu_cond
879 ntq_emit_bool_to_cond(struct v3d_compile *c, nir_src src)
880 {
881 nir_alu_instr *compare = ntq_get_alu_parent(src);
882 if (!compare)
883 goto out;
884
885 enum v3d_qpu_cond cond;
886 if (ntq_emit_comparison(c, compare, &cond))
887 return cond;
888
889 out:
890 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), ntq_get_src(c, src, 0)),
891 V3D_QPU_PF_PUSHZ);
892 return V3D_QPU_COND_IFNA;
893 }
894
895 static void
896 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
897 {
898 /* This should always be lowered to ALU operations for V3D. */
899 assert(!instr->dest.saturate);
900
901 /* Vectors are special in that they have non-scalarized writemasks,
902 * and just take the first swizzle channel for each argument in order
903 * into each writemask channel.
904 */
905 if (instr->op == nir_op_vec2 ||
906 instr->op == nir_op_vec3 ||
907 instr->op == nir_op_vec4) {
908 struct qreg srcs[4];
909 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
910 srcs[i] = ntq_get_src(c, instr->src[i].src,
911 instr->src[i].swizzle[0]);
912 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
913 ntq_store_dest(c, &instr->dest.dest, i,
914 vir_MOV(c, srcs[i]));
915 return;
916 }
917
918 /* General case: We can just grab the one used channel per src. */
919 struct qreg src[nir_op_infos[instr->op].num_inputs];
920 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
921 src[i] = ntq_get_alu_src(c, instr, i);
922 }
923
924 struct qreg result;
925
926 switch (instr->op) {
927 case nir_op_mov:
928 result = vir_MOV(c, src[0]);
929 break;
930
931 case nir_op_fneg:
932 result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
933 break;
934 case nir_op_ineg:
935 result = vir_NEG(c, src[0]);
936 break;
937
938 case nir_op_fmul:
939 result = vir_FMUL(c, src[0], src[1]);
940 break;
941 case nir_op_fadd:
942 result = vir_FADD(c, src[0], src[1]);
943 break;
944 case nir_op_fsub:
945 result = vir_FSUB(c, src[0], src[1]);
946 break;
947 case nir_op_fmin:
948 result = vir_FMIN(c, src[0], src[1]);
949 break;
950 case nir_op_fmax:
951 result = vir_FMAX(c, src[0], src[1]);
952 break;
953
954 case nir_op_f2i32: {
955 nir_alu_instr *src0_alu = ntq_get_alu_parent(instr->src[0].src);
956 if (src0_alu && src0_alu->op == nir_op_fround_even) {
957 result = vir_FTOIN(c, ntq_get_alu_src(c, src0_alu, 0));
958 } else {
959 result = vir_FTOIZ(c, src[0]);
960 }
961 break;
962 }
963
964 case nir_op_f2u32:
965 result = vir_FTOUZ(c, src[0]);
966 break;
967 case nir_op_i2f32:
968 result = vir_ITOF(c, src[0]);
969 break;
970 case nir_op_u2f32:
971 result = vir_UTOF(c, src[0]);
972 break;
973 case nir_op_b2f32:
974 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
975 break;
976 case nir_op_b2i32:
977 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
978 break;
979
980 case nir_op_iadd:
981 result = vir_ADD(c, src[0], src[1]);
982 break;
983 case nir_op_ushr:
984 result = vir_SHR(c, src[0], src[1]);
985 break;
986 case nir_op_isub:
987 result = vir_SUB(c, src[0], src[1]);
988 break;
989 case nir_op_ishr:
990 result = vir_ASR(c, src[0], src[1]);
991 break;
992 case nir_op_ishl:
993 result = vir_SHL(c, src[0], src[1]);
994 break;
995 case nir_op_imin:
996 result = vir_MIN(c, src[0], src[1]);
997 break;
998 case nir_op_umin:
999 result = vir_UMIN(c, src[0], src[1]);
1000 break;
1001 case nir_op_imax:
1002 result = vir_MAX(c, src[0], src[1]);
1003 break;
1004 case nir_op_umax:
1005 result = vir_UMAX(c, src[0], src[1]);
1006 break;
1007 case nir_op_iand:
1008 result = vir_AND(c, src[0], src[1]);
1009 break;
1010 case nir_op_ior:
1011 result = vir_OR(c, src[0], src[1]);
1012 break;
1013 case nir_op_ixor:
1014 result = vir_XOR(c, src[0], src[1]);
1015 break;
1016 case nir_op_inot:
1017 result = vir_NOT(c, src[0]);
1018 break;
1019
1020 case nir_op_ufind_msb:
1021 result = vir_SUB(c, vir_uniform_ui(c, 31), vir_CLZ(c, src[0]));
1022 break;
1023
1024 case nir_op_imul:
1025 result = vir_UMUL(c, src[0], src[1]);
1026 break;
1027
1028 case nir_op_seq:
1029 case nir_op_sne:
1030 case nir_op_sge:
1031 case nir_op_slt: {
1032 enum v3d_qpu_cond cond;
1033 ASSERTED bool ok = ntq_emit_comparison(c, instr, &cond);
1034 assert(ok);
1035 result = vir_MOV(c, vir_SEL(c, cond,
1036 vir_uniform_f(c, 1.0),
1037 vir_uniform_f(c, 0.0)));
1038 break;
1039 }
1040
1041 case nir_op_i2b32:
1042 case nir_op_f2b32:
1043 case nir_op_feq32:
1044 case nir_op_fne32:
1045 case nir_op_fge32:
1046 case nir_op_flt32:
1047 case nir_op_ieq32:
1048 case nir_op_ine32:
1049 case nir_op_ige32:
1050 case nir_op_uge32:
1051 case nir_op_ilt32:
1052 case nir_op_ult32: {
1053 enum v3d_qpu_cond cond;
1054 ASSERTED bool ok = ntq_emit_comparison(c, instr, &cond);
1055 assert(ok);
1056 result = vir_MOV(c, vir_SEL(c, cond,
1057 vir_uniform_ui(c, ~0),
1058 vir_uniform_ui(c, 0)));
1059 break;
1060 }
1061
1062 case nir_op_b32csel:
1063 result = vir_MOV(c,
1064 vir_SEL(c,
1065 ntq_emit_bool_to_cond(c, instr->src[0].src),
1066 src[1], src[2]));
1067 break;
1068
1069 case nir_op_fcsel:
1070 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), src[0]),
1071 V3D_QPU_PF_PUSHZ);
1072 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
1073 src[1], src[2]));
1074 break;
1075
1076 case nir_op_frcp:
1077 result = vir_RECIP(c, src[0]);
1078 break;
1079 case nir_op_frsq:
1080 result = vir_RSQRT(c, src[0]);
1081 break;
1082 case nir_op_fexp2:
1083 result = vir_EXP(c, src[0]);
1084 break;
1085 case nir_op_flog2:
1086 result = vir_LOG(c, src[0]);
1087 break;
1088
1089 case nir_op_fceil:
1090 result = vir_FCEIL(c, src[0]);
1091 break;
1092 case nir_op_ffloor:
1093 result = vir_FFLOOR(c, src[0]);
1094 break;
1095 case nir_op_fround_even:
1096 result = vir_FROUND(c, src[0]);
1097 break;
1098 case nir_op_ftrunc:
1099 result = vir_FTRUNC(c, src[0]);
1100 break;
1101
1102 case nir_op_fsin:
1103 result = ntq_fsincos(c, src[0], false);
1104 break;
1105 case nir_op_fcos:
1106 result = ntq_fsincos(c, src[0], true);
1107 break;
1108
1109 case nir_op_fsign:
1110 result = ntq_fsign(c, src[0]);
1111 break;
1112
1113 case nir_op_fabs: {
1114 result = vir_FMOV(c, src[0]);
1115 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
1116 break;
1117 }
1118
1119 case nir_op_iabs:
1120 result = vir_MAX(c, src[0], vir_NEG(c, src[0]));
1121 break;
1122
1123 case nir_op_fddx:
1124 case nir_op_fddx_coarse:
1125 case nir_op_fddx_fine:
1126 result = vir_FDX(c, src[0]);
1127 break;
1128
1129 case nir_op_fddy:
1130 case nir_op_fddy_coarse:
1131 case nir_op_fddy_fine:
1132 result = vir_FDY(c, src[0]);
1133 break;
1134
1135 case nir_op_uadd_carry:
1136 vir_set_pf(vir_ADD_dest(c, vir_nop_reg(), src[0], src[1]),
1137 V3D_QPU_PF_PUSHC);
1138 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1139 vir_uniform_ui(c, ~0),
1140 vir_uniform_ui(c, 0)));
1141 break;
1142
1143 case nir_op_pack_half_2x16_split:
1144 result = vir_VFPACK(c, src[0], src[1]);
1145 break;
1146
1147 case nir_op_unpack_half_2x16_split_x:
1148 result = vir_FMOV(c, src[0]);
1149 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_L);
1150 break;
1151
1152 case nir_op_unpack_half_2x16_split_y:
1153 result = vir_FMOV(c, src[0]);
1154 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_H);
1155 break;
1156
1157 default:
1158 fprintf(stderr, "unknown NIR ALU inst: ");
1159 nir_print_instr(&instr->instr, stderr);
1160 fprintf(stderr, "\n");
1161 abort();
1162 }
1163
1164 /* We have a scalar result, so the instruction should only have a
1165 * single channel written to.
1166 */
1167 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
1168 ntq_store_dest(c, &instr->dest.dest,
1169 ffs(instr->dest.write_mask) - 1, result);
1170 }
1171
1172 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
1173 * specifier. They come from a register that's preloaded with 0xffffffff
1174 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
1175 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
1176 */
1177 #define TLB_TYPE_F16_COLOR (3 << 6)
1178 #define TLB_TYPE_I32_COLOR (1 << 6)
1179 #define TLB_TYPE_F32_COLOR (0 << 6)
1180 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
1181 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
1182 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
1183 #define TLB_F16_SWAP_HI_LO (1 << 1)
1184 #define TLB_VEC_SIZE_4_F16 (1 << 0)
1185 #define TLB_VEC_SIZE_2_F16 (0 << 0)
1186 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
1187
1188 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
1189 * flag is set.
1190 */
1191 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
1192 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
1193 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
1194 #define TLB_V42_DEPTH_TYPE_INVARIANT (0 << 3) /* Unmodified sideband input used */
1195 #define TLB_V42_DEPTH_TYPE_PER_PIXEL (1 << 3) /* QPU result used */
1196
1197 /* Stencil is a single 32-bit write. */
1198 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1199
1200 static void
1201 vir_emit_tlb_color_write(struct v3d_compile *c, unsigned rt)
1202 {
1203 if (!(c->fs_key->cbufs & (1 << rt)) || !c->output_color_var[rt])
1204 return;
1205
1206 struct qreg tlb_reg = vir_magic_reg(V3D_QPU_WADDR_TLB);
1207 struct qreg tlbu_reg = vir_magic_reg(V3D_QPU_WADDR_TLBU);
1208
1209 nir_variable *var = c->output_color_var[rt];
1210 int num_components = glsl_get_vector_elements(var->type);
1211 uint32_t conf = 0xffffff00;
1212 struct qinst *inst;
1213
1214 conf |= c->msaa_per_sample_output ? TLB_SAMPLE_MODE_PER_SAMPLE :
1215 TLB_SAMPLE_MODE_PER_PIXEL;
1216 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1217
1218 if (c->fs_key->swap_color_rb & (1 << rt))
1219 num_components = MAX2(num_components, 3);
1220 assert(num_components != 0);
1221
1222 enum glsl_base_type type = glsl_get_base_type(var->type);
1223 bool is_int_format = type == GLSL_TYPE_INT || type == GLSL_TYPE_UINT;
1224 bool is_32b_tlb_format = is_int_format ||
1225 (c->fs_key->f32_color_rb & (1 << rt));
1226
1227 if (is_int_format) {
1228 /* The F32 vs I32 distinction was dropped in 4.2. */
1229 if (c->devinfo->ver < 42)
1230 conf |= TLB_TYPE_I32_COLOR;
1231 else
1232 conf |= TLB_TYPE_F32_COLOR;
1233 conf |= ((num_components - 1) << TLB_VEC_SIZE_MINUS_1_SHIFT);
1234 } else {
1235 if (c->fs_key->f32_color_rb & (1 << rt)) {
1236 conf |= TLB_TYPE_F32_COLOR;
1237 conf |= ((num_components - 1) <<
1238 TLB_VEC_SIZE_MINUS_1_SHIFT);
1239 } else {
1240 conf |= TLB_TYPE_F16_COLOR;
1241 conf |= TLB_F16_SWAP_HI_LO;
1242 if (num_components >= 3)
1243 conf |= TLB_VEC_SIZE_4_F16;
1244 else
1245 conf |= TLB_VEC_SIZE_2_F16;
1246 }
1247 }
1248
1249 int num_samples = c->msaa_per_sample_output ? V3D_MAX_SAMPLES : 1;
1250 for (int i = 0; i < num_samples; i++) {
1251 struct qreg *color = c->msaa_per_sample_output ?
1252 &c->sample_colors[(rt * V3D_MAX_SAMPLES + i) * 4] :
1253 &c->outputs[var->data.driver_location * 4];
1254
1255 struct qreg r = color[0];
1256 struct qreg g = color[1];
1257 struct qreg b = color[2];
1258 struct qreg a = color[3];
1259
1260 if (c->fs_key->swap_color_rb & (1 << rt)) {
1261 r = color[2];
1262 b = color[0];
1263 }
1264
1265 if (c->fs_key->sample_alpha_to_one)
1266 a = vir_uniform_f(c, 1.0);
1267
1268 if (is_32b_tlb_format) {
1269 if (i == 0) {
1270 inst = vir_MOV_dest(c, tlbu_reg, r);
1271 inst->uniform =
1272 vir_get_uniform_index(c,
1273 QUNIFORM_CONSTANT,
1274 conf);
1275 } else {
1276 inst = vir_MOV_dest(c, tlb_reg, r);
1277 }
1278
1279 if (num_components >= 2)
1280 vir_MOV_dest(c, tlb_reg, g);
1281 if (num_components >= 3)
1282 vir_MOV_dest(c, tlb_reg, b);
1283 if (num_components >= 4)
1284 vir_MOV_dest(c, tlb_reg, a);
1285 } else {
1286 inst = vir_VFPACK_dest(c, tlb_reg, r, g);
1287 if (conf != ~0 && i == 0) {
1288 inst->dst = tlbu_reg;
1289 inst->uniform =
1290 vir_get_uniform_index(c,
1291 QUNIFORM_CONSTANT,
1292 conf);
1293 }
1294
1295 if (num_components >= 3)
1296 inst = vir_VFPACK_dest(c, tlb_reg, b, a);
1297 }
1298 }
1299 }
1300
1301 static void
1302 emit_frag_end(struct v3d_compile *c)
1303 {
1304 /* XXX
1305 if (c->output_sample_mask_index != -1) {
1306 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1307 }
1308 */
1309
1310 bool has_any_tlb_color_write = false;
1311 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1312 if (c->fs_key->cbufs & (1 << rt) && c->output_color_var[rt])
1313 has_any_tlb_color_write = true;
1314 }
1315
1316 if (c->fs_key->sample_alpha_to_coverage && c->output_color_var[0]) {
1317 struct nir_variable *var = c->output_color_var[0];
1318 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1319
1320 vir_SETMSF_dest(c, vir_nop_reg(),
1321 vir_AND(c,
1322 vir_MSF(c),
1323 vir_FTOC(c, color[3])));
1324 }
1325
1326 struct qreg tlbu_reg = vir_magic_reg(V3D_QPU_WADDR_TLBU);
1327 if (c->output_position_index != -1) {
1328 struct qinst *inst = vir_MOV_dest(c, tlbu_reg,
1329 c->outputs[c->output_position_index]);
1330 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1331
1332 if (c->devinfo->ver >= 42) {
1333 tlb_specifier |= (TLB_V42_DEPTH_TYPE_PER_PIXEL |
1334 TLB_SAMPLE_MODE_PER_PIXEL);
1335 } else
1336 tlb_specifier |= TLB_DEPTH_TYPE_PER_PIXEL;
1337
1338 inst->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT,
1339 tlb_specifier |
1340 0xffffff00);
1341 c->writes_z = true;
1342 } else if (c->s->info.fs.uses_discard ||
1343 !c->s->info.fs.early_fragment_tests ||
1344 c->fs_key->sample_alpha_to_coverage ||
1345 !has_any_tlb_color_write) {
1346 /* Emit passthrough Z if it needed to be delayed until shader
1347 * end due to potential discards.
1348 *
1349 * Since (single-threaded) fragment shaders always need a TLB
1350 * write, emit passthrouh Z if we didn't have any color
1351 * buffers and flag us as potentially discarding, so that we
1352 * can use Z as the TLB write.
1353 */
1354 c->s->info.fs.uses_discard = true;
1355
1356 struct qinst *inst = vir_MOV_dest(c, tlbu_reg,
1357 vir_nop_reg());
1358 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1359
1360 if (c->devinfo->ver >= 42) {
1361 /* The spec says the PER_PIXEL flag is ignored for
1362 * invariant writes, but the simulator demands it.
1363 */
1364 tlb_specifier |= (TLB_V42_DEPTH_TYPE_INVARIANT |
1365 TLB_SAMPLE_MODE_PER_PIXEL);
1366 } else {
1367 tlb_specifier |= TLB_DEPTH_TYPE_INVARIANT;
1368 }
1369
1370 inst->uniform = vir_get_uniform_index(c,
1371 QUNIFORM_CONSTANT,
1372 tlb_specifier |
1373 0xffffff00);
1374 c->writes_z = true;
1375 }
1376
1377 /* XXX: Performance improvement: Merge Z write and color writes TLB
1378 * uniform setup
1379 */
1380 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++)
1381 vir_emit_tlb_color_write(c, rt);
1382 }
1383
1384 static inline void
1385 vir_VPM_WRITE_indirect(struct v3d_compile *c,
1386 struct qreg val,
1387 struct qreg vpm_index)
1388 {
1389 assert(c->devinfo->ver >= 40);
1390 vir_STVPMV(c, vpm_index, val);
1391 }
1392
1393 static void
1394 vir_VPM_WRITE(struct v3d_compile *c, struct qreg val, uint32_t vpm_index)
1395 {
1396 if (c->devinfo->ver >= 40) {
1397 vir_VPM_WRITE_indirect(c, val, vir_uniform_ui(c, vpm_index));
1398 } else {
1399 /* XXX: v3d33_vir_vpm_write_setup(c); */
1400 vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM), val);
1401 }
1402 }
1403
1404 static void
1405 emit_vert_end(struct v3d_compile *c)
1406 {
1407 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1408 */
1409 if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
1410 vir_VPMWT(c);
1411 }
1412
1413 static void
1414 emit_geom_end(struct v3d_compile *c)
1415 {
1416 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1417 */
1418 if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
1419 vir_VPMWT(c);
1420 }
1421
1422 void
1423 v3d_optimize_nir(struct nir_shader *s)
1424 {
1425 bool progress;
1426 unsigned lower_flrp =
1427 (s->options->lower_flrp16 ? 16 : 0) |
1428 (s->options->lower_flrp32 ? 32 : 0) |
1429 (s->options->lower_flrp64 ? 64 : 0);
1430
1431 do {
1432 progress = false;
1433
1434 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1435 NIR_PASS(progress, s, nir_lower_alu_to_scalar, NULL, NULL);
1436 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1437 NIR_PASS(progress, s, nir_copy_prop);
1438 NIR_PASS(progress, s, nir_opt_remove_phis);
1439 NIR_PASS(progress, s, nir_opt_dce);
1440 NIR_PASS(progress, s, nir_opt_dead_cf);
1441 NIR_PASS(progress, s, nir_opt_cse);
1442 NIR_PASS(progress, s, nir_opt_peephole_select, 8, true, true);
1443 NIR_PASS(progress, s, nir_opt_algebraic);
1444 NIR_PASS(progress, s, nir_opt_constant_folding);
1445
1446 if (lower_flrp != 0) {
1447 bool lower_flrp_progress = false;
1448
1449 NIR_PASS(lower_flrp_progress, s, nir_lower_flrp,
1450 lower_flrp,
1451 false /* always_precise */,
1452 s->options->lower_ffma);
1453 if (lower_flrp_progress) {
1454 NIR_PASS(progress, s, nir_opt_constant_folding);
1455 progress = true;
1456 }
1457
1458 /* Nothing should rematerialize any flrps, so we only
1459 * need to do this lowering once.
1460 */
1461 lower_flrp = 0;
1462 }
1463
1464 NIR_PASS(progress, s, nir_opt_undef);
1465 } while (progress);
1466
1467 NIR_PASS(progress, s, nir_opt_move, nir_move_load_ubo);
1468 }
1469
1470 static int
1471 driver_location_compare(const void *in_a, const void *in_b)
1472 {
1473 const nir_variable *const *a = in_a;
1474 const nir_variable *const *b = in_b;
1475
1476 if ((*a)->data.driver_location == (*b)->data.driver_location)
1477 return (*a)->data.location_frac - (*b)->data.location_frac;
1478
1479 return (*a)->data.driver_location - (*b)->data.driver_location;
1480 }
1481
1482 static struct qreg
1483 ntq_emit_vpm_read(struct v3d_compile *c,
1484 uint32_t *num_components_queued,
1485 uint32_t *remaining,
1486 uint32_t vpm_index)
1487 {
1488 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1489
1490 if (c->devinfo->ver >= 40 ) {
1491 return vir_LDVPMV_IN(c,
1492 vir_uniform_ui(c,
1493 (*num_components_queued)++));
1494 }
1495
1496 if (*num_components_queued != 0) {
1497 (*num_components_queued)--;
1498 return vir_MOV(c, vpm);
1499 }
1500
1501 uint32_t num_components = MIN2(*remaining, 32);
1502
1503 v3d33_vir_vpm_read_setup(c, num_components);
1504
1505 *num_components_queued = num_components - 1;
1506 *remaining -= num_components;
1507
1508 return vir_MOV(c, vpm);
1509 }
1510
1511 static void
1512 ntq_setup_vs_inputs(struct v3d_compile *c)
1513 {
1514 /* Figure out how many components of each vertex attribute the shader
1515 * uses. Each variable should have been split to individual
1516 * components and unused ones DCEed. The vertex fetcher will load
1517 * from the start of the attribute to the number of components we
1518 * declare we need in c->vattr_sizes[].
1519 */
1520 nir_foreach_shader_in_variable(var, c->s) {
1521 /* No VS attribute array support. */
1522 assert(MAX2(glsl_get_length(var->type), 1) == 1);
1523
1524 unsigned loc = var->data.driver_location;
1525 int start_component = var->data.location_frac;
1526 int num_components = glsl_get_components(var->type);
1527
1528 c->vattr_sizes[loc] = MAX2(c->vattr_sizes[loc],
1529 start_component + num_components);
1530 }
1531
1532 unsigned num_components = 0;
1533 uint32_t vpm_components_queued = 0;
1534 bool uses_iid = c->s->info.system_values_read &
1535 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1536 bool uses_vid = c->s->info.system_values_read &
1537 (1ull << SYSTEM_VALUE_VERTEX_ID);
1538 num_components += uses_iid;
1539 num_components += uses_vid;
1540
1541 for (int i = 0; i < ARRAY_SIZE(c->vattr_sizes); i++)
1542 num_components += c->vattr_sizes[i];
1543
1544 if (uses_iid) {
1545 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1546 &num_components, ~0);
1547 }
1548
1549 if (uses_vid) {
1550 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1551 &num_components, ~0);
1552 }
1553
1554 /* The actual loads will happen directly in nir_intrinsic_load_input
1555 * on newer versions.
1556 */
1557 if (c->devinfo->ver >= 40)
1558 return;
1559
1560 for (int loc = 0; loc < ARRAY_SIZE(c->vattr_sizes); loc++) {
1561 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1562 (loc + 1) * 4);
1563
1564 for (int i = 0; i < c->vattr_sizes[loc]; i++) {
1565 c->inputs[loc * 4 + i] =
1566 ntq_emit_vpm_read(c,
1567 &vpm_components_queued,
1568 &num_components,
1569 loc * 4 + i);
1570
1571 }
1572 }
1573
1574 if (c->devinfo->ver >= 40) {
1575 assert(vpm_components_queued == num_components);
1576 } else {
1577 assert(vpm_components_queued == 0);
1578 assert(num_components == 0);
1579 }
1580 }
1581
1582 static bool
1583 program_reads_point_coord(struct v3d_compile *c)
1584 {
1585 nir_foreach_shader_in_variable(var, c->s) {
1586 if (util_varying_is_point_coord(var->data.location,
1587 c->fs_key->point_sprite_mask)) {
1588 return true;
1589 }
1590 }
1591
1592 return false;
1593 }
1594
1595 static void
1596 get_sorted_input_variables(struct v3d_compile *c,
1597 unsigned *num_entries,
1598 nir_variable ***vars)
1599 {
1600 *num_entries = 0;
1601 nir_foreach_shader_in_variable(var, c->s)
1602 (*num_entries)++;
1603
1604 *vars = ralloc_array(c, nir_variable *, *num_entries);
1605
1606 unsigned i = 0;
1607 nir_foreach_shader_in_variable(var, c->s)
1608 (*vars)[i++] = var;
1609
1610 /* Sort the variables so that we emit the input setup in
1611 * driver_location order. This is required for VPM reads, whose data
1612 * is fetched into the VPM in driver_location (TGSI register index)
1613 * order.
1614 */
1615 qsort(*vars, *num_entries, sizeof(**vars), driver_location_compare);
1616 }
1617
1618 static void
1619 ntq_setup_gs_inputs(struct v3d_compile *c)
1620 {
1621 nir_variable **vars;
1622 unsigned num_entries;
1623 get_sorted_input_variables(c, &num_entries, &vars);
1624
1625 for (unsigned i = 0; i < num_entries; i++) {
1626 nir_variable *var = vars[i];
1627
1628 /* All GS inputs are arrays with as many entries as vertices
1629 * in the input primitive, but here we only care about the
1630 * per-vertex input type.
1631 */
1632 const struct glsl_type *type = glsl_without_array(var->type);
1633 unsigned array_len = MAX2(glsl_get_length(type), 1);
1634 unsigned loc = var->data.driver_location;
1635
1636 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1637 (loc + array_len) * 4);
1638
1639 for (unsigned j = 0; j < array_len; j++) {
1640 unsigned num_elements = glsl_get_vector_elements(type);
1641 for (unsigned k = 0; k < num_elements; k++) {
1642 unsigned chan = var->data.location_frac + k;
1643 unsigned input_idx = c->num_inputs++;
1644 struct v3d_varying_slot slot =
1645 v3d_slot_from_slot_and_component(var->data.location + j, chan);
1646 c->input_slots[input_idx] = slot;
1647 }
1648 }
1649 }
1650 }
1651
1652
1653 static void
1654 ntq_setup_fs_inputs(struct v3d_compile *c)
1655 {
1656 nir_variable **vars;
1657 unsigned num_entries;
1658 get_sorted_input_variables(c, &num_entries, &vars);
1659
1660 for (unsigned i = 0; i < num_entries; i++) {
1661 nir_variable *var = vars[i];
1662 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1663 unsigned loc = var->data.driver_location;
1664
1665 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1666 (loc + array_len) * 4);
1667
1668 if (var->data.location == VARYING_SLOT_POS) {
1669 emit_fragcoord_input(c, loc);
1670 } else if (util_varying_is_point_coord(var->data.location,
1671 c->fs_key->point_sprite_mask)) {
1672 c->inputs[loc * 4 + 0] = c->point_x;
1673 c->inputs[loc * 4 + 1] = c->point_y;
1674 } else if (var->data.compact) {
1675 for (int j = 0; j < array_len; j++)
1676 emit_compact_fragment_input(c, loc, var, j);
1677 } else {
1678 for (int j = 0; j < array_len; j++)
1679 emit_fragment_input(c, loc + j, var, j);
1680 }
1681 }
1682 }
1683
1684 static void
1685 ntq_setup_outputs(struct v3d_compile *c)
1686 {
1687 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
1688 return;
1689
1690 nir_foreach_shader_out_variable(var, c->s) {
1691 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1692 unsigned loc = var->data.driver_location * 4;
1693
1694 assert(array_len == 1);
1695 (void)array_len;
1696
1697 for (int i = 0; i < 4 - var->data.location_frac; i++) {
1698 add_output(c, loc + var->data.location_frac + i,
1699 var->data.location,
1700 var->data.location_frac + i);
1701 }
1702
1703 switch (var->data.location) {
1704 case FRAG_RESULT_COLOR:
1705 c->output_color_var[0] = var;
1706 c->output_color_var[1] = var;
1707 c->output_color_var[2] = var;
1708 c->output_color_var[3] = var;
1709 break;
1710 case FRAG_RESULT_DATA0:
1711 case FRAG_RESULT_DATA1:
1712 case FRAG_RESULT_DATA2:
1713 case FRAG_RESULT_DATA3:
1714 c->output_color_var[var->data.location -
1715 FRAG_RESULT_DATA0] = var;
1716 break;
1717 case FRAG_RESULT_DEPTH:
1718 c->output_position_index = loc;
1719 break;
1720 case FRAG_RESULT_SAMPLE_MASK:
1721 c->output_sample_mask_index = loc;
1722 break;
1723 }
1724 }
1725 }
1726
1727 /**
1728 * Sets up the mapping from nir_register to struct qreg *.
1729 *
1730 * Each nir_register gets a struct qreg per 32-bit component being stored.
1731 */
1732 static void
1733 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1734 {
1735 foreach_list_typed(nir_register, nir_reg, node, list) {
1736 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1737 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1738 array_len *
1739 nir_reg->num_components);
1740
1741 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1742
1743 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1744 qregs[i] = vir_get_temp(c);
1745 }
1746 }
1747
1748 static void
1749 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1750 {
1751 /* XXX perf: Experiment with using immediate loads to avoid having
1752 * these end up in the uniform stream. Watch out for breaking the
1753 * small immediates optimization in the process!
1754 */
1755 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1756 for (int i = 0; i < instr->def.num_components; i++)
1757 qregs[i] = vir_uniform_ui(c, instr->value[i].u32);
1758
1759 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1760 }
1761
1762 static void
1763 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1764 {
1765 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1766
1767 /* VIR needs there to be *some* value, so pick 0 (same as for
1768 * ntq_setup_registers().
1769 */
1770 for (int i = 0; i < instr->def.num_components; i++)
1771 qregs[i] = vir_uniform_ui(c, 0);
1772 }
1773
1774 static void
1775 ntq_emit_image_size(struct v3d_compile *c, nir_intrinsic_instr *instr)
1776 {
1777 unsigned image_index = nir_src_as_uint(instr->src[0]);
1778 bool is_array = nir_intrinsic_image_array(instr);
1779
1780 ntq_store_dest(c, &instr->dest, 0,
1781 vir_uniform(c, QUNIFORM_IMAGE_WIDTH, image_index));
1782 if (instr->num_components > 1) {
1783 ntq_store_dest(c, &instr->dest, 1,
1784 vir_uniform(c,
1785 instr->num_components == 2 && is_array ?
1786 QUNIFORM_IMAGE_ARRAY_SIZE :
1787 QUNIFORM_IMAGE_HEIGHT,
1788 image_index));
1789 }
1790 if (instr->num_components > 2) {
1791 ntq_store_dest(c, &instr->dest, 2,
1792 vir_uniform(c,
1793 is_array ?
1794 QUNIFORM_IMAGE_ARRAY_SIZE :
1795 QUNIFORM_IMAGE_DEPTH,
1796 image_index));
1797 }
1798 }
1799
1800 static void
1801 vir_emit_tlb_color_read(struct v3d_compile *c, nir_intrinsic_instr *instr)
1802 {
1803 assert(c->s->info.stage == MESA_SHADER_FRAGMENT);
1804
1805 int rt = nir_src_as_uint(instr->src[0]);
1806 assert(rt < V3D_MAX_DRAW_BUFFERS);
1807
1808 int sample_index = nir_intrinsic_base(instr) ;
1809 assert(sample_index < V3D_MAX_SAMPLES);
1810
1811 int component = nir_intrinsic_component(instr);
1812 assert(component < 4);
1813
1814 /* We need to emit our TLB reads after we have acquired the scoreboard
1815 * lock, or the GPU will hang. Usually, we do our scoreboard locking on
1816 * the last thread switch to improve parallelism, however, that is only
1817 * guaranteed to happen before the tlb color writes.
1818 *
1819 * To fix that, we make sure we always emit a thread switch before the
1820 * first tlb color read. If that happens to be the last thread switch
1821 * we emit, then everything is fine, but otherwsie, if any code after
1822 * this point needs to emit additional thread switches, then we will
1823 * switch the strategy to locking the scoreboard on the first thread
1824 * switch instead -- see vir_emit_thrsw().
1825 */
1826 if (!c->emitted_tlb_load) {
1827 if (!c->last_thrsw_at_top_level) {
1828 assert(c->devinfo->ver >= 41);
1829 vir_emit_thrsw(c);
1830 }
1831
1832 c->emitted_tlb_load = true;
1833 }
1834
1835 struct qreg *color_reads_for_sample =
1836 &c->color_reads[(rt * V3D_MAX_SAMPLES + sample_index) * 4];
1837
1838 if (color_reads_for_sample[component].file == QFILE_NULL) {
1839 enum pipe_format rt_format = c->fs_key->color_fmt[rt].format;
1840 int num_components =
1841 util_format_get_nr_components(rt_format);
1842
1843 const bool swap_rb = c->fs_key->swap_color_rb & (1 << rt);
1844 if (swap_rb)
1845 num_components = MAX2(num_components, 3);
1846
1847 nir_variable *var = c->output_color_var[rt];
1848 enum glsl_base_type type = glsl_get_base_type(var->type);
1849
1850 bool is_int_format = type == GLSL_TYPE_INT ||
1851 type == GLSL_TYPE_UINT;
1852
1853 bool is_32b_tlb_format = is_int_format ||
1854 (c->fs_key->f32_color_rb & (1 << rt));
1855
1856 int num_samples = c->fs_key->msaa ? V3D_MAX_SAMPLES : 1;
1857
1858 uint32_t conf = 0xffffff00;
1859 conf |= c->fs_key->msaa ? TLB_SAMPLE_MODE_PER_SAMPLE :
1860 TLB_SAMPLE_MODE_PER_PIXEL;
1861 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1862
1863 if (is_32b_tlb_format) {
1864 /* The F32 vs I32 distinction was dropped in 4.2. */
1865 conf |= (c->devinfo->ver < 42 && is_int_format) ?
1866 TLB_TYPE_I32_COLOR : TLB_TYPE_F32_COLOR;
1867
1868 conf |= ((num_components - 1) <<
1869 TLB_VEC_SIZE_MINUS_1_SHIFT);
1870 } else {
1871 conf |= TLB_TYPE_F16_COLOR;
1872 conf |= TLB_F16_SWAP_HI_LO;
1873
1874 if (num_components >= 3)
1875 conf |= TLB_VEC_SIZE_4_F16;
1876 else
1877 conf |= TLB_VEC_SIZE_2_F16;
1878 }
1879
1880
1881 for (int i = 0; i < num_samples; i++) {
1882 struct qreg r, g, b, a;
1883 if (is_32b_tlb_format) {
1884 r = conf != 0xffffffff && i == 0?
1885 vir_TLBU_COLOR_READ(c, conf) :
1886 vir_TLB_COLOR_READ(c);
1887 if (num_components >= 2)
1888 g = vir_TLB_COLOR_READ(c);
1889 if (num_components >= 3)
1890 b = vir_TLB_COLOR_READ(c);
1891 if (num_components >= 4)
1892 a = vir_TLB_COLOR_READ(c);
1893 } else {
1894 struct qreg rg = conf != 0xffffffff && i == 0 ?
1895 vir_TLBU_COLOR_READ(c, conf) :
1896 vir_TLB_COLOR_READ(c);
1897 r = vir_FMOV(c, rg);
1898 vir_set_unpack(c->defs[r.index], 0,
1899 V3D_QPU_UNPACK_L);
1900 g = vir_FMOV(c, rg);
1901 vir_set_unpack(c->defs[g.index], 0,
1902 V3D_QPU_UNPACK_H);
1903
1904 if (num_components > 2) {
1905 struct qreg ba = vir_TLB_COLOR_READ(c);
1906 b = vir_FMOV(c, ba);
1907 vir_set_unpack(c->defs[b.index], 0,
1908 V3D_QPU_UNPACK_L);
1909 a = vir_FMOV(c, ba);
1910 vir_set_unpack(c->defs[a.index], 0,
1911 V3D_QPU_UNPACK_H);
1912 }
1913 }
1914
1915 struct qreg *color_reads =
1916 &c->color_reads[(rt * V3D_MAX_SAMPLES + i) * 4];
1917
1918 color_reads[0] = swap_rb ? b : r;
1919 if (num_components >= 2)
1920 color_reads[1] = g;
1921 if (num_components >= 3)
1922 color_reads[2] = swap_rb ? r : b;
1923 if (num_components >= 4)
1924 color_reads[3] = a;
1925 }
1926 }
1927
1928 assert(color_reads_for_sample[component].file != QFILE_NULL);
1929 ntq_store_dest(c, &instr->dest, 0,
1930 vir_MOV(c, color_reads_for_sample[component]));
1931 }
1932
1933 static void
1934 ntq_emit_load_uniform(struct v3d_compile *c, nir_intrinsic_instr *instr)
1935 {
1936 if (nir_src_is_const(instr->src[0])) {
1937 int offset = (nir_intrinsic_base(instr) +
1938 nir_src_as_uint(instr->src[0]));
1939 assert(offset % 4 == 0);
1940 /* We need dwords */
1941 offset = offset / 4;
1942 for (int i = 0; i < instr->num_components; i++) {
1943 ntq_store_dest(c, &instr->dest, i,
1944 vir_uniform(c, QUNIFORM_UNIFORM,
1945 offset + i));
1946 }
1947 } else {
1948 ntq_emit_tmu_general(c, instr, false);
1949 }
1950 }
1951
1952 static void
1953 ntq_emit_load_input(struct v3d_compile *c, nir_intrinsic_instr *instr)
1954 {
1955 /* XXX: Use ldvpmv (uniform offset) or ldvpmd (non-uniform offset)
1956 * and enable PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR.
1957 */
1958 unsigned offset =
1959 nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[0]);
1960
1961 if (c->s->info.stage != MESA_SHADER_FRAGMENT && c->devinfo->ver >= 40) {
1962 /* Emit the LDVPM directly now, rather than at the top
1963 * of the shader like we did for V3D 3.x (which needs
1964 * vpmsetup when not just taking the next offset).
1965 *
1966 * Note that delaying like this may introduce stalls,
1967 * as LDVPMV takes a minimum of 1 instruction but may
1968 * be slower if the VPM unit is busy with another QPU.
1969 */
1970 int index = 0;
1971 if (c->s->info.system_values_read &
1972 (1ull << SYSTEM_VALUE_INSTANCE_ID)) {
1973 index++;
1974 }
1975 if (c->s->info.system_values_read &
1976 (1ull << SYSTEM_VALUE_VERTEX_ID)) {
1977 index++;
1978 }
1979 for (int i = 0; i < offset; i++)
1980 index += c->vattr_sizes[i];
1981 index += nir_intrinsic_component(instr);
1982 for (int i = 0; i < instr->num_components; i++) {
1983 struct qreg vpm_offset = vir_uniform_ui(c, index++);
1984 ntq_store_dest(c, &instr->dest, i,
1985 vir_LDVPMV_IN(c, vpm_offset));
1986 }
1987 } else {
1988 for (int i = 0; i < instr->num_components; i++) {
1989 int comp = nir_intrinsic_component(instr) + i;
1990 ntq_store_dest(c, &instr->dest, i,
1991 vir_MOV(c, c->inputs[offset * 4 + comp]));
1992 }
1993 }
1994 }
1995
1996 static void
1997 ntq_emit_per_sample_color_write(struct v3d_compile *c,
1998 nir_intrinsic_instr *instr)
1999 {
2000 assert(instr->intrinsic == nir_intrinsic_store_tlb_sample_color_v3d);
2001
2002 unsigned rt = nir_src_as_uint(instr->src[1]);
2003 assert(rt < V3D_MAX_DRAW_BUFFERS);
2004
2005 unsigned sample_idx = nir_intrinsic_base(instr);
2006 assert(sample_idx < V3D_MAX_SAMPLES);
2007
2008 unsigned offset = (rt * V3D_MAX_SAMPLES + sample_idx) * 4;
2009 for (int i = 0; i < instr->num_components; i++) {
2010 c->sample_colors[offset + i] =
2011 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
2012 }
2013 }
2014
2015 static void
2016 ntq_emit_color_write(struct v3d_compile *c,
2017 nir_intrinsic_instr *instr)
2018 {
2019 unsigned offset = (nir_intrinsic_base(instr) +
2020 nir_src_as_uint(instr->src[1])) * 4 +
2021 nir_intrinsic_component(instr);
2022 for (int i = 0; i < instr->num_components; i++) {
2023 c->outputs[offset + i] =
2024 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
2025 }
2026 }
2027
2028 static void
2029 emit_store_output_gs(struct v3d_compile *c, nir_intrinsic_instr *instr)
2030 {
2031 assert(instr->num_components == 1);
2032
2033 struct qreg offset = ntq_get_src(c, instr->src[1], 0);
2034
2035 uint32_t base_offset = nir_intrinsic_base(instr);
2036
2037 if (base_offset)
2038 offset = vir_ADD(c, vir_uniform_ui(c, base_offset), offset);
2039
2040 /* Usually, for VS or FS, we only emit outputs once at program end so
2041 * our VPM writes are never in non-uniform control flow, but this
2042 * is not true for GS, where we are emitting multiple vertices.
2043 */
2044 if (vir_in_nonuniform_control_flow(c)) {
2045 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2046 V3D_QPU_PF_PUSHZ);
2047 }
2048
2049 struct qreg val = ntq_get_src(c, instr->src[0], 0);
2050
2051 /* The offset isn’t necessarily dynamically uniform for a geometry
2052 * shader. This can happen if the shader sometimes doesn’t emit one of
2053 * the vertices. In that case subsequent vertices will be written to
2054 * different offsets in the VPM and we need to use the scatter write
2055 * instruction to have a different offset for each lane.
2056 */
2057 if (nir_src_is_dynamically_uniform(instr->src[1]))
2058 vir_VPM_WRITE_indirect(c, val, offset);
2059 else
2060 vir_STVPMD(c, offset, val);
2061
2062 if (vir_in_nonuniform_control_flow(c)) {
2063 struct qinst *last_inst =
2064 (struct qinst *)c->cur_block->instructions.prev;
2065 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
2066 }
2067 }
2068
2069 static void
2070 ntq_emit_store_output(struct v3d_compile *c, nir_intrinsic_instr *instr)
2071 {
2072 /* XXX perf: Use stvpmv with uniform non-constant offsets and
2073 * stvpmd with non-uniform offsets and enable
2074 * PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR.
2075 */
2076 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
2077 ntq_emit_color_write(c, instr);
2078 } else if (c->s->info.stage == MESA_SHADER_GEOMETRY) {
2079 emit_store_output_gs(c, instr);
2080 } else {
2081 assert(c->s->info.stage == MESA_SHADER_VERTEX);
2082 assert(instr->num_components == 1);
2083
2084 vir_VPM_WRITE(c,
2085 ntq_get_src(c, instr->src[0], 0),
2086 nir_intrinsic_base(instr));
2087 }
2088 }
2089
2090 static void
2091 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
2092 {
2093 switch (instr->intrinsic) {
2094 case nir_intrinsic_load_uniform:
2095 ntq_emit_load_uniform(c, instr);
2096 break;
2097
2098 case nir_intrinsic_load_ubo:
2099 ntq_emit_tmu_general(c, instr, false);
2100 break;
2101
2102 case nir_intrinsic_ssbo_atomic_add:
2103 case nir_intrinsic_ssbo_atomic_imin:
2104 case nir_intrinsic_ssbo_atomic_umin:
2105 case nir_intrinsic_ssbo_atomic_imax:
2106 case nir_intrinsic_ssbo_atomic_umax:
2107 case nir_intrinsic_ssbo_atomic_and:
2108 case nir_intrinsic_ssbo_atomic_or:
2109 case nir_intrinsic_ssbo_atomic_xor:
2110 case nir_intrinsic_ssbo_atomic_exchange:
2111 case nir_intrinsic_ssbo_atomic_comp_swap:
2112 case nir_intrinsic_load_ssbo:
2113 case nir_intrinsic_store_ssbo:
2114 ntq_emit_tmu_general(c, instr, false);
2115 break;
2116
2117 case nir_intrinsic_shared_atomic_add:
2118 case nir_intrinsic_shared_atomic_imin:
2119 case nir_intrinsic_shared_atomic_umin:
2120 case nir_intrinsic_shared_atomic_imax:
2121 case nir_intrinsic_shared_atomic_umax:
2122 case nir_intrinsic_shared_atomic_and:
2123 case nir_intrinsic_shared_atomic_or:
2124 case nir_intrinsic_shared_atomic_xor:
2125 case nir_intrinsic_shared_atomic_exchange:
2126 case nir_intrinsic_shared_atomic_comp_swap:
2127 case nir_intrinsic_load_shared:
2128 case nir_intrinsic_store_shared:
2129 case nir_intrinsic_load_scratch:
2130 case nir_intrinsic_store_scratch:
2131 ntq_emit_tmu_general(c, instr, true);
2132 break;
2133
2134 case nir_intrinsic_image_load:
2135 case nir_intrinsic_image_store:
2136 case nir_intrinsic_image_atomic_add:
2137 case nir_intrinsic_image_atomic_imin:
2138 case nir_intrinsic_image_atomic_umin:
2139 case nir_intrinsic_image_atomic_imax:
2140 case nir_intrinsic_image_atomic_umax:
2141 case nir_intrinsic_image_atomic_and:
2142 case nir_intrinsic_image_atomic_or:
2143 case nir_intrinsic_image_atomic_xor:
2144 case nir_intrinsic_image_atomic_exchange:
2145 case nir_intrinsic_image_atomic_comp_swap:
2146 v3d40_vir_emit_image_load_store(c, instr);
2147 break;
2148
2149 case nir_intrinsic_get_buffer_size:
2150 ntq_store_dest(c, &instr->dest, 0,
2151 vir_uniform(c, QUNIFORM_GET_BUFFER_SIZE,
2152 nir_src_as_uint(instr->src[0])));
2153 break;
2154
2155 case nir_intrinsic_load_user_clip_plane:
2156 for (int i = 0; i < nir_intrinsic_dest_components(instr); i++) {
2157 ntq_store_dest(c, &instr->dest, i,
2158 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
2159 nir_intrinsic_ucp_id(instr) *
2160 4 + i));
2161 }
2162 break;
2163
2164 case nir_intrinsic_load_viewport_x_scale:
2165 ntq_store_dest(c, &instr->dest, 0,
2166 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE, 0));
2167 break;
2168
2169 case nir_intrinsic_load_viewport_y_scale:
2170 ntq_store_dest(c, &instr->dest, 0,
2171 vir_uniform(c, QUNIFORM_VIEWPORT_Y_SCALE, 0));
2172 break;
2173
2174 case nir_intrinsic_load_viewport_z_scale:
2175 ntq_store_dest(c, &instr->dest, 0,
2176 vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0));
2177 break;
2178
2179 case nir_intrinsic_load_viewport_z_offset:
2180 ntq_store_dest(c, &instr->dest, 0,
2181 vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0));
2182 break;
2183
2184 case nir_intrinsic_load_alpha_ref_float:
2185 ntq_store_dest(c, &instr->dest, 0,
2186 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
2187 break;
2188
2189 case nir_intrinsic_load_line_coord:
2190 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->line_x));
2191 break;
2192
2193 case nir_intrinsic_load_line_width:
2194 ntq_store_dest(c, &instr->dest, 0,
2195 vir_uniform(c, QUNIFORM_LINE_WIDTH, 0));
2196 break;
2197
2198 case nir_intrinsic_load_aa_line_width:
2199 ntq_store_dest(c, &instr->dest, 0,
2200 vir_uniform(c, QUNIFORM_AA_LINE_WIDTH, 0));
2201 break;
2202
2203 case nir_intrinsic_load_sample_mask_in:
2204 ntq_store_dest(c, &instr->dest, 0, vir_MSF(c));
2205 break;
2206
2207 case nir_intrinsic_load_helper_invocation:
2208 vir_set_pf(vir_MSF_dest(c, vir_nop_reg()), V3D_QPU_PF_PUSHZ);
2209 ntq_store_dest(c, &instr->dest, 0,
2210 vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
2211 vir_uniform_ui(c, ~0),
2212 vir_uniform_ui(c, 0))));
2213 break;
2214
2215 case nir_intrinsic_load_front_face:
2216 /* The register contains 0 (front) or 1 (back), and we need to
2217 * turn it into a NIR bool where true means front.
2218 */
2219 ntq_store_dest(c, &instr->dest, 0,
2220 vir_ADD(c,
2221 vir_uniform_ui(c, -1),
2222 vir_REVF(c)));
2223 break;
2224
2225 case nir_intrinsic_load_instance_id:
2226 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
2227 break;
2228
2229 case nir_intrinsic_load_vertex_id:
2230 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
2231 break;
2232
2233 case nir_intrinsic_load_tlb_color_v3d:
2234 vir_emit_tlb_color_read(c, instr);
2235 break;
2236
2237 case nir_intrinsic_load_input:
2238 ntq_emit_load_input(c, instr);
2239 break;
2240
2241 case nir_intrinsic_store_tlb_sample_color_v3d:
2242 ntq_emit_per_sample_color_write(c, instr);
2243 break;
2244
2245 case nir_intrinsic_store_output:
2246 ntq_emit_store_output(c, instr);
2247 break;
2248
2249 case nir_intrinsic_image_size:
2250 ntq_emit_image_size(c, instr);
2251 break;
2252
2253 case nir_intrinsic_discard:
2254 if (vir_in_nonuniform_control_flow(c)) {
2255 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2256 V3D_QPU_PF_PUSHZ);
2257 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
2258 vir_uniform_ui(c, 0)),
2259 V3D_QPU_COND_IFA);
2260 } else {
2261 vir_SETMSF_dest(c, vir_nop_reg(),
2262 vir_uniform_ui(c, 0));
2263 }
2264 break;
2265
2266 case nir_intrinsic_discard_if: {
2267 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, instr->src[0]);
2268
2269 if (vir_in_nonuniform_control_flow(c)) {
2270 struct qinst *exec_flag = vir_MOV_dest(c, vir_nop_reg(),
2271 c->execute);
2272 if (cond == V3D_QPU_COND_IFA) {
2273 vir_set_uf(exec_flag, V3D_QPU_UF_ANDZ);
2274 } else {
2275 vir_set_uf(exec_flag, V3D_QPU_UF_NORNZ);
2276 cond = V3D_QPU_COND_IFA;
2277 }
2278 }
2279
2280 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
2281 vir_uniform_ui(c, 0)), cond);
2282
2283 break;
2284 }
2285
2286 case nir_intrinsic_memory_barrier:
2287 case nir_intrinsic_memory_barrier_buffer:
2288 case nir_intrinsic_memory_barrier_image:
2289 case nir_intrinsic_memory_barrier_shared:
2290 case nir_intrinsic_memory_barrier_tcs_patch:
2291 case nir_intrinsic_group_memory_barrier:
2292 /* We don't do any instruction scheduling of these NIR
2293 * instructions between each other, so we just need to make
2294 * sure that the TMU operations before the barrier are flushed
2295 * before the ones after the barrier. That is currently
2296 * handled by having a THRSW in each of them and a LDTMU
2297 * series or a TMUWT after.
2298 */
2299 break;
2300
2301 case nir_intrinsic_control_barrier:
2302 /* Emit a TSY op to get all invocations in the workgroup
2303 * (actually supergroup) to block until the last invocation
2304 * reaches the TSY op.
2305 */
2306 if (c->devinfo->ver >= 42) {
2307 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
2308 V3D_QPU_WADDR_SYNCB));
2309 } else {
2310 struct qinst *sync =
2311 vir_BARRIERID_dest(c,
2312 vir_reg(QFILE_MAGIC,
2313 V3D_QPU_WADDR_SYNCU));
2314 sync->uniform =
2315 vir_get_uniform_index(c, QUNIFORM_CONSTANT,
2316 0xffffff00 |
2317 V3D_TSY_WAIT_INC_CHECK);
2318
2319 }
2320
2321 /* The blocking of a TSY op only happens at the next thread
2322 * switch. No texturing may be outstanding at the time of a
2323 * TSY blocking operation.
2324 */
2325 vir_emit_thrsw(c);
2326 break;
2327
2328 case nir_intrinsic_load_num_work_groups:
2329 for (int i = 0; i < 3; i++) {
2330 ntq_store_dest(c, &instr->dest, i,
2331 vir_uniform(c, QUNIFORM_NUM_WORK_GROUPS,
2332 i));
2333 }
2334 break;
2335
2336 case nir_intrinsic_load_local_invocation_index:
2337 ntq_store_dest(c, &instr->dest, 0,
2338 vir_SHR(c, c->cs_payload[1],
2339 vir_uniform_ui(c, 32 - c->local_invocation_index_bits)));
2340 break;
2341
2342 case nir_intrinsic_load_work_group_id:
2343 ntq_store_dest(c, &instr->dest, 0,
2344 vir_AND(c, c->cs_payload[0],
2345 vir_uniform_ui(c, 0xffff)));
2346 ntq_store_dest(c, &instr->dest, 1,
2347 vir_SHR(c, c->cs_payload[0],
2348 vir_uniform_ui(c, 16)));
2349 ntq_store_dest(c, &instr->dest, 2,
2350 vir_AND(c, c->cs_payload[1],
2351 vir_uniform_ui(c, 0xffff)));
2352 break;
2353
2354 case nir_intrinsic_load_subgroup_id:
2355 ntq_store_dest(c, &instr->dest, 0, vir_EIDX(c));
2356 break;
2357
2358 case nir_intrinsic_load_per_vertex_input: {
2359 /* col: vertex index, row = varying index */
2360 struct qreg col = ntq_get_src(c, instr->src[0], 0);
2361 uint32_t row_idx = nir_intrinsic_base(instr) * 4 +
2362 nir_intrinsic_component(instr);
2363 for (int i = 0; i < instr->num_components; i++) {
2364 struct qreg row = vir_uniform_ui(c, row_idx++);
2365 ntq_store_dest(c, &instr->dest, i,
2366 vir_LDVPMG_IN(c, row, col));
2367 }
2368 break;
2369 }
2370
2371 case nir_intrinsic_emit_vertex:
2372 case nir_intrinsic_end_primitive:
2373 unreachable("Should have been lowered in v3d_nir_lower_io");
2374 break;
2375
2376 case nir_intrinsic_load_primitive_id: {
2377 /* gl_PrimitiveIdIn is written by the GBG in the first word of
2378 * VPM output header. According to docs, we should read this
2379 * using ldvpm(v,d)_in (See Table 71).
2380 */
2381 ntq_store_dest(c, &instr->dest, 0,
2382 vir_LDVPMV_IN(c, vir_uniform_ui(c, 0)));
2383 break;
2384 }
2385
2386 case nir_intrinsic_load_invocation_id:
2387 ntq_store_dest(c, &instr->dest, 0, vir_IID(c));
2388 break;
2389
2390 case nir_intrinsic_load_fb_layers_v3d:
2391 ntq_store_dest(c, &instr->dest, 0,
2392 vir_uniform(c, QUNIFORM_FB_LAYERS, 0));
2393 break;
2394
2395 default:
2396 fprintf(stderr, "Unknown intrinsic: ");
2397 nir_print_instr(&instr->instr, stderr);
2398 fprintf(stderr, "\n");
2399 break;
2400 }
2401 }
2402
2403 /* Clears (activates) the execute flags for any channels whose jump target
2404 * matches this block.
2405 *
2406 * XXX perf: Could we be using flpush/flpop somehow for our execution channel
2407 * enabling?
2408 *
2409 * XXX perf: For uniform control flow, we should be able to skip c->execute
2410 * handling entirely.
2411 */
2412 static void
2413 ntq_activate_execute_for_block(struct v3d_compile *c)
2414 {
2415 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
2416 c->execute, vir_uniform_ui(c, c->cur_block->index)),
2417 V3D_QPU_PF_PUSHZ);
2418
2419 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2420 }
2421
2422 static void
2423 ntq_emit_uniform_if(struct v3d_compile *c, nir_if *if_stmt)
2424 {
2425 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2426 bool empty_else_block =
2427 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2428 exec_list_is_empty(&nir_else_block->instr_list));
2429
2430 struct qblock *then_block = vir_new_block(c);
2431 struct qblock *after_block = vir_new_block(c);
2432 struct qblock *else_block;
2433 if (empty_else_block)
2434 else_block = after_block;
2435 else
2436 else_block = vir_new_block(c);
2437
2438 /* Set up the flags for the IF condition (taking the THEN branch). */
2439 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
2440
2441 /* Jump to ELSE. */
2442 vir_BRANCH(c, cond == V3D_QPU_COND_IFA ?
2443 V3D_QPU_BRANCH_COND_ALLNA :
2444 V3D_QPU_BRANCH_COND_ALLA);
2445 vir_link_blocks(c->cur_block, else_block);
2446 vir_link_blocks(c->cur_block, then_block);
2447
2448 /* Process the THEN block. */
2449 vir_set_emit_block(c, then_block);
2450 ntq_emit_cf_list(c, &if_stmt->then_list);
2451
2452 if (!empty_else_block) {
2453 /* At the end of the THEN block, jump to ENDIF */
2454 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALWAYS);
2455 vir_link_blocks(c->cur_block, after_block);
2456
2457 /* Emit the else block. */
2458 vir_set_emit_block(c, else_block);
2459 ntq_emit_cf_list(c, &if_stmt->else_list);
2460 }
2461
2462 vir_link_blocks(c->cur_block, after_block);
2463
2464 vir_set_emit_block(c, after_block);
2465 }
2466
2467 static void
2468 ntq_emit_nonuniform_if(struct v3d_compile *c, nir_if *if_stmt)
2469 {
2470 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2471 bool empty_else_block =
2472 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2473 exec_list_is_empty(&nir_else_block->instr_list));
2474
2475 struct qblock *then_block = vir_new_block(c);
2476 struct qblock *after_block = vir_new_block(c);
2477 struct qblock *else_block;
2478 if (empty_else_block)
2479 else_block = after_block;
2480 else
2481 else_block = vir_new_block(c);
2482
2483 bool was_uniform_control_flow = false;
2484 if (!vir_in_nonuniform_control_flow(c)) {
2485 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2486 was_uniform_control_flow = true;
2487 }
2488
2489 /* Set up the flags for the IF condition (taking the THEN branch). */
2490 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
2491
2492 /* Update the flags+cond to mean "Taking the ELSE branch (!cond) and
2493 * was previously active (execute Z) for updating the exec flags.
2494 */
2495 if (was_uniform_control_flow) {
2496 cond = v3d_qpu_cond_invert(cond);
2497 } else {
2498 struct qinst *inst = vir_MOV_dest(c, vir_nop_reg(), c->execute);
2499 if (cond == V3D_QPU_COND_IFA) {
2500 vir_set_uf(inst, V3D_QPU_UF_NORNZ);
2501 } else {
2502 vir_set_uf(inst, V3D_QPU_UF_ANDZ);
2503 cond = V3D_QPU_COND_IFA;
2504 }
2505 }
2506
2507 vir_MOV_cond(c, cond,
2508 c->execute,
2509 vir_uniform_ui(c, else_block->index));
2510
2511 /* Jump to ELSE if nothing is active for THEN, otherwise fall
2512 * through.
2513 */
2514 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ);
2515 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
2516 vir_link_blocks(c->cur_block, else_block);
2517 vir_link_blocks(c->cur_block, then_block);
2518
2519 /* Process the THEN block. */
2520 vir_set_emit_block(c, then_block);
2521 ntq_emit_cf_list(c, &if_stmt->then_list);
2522
2523 if (!empty_else_block) {
2524 /* Handle the end of the THEN block. First, all currently
2525 * active channels update their execute flags to point to
2526 * ENDIF
2527 */
2528 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2529 V3D_QPU_PF_PUSHZ);
2530 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2531 vir_uniform_ui(c, after_block->index));
2532
2533 /* If everything points at ENDIF, then jump there immediately. */
2534 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
2535 c->execute,
2536 vir_uniform_ui(c, after_block->index)),
2537 V3D_QPU_PF_PUSHZ);
2538 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
2539 vir_link_blocks(c->cur_block, after_block);
2540 vir_link_blocks(c->cur_block, else_block);
2541
2542 vir_set_emit_block(c, else_block);
2543 ntq_activate_execute_for_block(c);
2544 ntq_emit_cf_list(c, &if_stmt->else_list);
2545 }
2546
2547 vir_link_blocks(c->cur_block, after_block);
2548
2549 vir_set_emit_block(c, after_block);
2550 if (was_uniform_control_flow)
2551 c->execute = c->undef;
2552 else
2553 ntq_activate_execute_for_block(c);
2554 }
2555
2556 static void
2557 ntq_emit_if(struct v3d_compile *c, nir_if *nif)
2558 {
2559 bool was_in_control_flow = c->in_control_flow;
2560 c->in_control_flow = true;
2561 if (!vir_in_nonuniform_control_flow(c) &&
2562 nir_src_is_dynamically_uniform(nif->condition)) {
2563 ntq_emit_uniform_if(c, nif);
2564 } else {
2565 ntq_emit_nonuniform_if(c, nif);
2566 }
2567 c->in_control_flow = was_in_control_flow;
2568 }
2569
2570 static void
2571 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
2572 {
2573 switch (jump->type) {
2574 case nir_jump_break:
2575 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2576 V3D_QPU_PF_PUSHZ);
2577 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2578 vir_uniform_ui(c, c->loop_break_block->index));
2579 break;
2580
2581 case nir_jump_continue:
2582 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2583 V3D_QPU_PF_PUSHZ);
2584 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2585 vir_uniform_ui(c, c->loop_cont_block->index));
2586 break;
2587
2588 case nir_jump_return:
2589 unreachable("All returns shouold be lowered\n");
2590 break;
2591
2592 case nir_jump_goto:
2593 case nir_jump_goto_if:
2594 unreachable("not supported\n");
2595 break;
2596 }
2597 }
2598
2599 static void
2600 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
2601 {
2602 switch (instr->type) {
2603 case nir_instr_type_alu:
2604 ntq_emit_alu(c, nir_instr_as_alu(instr));
2605 break;
2606
2607 case nir_instr_type_intrinsic:
2608 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
2609 break;
2610
2611 case nir_instr_type_load_const:
2612 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
2613 break;
2614
2615 case nir_instr_type_ssa_undef:
2616 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
2617 break;
2618
2619 case nir_instr_type_tex:
2620 ntq_emit_tex(c, nir_instr_as_tex(instr));
2621 break;
2622
2623 case nir_instr_type_jump:
2624 ntq_emit_jump(c, nir_instr_as_jump(instr));
2625 break;
2626
2627 default:
2628 fprintf(stderr, "Unknown NIR instr type: ");
2629 nir_print_instr(instr, stderr);
2630 fprintf(stderr, "\n");
2631 abort();
2632 }
2633 }
2634
2635 static void
2636 ntq_emit_block(struct v3d_compile *c, nir_block *block)
2637 {
2638 nir_foreach_instr(instr, block) {
2639 ntq_emit_instr(c, instr);
2640 }
2641 }
2642
2643 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
2644
2645 static void
2646 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
2647 {
2648 bool was_in_control_flow = c->in_control_flow;
2649 c->in_control_flow = true;
2650
2651 bool was_uniform_control_flow = false;
2652 if (!vir_in_nonuniform_control_flow(c)) {
2653 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2654 was_uniform_control_flow = true;
2655 }
2656
2657 struct qblock *save_loop_cont_block = c->loop_cont_block;
2658 struct qblock *save_loop_break_block = c->loop_break_block;
2659
2660 c->loop_cont_block = vir_new_block(c);
2661 c->loop_break_block = vir_new_block(c);
2662
2663 vir_link_blocks(c->cur_block, c->loop_cont_block);
2664 vir_set_emit_block(c, c->loop_cont_block);
2665 ntq_activate_execute_for_block(c);
2666
2667 ntq_emit_cf_list(c, &loop->body);
2668
2669 /* Re-enable any previous continues now, so our ANYA check below
2670 * works.
2671 *
2672 * XXX: Use the .ORZ flags update, instead.
2673 */
2674 vir_set_pf(vir_XOR_dest(c,
2675 vir_nop_reg(),
2676 c->execute,
2677 vir_uniform_ui(c, c->loop_cont_block->index)),
2678 V3D_QPU_PF_PUSHZ);
2679 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2680
2681 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ);
2682
2683 struct qinst *branch = vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
2684 /* Pixels that were not dispatched or have been discarded should not
2685 * contribute to looping again.
2686 */
2687 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P;
2688 vir_link_blocks(c->cur_block, c->loop_cont_block);
2689 vir_link_blocks(c->cur_block, c->loop_break_block);
2690
2691 vir_set_emit_block(c, c->loop_break_block);
2692 if (was_uniform_control_flow)
2693 c->execute = c->undef;
2694 else
2695 ntq_activate_execute_for_block(c);
2696
2697 c->loop_break_block = save_loop_break_block;
2698 c->loop_cont_block = save_loop_cont_block;
2699
2700 c->loops++;
2701
2702 c->in_control_flow = was_in_control_flow;
2703 }
2704
2705 static void
2706 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
2707 {
2708 fprintf(stderr, "FUNCTIONS not handled.\n");
2709 abort();
2710 }
2711
2712 static void
2713 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
2714 {
2715 foreach_list_typed(nir_cf_node, node, node, list) {
2716 switch (node->type) {
2717 case nir_cf_node_block:
2718 ntq_emit_block(c, nir_cf_node_as_block(node));
2719 break;
2720
2721 case nir_cf_node_if:
2722 ntq_emit_if(c, nir_cf_node_as_if(node));
2723 break;
2724
2725 case nir_cf_node_loop:
2726 ntq_emit_loop(c, nir_cf_node_as_loop(node));
2727 break;
2728
2729 case nir_cf_node_function:
2730 ntq_emit_function(c, nir_cf_node_as_function(node));
2731 break;
2732
2733 default:
2734 fprintf(stderr, "Unknown NIR node type\n");
2735 abort();
2736 }
2737 }
2738 }
2739
2740 static void
2741 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
2742 {
2743 ntq_setup_registers(c, &impl->registers);
2744 ntq_emit_cf_list(c, &impl->body);
2745 }
2746
2747 static void
2748 nir_to_vir(struct v3d_compile *c)
2749 {
2750 switch (c->s->info.stage) {
2751 case MESA_SHADER_FRAGMENT:
2752 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
2753 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
2754 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
2755
2756 /* V3D 4.x can disable implicit point coordinate varyings if
2757 * they are not used.
2758 */
2759 if (c->fs_key->is_points &&
2760 (c->devinfo->ver < 40 || program_reads_point_coord(c))) {
2761 c->point_x = emit_fragment_varying(c, NULL, 0, 0);
2762 c->point_y = emit_fragment_varying(c, NULL, 0, 0);
2763 c->uses_implicit_point_line_varyings = true;
2764 } else if (c->fs_key->is_lines &&
2765 (c->devinfo->ver < 40 ||
2766 (c->s->info.system_values_read &
2767 BITFIELD64_BIT(SYSTEM_VALUE_LINE_COORD)))) {
2768 c->line_x = emit_fragment_varying(c, NULL, 0, 0);
2769 c->uses_implicit_point_line_varyings = true;
2770 }
2771 break;
2772 case MESA_SHADER_COMPUTE:
2773 /* Set up the TSO for barriers, assuming we do some. */
2774 if (c->devinfo->ver < 42) {
2775 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
2776 V3D_QPU_WADDR_SYNC));
2777 }
2778
2779 c->cs_payload[0] = vir_MOV(c, vir_reg(QFILE_REG, 0));
2780 c->cs_payload[1] = vir_MOV(c, vir_reg(QFILE_REG, 2));
2781
2782 /* Set up the division between gl_LocalInvocationIndex and
2783 * wg_in_mem in the payload reg.
2784 */
2785 int wg_size = (c->s->info.cs.local_size[0] *
2786 c->s->info.cs.local_size[1] *
2787 c->s->info.cs.local_size[2]);
2788 c->local_invocation_index_bits =
2789 ffs(util_next_power_of_two(MAX2(wg_size, 64))) - 1;
2790 assert(c->local_invocation_index_bits <= 8);
2791
2792 if (c->s->info.cs.shared_size) {
2793 struct qreg wg_in_mem = vir_SHR(c, c->cs_payload[1],
2794 vir_uniform_ui(c, 16));
2795 if (c->s->info.cs.local_size[0] != 1 ||
2796 c->s->info.cs.local_size[1] != 1 ||
2797 c->s->info.cs.local_size[2] != 1) {
2798 int wg_bits = (16 -
2799 c->local_invocation_index_bits);
2800 int wg_mask = (1 << wg_bits) - 1;
2801 wg_in_mem = vir_AND(c, wg_in_mem,
2802 vir_uniform_ui(c, wg_mask));
2803 }
2804 struct qreg shared_per_wg =
2805 vir_uniform_ui(c, c->s->info.cs.shared_size);
2806
2807 c->cs_shared_offset =
2808 vir_ADD(c,
2809 vir_uniform(c, QUNIFORM_SHARED_OFFSET,0),
2810 vir_UMUL(c, wg_in_mem, shared_per_wg));
2811 }
2812 break;
2813 default:
2814 break;
2815 }
2816
2817 if (c->s->scratch_size) {
2818 v3d_setup_spill_base(c);
2819 c->spill_size += V3D_CHANNELS * c->s->scratch_size;
2820 }
2821
2822 switch (c->s->info.stage) {
2823 case MESA_SHADER_VERTEX:
2824 ntq_setup_vs_inputs(c);
2825 break;
2826 case MESA_SHADER_GEOMETRY:
2827 ntq_setup_gs_inputs(c);
2828 break;
2829 case MESA_SHADER_FRAGMENT:
2830 ntq_setup_fs_inputs(c);
2831 break;
2832 case MESA_SHADER_COMPUTE:
2833 break;
2834 default:
2835 unreachable("unsupported shader stage");
2836 }
2837
2838 ntq_setup_outputs(c);
2839
2840 /* Find the main function and emit the body. */
2841 nir_foreach_function(function, c->s) {
2842 assert(strcmp(function->name, "main") == 0);
2843 assert(function->impl);
2844 ntq_emit_impl(c, function->impl);
2845 }
2846 }
2847
2848 const nir_shader_compiler_options v3d_nir_options = {
2849 .lower_all_io_to_temps = true,
2850 .lower_extract_byte = true,
2851 .lower_extract_word = true,
2852 .lower_bitfield_insert_to_shifts = true,
2853 .lower_bitfield_extract_to_shifts = true,
2854 .lower_bitfield_reverse = true,
2855 .lower_bit_count = true,
2856 .lower_cs_local_id_from_index = true,
2857 .lower_ffract = true,
2858 .lower_fmod = true,
2859 .lower_pack_unorm_2x16 = true,
2860 .lower_pack_snorm_2x16 = true,
2861 .lower_pack_unorm_4x8 = true,
2862 .lower_pack_snorm_4x8 = true,
2863 .lower_unpack_unorm_4x8 = true,
2864 .lower_unpack_snorm_4x8 = true,
2865 .lower_pack_half_2x16 = true,
2866 .lower_unpack_half_2x16 = true,
2867 .lower_fdiv = true,
2868 .lower_find_lsb = true,
2869 .lower_ffma = true,
2870 .lower_flrp32 = true,
2871 .lower_fpow = true,
2872 .lower_fsat = true,
2873 .lower_fsqrt = true,
2874 .lower_ifind_msb = true,
2875 .lower_isign = true,
2876 .lower_ldexp = true,
2877 .lower_mul_high = true,
2878 .lower_wpos_pntc = true,
2879 .lower_rotate = true,
2880 .lower_to_scalar = true,
2881 };
2882
2883 /**
2884 * When demoting a shader down to single-threaded, removes the THRSW
2885 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
2886 * program end).
2887 */
2888 static void
2889 vir_remove_thrsw(struct v3d_compile *c)
2890 {
2891 vir_for_each_block(block, c) {
2892 vir_for_each_inst_safe(inst, block) {
2893 if (inst->qpu.sig.thrsw)
2894 vir_remove_instruction(c, inst);
2895 }
2896 }
2897
2898 c->last_thrsw = NULL;
2899 }
2900
2901 void
2902 vir_emit_last_thrsw(struct v3d_compile *c)
2903 {
2904 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
2905 * switching, so disable threads if we didn't do any TMU ops (each of
2906 * which would have emitted a THRSW).
2907 */
2908 if (!c->last_thrsw_at_top_level && c->devinfo->ver < 41) {
2909 c->threads = 1;
2910 if (c->last_thrsw)
2911 vir_remove_thrsw(c);
2912 return;
2913 }
2914
2915 /* If we're threaded and the last THRSW was in conditional code, then
2916 * we need to emit another one so that we can flag it as the last
2917 * thrsw.
2918 */
2919 if (c->last_thrsw && !c->last_thrsw_at_top_level) {
2920 assert(c->devinfo->ver >= 41);
2921 vir_emit_thrsw(c);
2922 }
2923
2924 /* If we're threaded, then we need to mark the last THRSW instruction
2925 * so we can emit a pair of them at QPU emit time.
2926 *
2927 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2928 * post-last-THRSW state, so we can skip this.
2929 */
2930 if (!c->last_thrsw && c->s->info.stage == MESA_SHADER_FRAGMENT) {
2931 assert(c->devinfo->ver >= 41);
2932 vir_emit_thrsw(c);
2933 }
2934
2935 if (c->last_thrsw)
2936 c->last_thrsw->is_last_thrsw = true;
2937 }
2938
2939 /* There's a flag in the shader for "center W is needed for reasons other than
2940 * non-centroid varyings", so we just walk the program after VIR optimization
2941 * to see if it's used. It should be harmless to set even if we only use
2942 * center W for varyings.
2943 */
2944 static void
2945 vir_check_payload_w(struct v3d_compile *c)
2946 {
2947 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
2948 return;
2949
2950 vir_for_each_inst_inorder(inst, c) {
2951 for (int i = 0; i < vir_get_nsrc(inst); i++) {
2952 if (inst->src[i].file == QFILE_REG &&
2953 inst->src[i].index == 0) {
2954 c->uses_center_w = true;
2955 return;
2956 }
2957 }
2958 }
2959
2960 }
2961
2962 void
2963 v3d_nir_to_vir(struct v3d_compile *c)
2964 {
2965 if (V3D_DEBUG & (V3D_DEBUG_NIR |
2966 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2967 fprintf(stderr, "%s prog %d/%d NIR:\n",
2968 vir_get_stage_name(c),
2969 c->program_id, c->variant_id);
2970 nir_print_shader(c->s, stderr);
2971 }
2972
2973 nir_to_vir(c);
2974
2975 /* Emit the last THRSW before STVPM and TLB writes. */
2976 vir_emit_last_thrsw(c);
2977
2978 switch (c->s->info.stage) {
2979 case MESA_SHADER_FRAGMENT:
2980 emit_frag_end(c);
2981 break;
2982 case MESA_SHADER_GEOMETRY:
2983 emit_geom_end(c);
2984 break;
2985 case MESA_SHADER_VERTEX:
2986 emit_vert_end(c);
2987 break;
2988 case MESA_SHADER_COMPUTE:
2989 break;
2990 default:
2991 unreachable("bad stage");
2992 }
2993
2994 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2995 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2996 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
2997 vir_get_stage_name(c),
2998 c->program_id, c->variant_id);
2999 vir_dump(c);
3000 fprintf(stderr, "\n");
3001 }
3002
3003 vir_optimize(c);
3004
3005 vir_check_payload_w(c);
3006
3007 /* XXX perf: On VC4, we do a VIR-level instruction scheduling here.
3008 * We used that on that platform to pipeline TMU writes and reduce the
3009 * number of thread switches, as well as try (mostly successfully) to
3010 * reduce maximum register pressure to allow more threads. We should
3011 * do something of that sort for V3D -- either instruction scheduling
3012 * here, or delay the the THRSW and LDTMUs from our texture
3013 * instructions until the results are needed.
3014 */
3015
3016 if (V3D_DEBUG & (V3D_DEBUG_VIR |
3017 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
3018 fprintf(stderr, "%s prog %d/%d VIR:\n",
3019 vir_get_stage_name(c),
3020 c->program_id, c->variant_id);
3021 vir_dump(c);
3022 fprintf(stderr, "\n");
3023 }
3024
3025 /* Attempt to allocate registers for the temporaries. If we fail,
3026 * reduce thread count and try again.
3027 */
3028 int min_threads = (c->devinfo->ver >= 41) ? 2 : 1;
3029 struct qpu_reg *temp_registers;
3030 while (true) {
3031 bool spilled;
3032 temp_registers = v3d_register_allocate(c, &spilled);
3033 if (spilled)
3034 continue;
3035
3036 if (temp_registers)
3037 break;
3038
3039 if (c->threads == min_threads) {
3040 if (c->fallback_scheduler) {
3041 fprintf(stderr,
3042 "Failed to register allocate at %d "
3043 "threads:\n",
3044 c->threads);
3045