2 * Copyright © 2016 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "util/format/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
35 /* We don't do any address packing. */
36 #define __gen_user_data void
37 #define __gen_address_type uint32_t
38 #define __gen_address_offset(reloc) (*reloc)
39 #define __gen_emit_reloc(cl, reloc)
40 #include "cle/v3d_packet_v41_pack.h"
42 #define GENERAL_TMU_LOOKUP_PER_QUAD (0 << 7)
43 #define GENERAL_TMU_LOOKUP_PER_PIXEL (1 << 7)
44 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_I (0 << 0)
45 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_I (1 << 0)
46 #define GENERAL_TMU_LOOKUP_TYPE_VEC2 (2 << 0)
47 #define GENERAL_TMU_LOOKUP_TYPE_VEC3 (3 << 0)
48 #define GENERAL_TMU_LOOKUP_TYPE_VEC4 (4 << 0)
49 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_UI (5 << 0)
50 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_UI (6 << 0)
51 #define GENERAL_TMU_LOOKUP_TYPE_32BIT_UI (7 << 0)
53 #define V3D_TSY_SET_QUORUM 0
54 #define V3D_TSY_INC_WAITERS 1
55 #define V3D_TSY_DEC_WAITERS 2
56 #define V3D_TSY_INC_QUORUM 3
57 #define V3D_TSY_DEC_QUORUM 4
58 #define V3D_TSY_FREE_ALL 5
59 #define V3D_TSY_RELEASE 6
60 #define V3D_TSY_ACQUIRE 7
61 #define V3D_TSY_WAIT 8
62 #define V3D_TSY_WAIT_INC 9
63 #define V3D_TSY_WAIT_CHECK 10
64 #define V3D_TSY_WAIT_INC_CHECK 11
65 #define V3D_TSY_WAIT_CV 12
66 #define V3D_TSY_INC_SEMAPHORE 13
67 #define V3D_TSY_DEC_SEMAPHORE 14
68 #define V3D_TSY_SET_QUORUM_FREE_ALL 15
71 ntq_emit_cf_list(struct v3d_compile
*c
, struct exec_list
*list
);
74 resize_qreg_array(struct v3d_compile
*c
,
79 if (*size
>= decl_size
)
82 uint32_t old_size
= *size
;
83 *size
= MAX2(*size
* 2, decl_size
);
84 *regs
= reralloc(c
, *regs
, struct qreg
, *size
);
86 fprintf(stderr
, "Malloc failure\n");
90 for (uint32_t i
= old_size
; i
< *size
; i
++)
91 (*regs
)[i
] = c
->undef
;
95 vir_emit_thrsw(struct v3d_compile
*c
)
100 /* Always thread switch after each texture operation for now.
102 * We could do better by batching a bunch of texture fetches up and
103 * then doing one thread switch and collecting all their results
106 c
->last_thrsw
= vir_NOP(c
);
107 c
->last_thrsw
->qpu
.sig
.thrsw
= true;
108 c
->last_thrsw_at_top_level
= !c
->in_control_flow
;
110 /* We need to lock the scoreboard before any tlb acess happens. If this
111 * thread switch comes after we have emitted a tlb load, then it means
112 * that we can't lock on the last thread switch any more.
114 if (c
->emitted_tlb_load
)
115 c
->lock_scoreboard_on_first_thrsw
= true;
119 v3d_get_op_for_atomic_add(nir_intrinsic_instr
*instr
, unsigned src
)
121 if (nir_src_is_const(instr
->src
[src
])) {
122 int64_t add_val
= nir_src_as_int(instr
->src
[src
]);
124 return V3D_TMU_OP_WRITE_AND_READ_INC
;
125 else if (add_val
== -1)
126 return V3D_TMU_OP_WRITE_OR_READ_DEC
;
129 return V3D_TMU_OP_WRITE_ADD_READ_PREFETCH
;
133 v3d_general_tmu_op(nir_intrinsic_instr
*instr
)
135 switch (instr
->intrinsic
) {
136 case nir_intrinsic_load_ssbo
:
137 case nir_intrinsic_load_ubo
:
138 case nir_intrinsic_load_uniform
:
139 case nir_intrinsic_load_shared
:
140 case nir_intrinsic_load_scratch
:
141 case nir_intrinsic_store_ssbo
:
142 case nir_intrinsic_store_shared
:
143 case nir_intrinsic_store_scratch
:
144 return V3D_TMU_OP_REGULAR
;
145 case nir_intrinsic_ssbo_atomic_add
:
146 return v3d_get_op_for_atomic_add(instr
, 2);
147 case nir_intrinsic_shared_atomic_add
:
148 return v3d_get_op_for_atomic_add(instr
, 1);
149 case nir_intrinsic_ssbo_atomic_imin
:
150 case nir_intrinsic_shared_atomic_imin
:
151 return V3D_TMU_OP_WRITE_SMIN
;
152 case nir_intrinsic_ssbo_atomic_umin
:
153 case nir_intrinsic_shared_atomic_umin
:
154 return V3D_TMU_OP_WRITE_UMIN_FULL_L1_CLEAR
;
155 case nir_intrinsic_ssbo_atomic_imax
:
156 case nir_intrinsic_shared_atomic_imax
:
157 return V3D_TMU_OP_WRITE_SMAX
;
158 case nir_intrinsic_ssbo_atomic_umax
:
159 case nir_intrinsic_shared_atomic_umax
:
160 return V3D_TMU_OP_WRITE_UMAX
;
161 case nir_intrinsic_ssbo_atomic_and
:
162 case nir_intrinsic_shared_atomic_and
:
163 return V3D_TMU_OP_WRITE_AND_READ_INC
;
164 case nir_intrinsic_ssbo_atomic_or
:
165 case nir_intrinsic_shared_atomic_or
:
166 return V3D_TMU_OP_WRITE_OR_READ_DEC
;
167 case nir_intrinsic_ssbo_atomic_xor
:
168 case nir_intrinsic_shared_atomic_xor
:
169 return V3D_TMU_OP_WRITE_XOR_READ_NOT
;
170 case nir_intrinsic_ssbo_atomic_exchange
:
171 case nir_intrinsic_shared_atomic_exchange
:
172 return V3D_TMU_OP_WRITE_XCHG_READ_FLUSH
;
173 case nir_intrinsic_ssbo_atomic_comp_swap
:
174 case nir_intrinsic_shared_atomic_comp_swap
:
175 return V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH
;
177 unreachable("unknown intrinsic op");
182 * Implements indirect uniform loads and SSBO accesses through the TMU general
183 * memory access interface.
186 ntq_emit_tmu_general(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
,
187 bool is_shared_or_scratch
)
189 uint32_t tmu_op
= v3d_general_tmu_op(instr
);
191 /* If we were able to replace atomic_add for an inc/dec, then we
192 * need/can to do things slightly different, like not loading the
193 * amount to add/sub, as that is implicit.
195 bool atomic_add_replaced
=
196 ((instr
->intrinsic
== nir_intrinsic_ssbo_atomic_add
||
197 instr
->intrinsic
== nir_intrinsic_shared_atomic_add
) &&
198 (tmu_op
== V3D_TMU_OP_WRITE_AND_READ_INC
||
199 tmu_op
== V3D_TMU_OP_WRITE_OR_READ_DEC
));
201 bool is_store
= (instr
->intrinsic
== nir_intrinsic_store_ssbo
||
202 instr
->intrinsic
== nir_intrinsic_store_scratch
||
203 instr
->intrinsic
== nir_intrinsic_store_shared
);
205 bool is_load
= (instr
->intrinsic
== nir_intrinsic_load_uniform
||
206 instr
->intrinsic
== nir_intrinsic_load_ubo
||
207 instr
->intrinsic
== nir_intrinsic_load_ssbo
||
208 instr
->intrinsic
== nir_intrinsic_load_scratch
||
209 instr
->intrinsic
== nir_intrinsic_load_shared
);
212 c
->tmu_dirty_rcl
= true;
214 bool has_index
= !is_shared_or_scratch
;
217 if (instr
->intrinsic
== nir_intrinsic_load_uniform
) {
219 } else if (instr
->intrinsic
== nir_intrinsic_load_ssbo
||
220 instr
->intrinsic
== nir_intrinsic_load_ubo
||
221 instr
->intrinsic
== nir_intrinsic_load_scratch
||
222 instr
->intrinsic
== nir_intrinsic_load_shared
||
223 atomic_add_replaced
) {
224 offset_src
= 0 + has_index
;
225 } else if (is_store
) {
226 offset_src
= 1 + has_index
;
228 offset_src
= 0 + has_index
;
231 bool dynamic_src
= !nir_src_is_const(instr
->src
[offset_src
]);
232 uint32_t const_offset
= 0;
234 const_offset
= nir_src_as_uint(instr
->src
[offset_src
]);
236 struct qreg base_offset
;
237 if (instr
->intrinsic
== nir_intrinsic_load_uniform
) {
238 const_offset
+= nir_intrinsic_base(instr
);
239 base_offset
= vir_uniform(c
, QUNIFORM_UBO_ADDR
,
240 v3d_unit_data_create(0, const_offset
));
242 } else if (instr
->intrinsic
== nir_intrinsic_load_ubo
) {
243 uint32_t index
= nir_src_as_uint(instr
->src
[0]) + 1;
244 /* Note that QUNIFORM_UBO_ADDR takes a UBO index shifted up by
245 * 1 (0 is gallium's constant buffer 0).
248 vir_uniform(c
, QUNIFORM_UBO_ADDR
,
249 v3d_unit_data_create(index
, const_offset
));
251 } else if (is_shared_or_scratch
) {
252 /* Shared and scratch variables have no buffer index, and all
253 * start from a common base that we set up at the start of
256 if (instr
->intrinsic
== nir_intrinsic_load_scratch
||
257 instr
->intrinsic
== nir_intrinsic_store_scratch
) {
258 base_offset
= c
->spill_base
;
260 base_offset
= c
->cs_shared_offset
;
261 const_offset
+= nir_intrinsic_base(instr
);
264 base_offset
= vir_uniform(c
, QUNIFORM_SSBO_OFFSET
,
265 nir_src_as_uint(instr
->src
[is_store
?
269 struct qreg tmud
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_TMUD
);
270 unsigned writemask
= is_store
? nir_intrinsic_write_mask(instr
) : 0;
271 uint32_t base_const_offset
= const_offset
;
272 int first_component
= -1;
273 int last_component
= -1;
275 int tmu_writes
= 1; /* address */
278 /* Find the first set of consecutive components that
279 * are enabled in the writemask and emit the TMUD
280 * instructions for them.
282 first_component
= ffs(writemask
) - 1;
283 last_component
= first_component
;
284 while (writemask
& BITFIELD_BIT(last_component
+ 1))
287 assert(first_component
>= 0 &&
288 first_component
<= last_component
&&
289 last_component
< instr
->num_components
);
291 struct qreg tmud
= vir_reg(QFILE_MAGIC
,
293 for (int i
= first_component
; i
<= last_component
; i
++) {
295 ntq_get_src(c
, instr
->src
[0], i
);
296 vir_MOV_dest(c
, tmud
, data
);
300 /* Update the offset for the TMU write based on the
301 * the first component we are writing.
303 const_offset
= base_const_offset
+ first_component
* 4;
305 /* Clear these components from the writemask */
306 uint32_t written_mask
=
307 BITFIELD_RANGE(first_component
, tmu_writes
- 1);
308 writemask
&= ~written_mask
;
309 } else if (!is_load
&& !atomic_add_replaced
) {
311 ntq_get_src(c
, instr
->src
[1 + has_index
], 0);
312 vir_MOV_dest(c
, tmud
, data
);
314 if (tmu_op
== V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH
) {
315 data
= ntq_get_src(c
, instr
->src
[2 + has_index
],
317 vir_MOV_dest(c
, tmud
, data
);
322 /* Make sure we won't exceed the 16-entry TMU fifo if each
323 * thread is storing at the same time.
325 while (tmu_writes
> 16 / c
->threads
)
328 /* The spec says that for atomics, the TYPE field is ignored,
329 * but that doesn't seem to be the case for CMPXCHG. Just use
330 * the number of tmud writes we did to decide the type (or
331 * choose "32bit" for atomic reads, which has been fine).
333 uint32_t num_components
;
334 if (is_load
|| atomic_add_replaced
) {
335 num_components
= instr
->num_components
;
337 assert(tmu_writes
> 1);
338 num_components
= tmu_writes
- 1;
341 uint32_t config
= (0xffffff00 |
343 GENERAL_TMU_LOOKUP_PER_PIXEL
);
344 if (num_components
== 1) {
345 config
|= GENERAL_TMU_LOOKUP_TYPE_32BIT_UI
;
347 config
|= GENERAL_TMU_LOOKUP_TYPE_VEC2
+
351 if (vir_in_nonuniform_control_flow(c
)) {
352 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
),
358 tmua
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_TMUA
);
360 tmua
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_TMUAU
);
364 struct qreg offset
= base_offset
;
365 if (const_offset
!= 0) {
366 offset
= vir_ADD(c
, offset
,
367 vir_uniform_ui(c
, const_offset
));
370 ntq_get_src(c
, instr
->src
[offset_src
], 0);
371 tmu
= vir_ADD_dest(c
, tmua
, offset
, data
);
373 if (const_offset
!= 0) {
374 tmu
= vir_ADD_dest(c
, tmua
, base_offset
,
375 vir_uniform_ui(c
, const_offset
));
377 tmu
= vir_MOV_dest(c
, tmua
, base_offset
);
383 vir_get_uniform_index(c
, QUNIFORM_CONSTANT
,
387 if (vir_in_nonuniform_control_flow(c
))
388 vir_set_cond(tmu
, V3D_QPU_COND_IFA
);
392 /* Read the result, or wait for the TMU op to complete. */
393 for (int i
= 0; i
< nir_intrinsic_dest_components(instr
); i
++) {
394 ntq_store_dest(c
, &instr
->dest
, i
,
395 vir_MOV(c
, vir_LDTMU(c
)));
398 if (nir_intrinsic_dest_components(instr
) == 0)
400 } while (is_store
&& writemask
!= 0);
404 ntq_init_ssa_def(struct v3d_compile
*c
, nir_ssa_def
*def
)
406 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
407 def
->num_components
);
408 _mesa_hash_table_insert(c
->def_ht
, def
, qregs
);
413 is_ld_signal(const struct v3d_qpu_sig
*sig
)
415 return (sig
->ldunif
||
427 * This function is responsible for getting VIR results into the associated
428 * storage for a NIR instruction.
430 * If it's a NIR SSA def, then we just set the associated hash table entry to
433 * If it's a NIR reg, then we need to update the existing qreg assigned to the
434 * NIR destination with the incoming value. To do that without introducing
435 * new MOVs, we require that the incoming qreg either be a uniform, or be
436 * SSA-defined by the previous VIR instruction in the block and rewritable by
437 * this function. That lets us sneak ahead and insert the SF flag beforehand
438 * (knowing that the previous instruction doesn't depend on flags) and rewrite
439 * its destination to be the NIR reg's destination
442 ntq_store_dest(struct v3d_compile
*c
, nir_dest
*dest
, int chan
,
445 struct qinst
*last_inst
= NULL
;
446 if (!list_is_empty(&c
->cur_block
->instructions
))
447 last_inst
= (struct qinst
*)c
->cur_block
->instructions
.prev
;
449 assert((result
.file
== QFILE_TEMP
&&
450 last_inst
&& last_inst
== c
->defs
[result
.index
]));
453 assert(chan
< dest
->ssa
.num_components
);
456 struct hash_entry
*entry
=
457 _mesa_hash_table_search(c
->def_ht
, &dest
->ssa
);
462 qregs
= ntq_init_ssa_def(c
, &dest
->ssa
);
464 qregs
[chan
] = result
;
466 nir_register
*reg
= dest
->reg
.reg
;
467 assert(dest
->reg
.base_offset
== 0);
468 assert(reg
->num_array_elems
== 0);
469 struct hash_entry
*entry
=
470 _mesa_hash_table_search(c
->def_ht
, reg
);
471 struct qreg
*qregs
= entry
->data
;
473 /* If the previous instruction can't be predicated for
474 * the store into the nir_register, then emit a MOV
477 if (vir_in_nonuniform_control_flow(c
) &&
478 is_ld_signal(&c
->defs
[last_inst
->dst
.index
]->qpu
.sig
)) {
479 result
= vir_MOV(c
, result
);
480 last_inst
= c
->defs
[result
.index
];
483 /* We know they're both temps, so just rewrite index. */
484 c
->defs
[last_inst
->dst
.index
] = NULL
;
485 last_inst
->dst
.index
= qregs
[chan
].index
;
487 /* If we're in control flow, then make this update of the reg
488 * conditional on the execution mask.
490 if (vir_in_nonuniform_control_flow(c
)) {
491 last_inst
->dst
.index
= qregs
[chan
].index
;
493 /* Set the flags to the current exec mask.
495 c
->cursor
= vir_before_inst(last_inst
);
496 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
),
498 c
->cursor
= vir_after_inst(last_inst
);
500 vir_set_cond(last_inst
, V3D_QPU_COND_IFA
);
506 ntq_get_src(struct v3d_compile
*c
, nir_src src
, int i
)
508 struct hash_entry
*entry
;
510 entry
= _mesa_hash_table_search(c
->def_ht
, src
.ssa
);
511 assert(i
< src
.ssa
->num_components
);
513 nir_register
*reg
= src
.reg
.reg
;
514 entry
= _mesa_hash_table_search(c
->def_ht
, reg
);
515 assert(reg
->num_array_elems
== 0);
516 assert(src
.reg
.base_offset
== 0);
517 assert(i
< reg
->num_components
);
520 struct qreg
*qregs
= entry
->data
;
525 ntq_get_alu_src(struct v3d_compile
*c
, nir_alu_instr
*instr
,
528 assert(util_is_power_of_two_or_zero(instr
->dest
.write_mask
));
529 unsigned chan
= ffs(instr
->dest
.write_mask
) - 1;
530 struct qreg r
= ntq_get_src(c
, instr
->src
[src
].src
,
531 instr
->src
[src
].swizzle
[chan
]);
533 assert(!instr
->src
[src
].abs
);
534 assert(!instr
->src
[src
].negate
);
540 ntq_minify(struct v3d_compile
*c
, struct qreg size
, struct qreg level
)
542 return vir_MAX(c
, vir_SHR(c
, size
, level
), vir_uniform_ui(c
, 1));
546 ntq_emit_txs(struct v3d_compile
*c
, nir_tex_instr
*instr
)
548 unsigned unit
= instr
->texture_index
;
549 int lod_index
= nir_tex_instr_src_index(instr
, nir_tex_src_lod
);
550 int dest_size
= nir_tex_instr_dest_size(instr
);
552 struct qreg lod
= c
->undef
;
554 lod
= ntq_get_src(c
, instr
->src
[lod_index
].src
, 0);
556 for (int i
= 0; i
< dest_size
; i
++) {
558 enum quniform_contents contents
;
560 if (instr
->is_array
&& i
== dest_size
- 1)
561 contents
= QUNIFORM_TEXTURE_ARRAY_SIZE
;
563 contents
= QUNIFORM_TEXTURE_WIDTH
+ i
;
565 struct qreg size
= vir_uniform(c
, contents
, unit
);
567 switch (instr
->sampler_dim
) {
568 case GLSL_SAMPLER_DIM_1D
:
569 case GLSL_SAMPLER_DIM_2D
:
570 case GLSL_SAMPLER_DIM_MS
:
571 case GLSL_SAMPLER_DIM_3D
:
572 case GLSL_SAMPLER_DIM_CUBE
:
573 /* Don't minify the array size. */
574 if (!(instr
->is_array
&& i
== dest_size
- 1)) {
575 size
= ntq_minify(c
, size
, lod
);
579 case GLSL_SAMPLER_DIM_RECT
:
580 /* There's no LOD field for rects */
584 unreachable("Bad sampler type");
587 ntq_store_dest(c
, &instr
->dest
, i
, size
);
592 ntq_emit_tex(struct v3d_compile
*c
, nir_tex_instr
*instr
)
594 unsigned unit
= instr
->texture_index
;
596 /* Since each texture sampling op requires uploading uniforms to
597 * reference the texture, there's no HW support for texture size and
598 * you just upload uniforms containing the size.
601 case nir_texop_query_levels
:
602 ntq_store_dest(c
, &instr
->dest
, 0,
603 vir_uniform(c
, QUNIFORM_TEXTURE_LEVELS
, unit
));
606 ntq_emit_txs(c
, instr
);
612 if (c
->devinfo
->ver
>= 40)
613 v3d40_vir_emit_tex(c
, instr
);
615 v3d33_vir_emit_tex(c
, instr
);
619 ntq_fsincos(struct v3d_compile
*c
, struct qreg src
, bool is_cos
)
621 struct qreg input
= vir_FMUL(c
, src
, vir_uniform_f(c
, 1.0f
/ M_PI
));
623 input
= vir_FADD(c
, input
, vir_uniform_f(c
, 0.5));
625 struct qreg periods
= vir_FROUND(c
, input
);
626 struct qreg sin_output
= vir_SIN(c
, vir_FSUB(c
, input
, periods
));
627 return vir_XOR(c
, sin_output
, vir_SHL(c
,
628 vir_FTOIN(c
, periods
),
629 vir_uniform_ui(c
, -1)));
633 ntq_fsign(struct v3d_compile
*c
, struct qreg src
)
635 struct qreg t
= vir_get_temp(c
);
637 vir_MOV_dest(c
, t
, vir_uniform_f(c
, 0.0));
638 vir_set_pf(vir_FMOV_dest(c
, vir_nop_reg(), src
), V3D_QPU_PF_PUSHZ
);
639 vir_MOV_cond(c
, V3D_QPU_COND_IFNA
, t
, vir_uniform_f(c
, 1.0));
640 vir_set_pf(vir_FMOV_dest(c
, vir_nop_reg(), src
), V3D_QPU_PF_PUSHN
);
641 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, t
, vir_uniform_f(c
, -1.0));
642 return vir_MOV(c
, t
);
646 emit_fragcoord_input(struct v3d_compile
*c
, int attr
)
648 c
->inputs
[attr
* 4 + 0] = vir_FXCD(c
);
649 c
->inputs
[attr
* 4 + 1] = vir_FYCD(c
);
650 c
->inputs
[attr
* 4 + 2] = c
->payload_z
;
651 c
->inputs
[attr
* 4 + 3] = vir_RECIP(c
, c
->payload_w
);
655 emit_fragment_varying(struct v3d_compile
*c
, nir_variable
*var
,
656 uint8_t swizzle
, int array_index
)
658 struct qreg r3
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_R3
);
659 struct qreg r5
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_R5
);
662 if (c
->devinfo
->ver
>= 41) {
663 struct qinst
*ldvary
= vir_add_inst(V3D_QPU_A_NOP
, c
->undef
,
665 ldvary
->qpu
.sig
.ldvary
= true;
666 vary
= vir_emit_def(c
, ldvary
);
668 vir_NOP(c
)->qpu
.sig
.ldvary
= true;
672 /* For gl_PointCoord input or distance along a line, we'll be called
673 * with no nir_variable, and we don't count toward VPM size so we
674 * don't track an input slot.
677 return vir_FADD(c
, vir_FMUL(c
, vary
, c
->payload_w
), r5
);
680 int i
= c
->num_inputs
++;
682 v3d_slot_from_slot_and_component(var
->data
.location
+
683 array_index
, swizzle
);
685 switch (var
->data
.interpolation
) {
686 case INTERP_MODE_NONE
:
687 /* If a gl_FrontColor or gl_BackColor input has no interp
688 * qualifier, then if we're using glShadeModel(GL_FLAT) it
689 * needs to be flat shaded.
691 switch (var
->data
.location
+ array_index
) {
692 case VARYING_SLOT_COL0
:
693 case VARYING_SLOT_COL1
:
694 case VARYING_SLOT_BFC0
:
695 case VARYING_SLOT_BFC1
:
696 if (c
->fs_key
->shade_model_flat
) {
697 BITSET_SET(c
->flat_shade_flags
, i
);
698 vir_MOV_dest(c
, c
->undef
, vary
);
699 return vir_MOV(c
, r5
);
701 return vir_FADD(c
, vir_FMUL(c
, vary
,
708 case INTERP_MODE_SMOOTH
:
709 if (var
->data
.centroid
) {
710 BITSET_SET(c
->centroid_flags
, i
);
711 return vir_FADD(c
, vir_FMUL(c
, vary
,
712 c
->payload_w_centroid
), r5
);
714 return vir_FADD(c
, vir_FMUL(c
, vary
, c
->payload_w
), r5
);
716 case INTERP_MODE_NOPERSPECTIVE
:
717 BITSET_SET(c
->noperspective_flags
, i
);
718 return vir_FADD(c
, vir_MOV(c
, vary
), r5
);
719 case INTERP_MODE_FLAT
:
720 BITSET_SET(c
->flat_shade_flags
, i
);
721 vir_MOV_dest(c
, c
->undef
, vary
);
722 return vir_MOV(c
, r5
);
724 unreachable("Bad interp mode");
729 emit_fragment_input(struct v3d_compile
*c
, int attr
, nir_variable
*var
,
732 for (int i
= 0; i
< glsl_get_vector_elements(var
->type
); i
++) {
733 int chan
= var
->data
.location_frac
+ i
;
734 c
->inputs
[attr
* 4 + chan
] =
735 emit_fragment_varying(c
, var
, chan
, array_index
);
740 add_output(struct v3d_compile
*c
,
741 uint32_t decl_offset
,
745 uint32_t old_array_size
= c
->outputs_array_size
;
746 resize_qreg_array(c
, &c
->outputs
, &c
->outputs_array_size
,
749 if (old_array_size
!= c
->outputs_array_size
) {
750 c
->output_slots
= reralloc(c
,
752 struct v3d_varying_slot
,
753 c
->outputs_array_size
);
756 c
->output_slots
[decl_offset
] =
757 v3d_slot_from_slot_and_component(slot
, swizzle
);
761 * If compare_instr is a valid comparison instruction, emits the
762 * compare_instr's comparison and returns the sel_instr's return value based
763 * on the compare_instr's result.
766 ntq_emit_comparison(struct v3d_compile
*c
,
767 nir_alu_instr
*compare_instr
,
768 enum v3d_qpu_cond
*out_cond
)
770 struct qreg src0
= ntq_get_alu_src(c
, compare_instr
, 0);
772 if (nir_op_infos
[compare_instr
->op
].num_inputs
> 1)
773 src1
= ntq_get_alu_src(c
, compare_instr
, 1);
774 bool cond_invert
= false;
775 struct qreg nop
= vir_nop_reg();
777 switch (compare_instr
->op
) {
780 vir_set_pf(vir_FCMP_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
783 vir_set_pf(vir_XOR_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
788 vir_set_pf(vir_FCMP_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
792 vir_set_pf(vir_XOR_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
798 vir_set_pf(vir_FCMP_dest(c
, nop
, src1
, src0
), V3D_QPU_PF_PUSHC
);
801 vir_set_pf(vir_MIN_dest(c
, nop
, src1
, src0
), V3D_QPU_PF_PUSHC
);
805 vir_set_pf(vir_SUB_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHC
);
811 vir_set_pf(vir_FCMP_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHN
);
814 vir_set_pf(vir_MIN_dest(c
, nop
, src1
, src0
), V3D_QPU_PF_PUSHC
);
817 vir_set_pf(vir_SUB_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHC
);
821 vir_set_pf(vir_MOV_dest(c
, nop
, src0
), V3D_QPU_PF_PUSHZ
);
826 vir_set_pf(vir_FMOV_dest(c
, nop
, src0
), V3D_QPU_PF_PUSHZ
);
834 *out_cond
= cond_invert
? V3D_QPU_COND_IFNA
: V3D_QPU_COND_IFA
;
839 /* Finds an ALU instruction that generates our src value that could
840 * (potentially) be greedily emitted in the consuming instruction.
842 static struct nir_alu_instr
*
843 ntq_get_alu_parent(nir_src src
)
845 if (!src
.is_ssa
|| src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
847 nir_alu_instr
*instr
= nir_instr_as_alu(src
.ssa
->parent_instr
);
851 /* If the ALU instr's srcs are non-SSA, then we would have to avoid
852 * moving emission of the ALU instr down past another write of the
855 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
856 if (!instr
->src
[i
].src
.is_ssa
)
863 /* Turns a NIR bool into a condition code to predicate on. */
864 static enum v3d_qpu_cond
865 ntq_emit_bool_to_cond(struct v3d_compile
*c
, nir_src src
)
867 nir_alu_instr
*compare
= ntq_get_alu_parent(src
);
871 enum v3d_qpu_cond cond
;
872 if (ntq_emit_comparison(c
, compare
, &cond
))
876 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), ntq_get_src(c
, src
, 0)),
878 return V3D_QPU_COND_IFNA
;
882 ntq_emit_alu(struct v3d_compile
*c
, nir_alu_instr
*instr
)
884 /* This should always be lowered to ALU operations for V3D. */
885 assert(!instr
->dest
.saturate
);
887 /* Vectors are special in that they have non-scalarized writemasks,
888 * and just take the first swizzle channel for each argument in order
889 * into each writemask channel.
891 if (instr
->op
== nir_op_vec2
||
892 instr
->op
== nir_op_vec3
||
893 instr
->op
== nir_op_vec4
) {
895 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
896 srcs
[i
] = ntq_get_src(c
, instr
->src
[i
].src
,
897 instr
->src
[i
].swizzle
[0]);
898 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
899 ntq_store_dest(c
, &instr
->dest
.dest
, i
,
900 vir_MOV(c
, srcs
[i
]));
904 /* General case: We can just grab the one used channel per src. */
905 struct qreg src
[nir_op_infos
[instr
->op
].num_inputs
];
906 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
907 src
[i
] = ntq_get_alu_src(c
, instr
, i
);
914 result
= vir_MOV(c
, src
[0]);
918 result
= vir_XOR(c
, src
[0], vir_uniform_ui(c
, 1 << 31));
921 result
= vir_NEG(c
, src
[0]);
925 result
= vir_FMUL(c
, src
[0], src
[1]);
928 result
= vir_FADD(c
, src
[0], src
[1]);
931 result
= vir_FSUB(c
, src
[0], src
[1]);
934 result
= vir_FMIN(c
, src
[0], src
[1]);
937 result
= vir_FMAX(c
, src
[0], src
[1]);
941 nir_alu_instr
*src0_alu
= ntq_get_alu_parent(instr
->src
[0].src
);
942 if (src0_alu
&& src0_alu
->op
== nir_op_fround_even
) {
943 result
= vir_FTOIN(c
, ntq_get_alu_src(c
, src0_alu
, 0));
945 result
= vir_FTOIZ(c
, src
[0]);
951 result
= vir_FTOUZ(c
, src
[0]);
954 result
= vir_ITOF(c
, src
[0]);
957 result
= vir_UTOF(c
, src
[0]);
960 result
= vir_AND(c
, src
[0], vir_uniform_f(c
, 1.0));
963 result
= vir_AND(c
, src
[0], vir_uniform_ui(c
, 1));
967 result
= vir_ADD(c
, src
[0], src
[1]);
970 result
= vir_SHR(c
, src
[0], src
[1]);
973 result
= vir_SUB(c
, src
[0], src
[1]);
976 result
= vir_ASR(c
, src
[0], src
[1]);
979 result
= vir_SHL(c
, src
[0], src
[1]);
982 result
= vir_MIN(c
, src
[0], src
[1]);
985 result
= vir_UMIN(c
, src
[0], src
[1]);
988 result
= vir_MAX(c
, src
[0], src
[1]);
991 result
= vir_UMAX(c
, src
[0], src
[1]);
994 result
= vir_AND(c
, src
[0], src
[1]);
997 result
= vir_OR(c
, src
[0], src
[1]);
1000 result
= vir_XOR(c
, src
[0], src
[1]);
1003 result
= vir_NOT(c
, src
[0]);
1006 case nir_op_ufind_msb
:
1007 result
= vir_SUB(c
, vir_uniform_ui(c
, 31), vir_CLZ(c
, src
[0]));
1011 result
= vir_UMUL(c
, src
[0], src
[1]);
1018 enum v3d_qpu_cond cond
;
1019 ASSERTED
bool ok
= ntq_emit_comparison(c
, instr
, &cond
);
1021 result
= vir_MOV(c
, vir_SEL(c
, cond
,
1022 vir_uniform_f(c
, 1.0),
1023 vir_uniform_f(c
, 0.0)));
1038 case nir_op_ult32
: {
1039 enum v3d_qpu_cond cond
;
1040 ASSERTED
bool ok
= ntq_emit_comparison(c
, instr
, &cond
);
1042 result
= vir_MOV(c
, vir_SEL(c
, cond
,
1043 vir_uniform_ui(c
, ~0),
1044 vir_uniform_ui(c
, 0)));
1048 case nir_op_b32csel
:
1051 ntq_emit_bool_to_cond(c
, instr
->src
[0].src
),
1056 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), src
[0]),
1058 result
= vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFNA
,
1063 result
= vir_RECIP(c
, src
[0]);
1066 result
= vir_RSQRT(c
, src
[0]);
1069 result
= vir_EXP(c
, src
[0]);
1072 result
= vir_LOG(c
, src
[0]);
1076 result
= vir_FCEIL(c
, src
[0]);
1079 result
= vir_FFLOOR(c
, src
[0]);
1081 case nir_op_fround_even
:
1082 result
= vir_FROUND(c
, src
[0]);
1085 result
= vir_FTRUNC(c
, src
[0]);
1089 result
= ntq_fsincos(c
, src
[0], false);
1092 result
= ntq_fsincos(c
, src
[0], true);
1096 result
= ntq_fsign(c
, src
[0]);
1100 result
= vir_FMOV(c
, src
[0]);
1101 vir_set_unpack(c
->defs
[result
.index
], 0, V3D_QPU_UNPACK_ABS
);
1106 result
= vir_MAX(c
, src
[0], vir_NEG(c
, src
[0]));
1110 case nir_op_fddx_coarse
:
1111 case nir_op_fddx_fine
:
1112 result
= vir_FDX(c
, src
[0]);
1116 case nir_op_fddy_coarse
:
1117 case nir_op_fddy_fine
:
1118 result
= vir_FDY(c
, src
[0]);
1121 case nir_op_uadd_carry
:
1122 vir_set_pf(vir_ADD_dest(c
, vir_nop_reg(), src
[0], src
[1]),
1124 result
= vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFA
,
1125 vir_uniform_ui(c
, ~0),
1126 vir_uniform_ui(c
, 0)));
1129 case nir_op_pack_half_2x16_split
:
1130 result
= vir_VFPACK(c
, src
[0], src
[1]);
1133 case nir_op_unpack_half_2x16_split_x
:
1134 result
= vir_FMOV(c
, src
[0]);
1135 vir_set_unpack(c
->defs
[result
.index
], 0, V3D_QPU_UNPACK_L
);
1138 case nir_op_unpack_half_2x16_split_y
:
1139 result
= vir_FMOV(c
, src
[0]);
1140 vir_set_unpack(c
->defs
[result
.index
], 0, V3D_QPU_UNPACK_H
);
1144 fprintf(stderr
, "unknown NIR ALU inst: ");
1145 nir_print_instr(&instr
->instr
, stderr
);
1146 fprintf(stderr
, "\n");
1150 /* We have a scalar result, so the instruction should only have a
1151 * single channel written to.
1153 assert(util_is_power_of_two_or_zero(instr
->dest
.write_mask
));
1154 ntq_store_dest(c
, &instr
->dest
.dest
,
1155 ffs(instr
->dest
.write_mask
) - 1, result
);
1158 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
1159 * specifier. They come from a register that's preloaded with 0xffffffff
1160 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
1161 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
1163 #define TLB_TYPE_F16_COLOR (3 << 6)
1164 #define TLB_TYPE_I32_COLOR (1 << 6)
1165 #define TLB_TYPE_F32_COLOR (0 << 6)
1166 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
1167 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
1168 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
1169 #define TLB_F16_SWAP_HI_LO (1 << 1)
1170 #define TLB_VEC_SIZE_4_F16 (1 << 0)
1171 #define TLB_VEC_SIZE_2_F16 (0 << 0)
1172 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
1174 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
1177 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
1178 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
1179 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
1180 #define TLB_V42_DEPTH_TYPE_INVARIANT (0 << 3) /* Unmodified sideband input used */
1181 #define TLB_V42_DEPTH_TYPE_PER_PIXEL (1 << 3) /* QPU result used */
1183 /* Stencil is a single 32-bit write. */
1184 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1187 vir_emit_tlb_color_write(struct v3d_compile
*c
, unsigned rt
)
1189 if (!(c
->fs_key
->cbufs
& (1 << rt
)) || !c
->output_color_var
[rt
])
1192 struct qreg tlb_reg
= vir_magic_reg(V3D_QPU_WADDR_TLB
);
1193 struct qreg tlbu_reg
= vir_magic_reg(V3D_QPU_WADDR_TLBU
);
1195 nir_variable
*var
= c
->output_color_var
[rt
];
1196 int num_components
= glsl_get_vector_elements(var
->type
);
1197 uint32_t conf
= 0xffffff00;
1200 conf
|= c
->msaa_per_sample_output
? TLB_SAMPLE_MODE_PER_SAMPLE
:
1201 TLB_SAMPLE_MODE_PER_PIXEL
;
1202 conf
|= (7 - rt
) << TLB_RENDER_TARGET_SHIFT
;
1204 if (c
->fs_key
->swap_color_rb
& (1 << rt
))
1205 num_components
= MAX2(num_components
, 3);
1206 assert(num_components
!= 0);
1208 enum glsl_base_type type
= glsl_get_base_type(var
->type
);
1209 bool is_int_format
= type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
;
1210 bool is_32b_tlb_format
= is_int_format
||
1211 (c
->fs_key
->f32_color_rb
& (1 << rt
));
1213 if (is_int_format
) {
1214 /* The F32 vs I32 distinction was dropped in 4.2. */
1215 if (c
->devinfo
->ver
< 42)
1216 conf
|= TLB_TYPE_I32_COLOR
;
1218 conf
|= TLB_TYPE_F32_COLOR
;
1219 conf
|= ((num_components
- 1) << TLB_VEC_SIZE_MINUS_1_SHIFT
);
1221 if (c
->fs_key
->f32_color_rb
& (1 << rt
)) {
1222 conf
|= TLB_TYPE_F32_COLOR
;
1223 conf
|= ((num_components
- 1) <<
1224 TLB_VEC_SIZE_MINUS_1_SHIFT
);
1226 conf
|= TLB_TYPE_F16_COLOR
;
1227 conf
|= TLB_F16_SWAP_HI_LO
;
1228 if (num_components
>= 3)
1229 conf
|= TLB_VEC_SIZE_4_F16
;
1231 conf
|= TLB_VEC_SIZE_2_F16
;
1235 int num_samples
= c
->msaa_per_sample_output
? V3D_MAX_SAMPLES
: 1;
1236 for (int i
= 0; i
< num_samples
; i
++) {
1237 struct qreg
*color
= c
->msaa_per_sample_output
?
1238 &c
->sample_colors
[(rt
* V3D_MAX_SAMPLES
+ i
) * 4] :
1239 &c
->outputs
[var
->data
.driver_location
* 4];
1241 struct qreg r
= color
[0];
1242 struct qreg g
= color
[1];
1243 struct qreg b
= color
[2];
1244 struct qreg a
= color
[3];
1246 if (c
->fs_key
->swap_color_rb
& (1 << rt
)) {
1251 if (c
->fs_key
->sample_alpha_to_one
)
1252 a
= vir_uniform_f(c
, 1.0);
1254 if (is_32b_tlb_format
) {
1256 inst
= vir_MOV_dest(c
, tlbu_reg
, r
);
1258 vir_get_uniform_index(c
,
1262 inst
= vir_MOV_dest(c
, tlb_reg
, r
);
1265 if (num_components
>= 2)
1266 vir_MOV_dest(c
, tlb_reg
, g
);
1267 if (num_components
>= 3)
1268 vir_MOV_dest(c
, tlb_reg
, b
);
1269 if (num_components
>= 4)
1270 vir_MOV_dest(c
, tlb_reg
, a
);
1272 inst
= vir_VFPACK_dest(c
, tlb_reg
, r
, g
);
1273 if (conf
!= ~0 && i
== 0) {
1274 inst
->dst
= tlbu_reg
;
1276 vir_get_uniform_index(c
,
1281 if (num_components
>= 3)
1282 inst
= vir_VFPACK_dest(c
, tlb_reg
, b
, a
);
1288 emit_frag_end(struct v3d_compile
*c
)
1291 if (c->output_sample_mask_index != -1) {
1292 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1296 bool has_any_tlb_color_write
= false;
1297 for (int rt
= 0; rt
< V3D_MAX_DRAW_BUFFERS
; rt
++) {
1298 if (c
->fs_key
->cbufs
& (1 << rt
) && c
->output_color_var
[rt
])
1299 has_any_tlb_color_write
= true;
1302 if (c
->fs_key
->sample_alpha_to_coverage
&& c
->output_color_var
[0]) {
1303 struct nir_variable
*var
= c
->output_color_var
[0];
1304 struct qreg
*color
= &c
->outputs
[var
->data
.driver_location
* 4];
1306 vir_SETMSF_dest(c
, vir_nop_reg(),
1309 vir_FTOC(c
, color
[3])));
1312 struct qreg tlbu_reg
= vir_magic_reg(V3D_QPU_WADDR_TLBU
);
1313 if (c
->output_position_index
!= -1) {
1314 struct qinst
*inst
= vir_MOV_dest(c
, tlbu_reg
,
1315 c
->outputs
[c
->output_position_index
]);
1316 uint8_t tlb_specifier
= TLB_TYPE_DEPTH
;
1318 if (c
->devinfo
->ver
>= 42) {
1319 tlb_specifier
|= (TLB_V42_DEPTH_TYPE_PER_PIXEL
|
1320 TLB_SAMPLE_MODE_PER_PIXEL
);
1322 tlb_specifier
|= TLB_DEPTH_TYPE_PER_PIXEL
;
1324 inst
->uniform
= vir_get_uniform_index(c
, QUNIFORM_CONSTANT
,
1328 } else if (c
->s
->info
.fs
.uses_discard
||
1329 !c
->s
->info
.fs
.early_fragment_tests
||
1330 c
->fs_key
->sample_alpha_to_coverage
||
1331 !has_any_tlb_color_write
) {
1332 /* Emit passthrough Z if it needed to be delayed until shader
1333 * end due to potential discards.
1335 * Since (single-threaded) fragment shaders always need a TLB
1336 * write, emit passthrouh Z if we didn't have any color
1337 * buffers and flag us as potentially discarding, so that we
1338 * can use Z as the TLB write.
1340 c
->s
->info
.fs
.uses_discard
= true;
1342 struct qinst
*inst
= vir_MOV_dest(c
, tlbu_reg
,
1344 uint8_t tlb_specifier
= TLB_TYPE_DEPTH
;
1346 if (c
->devinfo
->ver
>= 42) {
1347 /* The spec says the PER_PIXEL flag is ignored for
1348 * invariant writes, but the simulator demands it.
1350 tlb_specifier
|= (TLB_V42_DEPTH_TYPE_INVARIANT
|
1351 TLB_SAMPLE_MODE_PER_PIXEL
);
1353 tlb_specifier
|= TLB_DEPTH_TYPE_INVARIANT
;
1356 inst
->uniform
= vir_get_uniform_index(c
,
1363 /* XXX: Performance improvement: Merge Z write and color writes TLB
1366 for (int rt
= 0; rt
< V3D_MAX_DRAW_BUFFERS
; rt
++)
1367 vir_emit_tlb_color_write(c
, rt
);
1371 vir_VPM_WRITE_indirect(struct v3d_compile
*c
,
1373 struct qreg vpm_index
)
1375 assert(c
->devinfo
->ver
>= 40);
1376 vir_STVPMV(c
, vpm_index
, val
);
1380 vir_VPM_WRITE(struct v3d_compile
*c
, struct qreg val
, uint32_t vpm_index
)
1382 if (c
->devinfo
->ver
>= 40) {
1383 vir_VPM_WRITE_indirect(c
, val
, vir_uniform_ui(c
, vpm_index
));
1385 /* XXX: v3d33_vir_vpm_write_setup(c); */
1386 vir_MOV_dest(c
, vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_VPM
), val
);
1391 emit_vert_end(struct v3d_compile
*c
)
1393 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1395 if (c
->devinfo
->ver
>= 40 && c
->devinfo
->ver
<= 42)
1400 emit_geom_end(struct v3d_compile
*c
)
1402 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1404 if (c
->devinfo
->ver
>= 40 && c
->devinfo
->ver
<= 42)
1409 v3d_optimize_nir(struct nir_shader
*s
)
1412 unsigned lower_flrp
=
1413 (s
->options
->lower_flrp16
? 16 : 0) |
1414 (s
->options
->lower_flrp32
? 32 : 0) |
1415 (s
->options
->lower_flrp64
? 64 : 0);
1420 NIR_PASS_V(s
, nir_lower_vars_to_ssa
);
1421 NIR_PASS(progress
, s
, nir_lower_alu_to_scalar
, NULL
, NULL
);
1422 NIR_PASS(progress
, s
, nir_lower_phis_to_scalar
);
1423 NIR_PASS(progress
, s
, nir_copy_prop
);
1424 NIR_PASS(progress
, s
, nir_opt_remove_phis
);
1425 NIR_PASS(progress
, s
, nir_opt_dce
);
1426 NIR_PASS(progress
, s
, nir_opt_dead_cf
);
1427 NIR_PASS(progress
, s
, nir_opt_cse
);
1428 NIR_PASS(progress
, s
, nir_opt_peephole_select
, 8, true, true);
1429 NIR_PASS(progress
, s
, nir_opt_algebraic
);
1430 NIR_PASS(progress
, s
, nir_opt_constant_folding
);
1432 if (lower_flrp
!= 0) {
1433 bool lower_flrp_progress
= false;
1435 NIR_PASS(lower_flrp_progress
, s
, nir_lower_flrp
,
1437 false /* always_precise */,
1438 s
->options
->lower_ffma
);
1439 if (lower_flrp_progress
) {
1440 NIR_PASS(progress
, s
, nir_opt_constant_folding
);
1444 /* Nothing should rematerialize any flrps, so we only
1445 * need to do this lowering once.
1450 NIR_PASS(progress
, s
, nir_opt_undef
);
1453 NIR_PASS(progress
, s
, nir_opt_move
, nir_move_load_ubo
);
1457 driver_location_compare(const void *in_a
, const void *in_b
)
1459 const nir_variable
*const *a
= in_a
;
1460 const nir_variable
*const *b
= in_b
;
1462 return (*a
)->data
.driver_location
- (*b
)->data
.driver_location
;
1466 ntq_emit_vpm_read(struct v3d_compile
*c
,
1467 uint32_t *num_components_queued
,
1468 uint32_t *remaining
,
1471 struct qreg vpm
= vir_reg(QFILE_VPM
, vpm_index
);
1473 if (c
->devinfo
->ver
>= 40 ) {
1474 return vir_LDVPMV_IN(c
,
1476 (*num_components_queued
)++));
1479 if (*num_components_queued
!= 0) {
1480 (*num_components_queued
)--;
1481 return vir_MOV(c
, vpm
);
1484 uint32_t num_components
= MIN2(*remaining
, 32);
1486 v3d33_vir_vpm_read_setup(c
, num_components
);
1488 *num_components_queued
= num_components
- 1;
1489 *remaining
-= num_components
;
1491 return vir_MOV(c
, vpm
);
1495 ntq_setup_vs_inputs(struct v3d_compile
*c
)
1497 /* Figure out how many components of each vertex attribute the shader
1498 * uses. Each variable should have been split to individual
1499 * components and unused ones DCEed. The vertex fetcher will load
1500 * from the start of the attribute to the number of components we
1501 * declare we need in c->vattr_sizes[].
1503 nir_foreach_variable(var
, &c
->s
->inputs
) {
1504 /* No VS attribute array support. */
1505 assert(MAX2(glsl_get_length(var
->type
), 1) == 1);
1507 unsigned loc
= var
->data
.driver_location
;
1508 int start_component
= var
->data
.location_frac
;
1509 int num_components
= glsl_get_components(var
->type
);
1511 c
->vattr_sizes
[loc
] = MAX2(c
->vattr_sizes
[loc
],
1512 start_component
+ num_components
);
1515 unsigned num_components
= 0;
1516 uint32_t vpm_components_queued
= 0;
1517 bool uses_iid
= c
->s
->info
.system_values_read
&
1518 (1ull << SYSTEM_VALUE_INSTANCE_ID
);
1519 bool uses_vid
= c
->s
->info
.system_values_read
&
1520 (1ull << SYSTEM_VALUE_VERTEX_ID
);
1521 num_components
+= uses_iid
;
1522 num_components
+= uses_vid
;
1524 for (int i
= 0; i
< ARRAY_SIZE(c
->vattr_sizes
); i
++)
1525 num_components
+= c
->vattr_sizes
[i
];
1528 c
->iid
= ntq_emit_vpm_read(c
, &vpm_components_queued
,
1529 &num_components
, ~0);
1533 c
->vid
= ntq_emit_vpm_read(c
, &vpm_components_queued
,
1534 &num_components
, ~0);
1537 /* The actual loads will happen directly in nir_intrinsic_load_input
1538 * on newer versions.
1540 if (c
->devinfo
->ver
>= 40)
1543 for (int loc
= 0; loc
< ARRAY_SIZE(c
->vattr_sizes
); loc
++) {
1544 resize_qreg_array(c
, &c
->inputs
, &c
->inputs_array_size
,
1547 for (int i
= 0; i
< c
->vattr_sizes
[loc
]; i
++) {
1548 c
->inputs
[loc
* 4 + i
] =
1549 ntq_emit_vpm_read(c
,
1550 &vpm_components_queued
,
1557 if (c
->devinfo
->ver
>= 40) {
1558 assert(vpm_components_queued
== num_components
);
1560 assert(vpm_components_queued
== 0);
1561 assert(num_components
== 0);
1566 var_needs_point_coord(struct v3d_compile
*c
, nir_variable
*var
)
1568 return (var
->data
.location
== VARYING_SLOT_PNTC
||
1569 (var
->data
.location
>= VARYING_SLOT_VAR0
&&
1570 (c
->fs_key
->point_sprite_mask
&
1571 (1 << (var
->data
.location
- VARYING_SLOT_VAR0
)))));
1575 program_reads_point_coord(struct v3d_compile
*c
)
1577 nir_foreach_variable(var
, &c
->s
->inputs
) {
1578 if (var_needs_point_coord(c
, var
))
1586 get_sorted_input_variables(struct v3d_compile
*c
,
1587 unsigned *num_entries
,
1588 nir_variable
***vars
)
1591 nir_foreach_variable(var
, &c
->s
->inputs
)
1594 *vars
= ralloc_array(c
, nir_variable
*, *num_entries
);
1597 nir_foreach_variable(var
, &c
->s
->inputs
)
1600 /* Sort the variables so that we emit the input setup in
1601 * driver_location order. This is required for VPM reads, whose data
1602 * is fetched into the VPM in driver_location (TGSI register index)
1605 qsort(*vars
, *num_entries
, sizeof(**vars
), driver_location_compare
);
1609 ntq_setup_gs_inputs(struct v3d_compile
*c
)
1611 nir_variable
**vars
;
1612 unsigned num_entries
;
1613 get_sorted_input_variables(c
, &num_entries
, &vars
);
1615 for (unsigned i
= 0; i
< num_entries
; i
++) {
1616 nir_variable
*var
= vars
[i
];
1618 /* All GS inputs are arrays with as many entries as vertices
1619 * in the input primitive, but here we only care about the
1620 * per-vertex input type.
1622 const struct glsl_type
*type
= glsl_without_array(var
->type
);
1623 unsigned array_len
= MAX2(glsl_get_length(type
), 1);
1624 unsigned loc
= var
->data
.driver_location
;
1626 resize_qreg_array(c
, &c
->inputs
, &c
->inputs_array_size
,
1627 (loc
+ array_len
) * 4);
1629 for (unsigned j
= 0; j
< array_len
; j
++) {
1630 unsigned num_elements
= glsl_get_vector_elements(type
);
1631 for (unsigned k
= 0; k
< num_elements
; k
++) {
1632 unsigned chan
= var
->data
.location_frac
+ k
;
1633 unsigned input_idx
= c
->num_inputs
++;
1634 struct v3d_varying_slot slot
=
1635 v3d_slot_from_slot_and_component(var
->data
.location
+ j
, chan
);
1636 c
->input_slots
[input_idx
] = slot
;
1644 ntq_setup_fs_inputs(struct v3d_compile
*c
)
1646 nir_variable
**vars
;
1647 unsigned num_entries
;
1648 get_sorted_input_variables(c
, &num_entries
, &vars
);
1650 for (unsigned i
= 0; i
< num_entries
; i
++) {
1651 nir_variable
*var
= vars
[i
];
1652 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1653 unsigned loc
= var
->data
.driver_location
;
1655 resize_qreg_array(c
, &c
->inputs
, &c
->inputs_array_size
,
1656 (loc
+ array_len
) * 4);
1658 if (var
->data
.location
== VARYING_SLOT_POS
) {
1659 emit_fragcoord_input(c
, loc
);
1660 } else if (var_needs_point_coord(c
, var
)) {
1661 c
->inputs
[loc
* 4 + 0] = c
->point_x
;
1662 c
->inputs
[loc
* 4 + 1] = c
->point_y
;
1664 for (int j
= 0; j
< array_len
; j
++)
1665 emit_fragment_input(c
, loc
+ j
, var
, j
);
1671 ntq_setup_outputs(struct v3d_compile
*c
)
1673 if (c
->s
->info
.stage
!= MESA_SHADER_FRAGMENT
)
1676 nir_foreach_variable(var
, &c
->s
->outputs
) {
1677 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1678 unsigned loc
= var
->data
.driver_location
* 4;
1680 assert(array_len
== 1);
1683 for (int i
= 0; i
< 4 - var
->data
.location_frac
; i
++) {
1684 add_output(c
, loc
+ var
->data
.location_frac
+ i
,
1686 var
->data
.location_frac
+ i
);
1689 switch (var
->data
.location
) {
1690 case FRAG_RESULT_COLOR
:
1691 c
->output_color_var
[0] = var
;
1692 c
->output_color_var
[1] = var
;
1693 c
->output_color_var
[2] = var
;
1694 c
->output_color_var
[3] = var
;
1696 case FRAG_RESULT_DATA0
:
1697 case FRAG_RESULT_DATA1
:
1698 case FRAG_RESULT_DATA2
:
1699 case FRAG_RESULT_DATA3
:
1700 c
->output_color_var
[var
->data
.location
-
1701 FRAG_RESULT_DATA0
] = var
;
1703 case FRAG_RESULT_DEPTH
:
1704 c
->output_position_index
= loc
;
1706 case FRAG_RESULT_SAMPLE_MASK
:
1707 c
->output_sample_mask_index
= loc
;
1714 * Sets up the mapping from nir_register to struct qreg *.
1716 * Each nir_register gets a struct qreg per 32-bit component being stored.
1719 ntq_setup_registers(struct v3d_compile
*c
, struct exec_list
*list
)
1721 foreach_list_typed(nir_register
, nir_reg
, node
, list
) {
1722 unsigned array_len
= MAX2(nir_reg
->num_array_elems
, 1);
1723 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
1725 nir_reg
->num_components
);
1727 _mesa_hash_table_insert(c
->def_ht
, nir_reg
, qregs
);
1729 for (int i
= 0; i
< array_len
* nir_reg
->num_components
; i
++)
1730 qregs
[i
] = vir_get_temp(c
);
1735 ntq_emit_load_const(struct v3d_compile
*c
, nir_load_const_instr
*instr
)
1737 /* XXX perf: Experiment with using immediate loads to avoid having
1738 * these end up in the uniform stream. Watch out for breaking the
1739 * small immediates optimization in the process!
1741 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1742 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1743 qregs
[i
] = vir_uniform_ui(c
, instr
->value
[i
].u32
);
1745 _mesa_hash_table_insert(c
->def_ht
, &instr
->def
, qregs
);
1749 ntq_emit_ssa_undef(struct v3d_compile
*c
, nir_ssa_undef_instr
*instr
)
1751 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1753 /* VIR needs there to be *some* value, so pick 0 (same as for
1754 * ntq_setup_registers().
1756 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1757 qregs
[i
] = vir_uniform_ui(c
, 0);
1761 ntq_emit_image_size(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
)
1763 assert(instr
->intrinsic
== nir_intrinsic_image_deref_size
);
1764 nir_variable
*var
= nir_intrinsic_get_var(instr
, 0);
1765 unsigned image_index
= var
->data
.driver_location
;
1766 const struct glsl_type
*sampler_type
= glsl_without_array(var
->type
);
1767 bool is_array
= glsl_sampler_type_is_array(sampler_type
);
1769 ntq_store_dest(c
, &instr
->dest
, 0,
1770 vir_uniform(c
, QUNIFORM_IMAGE_WIDTH
, image_index
));
1771 if (instr
->num_components
> 1) {
1772 ntq_store_dest(c
, &instr
->dest
, 1,
1773 vir_uniform(c
, QUNIFORM_IMAGE_HEIGHT
,
1776 if (instr
->num_components
> 2) {
1777 ntq_store_dest(c
, &instr
->dest
, 2,
1780 QUNIFORM_IMAGE_ARRAY_SIZE
:
1781 QUNIFORM_IMAGE_DEPTH
,
1787 vir_emit_tlb_color_read(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
)
1789 assert(c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
);
1791 int rt
= nir_src_as_uint(instr
->src
[0]);
1792 assert(rt
< V3D_MAX_DRAW_BUFFERS
);
1794 int sample_index
= nir_intrinsic_base(instr
) ;
1795 assert(sample_index
< V3D_MAX_SAMPLES
);
1797 int component
= nir_intrinsic_component(instr
);
1798 assert(component
< 4);
1800 /* We need to emit our TLB reads after we have acquired the scoreboard
1801 * lock, or the GPU will hang. Usually, we do our scoreboard locking on
1802 * the last thread switch to improve parallelism, however, that is only
1803 * guaranteed to happen before the tlb color writes.
1805 * To fix that, we make sure we always emit a thread switch before the
1806 * first tlb color read. If that happens to be the last thread switch
1807 * we emit, then everything is fine, but otherwsie, if any code after
1808 * this point needs to emit additional thread switches, then we will
1809 * switch the strategy to locking the scoreboard on the first thread
1810 * switch instead -- see vir_emit_thrsw().
1812 if (!c
->emitted_tlb_load
) {
1813 if (!c
->last_thrsw_at_top_level
) {
1814 assert(c
->devinfo
->ver
>= 41);
1818 c
->emitted_tlb_load
= true;
1821 struct qreg
*color_reads_for_sample
=
1822 &c
->color_reads
[(rt
* V3D_MAX_SAMPLES
+ sample_index
) * 4];
1824 if (color_reads_for_sample
[component
].file
== QFILE_NULL
) {
1825 enum pipe_format rt_format
= c
->fs_key
->color_fmt
[rt
].format
;
1826 int num_components
=
1827 util_format_get_nr_components(rt_format
);
1829 const bool swap_rb
= c
->fs_key
->swap_color_rb
& (1 << rt
);
1831 num_components
= MAX2(num_components
, 3);
1833 nir_variable
*var
= c
->output_color_var
[rt
];
1834 enum glsl_base_type type
= glsl_get_base_type(var
->type
);
1836 bool is_int_format
= type
== GLSL_TYPE_INT
||
1837 type
== GLSL_TYPE_UINT
;
1839 bool is_32b_tlb_format
= is_int_format
||
1840 (c
->fs_key
->f32_color_rb
& (1 << rt
));
1842 int num_samples
= c
->fs_key
->msaa
? V3D_MAX_SAMPLES
: 1;
1844 uint32_t conf
= 0xffffff00;
1845 conf
|= c
->fs_key
->msaa
? TLB_SAMPLE_MODE_PER_SAMPLE
:
1846 TLB_SAMPLE_MODE_PER_PIXEL
;
1847 conf
|= (7 - rt
) << TLB_RENDER_TARGET_SHIFT
;
1849 if (is_32b_tlb_format
) {
1850 /* The F32 vs I32 distinction was dropped in 4.2. */
1851 conf
|= (c
->devinfo
->ver
< 42 && is_int_format
) ?
1852 TLB_TYPE_I32_COLOR
: TLB_TYPE_F32_COLOR
;
1854 conf
|= ((num_components
- 1) <<
1855 TLB_VEC_SIZE_MINUS_1_SHIFT
);
1857 conf
|= TLB_TYPE_F16_COLOR
;
1858 conf
|= TLB_F16_SWAP_HI_LO
;
1860 if (num_components
>= 3)
1861 conf
|= TLB_VEC_SIZE_4_F16
;
1863 conf
|= TLB_VEC_SIZE_2_F16
;
1867 for (int i
= 0; i
< num_samples
; i
++) {
1868 struct qreg r
, g
, b
, a
;
1869 if (is_32b_tlb_format
) {
1870 r
= conf
!= 0xffffffff && i
== 0?
1871 vir_TLBU_COLOR_READ(c
, conf
) :
1872 vir_TLB_COLOR_READ(c
);
1873 if (num_components
>= 2)
1874 g
= vir_TLB_COLOR_READ(c
);
1875 if (num_components
>= 3)
1876 b
= vir_TLB_COLOR_READ(c
);
1877 if (num_components
>= 4)
1878 a
= vir_TLB_COLOR_READ(c
);
1880 struct qreg rg
= conf
!= 0xffffffff && i
== 0 ?
1881 vir_TLBU_COLOR_READ(c
, conf
) :
1882 vir_TLB_COLOR_READ(c
);
1883 r
= vir_FMOV(c
, rg
);
1884 vir_set_unpack(c
->defs
[r
.index
], 0,
1886 g
= vir_FMOV(c
, rg
);
1887 vir_set_unpack(c
->defs
[g
.index
], 0,
1890 if (num_components
> 2) {
1891 struct qreg ba
= vir_TLB_COLOR_READ(c
);
1892 b
= vir_FMOV(c
, ba
);
1893 vir_set_unpack(c
->defs
[b
.index
], 0,
1895 a
= vir_FMOV(c
, ba
);
1896 vir_set_unpack(c
->defs
[a
.index
], 0,
1901 struct qreg
*color_reads
=
1902 &c
->color_reads
[(rt
* V3D_MAX_SAMPLES
+ i
) * 4];
1904 color_reads
[0] = swap_rb
? b
: r
;
1905 if (num_components
>= 2)
1907 if (num_components
>= 3)
1908 color_reads
[2] = swap_rb
? r
: b
;
1909 if (num_components
>= 4)
1914 assert(color_reads_for_sample
[component
].file
!= QFILE_NULL
);
1915 ntq_store_dest(c
, &instr
->dest
, 0,
1916 vir_MOV(c
, color_reads_for_sample
[component
]));
1920 ntq_emit_load_uniform(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
)
1922 if (nir_src_is_const(instr
->src
[0])) {
1923 int offset
= (nir_intrinsic_base(instr
) +
1924 nir_src_as_uint(instr
->src
[0]));
1925 assert(offset
% 4 == 0);
1926 /* We need dwords */
1927 offset
= offset
/ 4;
1928 for (int i
= 0; i
< instr
->num_components
; i
++) {
1929 ntq_store_dest(c
, &instr
->dest
, i
,
1930 vir_uniform(c
, QUNIFORM_UNIFORM
,
1934 ntq_emit_tmu_general(c
, instr
, false);
1939 ntq_emit_load_input(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
)
1941 /* XXX: Use ldvpmv (uniform offset) or ldvpmd (non-uniform offset)
1942 * and enable PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR.
1945 nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[0]);
1947 if (c
->s
->info
.stage
!= MESA_SHADER_FRAGMENT
&& c
->devinfo
->ver
>= 40) {
1948 /* Emit the LDVPM directly now, rather than at the top
1949 * of the shader like we did for V3D 3.x (which needs
1950 * vpmsetup when not just taking the next offset).
1952 * Note that delaying like this may introduce stalls,
1953 * as LDVPMV takes a minimum of 1 instruction but may
1954 * be slower if the VPM unit is busy with another QPU.
1957 if (c
->s
->info
.system_values_read
&
1958 (1ull << SYSTEM_VALUE_INSTANCE_ID
)) {
1961 if (c
->s
->info
.system_values_read
&
1962 (1ull << SYSTEM_VALUE_VERTEX_ID
)) {
1965 for (int i
= 0; i
< offset
; i
++)
1966 index
+= c
->vattr_sizes
[i
];
1967 index
+= nir_intrinsic_component(instr
);
1968 for (int i
= 0; i
< instr
->num_components
; i
++) {
1969 struct qreg vpm_offset
= vir_uniform_ui(c
, index
++);
1970 ntq_store_dest(c
, &instr
->dest
, i
,
1971 vir_LDVPMV_IN(c
, vpm_offset
));
1974 for (int i
= 0; i
< instr
->num_components
; i
++) {
1975 int comp
= nir_intrinsic_component(instr
) + i
;
1976 ntq_store_dest(c
, &instr
->dest
, i
,
1977 vir_MOV(c
, c
->inputs
[offset
* 4 + comp
]));
1983 ntq_emit_per_sample_color_write(struct v3d_compile
*c
,
1984 nir_intrinsic_instr
*instr
)
1986 assert(instr
->intrinsic
== nir_intrinsic_store_tlb_sample_color_v3d
);
1988 unsigned rt
= nir_src_as_uint(instr
->src
[1]);
1989 assert(rt
< V3D_MAX_DRAW_BUFFERS
);
1991 unsigned sample_idx
= nir_intrinsic_base(instr
);
1992 assert(sample_idx
< V3D_MAX_SAMPLES
);
1994 unsigned offset
= (rt
* V3D_MAX_SAMPLES
+ sample_idx
) * 4;
1995 for (int i
= 0; i
< instr
->num_components
; i
++) {
1996 c
->sample_colors
[offset
+ i
] =
1997 vir_MOV(c
, ntq_get_src(c
, instr
->src
[0], i
));
2002 ntq_emit_color_write(struct v3d_compile
*c
,
2003 nir_intrinsic_instr
*instr
)
2005 unsigned offset
= (nir_intrinsic_base(instr
) +
2006 nir_src_as_uint(instr
->src
[1])) * 4 +
2007 nir_intrinsic_component(instr
);
2008 for (int i
= 0; i
< instr
->num_components
; i
++) {
2009 c
->outputs
[offset
+ i
] =
2010 vir_MOV(c
, ntq_get_src(c
, instr
->src
[0], i
));
2015 emit_store_output_gs(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
)
2017 assert(instr
->num_components
== 1);
2019 uint32_t base_offset
= nir_intrinsic_base(instr
);
2020 struct qreg src_offset
= ntq_get_src(c
, instr
->src
[1], 0);
2021 struct qreg offset
=
2022 vir_ADD(c
, vir_uniform_ui(c
, base_offset
), src_offset
);
2024 /* Usually, for VS or FS, we only emit outputs once at program end so
2025 * our VPM writes are never in non-uniform control flow, but this
2026 * is not true for GS, where we are emitting multiple vertices.
2028 if (vir_in_nonuniform_control_flow(c
)) {
2029 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
),
2033 vir_VPM_WRITE_indirect(c
, ntq_get_src(c
, instr
->src
[0], 0), offset
);
2035 if (vir_in_nonuniform_control_flow(c
)) {
2036 struct qinst
*last_inst
=
2037 (struct qinst
*)c
->cur_block
->instructions
.prev
;
2038 vir_set_cond(last_inst
, V3D_QPU_COND_IFA
);
2043 ntq_emit_store_output(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
)
2045 /* XXX perf: Use stvpmv with uniform non-constant offsets and
2046 * stvpmd with non-uniform offsets and enable
2047 * PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR.
2049 if (c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
) {
2050 ntq_emit_color_write(c
, instr
);
2051 } else if (c
->s
->info
.stage
== MESA_SHADER_GEOMETRY
) {
2052 emit_store_output_gs(c
, instr
);
2054 assert(c
->s
->info
.stage
== MESA_SHADER_VERTEX
);
2055 assert(instr
->num_components
== 1);
2058 ntq_get_src(c
, instr
->src
[0], 0),
2059 nir_intrinsic_base(instr
));
2064 ntq_emit_intrinsic(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
)
2066 switch (instr
->intrinsic
) {
2067 case nir_intrinsic_load_uniform
:
2068 ntq_emit_load_uniform(c
, instr
);
2071 case nir_intrinsic_load_ubo
:
2072 ntq_emit_tmu_general(c
, instr
, false);
2075 case nir_intrinsic_ssbo_atomic_add
:
2076 case nir_intrinsic_ssbo_atomic_imin
:
2077 case nir_intrinsic_ssbo_atomic_umin
:
2078 case nir_intrinsic_ssbo_atomic_imax
:
2079 case nir_intrinsic_ssbo_atomic_umax
:
2080 case nir_intrinsic_ssbo_atomic_and
:
2081 case nir_intrinsic_ssbo_atomic_or
:
2082 case nir_intrinsic_ssbo_atomic_xor
:
2083 case nir_intrinsic_ssbo_atomic_exchange
:
2084 case nir_intrinsic_ssbo_atomic_comp_swap
:
2085 case nir_intrinsic_load_ssbo
:
2086 case nir_intrinsic_store_ssbo
:
2087 ntq_emit_tmu_general(c
, instr
, false);
2090 case nir_intrinsic_shared_atomic_add
:
2091 case nir_intrinsic_shared_atomic_imin
:
2092 case nir_intrinsic_shared_atomic_umin
:
2093 case nir_intrinsic_shared_atomic_imax
:
2094 case nir_intrinsic_shared_atomic_umax
:
2095 case nir_intrinsic_shared_atomic_and
:
2096 case nir_intrinsic_shared_atomic_or
:
2097 case nir_intrinsic_shared_atomic_xor
:
2098 case nir_intrinsic_shared_atomic_exchange
:
2099 case nir_intrinsic_shared_atomic_comp_swap
:
2100 case nir_intrinsic_load_shared
:
2101 case nir_intrinsic_store_shared
:
2102 case nir_intrinsic_load_scratch
:
2103 case nir_intrinsic_store_scratch
:
2104 ntq_emit_tmu_general(c
, instr
, true);
2107 case nir_intrinsic_image_deref_load
:
2108 case nir_intrinsic_image_deref_store
:
2109 case nir_intrinsic_image_deref_atomic_add
:
2110 case nir_intrinsic_image_deref_atomic_imin
:
2111 case nir_intrinsic_image_deref_atomic_umin
:
2112 case nir_intrinsic_image_deref_atomic_imax
:
2113 case nir_intrinsic_image_deref_atomic_umax
:
2114 case nir_intrinsic_image_deref_atomic_and
:
2115 case nir_intrinsic_image_deref_atomic_or
:
2116 case nir_intrinsic_image_deref_atomic_xor
:
2117 case nir_intrinsic_image_deref_atomic_exchange
:
2118 case nir_intrinsic_image_deref_atomic_comp_swap
:
2119 v3d40_vir_emit_image_load_store(c
, instr
);
2122 case nir_intrinsic_get_buffer_size
:
2123 ntq_store_dest(c
, &instr
->dest
, 0,
2124 vir_uniform(c
, QUNIFORM_GET_BUFFER_SIZE
,
2125 nir_src_as_uint(instr
->src
[0])));
2128 case nir_intrinsic_load_user_clip_plane
:
2129 for (int i
= 0; i
< instr
->num_components
; i
++) {
2130 ntq_store_dest(c
, &instr
->dest
, i
,
2131 vir_uniform(c
, QUNIFORM_USER_CLIP_PLANE
,
2132 nir_intrinsic_ucp_id(instr
) *
2137 case nir_intrinsic_load_viewport_x_scale
:
2138 ntq_store_dest(c
, &instr
->dest
, 0,
2139 vir_uniform(c
, QUNIFORM_VIEWPORT_X_SCALE
, 0));
2142 case nir_intrinsic_load_viewport_y_scale
:
2143 ntq_store_dest(c
, &instr
->dest
, 0,
2144 vir_uniform(c
, QUNIFORM_VIEWPORT_Y_SCALE
, 0));
2147 case nir_intrinsic_load_viewport_z_scale
:
2148 ntq_store_dest(c
, &instr
->dest
, 0,
2149 vir_uniform(c
, QUNIFORM_VIEWPORT_Z_SCALE
, 0));
2152 case nir_intrinsic_load_viewport_z_offset
:
2153 ntq_store_dest(c
, &instr
->dest
, 0,
2154 vir_uniform(c
, QUNIFORM_VIEWPORT_Z_OFFSET
, 0));
2157 case nir_intrinsic_load_alpha_ref_float
:
2158 ntq_store_dest(c
, &instr
->dest
, 0,
2159 vir_uniform(c
, QUNIFORM_ALPHA_REF
, 0));
2162 case nir_intrinsic_load_sample_mask_in
:
2163 ntq_store_dest(c
, &instr
->dest
, 0, vir_MSF(c
));
2166 case nir_intrinsic_load_helper_invocation
:
2167 vir_set_pf(vir_MSF_dest(c
, vir_nop_reg()), V3D_QPU_PF_PUSHZ
);
2168 ntq_store_dest(c
, &instr
->dest
, 0,
2169 vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFA
,
2170 vir_uniform_ui(c
, ~0),
2171 vir_uniform_ui(c
, 0))));
2174 case nir_intrinsic_load_front_face
:
2175 /* The register contains 0 (front) or 1 (back), and we need to
2176 * turn it into a NIR bool where true means front.
2178 ntq_store_dest(c
, &instr
->dest
, 0,
2180 vir_uniform_ui(c
, -1),
2184 case nir_intrinsic_load_instance_id
:
2185 ntq_store_dest(c
, &instr
->dest
, 0, vir_MOV(c
, c
->iid
));
2188 case nir_intrinsic_load_vertex_id
:
2189 ntq_store_dest(c
, &instr
->dest
, 0, vir_MOV(c
, c
->vid
));
2192 case nir_intrinsic_load_tlb_color_v3d
:
2193 vir_emit_tlb_color_read(c
, instr
);
2196 case nir_intrinsic_load_input
:
2197 ntq_emit_load_input(c
, instr
);
2200 case nir_intrinsic_store_tlb_sample_color_v3d
:
2201 ntq_emit_per_sample_color_write(c
, instr
);
2204 case nir_intrinsic_store_output
:
2205 ntq_emit_store_output(c
, instr
);
2208 case nir_intrinsic_image_deref_size
:
2209 ntq_emit_image_size(c
, instr
);
2212 case nir_intrinsic_discard
:
2213 if (vir_in_nonuniform_control_flow(c
)) {
2214 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
),
2216 vir_set_cond(vir_SETMSF_dest(c
, vir_nop_reg(),
2217 vir_uniform_ui(c
, 0)),
2220 vir_SETMSF_dest(c
, vir_nop_reg(),
2221 vir_uniform_ui(c
, 0));
2225 case nir_intrinsic_discard_if
: {
2226 enum v3d_qpu_cond cond
= ntq_emit_bool_to_cond(c
, instr
->src
[0]);
2228 if (vir_in_nonuniform_control_flow(c
)) {
2229 struct qinst
*exec_flag
= vir_MOV_dest(c
, vir_nop_reg(),
2231 if (cond
== V3D_QPU_COND_IFA
) {
2232 vir_set_uf(exec_flag
, V3D_QPU_UF_ANDZ
);
2234 vir_set_uf(exec_flag
, V3D_QPU_UF_NORNZ
);
2235 cond
= V3D_QPU_COND_IFA
;
2239 vir_set_cond(vir_SETMSF_dest(c
, vir_nop_reg(),
2240 vir_uniform_ui(c
, 0)), cond
);
2245 case nir_intrinsic_memory_barrier
:
2246 case nir_intrinsic_memory_barrier_atomic_counter
:
2247 case nir_intrinsic_memory_barrier_buffer
:
2248 case nir_intrinsic_memory_barrier_image
:
2249 case nir_intrinsic_memory_barrier_shared
:
2250 case nir_intrinsic_memory_barrier_tcs_patch
:
2251 case nir_intrinsic_group_memory_barrier
:
2252 /* We don't do any instruction scheduling of these NIR
2253 * instructions between each other, so we just need to make
2254 * sure that the TMU operations before the barrier are flushed
2255 * before the ones after the barrier. That is currently
2256 * handled by having a THRSW in each of them and a LDTMU
2257 * series or a TMUWT after.
2261 case nir_intrinsic_barrier
:
2262 /* Emit a TSY op to get all invocations in the workgroup
2263 * (actually supergroup) to block until the last invocation
2264 * reaches the TSY op.
2266 if (c
->devinfo
->ver
>= 42) {
2267 vir_BARRIERID_dest(c
, vir_reg(QFILE_MAGIC
,
2268 V3D_QPU_WADDR_SYNCB
));
2270 struct qinst
*sync
=
2271 vir_BARRIERID_dest(c
,
2272 vir_reg(QFILE_MAGIC
,
2273 V3D_QPU_WADDR_SYNCU
));
2275 vir_get_uniform_index(c
, QUNIFORM_CONSTANT
,
2277 V3D_TSY_WAIT_INC_CHECK
);
2281 /* The blocking of a TSY op only happens at the next thread
2282 * switch. No texturing may be outstanding at the time of a
2283 * TSY blocking operation.
2288 case nir_intrinsic_load_num_work_groups
:
2289 for (int i
= 0; i
< 3; i
++) {
2290 ntq_store_dest(c
, &instr
->dest
, i
,
2291 vir_uniform(c
, QUNIFORM_NUM_WORK_GROUPS
,
2296 case nir_intrinsic_load_local_invocation_index
:
2297 ntq_store_dest(c
, &instr
->dest
, 0,
2298 vir_SHR(c
, c
->cs_payload
[1],
2299 vir_uniform_ui(c
, 32 - c
->local_invocation_index_bits
)));
2302 case nir_intrinsic_load_work_group_id
:
2303 ntq_store_dest(c
, &instr
->dest
, 0,
2304 vir_AND(c
, c
->cs_payload
[0],
2305 vir_uniform_ui(c
, 0xffff)));
2306 ntq_store_dest(c
, &instr
->dest
, 1,
2307 vir_SHR(c
, c
->cs_payload
[0],
2308 vir_uniform_ui(c
, 16)));
2309 ntq_store_dest(c
, &instr
->dest
, 2,
2310 vir_AND(c
, c
->cs_payload
[1],
2311 vir_uniform_ui(c
, 0xffff)));
2314 case nir_intrinsic_load_subgroup_id
:
2315 ntq_store_dest(c
, &instr
->dest
, 0, vir_EIDX(c
));
2318 case nir_intrinsic_load_per_vertex_input
: {
2319 /* col: vertex index, row = varying index */
2320 struct qreg col
= ntq_get_src(c
, instr
->src
[0], 0);
2321 uint32_t row_idx
= nir_intrinsic_base(instr
) * 4 +
2322 nir_intrinsic_component(instr
);
2323 for (int i
= 0; i
< instr
->num_components
; i
++) {
2324 struct qreg row
= vir_uniform_ui(c
, row_idx
++);
2325 ntq_store_dest(c
, &instr
->dest
, i
,
2326 vir_LDVPMG_IN(c
, row
, col
));
2331 case nir_intrinsic_emit_vertex
:
2332 case nir_intrinsic_end_primitive
:
2333 unreachable("Should have been lowered in v3d_nir_lower_io");
2336 case nir_intrinsic_load_primitive_id
: {
2337 /* gl_PrimitiveIdIn is written by the GBG in the first word of
2338 * VPM output header. According to docs, we should read this
2339 * using ldvpm(v,d)_in (See Table 71).
2341 ntq_store_dest(c
, &instr
->dest
, 0,
2342 vir_LDVPMV_IN(c
, vir_uniform_ui(c
, 0)));
2346 case nir_intrinsic_load_invocation_id
:
2347 ntq_store_dest(c
, &instr
->dest
, 0, vir_IID(c
));
2350 case nir_intrinsic_load_fb_layers_v3d
:
2351 ntq_store_dest(c
, &instr
->dest
, 0,
2352 vir_uniform(c
, QUNIFORM_FB_LAYERS
, 0));
2356 fprintf(stderr
, "Unknown intrinsic: ");
2357 nir_print_instr(&instr
->instr
, stderr
);
2358 fprintf(stderr
, "\n");
2363 /* Clears (activates) the execute flags for any channels whose jump target
2364 * matches this block.
2366 * XXX perf: Could we be using flpush/flpop somehow for our execution channel
2369 * XXX perf: For uniform control flow, we should be able to skip c->execute
2370 * handling entirely.
2373 ntq_activate_execute_for_block(struct v3d_compile
*c
)
2375 vir_set_pf(vir_XOR_dest(c
, vir_nop_reg(),
2376 c
->execute
, vir_uniform_ui(c
, c
->cur_block
->index
)),
2379 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
, vir_uniform_ui(c
, 0));
2383 ntq_emit_uniform_if(struct v3d_compile
*c
, nir_if
*if_stmt
)
2385 nir_block
*nir_else_block
= nir_if_first_else_block(if_stmt
);
2386 bool empty_else_block
=
2387 (nir_else_block
== nir_if_last_else_block(if_stmt
) &&
2388 exec_list_is_empty(&nir_else_block
->instr_list
));
2390 struct qblock
*then_block
= vir_new_block(c
);
2391 struct qblock
*after_block
= vir_new_block(c
);
2392 struct qblock
*else_block
;
2393 if (empty_else_block
)
2394 else_block
= after_block
;
2396 else_block
= vir_new_block(c
);
2398 /* Set up the flags for the IF condition (taking the THEN branch). */
2399 enum v3d_qpu_cond cond
= ntq_emit_bool_to_cond(c
, if_stmt
->condition
);
2402 vir_BRANCH(c
, cond
== V3D_QPU_COND_IFA
?
2403 V3D_QPU_BRANCH_COND_ALLNA
:
2404 V3D_QPU_BRANCH_COND_ALLA
);
2405 vir_link_blocks(c
->cur_block
, else_block
);
2406 vir_link_blocks(c
->cur_block
, then_block
);
2408 /* Process the THEN block. */
2409 vir_set_emit_block(c
, then_block
);
2410 ntq_emit_cf_list(c
, &if_stmt
->then_list
);
2412 if (!empty_else_block
) {
2413 /* At the end of the THEN block, jump to ENDIF */
2414 vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ALWAYS
);
2415 vir_link_blocks(c
->cur_block
, after_block
);
2417 /* Emit the else block. */
2418 vir_set_emit_block(c
, else_block
);
2419 ntq_emit_cf_list(c
, &if_stmt
->else_list
);
2422 vir_link_blocks(c
->cur_block
, after_block
);
2424 vir_set_emit_block(c
, after_block
);
2428 ntq_emit_nonuniform_if(struct v3d_compile
*c
, nir_if
*if_stmt
)
2430 nir_block
*nir_else_block
= nir_if_first_else_block(if_stmt
);
2431 bool empty_else_block
=
2432 (nir_else_block
== nir_if_last_else_block(if_stmt
) &&
2433 exec_list_is_empty(&nir_else_block
->instr_list
));
2435 struct qblock
*then_block
= vir_new_block(c
);
2436 struct qblock
*after_block
= vir_new_block(c
);
2437 struct qblock
*else_block
;
2438 if (empty_else_block
)
2439 else_block
= after_block
;
2441 else_block
= vir_new_block(c
);
2443 bool was_uniform_control_flow
= false;
2444 if (!vir_in_nonuniform_control_flow(c
)) {
2445 c
->execute
= vir_MOV(c
, vir_uniform_ui(c
, 0));
2446 was_uniform_control_flow
= true;
2449 /* Set up the flags for the IF condition (taking the THEN branch). */
2450 enum v3d_qpu_cond cond
= ntq_emit_bool_to_cond(c
, if_stmt
->condition
);
2452 /* Update the flags+cond to mean "Taking the ELSE branch (!cond) and
2453 * was previously active (execute Z) for updating the exec flags.
2455 if (was_uniform_control_flow
) {
2456 cond
= v3d_qpu_cond_invert(cond
);
2458 struct qinst
*inst
= vir_MOV_dest(c
, vir_nop_reg(), c
->execute
);
2459 if (cond
== V3D_QPU_COND_IFA
) {
2460 vir_set_uf(inst
, V3D_QPU_UF_NORNZ
);
2462 vir_set_uf(inst
, V3D_QPU_UF_ANDZ
);
2463 cond
= V3D_QPU_COND_IFA
;
2467 vir_MOV_cond(c
, cond
,
2469 vir_uniform_ui(c
, else_block
->index
));
2471 /* Jump to ELSE if nothing is active for THEN, otherwise fall
2474 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
), V3D_QPU_PF_PUSHZ
);
2475 vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ALLNA
);
2476 vir_link_blocks(c
->cur_block
, else_block
);
2477 vir_link_blocks(c
->cur_block
, then_block
);
2479 /* Process the THEN block. */
2480 vir_set_emit_block(c
, then_block
);
2481 ntq_emit_cf_list(c
, &if_stmt
->then_list
);
2483 if (!empty_else_block
) {
2484 /* Handle the end of the THEN block. First, all currently
2485 * active channels update their execute flags to point to
2488 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
),
2490 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
,
2491 vir_uniform_ui(c
, after_block
->index
));
2493 /* If everything points at ENDIF, then jump there immediately. */
2494 vir_set_pf(vir_XOR_dest(c
, vir_nop_reg(),
2496 vir_uniform_ui(c
, after_block
->index
)),
2498 vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ALLA
);
2499 vir_link_blocks(c
->cur_block
, after_block
);
2500 vir_link_blocks(c
->cur_block
, else_block
);
2502 vir_set_emit_block(c
, else_block
);
2503 ntq_activate_execute_for_block(c
);
2504 ntq_emit_cf_list(c
, &if_stmt
->else_list
);
2507 vir_link_blocks(c
->cur_block
, after_block
);
2509 vir_set_emit_block(c
, after_block
);
2510 if (was_uniform_control_flow
)
2511 c
->execute
= c
->undef
;
2513 ntq_activate_execute_for_block(c
);
2517 ntq_emit_if(struct v3d_compile
*c
, nir_if
*nif
)
2519 bool was_in_control_flow
= c
->in_control_flow
;
2520 c
->in_control_flow
= true;
2521 if (!vir_in_nonuniform_control_flow(c
) &&
2522 nir_src_is_dynamically_uniform(nif
->condition
)) {
2523 ntq_emit_uniform_if(c
, nif
);
2525 ntq_emit_nonuniform_if(c
, nif
);
2527 c
->in_control_flow
= was_in_control_flow
;
2531 ntq_emit_jump(struct v3d_compile
*c
, nir_jump_instr
*jump
)
2533 switch (jump
->type
) {
2534 case nir_jump_break
:
2535 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
),
2537 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
,
2538 vir_uniform_ui(c
, c
->loop_break_block
->index
));
2541 case nir_jump_continue
:
2542 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
),
2544 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
,
2545 vir_uniform_ui(c
, c
->loop_cont_block
->index
));
2548 case nir_jump_return
:
2549 unreachable("All returns shouold be lowered\n");
2554 ntq_emit_instr(struct v3d_compile
*c
, nir_instr
*instr
)
2556 switch (instr
->type
) {
2557 case nir_instr_type_deref
:
2558 /* ignored, will be walked by the intrinsic using it. */
2561 case nir_instr_type_alu
:
2562 ntq_emit_alu(c
, nir_instr_as_alu(instr
));
2565 case nir_instr_type_intrinsic
:
2566 ntq_emit_intrinsic(c
, nir_instr_as_intrinsic(instr
));
2569 case nir_instr_type_load_const
:
2570 ntq_emit_load_const(c
, nir_instr_as_load_const(instr
));
2573 case nir_instr_type_ssa_undef
:
2574 ntq_emit_ssa_undef(c
, nir_instr_as_ssa_undef(instr
));
2577 case nir_instr_type_tex
:
2578 ntq_emit_tex(c
, nir_instr_as_tex(instr
));
2581 case nir_instr_type_jump
:
2582 ntq_emit_jump(c
, nir_instr_as_jump(instr
));
2586 fprintf(stderr
, "Unknown NIR instr type: ");
2587 nir_print_instr(instr
, stderr
);
2588 fprintf(stderr
, "\n");
2594 ntq_emit_block(struct v3d_compile
*c
, nir_block
*block
)
2596 nir_foreach_instr(instr
, block
) {
2597 ntq_emit_instr(c
, instr
);
2601 static void ntq_emit_cf_list(struct v3d_compile
*c
, struct exec_list
*list
);
2604 ntq_emit_loop(struct v3d_compile
*c
, nir_loop
*loop
)
2606 bool was_in_control_flow
= c
->in_control_flow
;
2607 c
->in_control_flow
= true;
2609 bool was_uniform_control_flow
= false;
2610 if (!vir_in_nonuniform_control_flow(c
)) {
2611 c
->execute
= vir_MOV(c
, vir_uniform_ui(c
, 0));
2612 was_uniform_control_flow
= true;
2615 struct qblock
*save_loop_cont_block
= c
->loop_cont_block
;
2616 struct qblock
*save_loop_break_block
= c
->loop_break_block
;
2618 c
->loop_cont_block
= vir_new_block(c
);
2619 c
->loop_break_block
= vir_new_block(c
);
2621 vir_link_blocks(c
->cur_block
, c
->loop_cont_block
);
2622 vir_set_emit_block(c
, c
->loop_cont_block
);
2623 ntq_activate_execute_for_block(c
);
2625 ntq_emit_cf_list(c
, &loop
->body
);
2627 /* Re-enable any previous continues now, so our ANYA check below
2630 * XXX: Use the .ORZ flags update, instead.
2632 vir_set_pf(vir_XOR_dest(c
,
2635 vir_uniform_ui(c
, c
->loop_cont_block
->index
)),
2637 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
, vir_uniform_ui(c
, 0));
2639 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
), V3D_QPU_PF_PUSHZ
);
2641 struct qinst
*branch
= vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ANYA
);
2642 /* Pixels that were not dispatched or have been discarded should not
2643 * contribute to looping again.
2645 branch
->qpu
.branch
.msfign
= V3D_QPU_MSFIGN_P
;
2646 vir_link_blocks(c
->cur_block
, c
->loop_cont_block
);
2647 vir_link_blocks(c
->cur_block
, c
->loop_break_block
);
2649 vir_set_emit_block(c
, c
->loop_break_block
);
2650 if (was_uniform_control_flow
)
2651 c
->execute
= c
->undef
;
2653 ntq_activate_execute_for_block(c
);
2655 c
->loop_break_block
= save_loop_break_block
;
2656 c
->loop_cont_block
= save_loop_cont_block
;
2660 c
->in_control_flow
= was_in_control_flow
;
2664 ntq_emit_function(struct v3d_compile
*c
, nir_function_impl
*func
)
2666 fprintf(stderr
, "FUNCTIONS not handled.\n");
2671 ntq_emit_cf_list(struct v3d_compile
*c
, struct exec_list
*list
)
2673 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2674 switch (node
->type
) {
2675 case nir_cf_node_block
:
2676 ntq_emit_block(c
, nir_cf_node_as_block(node
));
2679 case nir_cf_node_if
:
2680 ntq_emit_if(c
, nir_cf_node_as_if(node
));
2683 case nir_cf_node_loop
:
2684 ntq_emit_loop(c
, nir_cf_node_as_loop(node
));
2687 case nir_cf_node_function
:
2688 ntq_emit_function(c
, nir_cf_node_as_function(node
));
2692 fprintf(stderr
, "Unknown NIR node type\n");
2699 ntq_emit_impl(struct v3d_compile
*c
, nir_function_impl
*impl
)
2701 ntq_setup_registers(c
, &impl
->registers
);
2702 ntq_emit_cf_list(c
, &impl
->body
);
2706 nir_to_vir(struct v3d_compile
*c
)
2708 switch (c
->s
->info
.stage
) {
2709 case MESA_SHADER_FRAGMENT
:
2710 c
->payload_w
= vir_MOV(c
, vir_reg(QFILE_REG
, 0));
2711 c
->payload_w_centroid
= vir_MOV(c
, vir_reg(QFILE_REG
, 1));
2712 c
->payload_z
= vir_MOV(c
, vir_reg(QFILE_REG
, 2));
2714 /* V3D 4.x can disable implicit point coordinate varyings if
2715 * they are not used.
2717 if (c
->fs_key
->is_points
&&
2718 (c
->devinfo
->ver
< 40 || program_reads_point_coord(c
))) {
2719 c
->point_x
= emit_fragment_varying(c
, NULL
, 0, 0);
2720 c
->point_y
= emit_fragment_varying(c
, NULL
, 0, 0);
2721 c
->uses_implicit_point_line_varyings
= true;
2722 } else if (c
->fs_key
->is_lines
&& c
->devinfo
->ver
< 40) {
2723 c
->line_x
= emit_fragment_varying(c
, NULL
, 0, 0);
2724 c
->uses_implicit_point_line_varyings
= true;
2727 case MESA_SHADER_COMPUTE
:
2728 /* Set up the TSO for barriers, assuming we do some. */
2729 if (c
->devinfo
->ver
< 42) {
2730 vir_BARRIERID_dest(c
, vir_reg(QFILE_MAGIC
,
2731 V3D_QPU_WADDR_SYNC
));
2734 c
->cs_payload
[0] = vir_MOV(c
, vir_reg(QFILE_REG
, 0));
2735 c
->cs_payload
[1] = vir_MOV(c
, vir_reg(QFILE_REG
, 2));
2737 /* Set up the division between gl_LocalInvocationIndex and
2738 * wg_in_mem in the payload reg.
2740 int wg_size
= (c
->s
->info
.cs
.local_size
[0] *
2741 c
->s
->info
.cs
.local_size
[1] *
2742 c
->s
->info
.cs
.local_size
[2]);
2743 c
->local_invocation_index_bits
=
2744 ffs(util_next_power_of_two(MAX2(wg_size
, 64))) - 1;
2745 assert(c
->local_invocation_index_bits
<= 8);
2747 if (c
->s
->info
.cs
.shared_size
) {
2748 struct qreg wg_in_mem
= vir_SHR(c
, c
->cs_payload
[1],
2749 vir_uniform_ui(c
, 16));
2750 if (c
->s
->info
.cs
.local_size
[0] != 1 ||
2751 c
->s
->info
.cs
.local_size
[1] != 1 ||
2752 c
->s
->info
.cs
.local_size
[2] != 1) {
2754 c
->local_invocation_index_bits
);
2755 int wg_mask
= (1 << wg_bits
) - 1;
2756 wg_in_mem
= vir_AND(c
, wg_in_mem
,
2757 vir_uniform_ui(c
, wg_mask
));
2759 struct qreg shared_per_wg
=
2760 vir_uniform_ui(c
, c
->s
->info
.cs
.shared_size
);
2762 c
->cs_shared_offset
=
2764 vir_uniform(c
, QUNIFORM_SHARED_OFFSET
,0),
2765 vir_UMUL(c
, wg_in_mem
, shared_per_wg
));
2772 if (c
->s
->scratch_size
) {
2773 v3d_setup_spill_base(c
);
2774 c
->spill_size
+= V3D_CHANNELS
* c
->s
->scratch_size
;
2777 switch (c
->s
->info
.stage
) {
2778 case MESA_SHADER_VERTEX
:
2779 ntq_setup_vs_inputs(c
);
2781 case MESA_SHADER_GEOMETRY
:
2782 ntq_setup_gs_inputs(c
);
2784 case MESA_SHADER_FRAGMENT
:
2785 ntq_setup_fs_inputs(c
);
2787 case MESA_SHADER_COMPUTE
:
2790 unreachable("unsupported shader stage");
2793 ntq_setup_outputs(c
);
2795 /* Find the main function and emit the body. */
2796 nir_foreach_function(function
, c
->s
) {
2797 assert(strcmp(function
->name
, "main") == 0);
2798 assert(function
->impl
);
2799 ntq_emit_impl(c
, function
->impl
);
2803 const nir_shader_compiler_options v3d_nir_options
= {
2804 .lower_all_io_to_temps
= true,
2805 .lower_extract_byte
= true,
2806 .lower_extract_word
= true,
2807 .lower_bitfield_insert_to_shifts
= true,
2808 .lower_bitfield_extract_to_shifts
= true,
2809 .lower_bitfield_reverse
= true,
2810 .lower_bit_count
= true,
2811 .lower_cs_local_id_from_index
= true,
2812 .lower_ffract
= true,
2814 .lower_pack_unorm_2x16
= true,
2815 .lower_pack_snorm_2x16
= true,
2816 .lower_pack_unorm_4x8
= true,
2817 .lower_pack_snorm_4x8
= true,
2818 .lower_unpack_unorm_4x8
= true,
2819 .lower_unpack_snorm_4x8
= true,
2820 .lower_pack_half_2x16
= true,
2821 .lower_unpack_half_2x16
= true,
2823 .lower_find_lsb
= true,
2825 .lower_flrp32
= true,
2828 .lower_fsqrt
= true,
2829 .lower_ifind_msb
= true,
2830 .lower_isign
= true,
2831 .lower_ldexp
= true,
2832 .lower_mul_high
= true,
2833 .lower_wpos_pntc
= true,
2834 .lower_rotate
= true,
2835 .lower_to_scalar
= true,
2839 * When demoting a shader down to single-threaded, removes the THRSW
2840 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
2844 vir_remove_thrsw(struct v3d_compile
*c
)
2846 vir_for_each_block(block
, c
) {
2847 vir_for_each_inst_safe(inst
, block
) {
2848 if (inst
->qpu
.sig
.thrsw
)
2849 vir_remove_instruction(c
, inst
);
2853 c
->last_thrsw
= NULL
;
2857 vir_emit_last_thrsw(struct v3d_compile
*c
)
2859 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
2860 * switching, so disable threads if we didn't do any TMU ops (each of
2861 * which would have emitted a THRSW).
2863 if (!c
->last_thrsw_at_top_level
&& c
->devinfo
->ver
< 41) {
2866 vir_remove_thrsw(c
);
2870 /* If we're threaded and the last THRSW was in conditional code, then
2871 * we need to emit another one so that we can flag it as the last
2874 if (c
->last_thrsw
&& !c
->last_thrsw_at_top_level
) {
2875 assert(c
->devinfo
->ver
>= 41);
2879 /* If we're threaded, then we need to mark the last THRSW instruction
2880 * so we can emit a pair of them at QPU emit time.
2882 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2883 * post-last-THRSW state, so we can skip this.
2885 if (!c
->last_thrsw
&& c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
) {
2886 assert(c
->devinfo
->ver
>= 41);
2891 c
->last_thrsw
->is_last_thrsw
= true;
2894 /* There's a flag in the shader for "center W is needed for reasons other than
2895 * non-centroid varyings", so we just walk the program after VIR optimization
2896 * to see if it's used. It should be harmless to set even if we only use
2897 * center W for varyings.
2900 vir_check_payload_w(struct v3d_compile
*c
)
2902 if (c
->s
->info
.stage
!= MESA_SHADER_FRAGMENT
)
2905 vir_for_each_inst_inorder(inst
, c
) {
2906 for (int i
= 0; i
< vir_get_nsrc(inst
); i
++) {
2907 if (inst
->src
[i
].file
== QFILE_REG
&&
2908 inst
->src
[i
].index
== 0) {
2909 c
->uses_center_w
= true;
2918 v3d_nir_to_vir(struct v3d_compile
*c
)
2920 if (V3D_DEBUG
& (V3D_DEBUG_NIR
|
2921 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
))) {
2922 fprintf(stderr
, "%s prog %d/%d NIR:\n",
2923 vir_get_stage_name(c
),
2924 c
->program_id
, c
->variant_id
);
2925 nir_print_shader(c
->s
, stderr
);
2930 /* Emit the last THRSW before STVPM and TLB writes. */
2931 vir_emit_last_thrsw(c
);
2933 switch (c
->s
->info
.stage
) {
2934 case MESA_SHADER_FRAGMENT
:
2937 case MESA_SHADER_GEOMETRY
:
2940 case MESA_SHADER_VERTEX
:
2943 case MESA_SHADER_COMPUTE
:
2946 unreachable("bad stage");
2949 if (V3D_DEBUG
& (V3D_DEBUG_VIR
|
2950 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
))) {
2951 fprintf(stderr
, "%s prog %d/%d pre-opt VIR:\n",
2952 vir_get_stage_name(c
),
2953 c
->program_id
, c
->variant_id
);
2955 fprintf(stderr
, "\n");
2960 vir_check_payload_w(c
);
2962 /* XXX perf: On VC4, we do a VIR-level instruction scheduling here.
2963 * We used that on that platform to pipeline TMU writes and reduce the
2964 * number of thread switches, as well as try (mostly successfully) to
2965 * reduce maximum register pressure to allow more threads. We should
2966 * do something of that sort for V3D -- either instruction scheduling
2967 * here, or delay the the THRSW and LDTMUs from our texture
2968 * instructions until the results are needed.
2971 if (V3D_DEBUG
& (V3D_DEBUG_VIR
|
2972 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
))) {
2973 fprintf(stderr
, "%s prog %d/%d VIR:\n",
2974 vir_get_stage_name(c
),
2975 c
->program_id
, c
->variant_id
);
2977 fprintf(stderr
, "\n");
2980 /* Attempt to allocate registers for the temporaries. If we fail,
2981 * reduce thread count and try again.
2983 int min_threads
= (c
->devinfo
->ver
>= 41) ? 2 : 1;
2984 struct qpu_reg
*temp_registers
;
2987 temp_registers
= v3d_register_allocate(c
, &spilled
);
2994 if (c
->threads
== min_threads
) {
2995 fprintf(stderr
, "Failed to register allocate at %d threads:\n",
3004 if (c
->threads
== 1)
3005 vir_remove_thrsw(c
);
3009 (V3D_DEBUG
& (V3D_DEBUG_VIR
|
3010 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
)))) {
3011 fprintf(stderr
, "%s prog %d/%d spilled VIR:\n",
3012 vir_get_stage_name(c
),
3013 c
->program_id
, c
->variant_id
);
3015 fprintf(stderr
, "\n");
3018 v3d_vir_to_qpu(c
, temp_registers
);