projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
v3d: add debug assert
[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/format/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
34
35 /* We don't do any address packing. */
36 #define __gen_user_data void
37 #define __gen_address_type uint32_t
38 #define __gen_address_offset(reloc) (*reloc)
39 #define __gen_emit_reloc(cl, reloc)
40 #include "cle/v3d_packet_v41_pack.h"
41
42 #define GENERAL_TMU_LOOKUP_PER_QUAD (0 << 7)
43 #define GENERAL_TMU_LOOKUP_PER_PIXEL (1 << 7)
44 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_I (0 << 0)
45 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_I (1 << 0)
46 #define GENERAL_TMU_LOOKUP_TYPE_VEC2 (2 << 0)
47 #define GENERAL_TMU_LOOKUP_TYPE_VEC3 (3 << 0)
48 #define GENERAL_TMU_LOOKUP_TYPE_VEC4 (4 << 0)
49 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_UI (5 << 0)
50 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_UI (6 << 0)
51 #define GENERAL_TMU_LOOKUP_TYPE_32BIT_UI (7 << 0)
52
53 #define V3D_TSY_SET_QUORUM 0
54 #define V3D_TSY_INC_WAITERS 1
55 #define V3D_TSY_DEC_WAITERS 2
56 #define V3D_TSY_INC_QUORUM 3
57 #define V3D_TSY_DEC_QUORUM 4
58 #define V3D_TSY_FREE_ALL 5
59 #define V3D_TSY_RELEASE 6
60 #define V3D_TSY_ACQUIRE 7
61 #define V3D_TSY_WAIT 8
62 #define V3D_TSY_WAIT_INC 9
63 #define V3D_TSY_WAIT_CHECK 10
64 #define V3D_TSY_WAIT_INC_CHECK 11
65 #define V3D_TSY_WAIT_CV 12
66 #define V3D_TSY_INC_SEMAPHORE 13
67 #define V3D_TSY_DEC_SEMAPHORE 14
68 #define V3D_TSY_SET_QUORUM_FREE_ALL 15
69
70 static void
71 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
72
73 static void
74 resize_qreg_array(struct v3d_compile *c,
75 struct qreg **regs,
76 uint32_t *size,
77 uint32_t decl_size)
78 {
79 if (*size >= decl_size)
80 return;
81
82 uint32_t old_size = *size;
83 *size = MAX2(*size * 2, decl_size);
84 *regs = reralloc(c, *regs, struct qreg, *size);
85 if (!*regs) {
86 fprintf(stderr, "Malloc failure\n");
87 abort();
88 }
89
90 for (uint32_t i = old_size; i < *size; i++)
91 (*regs)[i] = c->undef;
92 }
93
94 void
95 vir_emit_thrsw(struct v3d_compile *c)
96 {
97 if (c->threads == 1)
98 return;
99
100 /* Always thread switch after each texture operation for now.
101 *
102 * We could do better by batching a bunch of texture fetches up and
103 * then doing one thread switch and collecting all their results
104 * afterward.
105 */
106 c->last_thrsw = vir_NOP(c);
107 c->last_thrsw->qpu.sig.thrsw = true;
108 c->last_thrsw_at_top_level = !c->in_control_flow;
109
110 /* We need to lock the scoreboard before any tlb acess happens. If this
111 * thread switch comes after we have emitted a tlb load, then it means
112 * that we can't lock on the last thread switch any more.
113 */
114 if (c->emitted_tlb_load)
115 c->lock_scoreboard_on_first_thrsw = true;
116 }
117
118 uint32_t
119 v3d_get_op_for_atomic_add(nir_intrinsic_instr *instr, unsigned src)
120 {
121 if (nir_src_is_const(instr->src[src])) {
122 int64_t add_val = nir_src_as_int(instr->src[src]);
123 if (add_val == 1)
124 return V3D_TMU_OP_WRITE_AND_READ_INC;
125 else if (add_val == -1)
126 return V3D_TMU_OP_WRITE_OR_READ_DEC;
127 }
128
129 return V3D_TMU_OP_WRITE_ADD_READ_PREFETCH;
130 }
131
132 static uint32_t
133 v3d_general_tmu_op(nir_intrinsic_instr *instr)
134 {
135 switch (instr->intrinsic) {
136 case nir_intrinsic_load_ssbo:
137 case nir_intrinsic_load_ubo:
138 case nir_intrinsic_load_uniform:
139 case nir_intrinsic_load_shared:
140 case nir_intrinsic_load_scratch:
141 case nir_intrinsic_store_ssbo:
142 case nir_intrinsic_store_shared:
143 case nir_intrinsic_store_scratch:
144 return V3D_TMU_OP_REGULAR;
145 case nir_intrinsic_ssbo_atomic_add:
146 return v3d_get_op_for_atomic_add(instr, 2);
147 case nir_intrinsic_shared_atomic_add:
148 return v3d_get_op_for_atomic_add(instr, 1);
149 case nir_intrinsic_ssbo_atomic_imin:
150 case nir_intrinsic_shared_atomic_imin:
151 return V3D_TMU_OP_WRITE_SMIN;
152 case nir_intrinsic_ssbo_atomic_umin:
153 case nir_intrinsic_shared_atomic_umin:
154 return V3D_TMU_OP_WRITE_UMIN_FULL_L1_CLEAR;
155 case nir_intrinsic_ssbo_atomic_imax:
156 case nir_intrinsic_shared_atomic_imax:
157 return V3D_TMU_OP_WRITE_SMAX;
158 case nir_intrinsic_ssbo_atomic_umax:
159 case nir_intrinsic_shared_atomic_umax:
160 return V3D_TMU_OP_WRITE_UMAX;
161 case nir_intrinsic_ssbo_atomic_and:
162 case nir_intrinsic_shared_atomic_and:
163 return V3D_TMU_OP_WRITE_AND_READ_INC;
164 case nir_intrinsic_ssbo_atomic_or:
165 case nir_intrinsic_shared_atomic_or:
166 return V3D_TMU_OP_WRITE_OR_READ_DEC;
167 case nir_intrinsic_ssbo_atomic_xor:
168 case nir_intrinsic_shared_atomic_xor:
169 return V3D_TMU_OP_WRITE_XOR_READ_NOT;
170 case nir_intrinsic_ssbo_atomic_exchange:
171 case nir_intrinsic_shared_atomic_exchange:
172 return V3D_TMU_OP_WRITE_XCHG_READ_FLUSH;
173 case nir_intrinsic_ssbo_atomic_comp_swap:
174 case nir_intrinsic_shared_atomic_comp_swap:
175 return V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH;
176 default:
177 unreachable("unknown intrinsic op");
178 }
179 }
180
181 /**
182 * Implements indirect uniform loads and SSBO accesses through the TMU general
183 * memory access interface.
184 */
185 static void
186 ntq_emit_tmu_general(struct v3d_compile *c, nir_intrinsic_instr *instr,
187 bool is_shared_or_scratch)
188 {
189 uint32_t tmu_op = v3d_general_tmu_op(instr);
190
191 /* If we were able to replace atomic_add for an inc/dec, then we
192 * need/can to do things slightly different, like not loading the
193 * amount to add/sub, as that is implicit.
194 */
195 bool atomic_add_replaced =
196 ((instr->intrinsic == nir_intrinsic_ssbo_atomic_add ||
197 instr->intrinsic == nir_intrinsic_shared_atomic_add) &&
198 (tmu_op == V3D_TMU_OP_WRITE_AND_READ_INC ||
199 tmu_op == V3D_TMU_OP_WRITE_OR_READ_DEC));
200
201 bool is_store = (instr->intrinsic == nir_intrinsic_store_ssbo ||
202 instr->intrinsic == nir_intrinsic_store_scratch ||
203 instr->intrinsic == nir_intrinsic_store_shared);
204
205 bool is_load = (instr->intrinsic == nir_intrinsic_load_uniform ||
206 instr->intrinsic == nir_intrinsic_load_ubo ||
207 instr->intrinsic == nir_intrinsic_load_ssbo ||
208 instr->intrinsic == nir_intrinsic_load_scratch ||
209 instr->intrinsic == nir_intrinsic_load_shared);
210
211 if (!is_load)
212 c->tmu_dirty_rcl = true;
213
214 bool has_index = !is_shared_or_scratch;
215
216 int offset_src;
217 if (instr->intrinsic == nir_intrinsic_load_uniform) {
218 offset_src = 0;
219 } else if (instr->intrinsic == nir_intrinsic_load_ssbo ||
220 instr->intrinsic == nir_intrinsic_load_ubo ||
221 instr->intrinsic == nir_intrinsic_load_scratch ||
222 instr->intrinsic == nir_intrinsic_load_shared ||
223 atomic_add_replaced) {
224 offset_src = 0 + has_index;
225 } else if (is_store) {
226 offset_src = 1 + has_index;
227 } else {
228 offset_src = 0 + has_index;
229 }
230
231 bool dynamic_src = !nir_src_is_const(instr->src[offset_src]);
232 uint32_t const_offset = 0;
233 if (!dynamic_src)
234 const_offset = nir_src_as_uint(instr->src[offset_src]);
235
236 struct qreg base_offset;
237 if (instr->intrinsic == nir_intrinsic_load_uniform) {
238 const_offset += nir_intrinsic_base(instr);
239 base_offset = vir_uniform(c, QUNIFORM_UBO_ADDR,
240 v3d_unit_data_create(0, const_offset));
241 const_offset = 0;
242 } else if (instr->intrinsic == nir_intrinsic_load_ubo) {
243 uint32_t index = nir_src_as_uint(instr->src[0]) + 1;
244 /* Note that QUNIFORM_UBO_ADDR takes a UBO index shifted up by
245 * 1 (0 is gallium's constant buffer 0).
246 */
247 base_offset =
248 vir_uniform(c, QUNIFORM_UBO_ADDR,
249 v3d_unit_data_create(index, const_offset));
250 const_offset = 0;
251 } else if (is_shared_or_scratch) {
252 /* Shared and scratch variables have no buffer index, and all
253 * start from a common base that we set up at the start of
254 * dispatch.
255 */
256 if (instr->intrinsic == nir_intrinsic_load_scratch ||
257 instr->intrinsic == nir_intrinsic_store_scratch) {
258 base_offset = c->spill_base;
259 } else {
260 base_offset = c->cs_shared_offset;
261 const_offset += nir_intrinsic_base(instr);
262 }
263 } else {
264 base_offset = vir_uniform(c, QUNIFORM_SSBO_OFFSET,
265 nir_src_as_uint(instr->src[is_store ?
266 1 : 0]));
267 }
268
269 struct qreg tmud = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD);
270 unsigned writemask = is_store ? nir_intrinsic_write_mask(instr) : 0;
271 uint32_t base_const_offset = const_offset;
272 int first_component = -1;
273 int last_component = -1;
274 do {
275 int tmu_writes = 1; /* address */
276
277 if (is_store) {
278 /* Find the first set of consecutive components that
279 * are enabled in the writemask and emit the TMUD
280 * instructions for them.
281 */
282 first_component = ffs(writemask) - 1;
283 last_component = first_component;
284 while (writemask & BITFIELD_BIT(last_component + 1))
285 last_component++;
286
287 assert(first_component >= 0 &&
288 first_component <= last_component &&
289 last_component < instr->num_components);
290
291 struct qreg tmud = vir_reg(QFILE_MAGIC,
292 V3D_QPU_WADDR_TMUD);
293 for (int i = first_component; i <= last_component; i++) {
294 struct qreg data =
295 ntq_get_src(c, instr->src[0], i);
296 vir_MOV_dest(c, tmud, data);
297 tmu_writes++;
298 }
299
300 /* Update the offset for the TMU write based on the
301 * the first component we are writing.
302 */
303 const_offset = base_const_offset + first_component * 4;
304
305 /* Clear these components from the writemask */
306 uint32_t written_mask =
307 BITFIELD_RANGE(first_component, tmu_writes - 1);
308 writemask &= ~written_mask;
309 } else if (!is_load && !atomic_add_replaced) {
310 struct qreg data =
311 ntq_get_src(c, instr->src[1 + has_index], 0);
312 vir_MOV_dest(c, tmud, data);
313 tmu_writes++;
314 if (tmu_op == V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH) {
315 data = ntq_get_src(c, instr->src[2 + has_index],
316 0);
317 vir_MOV_dest(c, tmud, data);
318 tmu_writes++;
319 }
320 }
321
322 /* Make sure we won't exceed the 16-entry TMU fifo if each
323 * thread is storing at the same time.
324 */
325 while (tmu_writes > 16 / c->threads)
326 c->threads /= 2;
327
328 /* The spec says that for atomics, the TYPE field is ignored,
329 * but that doesn't seem to be the case for CMPXCHG. Just use
330 * the number of tmud writes we did to decide the type (or
331 * choose "32bit" for atomic reads, which has been fine).
332 */
333 uint32_t num_components;
334 if (is_load || atomic_add_replaced) {
335 num_components = instr->num_components;
336 } else {
337 assert(tmu_writes > 1);
338 num_components = tmu_writes - 1;
339 }
340
341 uint32_t config = (0xffffff00 |
342 tmu_op << 3|
343 GENERAL_TMU_LOOKUP_PER_PIXEL);
344 if (num_components == 1) {
345 config |= GENERAL_TMU_LOOKUP_TYPE_32BIT_UI;
346 } else {
347 config |= GENERAL_TMU_LOOKUP_TYPE_VEC2 +
348 num_components - 2;
349 }
350
351 if (vir_in_nonuniform_control_flow(c)) {
352 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
353 V3D_QPU_PF_PUSHZ);
354 }
355
356 struct qreg tmua;
357 if (config == ~0)
358 tmua = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA);
359 else
360 tmua = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUAU);
361
362 struct qinst *tmu;
363 if (dynamic_src) {
364 struct qreg offset = base_offset;
365 if (const_offset != 0) {
366 offset = vir_ADD(c, offset,
367 vir_uniform_ui(c, const_offset));
368 }
369 struct qreg data =
370 ntq_get_src(c, instr->src[offset_src], 0);
371 tmu = vir_ADD_dest(c, tmua, offset, data);
372 } else {
373 if (const_offset != 0) {
374 tmu = vir_ADD_dest(c, tmua, base_offset,
375 vir_uniform_ui(c, const_offset));
376 } else {
377 tmu = vir_MOV_dest(c, tmua, base_offset);
378 }
379 }
380
381 if (config != ~0) {
382 tmu->uniform =
383 vir_get_uniform_index(c, QUNIFORM_CONSTANT,
384 config);
385 }
386
387 if (vir_in_nonuniform_control_flow(c))
388 vir_set_cond(tmu, V3D_QPU_COND_IFA);
389
390 vir_emit_thrsw(c);
391
392 /* Read the result, or wait for the TMU op to complete. */
393 for (int i = 0; i < nir_intrinsic_dest_components(instr); i++) {
394 ntq_store_dest(c, &instr->dest, i,
395 vir_MOV(c, vir_LDTMU(c)));
396 }
397
398 if (nir_intrinsic_dest_components(instr) == 0)
399 vir_TMUWT(c);
400 } while (is_store && writemask != 0);
401 }
402
403 static struct qreg *
404 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
405 {
406 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
407 def->num_components);
408 _mesa_hash_table_insert(c->def_ht, def, qregs);
409 return qregs;
410 }
411
412 static bool
413 is_ld_signal(const struct v3d_qpu_sig *sig)
414 {
415 return (sig->ldunif ||
416 sig->ldunifa ||
417 sig->ldunifrf ||
418 sig->ldunifarf ||
419 sig->ldtmu ||
420 sig->ldvary ||
421 sig->ldvpm ||
422 sig->ldtlb ||
423 sig->ldtlbu);
424 }
425
426 /**
427 * This function is responsible for getting VIR results into the associated
428 * storage for a NIR instruction.
429 *
430 * If it's a NIR SSA def, then we just set the associated hash table entry to
431 * the new result.
432 *
433 * If it's a NIR reg, then we need to update the existing qreg assigned to the
434 * NIR destination with the incoming value. To do that without introducing
435 * new MOVs, we require that the incoming qreg either be a uniform, or be
436 * SSA-defined by the previous VIR instruction in the block and rewritable by
437 * this function. That lets us sneak ahead and insert the SF flag beforehand
438 * (knowing that the previous instruction doesn't depend on flags) and rewrite
439 * its destination to be the NIR reg's destination
440 */
441 void
442 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
443 struct qreg result)
444 {
445 struct qinst *last_inst = NULL;
446 if (!list_is_empty(&c->cur_block->instructions))
447 last_inst = (struct qinst *)c->cur_block->instructions.prev;
448
449 assert((result.file == QFILE_TEMP &&
450 last_inst && last_inst == c->defs[result.index]));
451
452 if (dest->is_ssa) {
453 assert(chan < dest->ssa.num_components);
454
455 struct qreg *qregs;
456 struct hash_entry *entry =
457 _mesa_hash_table_search(c->def_ht, &dest->ssa);
458
459 if (entry)
460 qregs = entry->data;
461 else
462 qregs = ntq_init_ssa_def(c, &dest->ssa);
463
464 qregs[chan] = result;
465 } else {
466 nir_register *reg = dest->reg.reg;
467 assert(dest->reg.base_offset == 0);
468 assert(reg->num_array_elems == 0);
469 struct hash_entry *entry =
470 _mesa_hash_table_search(c->def_ht, reg);
471 struct qreg *qregs = entry->data;
472
473 /* If the previous instruction can't be predicated for
474 * the store into the nir_register, then emit a MOV
475 * that can be.
476 */
477 if (vir_in_nonuniform_control_flow(c) &&
478 is_ld_signal(&c->defs[last_inst->dst.index]->qpu.sig)) {
479 result = vir_MOV(c, result);
480 last_inst = c->defs[result.index];
481 }
482
483 /* We know they're both temps, so just rewrite index. */
484 c->defs[last_inst->dst.index] = NULL;
485 last_inst->dst.index = qregs[chan].index;
486
487 /* If we're in control flow, then make this update of the reg
488 * conditional on the execution mask.
489 */
490 if (vir_in_nonuniform_control_flow(c)) {
491 last_inst->dst.index = qregs[chan].index;
492
493 /* Set the flags to the current exec mask.
494 */
495 c->cursor = vir_before_inst(last_inst);
496 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
497 V3D_QPU_PF_PUSHZ);
498 c->cursor = vir_after_inst(last_inst);
499
500 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
501 }
502 }
503 }
504
505 struct qreg
506 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
507 {
508 struct hash_entry *entry;
509 if (src.is_ssa) {
510 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
511 assert(i < src.ssa->num_components);
512 } else {
513 nir_register *reg = src.reg.reg;
514 entry = _mesa_hash_table_search(c->def_ht, reg);
515 assert(reg->num_array_elems == 0);
516 assert(src.reg.base_offset == 0);
517 assert(i < reg->num_components);
518 }
519
520 struct qreg *qregs = entry->data;
521 return qregs[i];
522 }
523
524 static struct qreg
525 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
526 unsigned src)
527 {
528 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
529 unsigned chan = ffs(instr->dest.write_mask) - 1;
530 struct qreg r = ntq_get_src(c, instr->src[src].src,
531 instr->src[src].swizzle[chan]);
532
533 assert(!instr->src[src].abs);
534 assert(!instr->src[src].negate);
535
536 return r;
537 };
538
539 static struct qreg
540 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
541 {
542 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
543 }
544
545 static void
546 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
547 {
548 unsigned unit = instr->texture_index;
549 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
550 int dest_size = nir_tex_instr_dest_size(instr);
551
552 struct qreg lod = c->undef;
553 if (lod_index != -1)
554 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
555
556 for (int i = 0; i < dest_size; i++) {
557 assert(i < 3);
558 enum quniform_contents contents;
559
560 if (instr->is_array && i == dest_size - 1)
561 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
562 else
563 contents = QUNIFORM_TEXTURE_WIDTH + i;
564
565 struct qreg size = vir_uniform(c, contents, unit);
566
567 switch (instr->sampler_dim) {
568 case GLSL_SAMPLER_DIM_1D:
569 case GLSL_SAMPLER_DIM_2D:
570 case GLSL_SAMPLER_DIM_MS:
571 case GLSL_SAMPLER_DIM_3D:
572 case GLSL_SAMPLER_DIM_CUBE:
573 /* Don't minify the array size. */
574 if (!(instr->is_array && i == dest_size - 1)) {
575 size = ntq_minify(c, size, lod);
576 }
577 break;
578
579 case GLSL_SAMPLER_DIM_RECT:
580 /* There's no LOD field for rects */
581 break;
582
583 default:
584 unreachable("Bad sampler type");
585 }
586
587 ntq_store_dest(c, &instr->dest, i, size);
588 }
589 }
590
591 static void
592 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
593 {
594 unsigned unit = instr->texture_index;
595
596 /* Since each texture sampling op requires uploading uniforms to
597 * reference the texture, there's no HW support for texture size and
598 * you just upload uniforms containing the size.
599 */
600 switch (instr->op) {
601 case nir_texop_query_levels:
602 ntq_store_dest(c, &instr->dest, 0,
603 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
604 return;
605 case nir_texop_txs:
606 ntq_emit_txs(c, instr);
607 return;
608 default:
609 break;
610 }
611
612 if (c->devinfo->ver >= 40)
613 v3d40_vir_emit_tex(c, instr);
614 else
615 v3d33_vir_emit_tex(c, instr);
616 }
617
618 static struct qreg
619 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
620 {
621 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
622 if (is_cos)
623 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
624
625 struct qreg periods = vir_FROUND(c, input);
626 struct qreg sin_output = vir_SIN(c, vir_FSUB(c, input, periods));
627 return vir_XOR(c, sin_output, vir_SHL(c,
628 vir_FTOIN(c, periods),
629 vir_uniform_ui(c, -1)));
630 }
631
632 static struct qreg
633 ntq_fsign(struct v3d_compile *c, struct qreg src)
634 {
635 struct qreg t = vir_get_temp(c);
636
637 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
638 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHZ);
639 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
640 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHN);
641 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
642 return vir_MOV(c, t);
643 }
644
645 static void
646 emit_fragcoord_input(struct v3d_compile *c, int attr)
647 {
648 c->inputs[attr * 4 + 0] = vir_FXCD(c);
649 c->inputs[attr * 4 + 1] = vir_FYCD(c);
650 c->inputs[attr * 4 + 2] = c->payload_z;
651 c->inputs[attr * 4 + 3] = vir_RECIP(c, c->payload_w);
652 }
653
654 static struct qreg
655 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
656 uint8_t swizzle, int array_index)
657 {
658 struct qreg r3 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R3);
659 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
660
661 struct qreg vary;
662 if (c->devinfo->ver >= 41) {
663 struct qinst *ldvary = vir_add_inst(V3D_QPU_A_NOP, c->undef,
664 c->undef, c->undef);
665 ldvary->qpu.sig.ldvary = true;
666 vary = vir_emit_def(c, ldvary);
667 } else {
668 vir_NOP(c)->qpu.sig.ldvary = true;
669 vary = r3;
670 }
671
672 /* For gl_PointCoord input or distance along a line, we'll be called
673 * with no nir_variable, and we don't count toward VPM size so we
674 * don't track an input slot.
675 */
676 if (!var) {
677 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
678 }
679
680 int i = c->num_inputs++;
681 c->input_slots[i] =
682 v3d_slot_from_slot_and_component(var->data.location +
683 array_index, swizzle);
684
685 switch (var->data.interpolation) {
686 case INTERP_MODE_NONE:
687 /* If a gl_FrontColor or gl_BackColor input has no interp
688 * qualifier, then if we're using glShadeModel(GL_FLAT) it
689 * needs to be flat shaded.
690 */
691 switch (var->data.location + array_index) {
692 case VARYING_SLOT_COL0:
693 case VARYING_SLOT_COL1:
694 case VARYING_SLOT_BFC0:
695 case VARYING_SLOT_BFC1:
696 if (c->fs_key->shade_model_flat) {
697 BITSET_SET(c->flat_shade_flags, i);
698 vir_MOV_dest(c, c->undef, vary);
699 return vir_MOV(c, r5);
700 } else {
701 return vir_FADD(c, vir_FMUL(c, vary,
702 c->payload_w), r5);
703 }
704 default:
705 break;
706 }
707 /* FALLTHROUGH */
708 case INTERP_MODE_SMOOTH:
709 if (var->data.centroid) {
710 BITSET_SET(c->centroid_flags, i);
711 return vir_FADD(c, vir_FMUL(c, vary,
712 c->payload_w_centroid), r5);
713 } else {
714 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
715 }
716 case INTERP_MODE_NOPERSPECTIVE:
717 BITSET_SET(c->noperspective_flags, i);
718 return vir_FADD(c, vir_MOV(c, vary), r5);
719 case INTERP_MODE_FLAT:
720 BITSET_SET(c->flat_shade_flags, i);
721 vir_MOV_dest(c, c->undef, vary);
722 return vir_MOV(c, r5);
723 default:
724 unreachable("Bad interp mode");
725 }
726 }
727
728 static void
729 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var,
730 int array_index)
731 {
732 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
733 int chan = var->data.location_frac + i;
734 c->inputs[attr * 4 + chan] =
735 emit_fragment_varying(c, var, chan, array_index);
736 }
737 }
738
739 static void
740 add_output(struct v3d_compile *c,
741 uint32_t decl_offset,
742 uint8_t slot,
743 uint8_t swizzle)
744 {
745 uint32_t old_array_size = c->outputs_array_size;
746 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
747 decl_offset + 1);
748
749 if (old_array_size != c->outputs_array_size) {
750 c->output_slots = reralloc(c,
751 c->output_slots,
752 struct v3d_varying_slot,
753 c->outputs_array_size);
754 }
755
756 c->output_slots[decl_offset] =
757 v3d_slot_from_slot_and_component(slot, swizzle);
758 }
759
760 /**
761 * If compare_instr is a valid comparison instruction, emits the
762 * compare_instr's comparison and returns the sel_instr's return value based
763 * on the compare_instr's result.
764 */
765 static bool
766 ntq_emit_comparison(struct v3d_compile *c,
767 nir_alu_instr *compare_instr,
768 enum v3d_qpu_cond *out_cond)
769 {
770 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
771 struct qreg src1;
772 if (nir_op_infos[compare_instr->op].num_inputs > 1)
773 src1 = ntq_get_alu_src(c, compare_instr, 1);
774 bool cond_invert = false;
775 struct qreg nop = vir_nop_reg();
776
777 switch (compare_instr->op) {
778 case nir_op_feq32:
779 case nir_op_seq:
780 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
781 break;
782 case nir_op_ieq32:
783 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
784 break;
785
786 case nir_op_fne32:
787 case nir_op_sne:
788 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
789 cond_invert = true;
790 break;
791 case nir_op_ine32:
792 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
793 cond_invert = true;
794 break;
795
796 case nir_op_fge32:
797 case nir_op_sge:
798 vir_set_pf(vir_FCMP_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
799 break;
800 case nir_op_ige32:
801 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
802 cond_invert = true;
803 break;
804 case nir_op_uge32:
805 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
806 cond_invert = true;
807 break;
808
809 case nir_op_slt:
810 case nir_op_flt32:
811 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHN);
812 break;
813 case nir_op_ilt32:
814 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
815 break;
816 case nir_op_ult32:
817 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
818 break;
819
820 case nir_op_i2b32:
821 vir_set_pf(vir_MOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ);
822 cond_invert = true;
823 break;
824
825 case nir_op_f2b32:
826 vir_set_pf(vir_FMOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ);
827 cond_invert = true;
828 break;
829
830 default:
831 return false;
832 }
833
834 *out_cond = cond_invert ? V3D_QPU_COND_IFNA : V3D_QPU_COND_IFA;
835
836 return true;
837 }
838
839 /* Finds an ALU instruction that generates our src value that could
840 * (potentially) be greedily emitted in the consuming instruction.
841 */
842 static struct nir_alu_instr *
843 ntq_get_alu_parent(nir_src src)
844 {
845 if (!src.is_ssa || src.ssa->parent_instr->type != nir_instr_type_alu)
846 return NULL;
847 nir_alu_instr *instr = nir_instr_as_alu(src.ssa->parent_instr);
848 if (!instr)
849 return NULL;
850
851 /* If the ALU instr's srcs are non-SSA, then we would have to avoid
852 * moving emission of the ALU instr down past another write of the
853 * src.
854 */
855 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
856 if (!instr->src[i].src.is_ssa)
857 return NULL;
858 }
859
860 return instr;
861 }
862
863 /* Turns a NIR bool into a condition code to predicate on. */
864 static enum v3d_qpu_cond
865 ntq_emit_bool_to_cond(struct v3d_compile *c, nir_src src)
866 {
867 nir_alu_instr *compare = ntq_get_alu_parent(src);
868 if (!compare)
869 goto out;
870
871 enum v3d_qpu_cond cond;
872 if (ntq_emit_comparison(c, compare, &cond))
873 return cond;
874
875 out:
876 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), ntq_get_src(c, src, 0)),
877 V3D_QPU_PF_PUSHZ);
878 return V3D_QPU_COND_IFNA;
879 }
880
881 static void
882 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
883 {
884 /* This should always be lowered to ALU operations for V3D. */
885 assert(!instr->dest.saturate);
886
887 /* Vectors are special in that they have non-scalarized writemasks,
888 * and just take the first swizzle channel for each argument in order
889 * into each writemask channel.
890 */
891 if (instr->op == nir_op_vec2 ||
892 instr->op == nir_op_vec3 ||
893 instr->op == nir_op_vec4) {
894 struct qreg srcs[4];
895 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
896 srcs[i] = ntq_get_src(c, instr->src[i].src,
897 instr->src[i].swizzle[0]);
898 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
899 ntq_store_dest(c, &instr->dest.dest, i,
900 vir_MOV(c, srcs[i]));
901 return;
902 }
903
904 /* General case: We can just grab the one used channel per src. */
905 struct qreg src[nir_op_infos[instr->op].num_inputs];
906 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
907 src[i] = ntq_get_alu_src(c, instr, i);
908 }
909
910 struct qreg result;
911
912 switch (instr->op) {
913 case nir_op_mov:
914 result = vir_MOV(c, src[0]);
915 break;
916
917 case nir_op_fneg:
918 result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
919 break;
920 case nir_op_ineg:
921 result = vir_NEG(c, src[0]);
922 break;
923
924 case nir_op_fmul:
925 result = vir_FMUL(c, src[0], src[1]);
926 break;
927 case nir_op_fadd:
928 result = vir_FADD(c, src[0], src[1]);
929 break;
930 case nir_op_fsub:
931 result = vir_FSUB(c, src[0], src[1]);
932 break;
933 case nir_op_fmin:
934 result = vir_FMIN(c, src[0], src[1]);
935 break;
936 case nir_op_fmax:
937 result = vir_FMAX(c, src[0], src[1]);
938 break;
939
940 case nir_op_f2i32: {
941 nir_alu_instr *src0_alu = ntq_get_alu_parent(instr->src[0].src);
942 if (src0_alu && src0_alu->op == nir_op_fround_even) {
943 result = vir_FTOIN(c, ntq_get_alu_src(c, src0_alu, 0));
944 } else {
945 result = vir_FTOIZ(c, src[0]);
946 }
947 break;
948 }
949
950 case nir_op_f2u32:
951 result = vir_FTOUZ(c, src[0]);
952 break;
953 case nir_op_i2f32:
954 result = vir_ITOF(c, src[0]);
955 break;
956 case nir_op_u2f32:
957 result = vir_UTOF(c, src[0]);
958 break;
959 case nir_op_b2f32:
960 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
961 break;
962 case nir_op_b2i32:
963 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
964 break;
965
966 case nir_op_iadd:
967 result = vir_ADD(c, src[0], src[1]);
968 break;
969 case nir_op_ushr:
970 result = vir_SHR(c, src[0], src[1]);
971 break;
972 case nir_op_isub:
973 result = vir_SUB(c, src[0], src[1]);
974 break;
975 case nir_op_ishr:
976 result = vir_ASR(c, src[0], src[1]);
977 break;
978 case nir_op_ishl:
979 result = vir_SHL(c, src[0], src[1]);
980 break;
981 case nir_op_imin:
982 result = vir_MIN(c, src[0], src[1]);
983 break;
984 case nir_op_umin:
985 result = vir_UMIN(c, src[0], src[1]);
986 break;
987 case nir_op_imax:
988 result = vir_MAX(c, src[0], src[1]);
989 break;
990 case nir_op_umax:
991 result = vir_UMAX(c, src[0], src[1]);
992 break;
993 case nir_op_iand:
994 result = vir_AND(c, src[0], src[1]);
995 break;
996 case nir_op_ior:
997 result = vir_OR(c, src[0], src[1]);
998 break;
999 case nir_op_ixor:
1000 result = vir_XOR(c, src[0], src[1]);
1001 break;
1002 case nir_op_inot:
1003 result = vir_NOT(c, src[0]);
1004 break;
1005
1006 case nir_op_ufind_msb:
1007 result = vir_SUB(c, vir_uniform_ui(c, 31), vir_CLZ(c, src[0]));
1008 break;
1009
1010 case nir_op_imul:
1011 result = vir_UMUL(c, src[0], src[1]);
1012 break;
1013
1014 case nir_op_seq:
1015 case nir_op_sne:
1016 case nir_op_sge:
1017 case nir_op_slt: {
1018 enum v3d_qpu_cond cond;
1019 ASSERTED bool ok = ntq_emit_comparison(c, instr, &cond);
1020 assert(ok);
1021 result = vir_MOV(c, vir_SEL(c, cond,
1022 vir_uniform_f(c, 1.0),
1023 vir_uniform_f(c, 0.0)));
1024 break;
1025 }
1026
1027 case nir_op_i2b32:
1028 case nir_op_f2b32:
1029 case nir_op_feq32:
1030 case nir_op_fne32:
1031 case nir_op_fge32:
1032 case nir_op_flt32:
1033 case nir_op_ieq32:
1034 case nir_op_ine32:
1035 case nir_op_ige32:
1036 case nir_op_uge32:
1037 case nir_op_ilt32:
1038 case nir_op_ult32: {
1039 enum v3d_qpu_cond cond;
1040 ASSERTED bool ok = ntq_emit_comparison(c, instr, &cond);
1041 assert(ok);
1042 result = vir_MOV(c, vir_SEL(c, cond,
1043 vir_uniform_ui(c, ~0),
1044 vir_uniform_ui(c, 0)));
1045 break;
1046 }
1047
1048 case nir_op_b32csel:
1049 result = vir_MOV(c,
1050 vir_SEL(c,
1051 ntq_emit_bool_to_cond(c, instr->src[0].src),
1052 src[1], src[2]));
1053 break;
1054
1055 case nir_op_fcsel:
1056 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), src[0]),
1057 V3D_QPU_PF_PUSHZ);
1058 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
1059 src[1], src[2]));
1060 break;
1061
1062 case nir_op_frcp:
1063 result = vir_RECIP(c, src[0]);
1064 break;
1065 case nir_op_frsq:
1066 result = vir_RSQRT(c, src[0]);
1067 break;
1068 case nir_op_fexp2:
1069 result = vir_EXP(c, src[0]);
1070 break;
1071 case nir_op_flog2:
1072 result = vir_LOG(c, src[0]);
1073 break;
1074
1075 case nir_op_fceil:
1076 result = vir_FCEIL(c, src[0]);
1077 break;
1078 case nir_op_ffloor:
1079 result = vir_FFLOOR(c, src[0]);
1080 break;
1081 case nir_op_fround_even:
1082 result = vir_FROUND(c, src[0]);
1083 break;
1084 case nir_op_ftrunc:
1085 result = vir_FTRUNC(c, src[0]);
1086 break;
1087
1088 case nir_op_fsin:
1089 result = ntq_fsincos(c, src[0], false);
1090 break;
1091 case nir_op_fcos:
1092 result = ntq_fsincos(c, src[0], true);
1093 break;
1094
1095 case nir_op_fsign:
1096 result = ntq_fsign(c, src[0]);
1097 break;
1098
1099 case nir_op_fabs: {
1100 result = vir_FMOV(c, src[0]);
1101 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
1102 break;
1103 }
1104
1105 case nir_op_iabs:
1106 result = vir_MAX(c, src[0], vir_NEG(c, src[0]));
1107 break;
1108
1109 case nir_op_fddx:
1110 case nir_op_fddx_coarse:
1111 case nir_op_fddx_fine:
1112 result = vir_FDX(c, src[0]);
1113 break;
1114
1115 case nir_op_fddy:
1116 case nir_op_fddy_coarse:
1117 case nir_op_fddy_fine:
1118 result = vir_FDY(c, src[0]);
1119 break;
1120
1121 case nir_op_uadd_carry:
1122 vir_set_pf(vir_ADD_dest(c, vir_nop_reg(), src[0], src[1]),
1123 V3D_QPU_PF_PUSHC);
1124 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1125 vir_uniform_ui(c, ~0),
1126 vir_uniform_ui(c, 0)));
1127 break;
1128
1129 case nir_op_pack_half_2x16_split:
1130 result = vir_VFPACK(c, src[0], src[1]);
1131 break;
1132
1133 case nir_op_unpack_half_2x16_split_x:
1134 result = vir_FMOV(c, src[0]);
1135 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_L);
1136 break;
1137
1138 case nir_op_unpack_half_2x16_split_y:
1139 result = vir_FMOV(c, src[0]);
1140 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_H);
1141 break;
1142
1143 default:
1144 fprintf(stderr, "unknown NIR ALU inst: ");
1145 nir_print_instr(&instr->instr, stderr);
1146 fprintf(stderr, "\n");
1147 abort();
1148 }
1149
1150 /* We have a scalar result, so the instruction should only have a
1151 * single channel written to.
1152 */
1153 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
1154 ntq_store_dest(c, &instr->dest.dest,
1155 ffs(instr->dest.write_mask) - 1, result);
1156 }
1157
1158 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
1159 * specifier. They come from a register that's preloaded with 0xffffffff
1160 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
1161 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
1162 */
1163 #define TLB_TYPE_F16_COLOR (3 << 6)
1164 #define TLB_TYPE_I32_COLOR (1 << 6)
1165 #define TLB_TYPE_F32_COLOR (0 << 6)
1166 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
1167 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
1168 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
1169 #define TLB_F16_SWAP_HI_LO (1 << 1)
1170 #define TLB_VEC_SIZE_4_F16 (1 << 0)
1171 #define TLB_VEC_SIZE_2_F16 (0 << 0)
1172 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
1173
1174 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
1175 * flag is set.
1176 */
1177 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
1178 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
1179 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
1180 #define TLB_V42_DEPTH_TYPE_INVARIANT (0 << 3) /* Unmodified sideband input used */
1181 #define TLB_V42_DEPTH_TYPE_PER_PIXEL (1 << 3) /* QPU result used */
1182
1183 /* Stencil is a single 32-bit write. */
1184 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1185
1186 static void
1187 vir_emit_tlb_color_write(struct v3d_compile *c, unsigned rt)
1188 {
1189 if (!(c->fs_key->cbufs & (1 << rt)) || !c->output_color_var[rt])
1190 return;
1191
1192 struct qreg tlb_reg = vir_magic_reg(V3D_QPU_WADDR_TLB);
1193 struct qreg tlbu_reg = vir_magic_reg(V3D_QPU_WADDR_TLBU);
1194
1195 nir_variable *var = c->output_color_var[rt];
1196 int num_components = glsl_get_vector_elements(var->type);
1197 uint32_t conf = 0xffffff00;
1198 struct qinst *inst;
1199
1200 conf |= c->msaa_per_sample_output ? TLB_SAMPLE_MODE_PER_SAMPLE :
1201 TLB_SAMPLE_MODE_PER_PIXEL;
1202 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1203
1204 if (c->fs_key->swap_color_rb & (1 << rt))
1205 num_components = MAX2(num_components, 3);
1206 assert(num_components != 0);
1207
1208 enum glsl_base_type type = glsl_get_base_type(var->type);
1209 bool is_int_format = type == GLSL_TYPE_INT || type == GLSL_TYPE_UINT;
1210 bool is_32b_tlb_format = is_int_format ||
1211 (c->fs_key->f32_color_rb & (1 << rt));
1212
1213 if (is_int_format) {
1214 /* The F32 vs I32 distinction was dropped in 4.2. */
1215 if (c->devinfo->ver < 42)
1216 conf |= TLB_TYPE_I32_COLOR;
1217 else
1218 conf |= TLB_TYPE_F32_COLOR;
1219 conf |= ((num_components - 1) << TLB_VEC_SIZE_MINUS_1_SHIFT);
1220 } else {
1221 if (c->fs_key->f32_color_rb & (1 << rt)) {
1222 conf |= TLB_TYPE_F32_COLOR;
1223 conf |= ((num_components - 1) <<
1224 TLB_VEC_SIZE_MINUS_1_SHIFT);
1225 } else {
1226 conf |= TLB_TYPE_F16_COLOR;
1227 conf |= TLB_F16_SWAP_HI_LO;
1228 if (num_components >= 3)
1229 conf |= TLB_VEC_SIZE_4_F16;
1230 else
1231 conf |= TLB_VEC_SIZE_2_F16;
1232 }
1233 }
1234
1235 int num_samples = c->msaa_per_sample_output ? V3D_MAX_SAMPLES : 1;
1236 for (int i = 0; i < num_samples; i++) {
1237 struct qreg *color = c->msaa_per_sample_output ?
1238 &c->sample_colors[(rt * V3D_MAX_SAMPLES + i) * 4] :
1239 &c->outputs[var->data.driver_location * 4];
1240
1241 struct qreg r = color[0];
1242 struct qreg g = color[1];
1243 struct qreg b = color[2];
1244 struct qreg a = color[3];
1245
1246 if (c->fs_key->swap_color_rb & (1 << rt)) {
1247 r = color[2];
1248 b = color[0];
1249 }
1250
1251 if (c->fs_key->sample_alpha_to_one)
1252 a = vir_uniform_f(c, 1.0);
1253
1254 if (is_32b_tlb_format) {
1255 if (i == 0) {
1256 inst = vir_MOV_dest(c, tlbu_reg, r);
1257 inst->uniform =
1258 vir_get_uniform_index(c,
1259 QUNIFORM_CONSTANT,
1260 conf);
1261 } else {
1262 inst = vir_MOV_dest(c, tlb_reg, r);
1263 }
1264
1265 if (num_components >= 2)
1266 vir_MOV_dest(c, tlb_reg, g);
1267 if (num_components >= 3)
1268 vir_MOV_dest(c, tlb_reg, b);
1269 if (num_components >= 4)
1270 vir_MOV_dest(c, tlb_reg, a);
1271 } else {
1272 inst = vir_VFPACK_dest(c, tlb_reg, r, g);
1273 if (conf != ~0 && i == 0) {
1274 inst->dst = tlbu_reg;
1275 inst->uniform =
1276 vir_get_uniform_index(c,
1277 QUNIFORM_CONSTANT,
1278 conf);
1279 }
1280
1281 if (num_components >= 3)
1282 inst = vir_VFPACK_dest(c, tlb_reg, b, a);
1283 }
1284 }
1285 }
1286
1287 static void
1288 emit_frag_end(struct v3d_compile *c)
1289 {
1290 /* XXX
1291 if (c->output_sample_mask_index != -1) {
1292 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1293 }
1294 */
1295
1296 bool has_any_tlb_color_write = false;
1297 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1298 if (c->fs_key->cbufs & (1 << rt) && c->output_color_var[rt])
1299 has_any_tlb_color_write = true;
1300 }
1301
1302 if (c->fs_key->sample_alpha_to_coverage && c->output_color_var[0]) {
1303 struct nir_variable *var = c->output_color_var[0];
1304 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1305
1306 vir_SETMSF_dest(c, vir_nop_reg(),
1307 vir_AND(c,
1308 vir_MSF(c),
1309 vir_FTOC(c, color[3])));
1310 }
1311
1312 struct qreg tlbu_reg = vir_magic_reg(V3D_QPU_WADDR_TLBU);
1313 if (c->output_position_index != -1) {
1314 struct qinst *inst = vir_MOV_dest(c, tlbu_reg,
1315 c->outputs[c->output_position_index]);
1316 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1317
1318 if (c->devinfo->ver >= 42) {
1319 tlb_specifier |= (TLB_V42_DEPTH_TYPE_PER_PIXEL |
1320 TLB_SAMPLE_MODE_PER_PIXEL);
1321 } else
1322 tlb_specifier |= TLB_DEPTH_TYPE_PER_PIXEL;
1323
1324 inst->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT,
1325 tlb_specifier |
1326 0xffffff00);
1327 c->writes_z = true;
1328 } else if (c->s->info.fs.uses_discard ||
1329 !c->s->info.fs.early_fragment_tests ||
1330 c->fs_key->sample_alpha_to_coverage ||
1331 !has_any_tlb_color_write) {
1332 /* Emit passthrough Z if it needed to be delayed until shader
1333 * end due to potential discards.
1334 *
1335 * Since (single-threaded) fragment shaders always need a TLB
1336 * write, emit passthrouh Z if we didn't have any color
1337 * buffers and flag us as potentially discarding, so that we
1338 * can use Z as the TLB write.
1339 */
1340 c->s->info.fs.uses_discard = true;
1341
1342 struct qinst *inst = vir_MOV_dest(c, tlbu_reg,
1343 vir_nop_reg());
1344 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1345
1346 if (c->devinfo->ver >= 42) {
1347 /* The spec says the PER_PIXEL flag is ignored for
1348 * invariant writes, but the simulator demands it.
1349 */
1350 tlb_specifier |= (TLB_V42_DEPTH_TYPE_INVARIANT |
1351 TLB_SAMPLE_MODE_PER_PIXEL);
1352 } else {
1353 tlb_specifier |= TLB_DEPTH_TYPE_INVARIANT;
1354 }
1355
1356 inst->uniform = vir_get_uniform_index(c,
1357 QUNIFORM_CONSTANT,
1358 tlb_specifier |
1359 0xffffff00);
1360 c->writes_z = true;
1361 }
1362
1363 /* XXX: Performance improvement: Merge Z write and color writes TLB
1364 * uniform setup
1365 */
1366 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++)
1367 vir_emit_tlb_color_write(c, rt);
1368 }
1369
1370 static void
1371 vir_VPM_WRITE(struct v3d_compile *c, struct qreg val, uint32_t vpm_index)
1372 {
1373 if (c->devinfo->ver >= 40) {
1374 vir_STVPMV(c, vir_uniform_ui(c, vpm_index), val);
1375 } else {
1376 /* XXX: v3d33_vir_vpm_write_setup(c); */
1377 vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM), val);
1378 }
1379 }
1380
1381 static void
1382 emit_vert_end(struct v3d_compile *c)
1383 {
1384 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1385 */
1386 if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
1387 vir_VPMWT(c);
1388 }
1389
1390 void
1391 v3d_optimize_nir(struct nir_shader *s)
1392 {
1393 bool progress;
1394 unsigned lower_flrp =
1395 (s->options->lower_flrp16 ? 16 : 0) |
1396 (s->options->lower_flrp32 ? 32 : 0) |
1397 (s->options->lower_flrp64 ? 64 : 0);
1398
1399 do {
1400 progress = false;
1401
1402 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1403 NIR_PASS(progress, s, nir_lower_alu_to_scalar, NULL, NULL);
1404 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1405 NIR_PASS(progress, s, nir_copy_prop);
1406 NIR_PASS(progress, s, nir_opt_remove_phis);
1407 NIR_PASS(progress, s, nir_opt_dce);
1408 NIR_PASS(progress, s, nir_opt_dead_cf);
1409 NIR_PASS(progress, s, nir_opt_cse);
1410 NIR_PASS(progress, s, nir_opt_peephole_select, 8, true, true);
1411 NIR_PASS(progress, s, nir_opt_algebraic);
1412 NIR_PASS(progress, s, nir_opt_constant_folding);
1413
1414 if (lower_flrp != 0) {
1415 bool lower_flrp_progress = false;
1416
1417 NIR_PASS(lower_flrp_progress, s, nir_lower_flrp,
1418 lower_flrp,
1419 false /* always_precise */,
1420 s->options->lower_ffma);
1421 if (lower_flrp_progress) {
1422 NIR_PASS(progress, s, nir_opt_constant_folding);
1423 progress = true;
1424 }
1425
1426 /* Nothing should rematerialize any flrps, so we only
1427 * need to do this lowering once.
1428 */
1429 lower_flrp = 0;
1430 }
1431
1432 NIR_PASS(progress, s, nir_opt_undef);
1433 } while (progress);
1434
1435 NIR_PASS(progress, s, nir_opt_move, nir_move_load_ubo);
1436 }
1437
1438 static int
1439 driver_location_compare(const void *in_a, const void *in_b)
1440 {
1441 const nir_variable *const *a = in_a;
1442 const nir_variable *const *b = in_b;
1443
1444 return (*a)->data.driver_location - (*b)->data.driver_location;
1445 }
1446
1447 static struct qreg
1448 ntq_emit_vpm_read(struct v3d_compile *c,
1449 uint32_t *num_components_queued,
1450 uint32_t *remaining,
1451 uint32_t vpm_index)
1452 {
1453 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1454
1455 if (c->devinfo->ver >= 40 ) {
1456 return vir_LDVPMV_IN(c,
1457 vir_uniform_ui(c,
1458 (*num_components_queued)++));
1459 }
1460
1461 if (*num_components_queued != 0) {
1462 (*num_components_queued)--;
1463 return vir_MOV(c, vpm);
1464 }
1465
1466 uint32_t num_components = MIN2(*remaining, 32);
1467
1468 v3d33_vir_vpm_read_setup(c, num_components);
1469
1470 *num_components_queued = num_components - 1;
1471 *remaining -= num_components;
1472
1473 return vir_MOV(c, vpm);
1474 }
1475
1476 static void
1477 ntq_setup_vpm_inputs(struct v3d_compile *c)
1478 {
1479 /* Figure out how many components of each vertex attribute the shader
1480 * uses. Each variable should have been split to individual
1481 * components and unused ones DCEed. The vertex fetcher will load
1482 * from the start of the attribute to the number of components we
1483 * declare we need in c->vattr_sizes[].
1484 */
1485 nir_foreach_variable(var, &c->s->inputs) {
1486 /* No VS attribute array support. */
1487 assert(MAX2(glsl_get_length(var->type), 1) == 1);
1488
1489 unsigned loc = var->data.driver_location;
1490 int start_component = var->data.location_frac;
1491 int num_components = glsl_get_components(var->type);
1492
1493 c->vattr_sizes[loc] = MAX2(c->vattr_sizes[loc],
1494 start_component + num_components);
1495 }
1496
1497 unsigned num_components = 0;
1498 uint32_t vpm_components_queued = 0;
1499 bool uses_iid = c->s->info.system_values_read &
1500 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1501 bool uses_vid = c->s->info.system_values_read &
1502 (1ull << SYSTEM_VALUE_VERTEX_ID);
1503 num_components += uses_iid;
1504 num_components += uses_vid;
1505
1506 for (int i = 0; i < ARRAY_SIZE(c->vattr_sizes); i++)
1507 num_components += c->vattr_sizes[i];
1508
1509 if (uses_iid) {
1510 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1511 &num_components, ~0);
1512 }
1513
1514 if (uses_vid) {
1515 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1516 &num_components, ~0);
1517 }
1518
1519 /* The actual loads will happen directly in nir_intrinsic_load_input
1520 * on newer versions.
1521 */
1522 if (c->devinfo->ver >= 40)
1523 return;
1524
1525 for (int loc = 0; loc < ARRAY_SIZE(c->vattr_sizes); loc++) {
1526 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1527 (loc + 1) * 4);
1528
1529 for (int i = 0; i < c->vattr_sizes[loc]; i++) {
1530 c->inputs[loc * 4 + i] =
1531 ntq_emit_vpm_read(c,
1532 &vpm_components_queued,
1533 &num_components,
1534 loc * 4 + i);
1535
1536 }
1537 }
1538
1539 if (c->devinfo->ver >= 40) {
1540 assert(vpm_components_queued == num_components);
1541 } else {
1542 assert(vpm_components_queued == 0);
1543 assert(num_components == 0);
1544 }
1545 }
1546
1547 static bool
1548 var_needs_point_coord(struct v3d_compile *c, nir_variable *var)
1549 {
1550 return (var->data.location == VARYING_SLOT_PNTC ||
1551 (var->data.location >= VARYING_SLOT_VAR0 &&
1552 (c->fs_key->point_sprite_mask &
1553 (1 << (var->data.location - VARYING_SLOT_VAR0)))));
1554 }
1555
1556 static bool
1557 program_reads_point_coord(struct v3d_compile *c)
1558 {
1559 nir_foreach_variable(var, &c->s->inputs) {
1560 if (var_needs_point_coord(c, var))
1561 return true;
1562 }
1563
1564 return false;
1565 }
1566
1567 static void
1568 ntq_setup_fs_inputs(struct v3d_compile *c)
1569 {
1570 unsigned num_entries = 0;
1571 unsigned num_components = 0;
1572 nir_foreach_variable(var, &c->s->inputs) {
1573 num_entries++;
1574 num_components += glsl_get_components(var->type);
1575 }
1576
1577 nir_variable *vars[num_entries];
1578
1579 unsigned i = 0;
1580 nir_foreach_variable(var, &c->s->inputs)
1581 vars[i++] = var;
1582
1583 /* Sort the variables so that we emit the input setup in
1584 * driver_location order. This is required for VPM reads, whose data
1585 * is fetched into the VPM in driver_location (TGSI register index)
1586 * order.
1587 */
1588 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1589
1590 for (unsigned i = 0; i < num_entries; i++) {
1591 nir_variable *var = vars[i];
1592 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1593 unsigned loc = var->data.driver_location;
1594
1595 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1596 (loc + array_len) * 4);
1597
1598 if (var->data.location == VARYING_SLOT_POS) {
1599 emit_fragcoord_input(c, loc);
1600 } else if (var_needs_point_coord(c, var)) {
1601 c->inputs[loc * 4 + 0] = c->point_x;
1602 c->inputs[loc * 4 + 1] = c->point_y;
1603 } else {
1604 for (int j = 0; j < array_len; j++)
1605 emit_fragment_input(c, loc + j, var, j);
1606 }
1607 }
1608 }
1609
1610 static void
1611 ntq_setup_outputs(struct v3d_compile *c)
1612 {
1613 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
1614 return;
1615
1616 nir_foreach_variable(var, &c->s->outputs) {
1617 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1618 unsigned loc = var->data.driver_location * 4;
1619
1620 assert(array_len == 1);
1621 (void)array_len;
1622
1623 for (int i = 0; i < 4 - var->data.location_frac; i++) {
1624 add_output(c, loc + var->data.location_frac + i,
1625 var->data.location,
1626 var->data.location_frac + i);
1627 }
1628
1629 switch (var->data.location) {
1630 case FRAG_RESULT_COLOR:
1631 c->output_color_var[0] = var;
1632 c->output_color_var[1] = var;
1633 c->output_color_var[2] = var;
1634 c->output_color_var[3] = var;
1635 break;
1636 case FRAG_RESULT_DATA0:
1637 case FRAG_RESULT_DATA1:
1638 case FRAG_RESULT_DATA2:
1639 case FRAG_RESULT_DATA3:
1640 c->output_color_var[var->data.location -
1641 FRAG_RESULT_DATA0] = var;
1642 break;
1643 case FRAG_RESULT_DEPTH:
1644 c->output_position_index = loc;
1645 break;
1646 case FRAG_RESULT_SAMPLE_MASK:
1647 c->output_sample_mask_index = loc;
1648 break;
1649 }
1650 }
1651 }
1652
1653 /**
1654 * Sets up the mapping from nir_register to struct qreg *.
1655 *
1656 * Each nir_register gets a struct qreg per 32-bit component being stored.
1657 */
1658 static void
1659 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1660 {
1661 foreach_list_typed(nir_register, nir_reg, node, list) {
1662 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1663 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1664 array_len *
1665 nir_reg->num_components);
1666
1667 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1668
1669 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1670 qregs[i] = vir_get_temp(c);
1671 }
1672 }
1673
1674 static void
1675 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1676 {
1677 /* XXX perf: Experiment with using immediate loads to avoid having
1678 * these end up in the uniform stream. Watch out for breaking the
1679 * small immediates optimization in the process!
1680 */
1681 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1682 for (int i = 0; i < instr->def.num_components; i++)
1683 qregs[i] = vir_uniform_ui(c, instr->value[i].u32);
1684
1685 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1686 }
1687
1688 static void
1689 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1690 {
1691 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1692
1693 /* VIR needs there to be *some* value, so pick 0 (same as for
1694 * ntq_setup_registers().
1695 */
1696 for (int i = 0; i < instr->def.num_components; i++)
1697 qregs[i] = vir_uniform_ui(c, 0);
1698 }
1699
1700 static void
1701 ntq_emit_image_size(struct v3d_compile *c, nir_intrinsic_instr *instr)
1702 {
1703 assert(instr->intrinsic == nir_intrinsic_image_deref_size);
1704 nir_variable *var = nir_intrinsic_get_var(instr, 0);
1705 unsigned image_index = var->data.driver_location;
1706 const struct glsl_type *sampler_type = glsl_without_array(var->type);
1707 bool is_array = glsl_sampler_type_is_array(sampler_type);
1708
1709 ntq_store_dest(c, &instr->dest, 0,
1710 vir_uniform(c, QUNIFORM_IMAGE_WIDTH, image_index));
1711 if (instr->num_components > 1) {
1712 ntq_store_dest(c, &instr->dest, 1,
1713 vir_uniform(c, QUNIFORM_IMAGE_HEIGHT,
1714 image_index));
1715 }
1716 if (instr->num_components > 2) {
1717 ntq_store_dest(c, &instr->dest, 2,
1718 vir_uniform(c,
1719 is_array ?
1720 QUNIFORM_IMAGE_ARRAY_SIZE :
1721 QUNIFORM_IMAGE_DEPTH,
1722 image_index));
1723 }
1724 }
1725
1726 static void
1727 vir_emit_tlb_color_read(struct v3d_compile *c, nir_intrinsic_instr *instr)
1728 {
1729 assert(c->s->info.stage == MESA_SHADER_FRAGMENT);
1730
1731 int rt = nir_src_as_uint(instr->src[0]);
1732 assert(rt < V3D_MAX_DRAW_BUFFERS);
1733
1734 int sample_index = nir_intrinsic_base(instr) ;
1735 assert(sample_index < V3D_MAX_SAMPLES);
1736
1737 int component = nir_intrinsic_component(instr);
1738 assert(component < 4);
1739
1740 /* We need to emit our TLB reads after we have acquired the scoreboard
1741 * lock, or the GPU will hang. Usually, we do our scoreboard locking on
1742 * the last thread switch to improve parallelism, however, that is only
1743 * guaranteed to happen before the tlb color writes.
1744 *
1745 * To fix that, we make sure we always emit a thread switch before the
1746 * first tlb color read. If that happens to be the last thread switch
1747 * we emit, then everything is fine, but otherwsie, if any code after
1748 * this point needs to emit additional thread switches, then we will
1749 * switch the strategy to locking the scoreboard on the first thread
1750 * switch instead -- see vir_emit_thrsw().
1751 */
1752 if (!c->emitted_tlb_load) {
1753 if (!c->last_thrsw_at_top_level) {
1754 assert(c->devinfo->ver >= 41);
1755 vir_emit_thrsw(c);
1756 }
1757
1758 c->emitted_tlb_load = true;
1759 }
1760
1761 struct qreg *color_reads_for_sample =
1762 &c->color_reads[(rt * V3D_MAX_SAMPLES + sample_index) * 4];
1763
1764 if (color_reads_for_sample[component].file == QFILE_NULL) {
1765 enum pipe_format rt_format = c->fs_key->color_fmt[rt].format;
1766 int num_components =
1767 util_format_get_nr_components(rt_format);
1768
1769 const bool swap_rb = c->fs_key->swap_color_rb & (1 << rt);
1770 if (swap_rb)
1771 num_components = MAX2(num_components, 3);
1772
1773 nir_variable *var = c->output_color_var[rt];
1774 enum glsl_base_type type = glsl_get_base_type(var->type);
1775
1776 bool is_int_format = type == GLSL_TYPE_INT ||
1777 type == GLSL_TYPE_UINT;
1778
1779 bool is_32b_tlb_format = is_int_format ||
1780 (c->fs_key->f32_color_rb & (1 << rt));
1781
1782 int num_samples = c->fs_key->msaa ? V3D_MAX_SAMPLES : 1;
1783
1784 uint32_t conf = 0xffffff00;
1785 conf |= c->fs_key->msaa ? TLB_SAMPLE_MODE_PER_SAMPLE :
1786 TLB_SAMPLE_MODE_PER_PIXEL;
1787 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1788
1789 if (is_32b_tlb_format) {
1790 /* The F32 vs I32 distinction was dropped in 4.2. */
1791 conf |= (c->devinfo->ver < 42 && is_int_format) ?
1792 TLB_TYPE_I32_COLOR : TLB_TYPE_F32_COLOR;
1793
1794 conf |= ((num_components - 1) <<
1795 TLB_VEC_SIZE_MINUS_1_SHIFT);
1796 } else {
1797 conf |= TLB_TYPE_F16_COLOR;
1798 conf |= TLB_F16_SWAP_HI_LO;
1799
1800 if (num_components >= 3)
1801 conf |= TLB_VEC_SIZE_4_F16;
1802 else
1803 conf |= TLB_VEC_SIZE_2_F16;
1804 }
1805
1806
1807 for (int i = 0; i < num_samples; i++) {
1808 struct qreg r, g, b, a;
1809 if (is_32b_tlb_format) {
1810 r = conf != 0xffffffff && i == 0?
1811 vir_TLBU_COLOR_READ(c, conf) :
1812 vir_TLB_COLOR_READ(c);
1813 if (num_components >= 2)
1814 g = vir_TLB_COLOR_READ(c);
1815 if (num_components >= 3)
1816 b = vir_TLB_COLOR_READ(c);
1817 if (num_components >= 4)
1818 a = vir_TLB_COLOR_READ(c);
1819 } else {
1820 struct qreg rg = conf != 0xffffffff && i == 0 ?
1821 vir_TLBU_COLOR_READ(c, conf) :
1822 vir_TLB_COLOR_READ(c);
1823 r = vir_FMOV(c, rg);
1824 vir_set_unpack(c->defs[r.index], 0,
1825 V3D_QPU_UNPACK_L);
1826 g = vir_FMOV(c, rg);
1827 vir_set_unpack(c->defs[g.index], 0,
1828 V3D_QPU_UNPACK_H);
1829
1830 if (num_components > 2) {
1831 struct qreg ba = vir_TLB_COLOR_READ(c);
1832 b = vir_FMOV(c, ba);
1833 vir_set_unpack(c->defs[b.index], 0,
1834 V3D_QPU_UNPACK_L);
1835 a = vir_FMOV(c, ba);
1836 vir_set_unpack(c->defs[a.index], 0,
1837 V3D_QPU_UNPACK_H);
1838 }
1839 }
1840
1841 struct qreg *color_reads =
1842 &c->color_reads[(rt * V3D_MAX_SAMPLES + i) * 4];
1843
1844 color_reads[0] = swap_rb ? b : r;
1845 if (num_components >= 2)
1846 color_reads[1] = g;
1847 if (num_components >= 3)
1848 color_reads[2] = swap_rb ? r : b;
1849 if (num_components >= 4)
1850 color_reads[3] = a;
1851 }
1852 }
1853
1854 assert(color_reads_for_sample[component].file != QFILE_NULL);
1855 ntq_store_dest(c, &instr->dest, 0,
1856 vir_MOV(c, color_reads_for_sample[component]));
1857 }
1858
1859 static void
1860 ntq_emit_load_uniform(struct v3d_compile *c, nir_intrinsic_instr *instr)
1861 {
1862 if (nir_src_is_const(instr->src[0])) {
1863 int offset = (nir_intrinsic_base(instr) +
1864 nir_src_as_uint(instr->src[0]));
1865 assert(offset % 4 == 0);
1866 /* We need dwords */
1867 offset = offset / 4;
1868 for (int i = 0; i < instr->num_components; i++) {
1869 ntq_store_dest(c, &instr->dest, i,
1870 vir_uniform(c, QUNIFORM_UNIFORM,
1871 offset + i));
1872 }
1873 } else {
1874 ntq_emit_tmu_general(c, instr, false);
1875 }
1876 }
1877
1878 static void
1879 ntq_emit_load_input(struct v3d_compile *c, nir_intrinsic_instr *instr)
1880 {
1881 /* XXX: Use ldvpmv (uniform offset) or ldvpmd (non-uniform offset)
1882 * and enable PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR.
1883 */
1884 unsigned offset =
1885 nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[0]);
1886
1887 if (c->s->info.stage != MESA_SHADER_FRAGMENT && c->devinfo->ver >= 40) {
1888 /* Emit the LDVPM directly now, rather than at the top
1889 * of the shader like we did for V3D 3.x (which needs
1890 * vpmsetup when not just taking the next offset).
1891 *
1892 * Note that delaying like this may introduce stalls,
1893 * as LDVPMV takes a minimum of 1 instruction but may
1894 * be slower if the VPM unit is busy with another QPU.
1895 */
1896 int index = 0;
1897 if (c->s->info.system_values_read &
1898 (1ull << SYSTEM_VALUE_INSTANCE_ID)) {
1899 index++;
1900 }
1901 if (c->s->info.system_values_read &
1902 (1ull << SYSTEM_VALUE_VERTEX_ID)) {
1903 index++;
1904 }
1905 for (int i = 0; i < offset; i++)
1906 index += c->vattr_sizes[i];
1907 index += nir_intrinsic_component(instr);
1908 for (int i = 0; i < instr->num_components; i++) {
1909 struct qreg vpm_offset = vir_uniform_ui(c, index++);
1910 ntq_store_dest(c, &instr->dest, i,
1911 vir_LDVPMV_IN(c, vpm_offset));
1912 }
1913 } else {
1914 for (int i = 0; i < instr->num_components; i++) {
1915 int comp = nir_intrinsic_component(instr) + i;
1916 ntq_store_dest(c, &instr->dest, i,
1917 vir_MOV(c, c->inputs[offset * 4 + comp]));
1918 }
1919 }
1920 }
1921
1922 static void
1923 ntq_emit_per_sample_color_write(struct v3d_compile *c,
1924 nir_intrinsic_instr *instr)
1925 {
1926 assert(instr->intrinsic == nir_intrinsic_store_tlb_sample_color_v3d);
1927
1928 unsigned rt = nir_src_as_uint(instr->src[1]);
1929 assert(rt < V3D_MAX_DRAW_BUFFERS);
1930
1931 unsigned sample_idx = nir_intrinsic_base(instr);
1932 assert(sample_idx < V3D_MAX_SAMPLES);
1933
1934 unsigned offset = (rt * V3D_MAX_SAMPLES + sample_idx) * 4;
1935 for (int i = 0; i < instr->num_components; i++) {
1936 c->sample_colors[offset + i] =
1937 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
1938 }
1939 }
1940
1941 static void
1942 ntq_emit_color_write(struct v3d_compile *c,
1943 nir_intrinsic_instr *instr)
1944 {
1945 unsigned offset = (nir_intrinsic_base(instr) +
1946 nir_src_as_uint(instr->src[1])) * 4 +
1947 nir_intrinsic_component(instr);
1948 for (int i = 0; i < instr->num_components; i++) {
1949 c->outputs[offset + i] =
1950 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
1951 }
1952 }
1953
1954 static void
1955 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
1956 {
1957 switch (instr->intrinsic) {
1958 case nir_intrinsic_load_uniform:
1959 ntq_emit_load_uniform(c, instr);
1960 break;
1961
1962 case nir_intrinsic_load_ubo:
1963 ntq_emit_tmu_general(c, instr, false);
1964 break;
1965
1966 case nir_intrinsic_ssbo_atomic_add:
1967 case nir_intrinsic_ssbo_atomic_imin:
1968 case nir_intrinsic_ssbo_atomic_umin:
1969 case nir_intrinsic_ssbo_atomic_imax:
1970 case nir_intrinsic_ssbo_atomic_umax:
1971 case nir_intrinsic_ssbo_atomic_and:
1972 case nir_intrinsic_ssbo_atomic_or:
1973 case nir_intrinsic_ssbo_atomic_xor:
1974 case nir_intrinsic_ssbo_atomic_exchange:
1975 case nir_intrinsic_ssbo_atomic_comp_swap:
1976 case nir_intrinsic_load_ssbo:
1977 case nir_intrinsic_store_ssbo:
1978 ntq_emit_tmu_general(c, instr, false);
1979 break;
1980
1981 case nir_intrinsic_shared_atomic_add:
1982 case nir_intrinsic_shared_atomic_imin:
1983 case nir_intrinsic_shared_atomic_umin:
1984 case nir_intrinsic_shared_atomic_imax:
1985 case nir_intrinsic_shared_atomic_umax:
1986 case nir_intrinsic_shared_atomic_and:
1987 case nir_intrinsic_shared_atomic_or:
1988 case nir_intrinsic_shared_atomic_xor:
1989 case nir_intrinsic_shared_atomic_exchange:
1990 case nir_intrinsic_shared_atomic_comp_swap:
1991 case nir_intrinsic_load_shared:
1992 case nir_intrinsic_store_shared:
1993 case nir_intrinsic_load_scratch:
1994 case nir_intrinsic_store_scratch:
1995 ntq_emit_tmu_general(c, instr, true);
1996 break;
1997
1998 case nir_intrinsic_image_deref_load:
1999 case nir_intrinsic_image_deref_store:
2000 case nir_intrinsic_image_deref_atomic_add:
2001 case nir_intrinsic_image_deref_atomic_imin:
2002 case nir_intrinsic_image_deref_atomic_umin:
2003 case nir_intrinsic_image_deref_atomic_imax:
2004 case nir_intrinsic_image_deref_atomic_umax:
2005 case nir_intrinsic_image_deref_atomic_and:
2006 case nir_intrinsic_image_deref_atomic_or:
2007 case nir_intrinsic_image_deref_atomic_xor:
2008 case nir_intrinsic_image_deref_atomic_exchange:
2009 case nir_intrinsic_image_deref_atomic_comp_swap:
2010 v3d40_vir_emit_image_load_store(c, instr);
2011 break;
2012
2013 case nir_intrinsic_get_buffer_size:
2014 ntq_store_dest(c, &instr->dest, 0,
2015 vir_uniform(c, QUNIFORM_GET_BUFFER_SIZE,
2016 nir_src_as_uint(instr->src[0])));
2017 break;
2018
2019 case nir_intrinsic_load_user_clip_plane:
2020 for (int i = 0; i < instr->num_components; i++) {
2021 ntq_store_dest(c, &instr->dest, i,
2022 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
2023 nir_intrinsic_ucp_id(instr) *
2024 4 + i));
2025 }
2026 break;
2027
2028 case nir_intrinsic_load_viewport_x_scale:
2029 ntq_store_dest(c, &instr->dest, 0,
2030 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE, 0));
2031 break;
2032
2033 case nir_intrinsic_load_viewport_y_scale:
2034 ntq_store_dest(c, &instr->dest, 0,
2035 vir_uniform(c, QUNIFORM_VIEWPORT_Y_SCALE, 0));
2036 break;
2037
2038 case nir_intrinsic_load_viewport_z_scale:
2039 ntq_store_dest(c, &instr->dest, 0,
2040 vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0));
2041 break;
2042
2043 case nir_intrinsic_load_viewport_z_offset:
2044 ntq_store_dest(c, &instr->dest, 0,
2045 vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0));
2046 break;
2047
2048 case nir_intrinsic_load_alpha_ref_float:
2049 ntq_store_dest(c, &instr->dest, 0,
2050 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
2051 break;
2052
2053 case nir_intrinsic_load_sample_mask_in:
2054 ntq_store_dest(c, &instr->dest, 0, vir_MSF(c));
2055 break;
2056
2057 case nir_intrinsic_load_helper_invocation:
2058 vir_set_pf(vir_MSF_dest(c, vir_nop_reg()), V3D_QPU_PF_PUSHZ);
2059 ntq_store_dest(c, &instr->dest, 0,
2060 vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
2061 vir_uniform_ui(c, ~0),
2062 vir_uniform_ui(c, 0))));
2063 break;
2064
2065 case nir_intrinsic_load_front_face:
2066 /* The register contains 0 (front) or 1 (back), and we need to
2067 * turn it into a NIR bool where true means front.
2068 */
2069 ntq_store_dest(c, &instr->dest, 0,
2070 vir_ADD(c,
2071 vir_uniform_ui(c, -1),
2072 vir_REVF(c)));
2073 break;
2074
2075 case nir_intrinsic_load_instance_id:
2076 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
2077 break;
2078
2079 case nir_intrinsic_load_vertex_id:
2080 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
2081 break;
2082
2083 case nir_intrinsic_load_tlb_color_v3d:
2084 vir_emit_tlb_color_read(c, instr);
2085 break;
2086
2087 case nir_intrinsic_load_input:
2088 ntq_emit_load_input(c, instr);
2089 break;
2090
2091 case nir_intrinsic_store_tlb_sample_color_v3d:
2092 ntq_emit_per_sample_color_write(c, instr);
2093 break;
2094
2095 case nir_intrinsic_store_output:
2096 /* XXX perf: Use stvpmv with uniform non-constant offsets and
2097 * stvpmd with non-uniform offsets and enable
2098 * PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR.
2099 */
2100 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
2101 ntq_emit_color_write(c, instr);
2102 } else {
2103 assert(instr->num_components == 1);
2104
2105 vir_VPM_WRITE(c,
2106 ntq_get_src(c, instr->src[0], 0),
2107 nir_intrinsic_base(instr));
2108 }
2109 break;
2110
2111 case nir_intrinsic_image_deref_size:
2112 ntq_emit_image_size(c, instr);
2113 break;
2114
2115 case nir_intrinsic_discard:
2116 if (vir_in_nonuniform_control_flow(c)) {
2117 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2118 V3D_QPU_PF_PUSHZ);
2119 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
2120 vir_uniform_ui(c, 0)),
2121 V3D_QPU_COND_IFA);
2122 } else {
2123 vir_SETMSF_dest(c, vir_nop_reg(),
2124 vir_uniform_ui(c, 0));
2125 }
2126 break;
2127
2128 case nir_intrinsic_discard_if: {
2129 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, instr->src[0]);
2130
2131 if (vir_in_nonuniform_control_flow(c)) {
2132 struct qinst *exec_flag = vir_MOV_dest(c, vir_nop_reg(),
2133 c->execute);
2134 if (cond == V3D_QPU_COND_IFA) {
2135 vir_set_uf(exec_flag, V3D_QPU_UF_ANDZ);
2136 } else {
2137 vir_set_uf(exec_flag, V3D_QPU_UF_NORNZ);
2138 cond = V3D_QPU_COND_IFA;
2139 }
2140 }
2141
2142 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
2143 vir_uniform_ui(c, 0)), cond);
2144
2145 break;
2146 }
2147
2148 case nir_intrinsic_memory_barrier:
2149 case nir_intrinsic_memory_barrier_atomic_counter:
2150 case nir_intrinsic_memory_barrier_buffer:
2151 case nir_intrinsic_memory_barrier_image:
2152 case nir_intrinsic_memory_barrier_shared:
2153 case nir_intrinsic_group_memory_barrier:
2154 /* We don't do any instruction scheduling of these NIR
2155 * instructions between each other, so we just need to make
2156 * sure that the TMU operations before the barrier are flushed
2157 * before the ones after the barrier. That is currently
2158 * handled by having a THRSW in each of them and a LDTMU
2159 * series or a TMUWT after.
2160 */
2161 break;
2162
2163 case nir_intrinsic_barrier:
2164 /* Emit a TSY op to get all invocations in the workgroup
2165 * (actually supergroup) to block until the last invocation
2166 * reaches the TSY op.
2167 */
2168 if (c->devinfo->ver >= 42) {
2169 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
2170 V3D_QPU_WADDR_SYNCB));
2171 } else {
2172 struct qinst *sync =
2173 vir_BARRIERID_dest(c,
2174 vir_reg(QFILE_MAGIC,
2175 V3D_QPU_WADDR_SYNCU));
2176 sync->uniform =
2177 vir_get_uniform_index(c, QUNIFORM_CONSTANT,
2178 0xffffff00 |
2179 V3D_TSY_WAIT_INC_CHECK);
2180
2181 }
2182
2183 /* The blocking of a TSY op only happens at the next thread
2184 * switch. No texturing may be outstanding at the time of a
2185 * TSY blocking operation.
2186 */
2187 vir_emit_thrsw(c);
2188 break;
2189
2190 case nir_intrinsic_load_num_work_groups:
2191 for (int i = 0; i < 3; i++) {
2192 ntq_store_dest(c, &instr->dest, i,
2193 vir_uniform(c, QUNIFORM_NUM_WORK_GROUPS,
2194 i));
2195 }
2196 break;
2197
2198 case nir_intrinsic_load_local_invocation_index:
2199 ntq_store_dest(c, &instr->dest, 0,
2200 vir_SHR(c, c->cs_payload[1],
2201 vir_uniform_ui(c, 32 - c->local_invocation_index_bits)));
2202 break;
2203
2204 case nir_intrinsic_load_work_group_id:
2205 ntq_store_dest(c, &instr->dest, 0,
2206 vir_AND(c, c->cs_payload[0],
2207 vir_uniform_ui(c, 0xffff)));
2208 ntq_store_dest(c, &instr->dest, 1,
2209 vir_SHR(c, c->cs_payload[0],
2210 vir_uniform_ui(c, 16)));
2211 ntq_store_dest(c, &instr->dest, 2,
2212 vir_AND(c, c->cs_payload[1],
2213 vir_uniform_ui(c, 0xffff)));
2214 break;
2215
2216 case nir_intrinsic_load_subgroup_id:
2217 ntq_store_dest(c, &instr->dest, 0, vir_EIDX(c));
2218 break;
2219
2220 default:
2221 fprintf(stderr, "Unknown intrinsic: ");
2222 nir_print_instr(&instr->instr, stderr);
2223 fprintf(stderr, "\n");
2224 break;
2225 }
2226 }
2227
2228 /* Clears (activates) the execute flags for any channels whose jump target
2229 * matches this block.
2230 *
2231 * XXX perf: Could we be using flpush/flpop somehow for our execution channel
2232 * enabling?
2233 *
2234 * XXX perf: For uniform control flow, we should be able to skip c->execute
2235 * handling entirely.
2236 */
2237 static void
2238 ntq_activate_execute_for_block(struct v3d_compile *c)
2239 {
2240 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
2241 c->execute, vir_uniform_ui(c, c->cur_block->index)),
2242 V3D_QPU_PF_PUSHZ);
2243
2244 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2245 }
2246
2247 static void
2248 ntq_emit_uniform_if(struct v3d_compile *c, nir_if *if_stmt)
2249 {
2250 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2251 bool empty_else_block =
2252 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2253 exec_list_is_empty(&nir_else_block->instr_list));
2254
2255 struct qblock *then_block = vir_new_block(c);
2256 struct qblock *after_block = vir_new_block(c);
2257 struct qblock *else_block;
2258 if (empty_else_block)
2259 else_block = after_block;
2260 else
2261 else_block = vir_new_block(c);
2262
2263 /* Set up the flags for the IF condition (taking the THEN branch). */
2264 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
2265
2266 /* Jump to ELSE. */
2267 vir_BRANCH(c, cond == V3D_QPU_COND_IFA ?
2268 V3D_QPU_BRANCH_COND_ALLNA :
2269 V3D_QPU_BRANCH_COND_ALLA);
2270 vir_link_blocks(c->cur_block, else_block);
2271 vir_link_blocks(c->cur_block, then_block);
2272
2273 /* Process the THEN block. */
2274 vir_set_emit_block(c, then_block);
2275 ntq_emit_cf_list(c, &if_stmt->then_list);
2276
2277 if (!empty_else_block) {
2278 /* At the end of the THEN block, jump to ENDIF */
2279 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALWAYS);
2280 vir_link_blocks(c->cur_block, after_block);
2281
2282 /* Emit the else block. */
2283 vir_set_emit_block(c, else_block);
2284 ntq_emit_cf_list(c, &if_stmt->else_list);
2285 }
2286
2287 vir_link_blocks(c->cur_block, after_block);
2288
2289 vir_set_emit_block(c, after_block);
2290 }
2291
2292 static void
2293 ntq_emit_nonuniform_if(struct v3d_compile *c, nir_if *if_stmt)
2294 {
2295 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2296 bool empty_else_block =
2297 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2298 exec_list_is_empty(&nir_else_block->instr_list));
2299
2300 struct qblock *then_block = vir_new_block(c);
2301 struct qblock *after_block = vir_new_block(c);
2302 struct qblock *else_block;
2303 if (empty_else_block)
2304 else_block = after_block;
2305 else
2306 else_block = vir_new_block(c);
2307
2308 bool was_uniform_control_flow = false;
2309 if (!vir_in_nonuniform_control_flow(c)) {
2310 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2311 was_uniform_control_flow = true;
2312 }
2313
2314 /* Set up the flags for the IF condition (taking the THEN branch). */
2315 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
2316
2317 /* Update the flags+cond to mean "Taking the ELSE branch (!cond) and
2318 * was previously active (execute Z) for updating the exec flags.
2319 */
2320 if (was_uniform_control_flow) {
2321 cond = v3d_qpu_cond_invert(cond);
2322 } else {
2323 struct qinst *inst = vir_MOV_dest(c, vir_nop_reg(), c->execute);
2324 if (cond == V3D_QPU_COND_IFA) {
2325 vir_set_uf(inst, V3D_QPU_UF_NORNZ);
2326 } else {
2327 vir_set_uf(inst, V3D_QPU_UF_ANDZ);
2328 cond = V3D_QPU_COND_IFA;
2329 }
2330 }
2331
2332 vir_MOV_cond(c, cond,
2333 c->execute,
2334 vir_uniform_ui(c, else_block->index));
2335
2336 /* Jump to ELSE if nothing is active for THEN, otherwise fall
2337 * through.
2338 */
2339 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ);
2340 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
2341 vir_link_blocks(c->cur_block, else_block);
2342 vir_link_blocks(c->cur_block, then_block);
2343
2344 /* Process the THEN block. */
2345 vir_set_emit_block(c, then_block);
2346 ntq_emit_cf_list(c, &if_stmt->then_list);
2347
2348 if (!empty_else_block) {
2349 /* Handle the end of the THEN block. First, all currently
2350 * active channels update their execute flags to point to
2351 * ENDIF
2352 */
2353 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2354 V3D_QPU_PF_PUSHZ);
2355 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2356 vir_uniform_ui(c, after_block->index));
2357
2358 /* If everything points at ENDIF, then jump there immediately. */
2359 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
2360 c->execute,
2361 vir_uniform_ui(c, after_block->index)),
2362 V3D_QPU_PF_PUSHZ);
2363 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
2364 vir_link_blocks(c->cur_block, after_block);
2365 vir_link_blocks(c->cur_block, else_block);
2366
2367 vir_set_emit_block(c, else_block);
2368 ntq_activate_execute_for_block(c);
2369 ntq_emit_cf_list(c, &if_stmt->else_list);
2370 }
2371
2372 vir_link_blocks(c->cur_block, after_block);
2373
2374 vir_set_emit_block(c, after_block);
2375 if (was_uniform_control_flow)
2376 c->execute = c->undef;
2377 else
2378 ntq_activate_execute_for_block(c);
2379 }
2380
2381 static void
2382 ntq_emit_if(struct v3d_compile *c, nir_if *nif)
2383 {
2384 bool was_in_control_flow = c->in_control_flow;
2385 c->in_control_flow = true;
2386 if (!vir_in_nonuniform_control_flow(c) &&
2387 nir_src_is_dynamically_uniform(nif->condition)) {
2388 ntq_emit_uniform_if(c, nif);
2389 } else {
2390 ntq_emit_nonuniform_if(c, nif);
2391 }
2392 c->in_control_flow = was_in_control_flow;
2393 }
2394
2395 static void
2396 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
2397 {
2398 switch (jump->type) {
2399 case nir_jump_break:
2400 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2401 V3D_QPU_PF_PUSHZ);
2402 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2403 vir_uniform_ui(c, c->loop_break_block->index));
2404 break;
2405
2406 case nir_jump_continue:
2407 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2408 V3D_QPU_PF_PUSHZ);
2409 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2410 vir_uniform_ui(c, c->loop_cont_block->index));
2411 break;
2412
2413 case nir_jump_return:
2414 unreachable("All returns shouold be lowered\n");
2415 }
2416 }
2417
2418 static void
2419 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
2420 {
2421 switch (instr->type) {
2422 case nir_instr_type_deref:
2423 /* ignored, will be walked by the intrinsic using it. */
2424 break;
2425
2426 case nir_instr_type_alu:
2427 ntq_emit_alu(c, nir_instr_as_alu(instr));
2428 break;
2429
2430 case nir_instr_type_intrinsic:
2431 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
2432 break;
2433
2434 case nir_instr_type_load_const:
2435 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
2436 break;
2437
2438 case nir_instr_type_ssa_undef:
2439 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
2440 break;
2441
2442 case nir_instr_type_tex:
2443 ntq_emit_tex(c, nir_instr_as_tex(instr));
2444 break;
2445
2446 case nir_instr_type_jump:
2447 ntq_emit_jump(c, nir_instr_as_jump(instr));
2448 break;
2449
2450 default:
2451 fprintf(stderr, "Unknown NIR instr type: ");
2452 nir_print_instr(instr, stderr);
2453 fprintf(stderr, "\n");
2454 abort();
2455 }
2456 }
2457
2458 static void
2459 ntq_emit_block(struct v3d_compile *c, nir_block *block)
2460 {
2461 nir_foreach_instr(instr, block) {
2462 ntq_emit_instr(c, instr);
2463 }
2464 }
2465
2466 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
2467
2468 static void
2469 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
2470 {
2471 bool was_in_control_flow = c->in_control_flow;
2472 c->in_control_flow = true;
2473
2474 bool was_uniform_control_flow = false;
2475 if (!vir_in_nonuniform_control_flow(c)) {
2476 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2477 was_uniform_control_flow = true;
2478 }
2479
2480 struct qblock *save_loop_cont_block = c->loop_cont_block;
2481 struct qblock *save_loop_break_block = c->loop_break_block;
2482
2483 c->loop_cont_block = vir_new_block(c);
2484 c->loop_break_block = vir_new_block(c);
2485
2486 vir_link_blocks(c->cur_block, c->loop_cont_block);
2487 vir_set_emit_block(c, c->loop_cont_block);
2488 ntq_activate_execute_for_block(c);
2489
2490 ntq_emit_cf_list(c, &loop->body);
2491
2492 /* Re-enable any previous continues now, so our ANYA check below
2493 * works.
2494 *
2495 * XXX: Use the .ORZ flags update, instead.
2496 */
2497 vir_set_pf(vir_XOR_dest(c,
2498 vir_nop_reg(),
2499 c->execute,
2500 vir_uniform_ui(c, c->loop_cont_block->index)),
2501 V3D_QPU_PF_PUSHZ);
2502 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2503
2504 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ);
2505
2506 struct qinst *branch = vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
2507 /* Pixels that were not dispatched or have been discarded should not
2508 * contribute to looping again.
2509 */
2510 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P;
2511 vir_link_blocks(c->cur_block, c->loop_cont_block);
2512 vir_link_blocks(c->cur_block, c->loop_break_block);
2513
2514 vir_set_emit_block(c, c->loop_break_block);
2515 if (was_uniform_control_flow)
2516 c->execute = c->undef;
2517 else
2518 ntq_activate_execute_for_block(c);
2519
2520 c->loop_break_block = save_loop_break_block;
2521 c->loop_cont_block = save_loop_cont_block;
2522
2523 c->loops++;
2524
2525 c->in_control_flow = was_in_control_flow;
2526 }
2527
2528 static void
2529 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
2530 {
2531 fprintf(stderr, "FUNCTIONS not handled.\n");
2532 abort();
2533 }
2534
2535 static void
2536 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
2537 {
2538 foreach_list_typed(nir_cf_node, node, node, list) {
2539 switch (node->type) {
2540 case nir_cf_node_block:
2541 ntq_emit_block(c, nir_cf_node_as_block(node));
2542 break;
2543
2544 case nir_cf_node_if:
2545 ntq_emit_if(c, nir_cf_node_as_if(node));
2546 break;
2547
2548 case nir_cf_node_loop:
2549 ntq_emit_loop(c, nir_cf_node_as_loop(node));
2550 break;
2551
2552 case nir_cf_node_function:
2553 ntq_emit_function(c, nir_cf_node_as_function(node));
2554 break;
2555
2556 default:
2557 fprintf(stderr, "Unknown NIR node type\n");
2558 abort();
2559 }
2560 }
2561 }
2562
2563 static void
2564 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
2565 {
2566 ntq_setup_registers(c, &impl->registers);
2567 ntq_emit_cf_list(c, &impl->body);
2568 }
2569
2570 static void
2571 nir_to_vir(struct v3d_compile *c)
2572 {
2573 switch (c->s->info.stage) {
2574 case MESA_SHADER_FRAGMENT:
2575 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
2576 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
2577 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
2578
2579 /* V3D 4.x can disable implicit point coordinate varyings if
2580 * they are not used.
2581 */
2582 if (c->fs_key->is_points &&
2583 (c->devinfo->ver < 40 || program_reads_point_coord(c))) {
2584 c->point_x = emit_fragment_varying(c, NULL, 0, 0);
2585 c->point_y = emit_fragment_varying(c, NULL, 0, 0);
2586 c->uses_implicit_point_line_varyings = true;
2587 } else if (c->fs_key->is_lines && c->devinfo->ver < 40) {
2588 c->line_x = emit_fragment_varying(c, NULL, 0, 0);
2589 c->uses_implicit_point_line_varyings = true;
2590 }
2591 break;
2592 case MESA_SHADER_COMPUTE:
2593 /* Set up the TSO for barriers, assuming we do some. */
2594 if (c->devinfo->ver < 42) {
2595 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
2596 V3D_QPU_WADDR_SYNC));
2597 }
2598
2599 c->cs_payload[0] = vir_MOV(c, vir_reg(QFILE_REG, 0));
2600 c->cs_payload[1] = vir_MOV(c, vir_reg(QFILE_REG, 2));
2601
2602 /* Set up the division between gl_LocalInvocationIndex and
2603 * wg_in_mem in the payload reg.
2604 */
2605 int wg_size = (c->s->info.cs.local_size[0] *
2606 c->s->info.cs.local_size[1] *
2607 c->s->info.cs.local_size[2]);
2608 c->local_invocation_index_bits =
2609 ffs(util_next_power_of_two(MAX2(wg_size, 64))) - 1;
2610 assert(c->local_invocation_index_bits <= 8);
2611
2612 if (c->s->info.cs.shared_size) {
2613 struct qreg wg_in_mem = vir_SHR(c, c->cs_payload[1],
2614 vir_uniform_ui(c, 16));
2615 if (c->s->info.cs.local_size[0] != 1 ||
2616 c->s->info.cs.local_size[1] != 1 ||
2617 c->s->info.cs.local_size[2] != 1) {
2618 int wg_bits = (16 -
2619 c->local_invocation_index_bits);
2620 int wg_mask = (1 << wg_bits) - 1;
2621 wg_in_mem = vir_AND(c, wg_in_mem,
2622 vir_uniform_ui(c, wg_mask));
2623 }
2624 struct qreg shared_per_wg =
2625 vir_uniform_ui(c, c->s->info.cs.shared_size);
2626
2627 c->cs_shared_offset =
2628 vir_ADD(c,
2629 vir_uniform(c, QUNIFORM_SHARED_OFFSET,0),
2630 vir_UMUL(c, wg_in_mem, shared_per_wg));
2631 }
2632 break;
2633 default:
2634 break;
2635 }
2636
2637 if (c->s->scratch_size) {
2638 v3d_setup_spill_base(c);
2639 c->spill_size += V3D_CHANNELS * c->s->scratch_size;
2640 }
2641
2642 if (c->s->info.stage == MESA_SHADER_FRAGMENT)
2643 ntq_setup_fs_inputs(c);
2644 else
2645 ntq_setup_vpm_inputs(c);
2646
2647 ntq_setup_outputs(c);
2648
2649 /* Find the main function and emit the body. */
2650 nir_foreach_function(function, c->s) {
2651 assert(strcmp(function->name, "main") == 0);
2652 assert(function->impl);
2653 ntq_emit_impl(c, function->impl);
2654 }
2655 }
2656
2657 const nir_shader_compiler_options v3d_nir_options = {
2658 .lower_all_io_to_temps = true,
2659 .lower_extract_byte = true,
2660 .lower_extract_word = true,
2661 .lower_bitfield_insert_to_shifts = true,
2662 .lower_bitfield_extract_to_shifts = true,
2663 .lower_bitfield_reverse = true,
2664 .lower_bit_count = true,
2665 .lower_cs_local_id_from_index = true,
2666 .lower_ffract = true,
2667 .lower_fmod = true,
2668 .lower_pack_unorm_2x16 = true,
2669 .lower_pack_snorm_2x16 = true,
2670 .lower_pack_unorm_4x8 = true,
2671 .lower_pack_snorm_4x8 = true,
2672 .lower_unpack_unorm_4x8 = true,
2673 .lower_unpack_snorm_4x8 = true,
2674 .lower_pack_half_2x16 = true,
2675 .lower_unpack_half_2x16 = true,
2676 .lower_fdiv = true,
2677 .lower_find_lsb = true,
2678 .lower_ffma = true,
2679 .lower_flrp32 = true,
2680 .lower_fpow = true,
2681 .lower_fsat = true,
2682 .lower_fsqrt = true,
2683 .lower_ifind_msb = true,
2684 .lower_isign = true,
2685 .lower_ldexp = true,
2686 .lower_mul_high = true,
2687 .lower_wpos_pntc = true,
2688 .lower_rotate = true,
2689 .lower_to_scalar = true,
2690 };
2691
2692 /**
2693 * When demoting a shader down to single-threaded, removes the THRSW
2694 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
2695 * program end).
2696 */
2697 static void
2698 vir_remove_thrsw(struct v3d_compile *c)
2699 {
2700 vir_for_each_block(block, c) {
2701 vir_for_each_inst_safe(inst, block) {
2702 if (inst->qpu.sig.thrsw)
2703 vir_remove_instruction(c, inst);
2704 }
2705 }
2706
2707 c->last_thrsw = NULL;
2708 }
2709
2710 void
2711 vir_emit_last_thrsw(struct v3d_compile *c)
2712 {
2713 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
2714 * switching, so disable threads if we didn't do any TMU ops (each of
2715 * which would have emitted a THRSW).
2716 */
2717 if (!c->last_thrsw_at_top_level && c->devinfo->ver < 41) {
2718 c->threads = 1;
2719 if (c->last_thrsw)
2720 vir_remove_thrsw(c);
2721 return;
2722 }
2723
2724 /* If we're threaded and the last THRSW was in conditional code, then
2725 * we need to emit another one so that we can flag it as the last
2726 * thrsw.
2727 */
2728 if (c->last_thrsw && !c->last_thrsw_at_top_level) {
2729 assert(c->devinfo->ver >= 41);
2730 vir_emit_thrsw(c);
2731 }
2732
2733 /* If we're threaded, then we need to mark the last THRSW instruction
2734 * so we can emit a pair of them at QPU emit time.
2735 *
2736 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2737 * post-last-THRSW state, so we can skip this.
2738 */
2739 if (!c->last_thrsw && c->s->info.stage == MESA_SHADER_FRAGMENT) {
2740 assert(c->devinfo->ver >= 41);
2741 vir_emit_thrsw(c);
2742 }
2743
2744 if (c->last_thrsw)
2745 c->last_thrsw->is_last_thrsw = true;
2746 }
2747
2748 /* There's a flag in the shader for "center W is needed for reasons other than
2749 * non-centroid varyings", so we just walk the program after VIR optimization
2750 * to see if it's used. It should be harmless to set even if we only use
2751 * center W for varyings.
2752 */
2753 static void
2754 vir_check_payload_w(struct v3d_compile *c)
2755 {
2756 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
2757 return;
2758
2759 vir_for_each_inst_inorder(inst, c) {
2760 for (int i = 0; i < vir_get_nsrc(inst); i++) {
2761 if (inst->src[i].file == QFILE_REG &&
2762 inst->src[i].index == 0) {
2763 c->uses_center_w = true;
2764 return;
2765 }
2766 }
2767 }
2768
2769 }
2770
2771 void
2772 v3d_nir_to_vir(struct v3d_compile *c)
2773 {
2774 if (V3D_DEBUG & (V3D_DEBUG_NIR |
2775 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2776 fprintf(stderr, "%s prog %d/%d NIR:\n",
2777 vir_get_stage_name(c),
2778 c->program_id, c->variant_id);
2779 nir_print_shader(c->s, stderr);
2780 }
2781
2782 nir_to_vir(c);
2783
2784 /* Emit the last THRSW before STVPM and TLB writes. */
2785 vir_emit_last_thrsw(c);
2786
2787 switch (c->s->info.stage) {
2788 case MESA_SHADER_FRAGMENT:
2789 emit_frag_end(c);
2790 break;
2791 case MESA_SHADER_VERTEX:
2792 emit_vert_end(c);
2793 break;
2794 case MESA_SHADER_COMPUTE:
2795 break;
2796 default:
2797 unreachable("bad stage");
2798 }
2799
2800 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2801 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2802 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
2803 vir_get_stage_name(c),
2804 c->program_id, c->variant_id);
2805 vir_dump(c);
2806 fprintf(stderr, "\n");
2807 }
2808
2809 vir_optimize(c);
2810
2811 vir_check_payload_w(c);
2812
2813 /* XXX perf: On VC4, we do a VIR-level instruction scheduling here.
2814 * We used that on that platform to pipeline TMU writes and reduce the
2815 * number of thread switches, as well as try (mostly successfully) to
2816 * reduce maximum register pressure to allow more threads. We should
2817 * do something of that sort for V3D -- either instruction scheduling
2818 * here, or delay the the THRSW and LDTMUs from our texture
2819 * instructions until the results are needed.
2820 */
2821
2822 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2823 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2824 fprintf(stderr, "%s prog %d/%d VIR:\n",
2825 vir_get_stage_name(c),
2826 c->program_id, c->variant_id);
2827 vir_dump(c);
2828 fprintf(stderr, "\n");
2829 }
2830
2831 /* Attempt to allocate registers for the temporaries. If we fail,
2832 * reduce thread count and try again.
2833 */
2834 int min_threads = (c->devinfo->ver >= 41) ? 2 : 1;
2835 struct qpu_reg *temp_registers;
2836 while (true) {
2837 bool spilled;
2838 temp_registers = v3d_register_allocate(c, &spilled);
2839 if (spilled)
2840 continue;
2841
2842 if (temp_registers)
2843 break;
2844
2845 if (c->threads == min_threads) {
2846 fprintf(stderr, "Failed to register allocate at %d threads:\n",
2847 c->threads);
2848 vir_dump(c);
2849 c->failed = true;
2850 return;
2851 }
2852
2853 c->threads /= 2;
2854
2855 if (c->threads == 1)
2856 vir_remove_thrsw(c);
2857 }
2858
2859 if (c->spills &&
2860 (V3D_DEBUG & (V3D_DEBUG_VIR |
2861 v3d_debug_flag_for_shader_stage(c->s->info.stage)))) {
2862 fprintf(stderr, "%s prog %d/%d spilled VIR:\n",
2863 vir_get_stage_name(c),
2864 c->program_id, c->variant_id);
2865 vir_dump(c);
2866 fprintf(stderr, "\n");
2867 }
2868
2869 v3d_vir_to_qpu(c, temp_registers);
2870 }