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v3d: handle nir_intrinsic_store_tlb_sample_color_v3d
[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
34
35 /* We don't do any address packing. */
36 #define __gen_user_data void
37 #define __gen_address_type uint32_t
38 #define __gen_address_offset(reloc) (*reloc)
39 #define __gen_emit_reloc(cl, reloc)
40 #include "cle/v3d_packet_v41_pack.h"
41
42 #define GENERAL_TMU_LOOKUP_PER_QUAD (0 << 7)
43 #define GENERAL_TMU_LOOKUP_PER_PIXEL (1 << 7)
44 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_I (0 << 0)
45 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_I (1 << 0)
46 #define GENERAL_TMU_LOOKUP_TYPE_VEC2 (2 << 0)
47 #define GENERAL_TMU_LOOKUP_TYPE_VEC3 (3 << 0)
48 #define GENERAL_TMU_LOOKUP_TYPE_VEC4 (4 << 0)
49 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_UI (5 << 0)
50 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_UI (6 << 0)
51 #define GENERAL_TMU_LOOKUP_TYPE_32BIT_UI (7 << 0)
52
53 #define V3D_TSY_SET_QUORUM 0
54 #define V3D_TSY_INC_WAITERS 1
55 #define V3D_TSY_DEC_WAITERS 2
56 #define V3D_TSY_INC_QUORUM 3
57 #define V3D_TSY_DEC_QUORUM 4
58 #define V3D_TSY_FREE_ALL 5
59 #define V3D_TSY_RELEASE 6
60 #define V3D_TSY_ACQUIRE 7
61 #define V3D_TSY_WAIT 8
62 #define V3D_TSY_WAIT_INC 9
63 #define V3D_TSY_WAIT_CHECK 10
64 #define V3D_TSY_WAIT_INC_CHECK 11
65 #define V3D_TSY_WAIT_CV 12
66 #define V3D_TSY_INC_SEMAPHORE 13
67 #define V3D_TSY_DEC_SEMAPHORE 14
68 #define V3D_TSY_SET_QUORUM_FREE_ALL 15
69
70 static void
71 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
72
73 static void
74 resize_qreg_array(struct v3d_compile *c,
75 struct qreg **regs,
76 uint32_t *size,
77 uint32_t decl_size)
78 {
79 if (*size >= decl_size)
80 return;
81
82 uint32_t old_size = *size;
83 *size = MAX2(*size * 2, decl_size);
84 *regs = reralloc(c, *regs, struct qreg, *size);
85 if (!*regs) {
86 fprintf(stderr, "Malloc failure\n");
87 abort();
88 }
89
90 for (uint32_t i = old_size; i < *size; i++)
91 (*regs)[i] = c->undef;
92 }
93
94 void
95 vir_emit_thrsw(struct v3d_compile *c)
96 {
97 if (c->threads == 1)
98 return;
99
100 /* Always thread switch after each texture operation for now.
101 *
102 * We could do better by batching a bunch of texture fetches up and
103 * then doing one thread switch and collecting all their results
104 * afterward.
105 */
106 c->last_thrsw = vir_NOP(c);
107 c->last_thrsw->qpu.sig.thrsw = true;
108 c->last_thrsw_at_top_level = !c->in_control_flow;
109
110 /* We need to lock the scoreboard before any tlb acess happens. If this
111 * thread switch comes after we have emitted a tlb load, then it means
112 * that we can't lock on the last thread switch any more.
113 */
114 if (c->emitted_tlb_load)
115 c->lock_scoreboard_on_first_thrsw = true;
116 }
117
118 uint32_t
119 v3d_get_op_for_atomic_add(nir_intrinsic_instr *instr, unsigned src)
120 {
121 if (nir_src_is_const(instr->src[src])) {
122 int64_t add_val = nir_src_as_int(instr->src[src]);
123 if (add_val == 1)
124 return V3D_TMU_OP_WRITE_AND_READ_INC;
125 else if (add_val == -1)
126 return V3D_TMU_OP_WRITE_OR_READ_DEC;
127 }
128
129 return V3D_TMU_OP_WRITE_ADD_READ_PREFETCH;
130 }
131
132 static uint32_t
133 v3d_general_tmu_op(nir_intrinsic_instr *instr)
134 {
135 switch (instr->intrinsic) {
136 case nir_intrinsic_load_ssbo:
137 case nir_intrinsic_load_ubo:
138 case nir_intrinsic_load_uniform:
139 case nir_intrinsic_load_shared:
140 case nir_intrinsic_load_scratch:
141 case nir_intrinsic_store_ssbo:
142 case nir_intrinsic_store_shared:
143 case nir_intrinsic_store_scratch:
144 return V3D_TMU_OP_REGULAR;
145 case nir_intrinsic_ssbo_atomic_add:
146 return v3d_get_op_for_atomic_add(instr, 2);
147 case nir_intrinsic_shared_atomic_add:
148 return v3d_get_op_for_atomic_add(instr, 1);
149 case nir_intrinsic_ssbo_atomic_imin:
150 case nir_intrinsic_shared_atomic_imin:
151 return V3D_TMU_OP_WRITE_SMIN;
152 case nir_intrinsic_ssbo_atomic_umin:
153 case nir_intrinsic_shared_atomic_umin:
154 return V3D_TMU_OP_WRITE_UMIN_FULL_L1_CLEAR;
155 case nir_intrinsic_ssbo_atomic_imax:
156 case nir_intrinsic_shared_atomic_imax:
157 return V3D_TMU_OP_WRITE_SMAX;
158 case nir_intrinsic_ssbo_atomic_umax:
159 case nir_intrinsic_shared_atomic_umax:
160 return V3D_TMU_OP_WRITE_UMAX;
161 case nir_intrinsic_ssbo_atomic_and:
162 case nir_intrinsic_shared_atomic_and:
163 return V3D_TMU_OP_WRITE_AND_READ_INC;
164 case nir_intrinsic_ssbo_atomic_or:
165 case nir_intrinsic_shared_atomic_or:
166 return V3D_TMU_OP_WRITE_OR_READ_DEC;
167 case nir_intrinsic_ssbo_atomic_xor:
168 case nir_intrinsic_shared_atomic_xor:
169 return V3D_TMU_OP_WRITE_XOR_READ_NOT;
170 case nir_intrinsic_ssbo_atomic_exchange:
171 case nir_intrinsic_shared_atomic_exchange:
172 return V3D_TMU_OP_WRITE_XCHG_READ_FLUSH;
173 case nir_intrinsic_ssbo_atomic_comp_swap:
174 case nir_intrinsic_shared_atomic_comp_swap:
175 return V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH;
176 default:
177 unreachable("unknown intrinsic op");
178 }
179 }
180
181 /**
182 * Implements indirect uniform loads and SSBO accesses through the TMU general
183 * memory access interface.
184 */
185 static void
186 ntq_emit_tmu_general(struct v3d_compile *c, nir_intrinsic_instr *instr,
187 bool is_shared_or_scratch)
188 {
189 uint32_t tmu_op = v3d_general_tmu_op(instr);
190
191 /* If we were able to replace atomic_add for an inc/dec, then we
192 * need/can to do things slightly different, like not loading the
193 * amount to add/sub, as that is implicit.
194 */
195 bool atomic_add_replaced = ((instr->intrinsic == nir_intrinsic_ssbo_atomic_add ||
196 instr->intrinsic == nir_intrinsic_shared_atomic_add) &&
197 (tmu_op == V3D_TMU_OP_WRITE_AND_READ_INC ||
198 tmu_op == V3D_TMU_OP_WRITE_OR_READ_DEC));
199 bool is_store = (instr->intrinsic == nir_intrinsic_store_ssbo ||
200 instr->intrinsic == nir_intrinsic_store_scratch ||
201 instr->intrinsic == nir_intrinsic_store_shared);
202 bool has_index = !is_shared_or_scratch;
203
204 int offset_src;
205 int tmu_writes = 1; /* address */
206 if (instr->intrinsic == nir_intrinsic_load_uniform) {
207 offset_src = 0;
208 } else if (instr->intrinsic == nir_intrinsic_load_ssbo ||
209 instr->intrinsic == nir_intrinsic_load_ubo ||
210 instr->intrinsic == nir_intrinsic_load_scratch ||
211 instr->intrinsic == nir_intrinsic_load_shared ||
212 atomic_add_replaced) {
213 offset_src = 0 + has_index;
214 } else if (is_store) {
215 offset_src = 1 + has_index;
216 for (int i = 0; i < instr->num_components; i++) {
217 vir_MOV_dest(c,
218 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
219 ntq_get_src(c, instr->src[0], i));
220 tmu_writes++;
221 }
222 } else {
223 offset_src = 0 + has_index;
224 vir_MOV_dest(c,
225 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
226 ntq_get_src(c, instr->src[1 + has_index], 0));
227 tmu_writes++;
228 if (tmu_op == V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH) {
229 vir_MOV_dest(c,
230 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
231 ntq_get_src(c, instr->src[2 + has_index],
232 0));
233 tmu_writes++;
234 }
235 }
236
237 bool dynamic_src = !nir_src_is_const(instr->src[offset_src]);
238 uint32_t const_offset = 0;
239 if (!dynamic_src)
240 const_offset = nir_src_as_uint(instr->src[offset_src]);
241
242 /* Make sure we won't exceed the 16-entry TMU fifo if each thread is
243 * storing at the same time.
244 */
245 while (tmu_writes > 16 / c->threads)
246 c->threads /= 2;
247
248 struct qreg offset;
249 if (instr->intrinsic == nir_intrinsic_load_uniform) {
250 const_offset += nir_intrinsic_base(instr);
251 offset = vir_uniform(c, QUNIFORM_UBO_ADDR,
252 v3d_unit_data_create(0, const_offset));
253 const_offset = 0;
254 } else if (instr->intrinsic == nir_intrinsic_load_ubo) {
255 uint32_t index = nir_src_as_uint(instr->src[0]) + 1;
256 /* Note that QUNIFORM_UBO_ADDR takes a UBO index shifted up by
257 * 1 (0 is gallium's constant buffer 0).
258 */
259 offset = vir_uniform(c, QUNIFORM_UBO_ADDR,
260 v3d_unit_data_create(index, const_offset));
261 const_offset = 0;
262 } else if (is_shared_or_scratch) {
263 /* Shared and scratch variables have no buffer index, and all
264 * start from a common base that we set up at the start of
265 * dispatch.
266 */
267 if (instr->intrinsic == nir_intrinsic_load_scratch ||
268 instr->intrinsic == nir_intrinsic_store_scratch) {
269 offset = c->spill_base;
270 } else {
271 offset = c->cs_shared_offset;
272 const_offset += nir_intrinsic_base(instr);
273 }
274 } else {
275 offset = vir_uniform(c, QUNIFORM_SSBO_OFFSET,
276 nir_src_as_uint(instr->src[is_store ?
277 1 : 0]));
278 }
279
280 /* The spec says that for atomics, the TYPE field is ignored, but that
281 * doesn't seem to be the case for CMPXCHG. Just use the number of
282 * tmud writes we did to decide the type (or choose "32bit" for atomic
283 * reads, which has been fine).
284 */
285 int num_components;
286 if (tmu_op == V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH)
287 num_components = 2;
288 else
289 num_components = instr->num_components;
290
291 uint32_t config = (0xffffff00 |
292 tmu_op << 3|
293 GENERAL_TMU_LOOKUP_PER_PIXEL);
294 if (num_components == 1) {
295 config |= GENERAL_TMU_LOOKUP_TYPE_32BIT_UI;
296 } else {
297 config |= GENERAL_TMU_LOOKUP_TYPE_VEC2 + num_components - 2;
298 }
299
300 if (vir_in_nonuniform_control_flow(c)) {
301 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
302 V3D_QPU_PF_PUSHZ);
303 }
304
305 struct qreg tmua;
306 if (config == ~0)
307 tmua = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA);
308 else
309 tmua = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUAU);
310
311 struct qinst *tmu;
312 if (dynamic_src) {
313 if (const_offset != 0) {
314 offset = vir_ADD(c, offset,
315 vir_uniform_ui(c, const_offset));
316 }
317 tmu = vir_ADD_dest(c, tmua, offset,
318 ntq_get_src(c, instr->src[offset_src], 0));
319 } else {
320 if (const_offset != 0) {
321 tmu = vir_ADD_dest(c, tmua, offset,
322 vir_uniform_ui(c, const_offset));
323 } else {
324 tmu = vir_MOV_dest(c, tmua, offset);
325 }
326 }
327
328 if (config != ~0) {
329 tmu->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT,
330 config);
331 }
332
333 if (vir_in_nonuniform_control_flow(c))
334 vir_set_cond(tmu, V3D_QPU_COND_IFA);
335
336 vir_emit_thrsw(c);
337
338 /* Read the result, or wait for the TMU op to complete. */
339 for (int i = 0; i < nir_intrinsic_dest_components(instr); i++)
340 ntq_store_dest(c, &instr->dest, i, vir_MOV(c, vir_LDTMU(c)));
341
342 if (nir_intrinsic_dest_components(instr) == 0)
343 vir_TMUWT(c);
344 }
345
346 static struct qreg *
347 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
348 {
349 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
350 def->num_components);
351 _mesa_hash_table_insert(c->def_ht, def, qregs);
352 return qregs;
353 }
354
355 /**
356 * This function is responsible for getting VIR results into the associated
357 * storage for a NIR instruction.
358 *
359 * If it's a NIR SSA def, then we just set the associated hash table entry to
360 * the new result.
361 *
362 * If it's a NIR reg, then we need to update the existing qreg assigned to the
363 * NIR destination with the incoming value. To do that without introducing
364 * new MOVs, we require that the incoming qreg either be a uniform, or be
365 * SSA-defined by the previous VIR instruction in the block and rewritable by
366 * this function. That lets us sneak ahead and insert the SF flag beforehand
367 * (knowing that the previous instruction doesn't depend on flags) and rewrite
368 * its destination to be the NIR reg's destination
369 */
370 void
371 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
372 struct qreg result)
373 {
374 struct qinst *last_inst = NULL;
375 if (!list_empty(&c->cur_block->instructions))
376 last_inst = (struct qinst *)c->cur_block->instructions.prev;
377
378 assert((result.file == QFILE_TEMP &&
379 last_inst && last_inst == c->defs[result.index]));
380
381 if (dest->is_ssa) {
382 assert(chan < dest->ssa.num_components);
383
384 struct qreg *qregs;
385 struct hash_entry *entry =
386 _mesa_hash_table_search(c->def_ht, &dest->ssa);
387
388 if (entry)
389 qregs = entry->data;
390 else
391 qregs = ntq_init_ssa_def(c, &dest->ssa);
392
393 qregs[chan] = result;
394 } else {
395 nir_register *reg = dest->reg.reg;
396 assert(dest->reg.base_offset == 0);
397 assert(reg->num_array_elems == 0);
398 struct hash_entry *entry =
399 _mesa_hash_table_search(c->def_ht, reg);
400 struct qreg *qregs = entry->data;
401
402 /* Insert a MOV if the source wasn't an SSA def in the
403 * previous instruction.
404 */
405 if ((vir_in_nonuniform_control_flow(c) &&
406 c->defs[last_inst->dst.index]->qpu.sig.ldunif)) {
407 result = vir_MOV(c, result);
408 last_inst = c->defs[result.index];
409 }
410
411 /* We know they're both temps, so just rewrite index. */
412 c->defs[last_inst->dst.index] = NULL;
413 last_inst->dst.index = qregs[chan].index;
414
415 /* If we're in control flow, then make this update of the reg
416 * conditional on the execution mask.
417 */
418 if (vir_in_nonuniform_control_flow(c)) {
419 last_inst->dst.index = qregs[chan].index;
420
421 /* Set the flags to the current exec mask.
422 */
423 c->cursor = vir_before_inst(last_inst);
424 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
425 V3D_QPU_PF_PUSHZ);
426 c->cursor = vir_after_inst(last_inst);
427
428 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
429 }
430 }
431 }
432
433 struct qreg
434 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
435 {
436 struct hash_entry *entry;
437 if (src.is_ssa) {
438 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
439 assert(i < src.ssa->num_components);
440 } else {
441 nir_register *reg = src.reg.reg;
442 entry = _mesa_hash_table_search(c->def_ht, reg);
443 assert(reg->num_array_elems == 0);
444 assert(src.reg.base_offset == 0);
445 assert(i < reg->num_components);
446 }
447
448 struct qreg *qregs = entry->data;
449 return qregs[i];
450 }
451
452 static struct qreg
453 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
454 unsigned src)
455 {
456 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
457 unsigned chan = ffs(instr->dest.write_mask) - 1;
458 struct qreg r = ntq_get_src(c, instr->src[src].src,
459 instr->src[src].swizzle[chan]);
460
461 assert(!instr->src[src].abs);
462 assert(!instr->src[src].negate);
463
464 return r;
465 };
466
467 static struct qreg
468 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
469 {
470 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
471 }
472
473 static void
474 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
475 {
476 unsigned unit = instr->texture_index;
477 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
478 int dest_size = nir_tex_instr_dest_size(instr);
479
480 struct qreg lod = c->undef;
481 if (lod_index != -1)
482 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
483
484 for (int i = 0; i < dest_size; i++) {
485 assert(i < 3);
486 enum quniform_contents contents;
487
488 if (instr->is_array && i == dest_size - 1)
489 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
490 else
491 contents = QUNIFORM_TEXTURE_WIDTH + i;
492
493 struct qreg size = vir_uniform(c, contents, unit);
494
495 switch (instr->sampler_dim) {
496 case GLSL_SAMPLER_DIM_1D:
497 case GLSL_SAMPLER_DIM_2D:
498 case GLSL_SAMPLER_DIM_MS:
499 case GLSL_SAMPLER_DIM_3D:
500 case GLSL_SAMPLER_DIM_CUBE:
501 /* Don't minify the array size. */
502 if (!(instr->is_array && i == dest_size - 1)) {
503 size = ntq_minify(c, size, lod);
504 }
505 break;
506
507 case GLSL_SAMPLER_DIM_RECT:
508 /* There's no LOD field for rects */
509 break;
510
511 default:
512 unreachable("Bad sampler type");
513 }
514
515 ntq_store_dest(c, &instr->dest, i, size);
516 }
517 }
518
519 static void
520 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
521 {
522 unsigned unit = instr->texture_index;
523
524 /* Since each texture sampling op requires uploading uniforms to
525 * reference the texture, there's no HW support for texture size and
526 * you just upload uniforms containing the size.
527 */
528 switch (instr->op) {
529 case nir_texop_query_levels:
530 ntq_store_dest(c, &instr->dest, 0,
531 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
532 return;
533 case nir_texop_txs:
534 ntq_emit_txs(c, instr);
535 return;
536 default:
537 break;
538 }
539
540 if (c->devinfo->ver >= 40)
541 v3d40_vir_emit_tex(c, instr);
542 else
543 v3d33_vir_emit_tex(c, instr);
544 }
545
546 static struct qreg
547 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
548 {
549 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
550 if (is_cos)
551 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
552
553 struct qreg periods = vir_FROUND(c, input);
554 struct qreg sin_output = vir_SIN(c, vir_FSUB(c, input, periods));
555 return vir_XOR(c, sin_output, vir_SHL(c,
556 vir_FTOIN(c, periods),
557 vir_uniform_ui(c, -1)));
558 }
559
560 static struct qreg
561 ntq_fsign(struct v3d_compile *c, struct qreg src)
562 {
563 struct qreg t = vir_get_temp(c);
564
565 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
566 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHZ);
567 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
568 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHN);
569 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
570 return vir_MOV(c, t);
571 }
572
573 static void
574 emit_fragcoord_input(struct v3d_compile *c, int attr)
575 {
576 c->inputs[attr * 4 + 0] = vir_FXCD(c);
577 c->inputs[attr * 4 + 1] = vir_FYCD(c);
578 c->inputs[attr * 4 + 2] = c->payload_z;
579 c->inputs[attr * 4 + 3] = vir_RECIP(c, c->payload_w);
580 }
581
582 static struct qreg
583 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
584 uint8_t swizzle, int array_index)
585 {
586 struct qreg r3 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R3);
587 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
588
589 struct qreg vary;
590 if (c->devinfo->ver >= 41) {
591 struct qinst *ldvary = vir_add_inst(V3D_QPU_A_NOP, c->undef,
592 c->undef, c->undef);
593 ldvary->qpu.sig.ldvary = true;
594 vary = vir_emit_def(c, ldvary);
595 } else {
596 vir_NOP(c)->qpu.sig.ldvary = true;
597 vary = r3;
598 }
599
600 /* For gl_PointCoord input or distance along a line, we'll be called
601 * with no nir_variable, and we don't count toward VPM size so we
602 * don't track an input slot.
603 */
604 if (!var) {
605 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
606 }
607
608 int i = c->num_inputs++;
609 c->input_slots[i] =
610 v3d_slot_from_slot_and_component(var->data.location +
611 array_index, swizzle);
612
613 switch (var->data.interpolation) {
614 case INTERP_MODE_NONE:
615 /* If a gl_FrontColor or gl_BackColor input has no interp
616 * qualifier, then if we're using glShadeModel(GL_FLAT) it
617 * needs to be flat shaded.
618 */
619 switch (var->data.location + array_index) {
620 case VARYING_SLOT_COL0:
621 case VARYING_SLOT_COL1:
622 case VARYING_SLOT_BFC0:
623 case VARYING_SLOT_BFC1:
624 if (c->fs_key->shade_model_flat) {
625 BITSET_SET(c->flat_shade_flags, i);
626 vir_MOV_dest(c, c->undef, vary);
627 return vir_MOV(c, r5);
628 } else {
629 return vir_FADD(c, vir_FMUL(c, vary,
630 c->payload_w), r5);
631 }
632 default:
633 break;
634 }
635 /* FALLTHROUGH */
636 case INTERP_MODE_SMOOTH:
637 if (var->data.centroid) {
638 BITSET_SET(c->centroid_flags, i);
639 return vir_FADD(c, vir_FMUL(c, vary,
640 c->payload_w_centroid), r5);
641 } else {
642 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
643 }
644 case INTERP_MODE_NOPERSPECTIVE:
645 BITSET_SET(c->noperspective_flags, i);
646 return vir_FADD(c, vir_MOV(c, vary), r5);
647 case INTERP_MODE_FLAT:
648 BITSET_SET(c->flat_shade_flags, i);
649 vir_MOV_dest(c, c->undef, vary);
650 return vir_MOV(c, r5);
651 default:
652 unreachable("Bad interp mode");
653 }
654 }
655
656 static void
657 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var,
658 int array_index)
659 {
660 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
661 int chan = var->data.location_frac + i;
662 c->inputs[attr * 4 + chan] =
663 emit_fragment_varying(c, var, chan, array_index);
664 }
665 }
666
667 static void
668 add_output(struct v3d_compile *c,
669 uint32_t decl_offset,
670 uint8_t slot,
671 uint8_t swizzle)
672 {
673 uint32_t old_array_size = c->outputs_array_size;
674 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
675 decl_offset + 1);
676
677 if (old_array_size != c->outputs_array_size) {
678 c->output_slots = reralloc(c,
679 c->output_slots,
680 struct v3d_varying_slot,
681 c->outputs_array_size);
682 }
683
684 c->output_slots[decl_offset] =
685 v3d_slot_from_slot_and_component(slot, swizzle);
686 }
687
688 /**
689 * If compare_instr is a valid comparison instruction, emits the
690 * compare_instr's comparison and returns the sel_instr's return value based
691 * on the compare_instr's result.
692 */
693 static bool
694 ntq_emit_comparison(struct v3d_compile *c,
695 nir_alu_instr *compare_instr,
696 enum v3d_qpu_cond *out_cond)
697 {
698 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
699 struct qreg src1;
700 if (nir_op_infos[compare_instr->op].num_inputs > 1)
701 src1 = ntq_get_alu_src(c, compare_instr, 1);
702 bool cond_invert = false;
703 struct qreg nop = vir_nop_reg();
704
705 switch (compare_instr->op) {
706 case nir_op_feq32:
707 case nir_op_seq:
708 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
709 break;
710 case nir_op_ieq32:
711 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
712 break;
713
714 case nir_op_fne32:
715 case nir_op_sne:
716 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
717 cond_invert = true;
718 break;
719 case nir_op_ine32:
720 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
721 cond_invert = true;
722 break;
723
724 case nir_op_fge32:
725 case nir_op_sge:
726 vir_set_pf(vir_FCMP_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
727 break;
728 case nir_op_ige32:
729 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
730 cond_invert = true;
731 break;
732 case nir_op_uge32:
733 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
734 cond_invert = true;
735 break;
736
737 case nir_op_slt:
738 case nir_op_flt32:
739 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHN);
740 break;
741 case nir_op_ilt32:
742 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
743 break;
744 case nir_op_ult32:
745 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
746 break;
747
748 case nir_op_i2b32:
749 vir_set_pf(vir_MOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ);
750 cond_invert = true;
751 break;
752
753 case nir_op_f2b32:
754 vir_set_pf(vir_FMOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ);
755 cond_invert = true;
756 break;
757
758 default:
759 return false;
760 }
761
762 *out_cond = cond_invert ? V3D_QPU_COND_IFNA : V3D_QPU_COND_IFA;
763
764 return true;
765 }
766
767 /* Finds an ALU instruction that generates our src value that could
768 * (potentially) be greedily emitted in the consuming instruction.
769 */
770 static struct nir_alu_instr *
771 ntq_get_alu_parent(nir_src src)
772 {
773 if (!src.is_ssa || src.ssa->parent_instr->type != nir_instr_type_alu)
774 return NULL;
775 nir_alu_instr *instr = nir_instr_as_alu(src.ssa->parent_instr);
776 if (!instr)
777 return NULL;
778
779 /* If the ALU instr's srcs are non-SSA, then we would have to avoid
780 * moving emission of the ALU instr down past another write of the
781 * src.
782 */
783 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
784 if (!instr->src[i].src.is_ssa)
785 return NULL;
786 }
787
788 return instr;
789 }
790
791 /* Turns a NIR bool into a condition code to predicate on. */
792 static enum v3d_qpu_cond
793 ntq_emit_bool_to_cond(struct v3d_compile *c, nir_src src)
794 {
795 nir_alu_instr *compare = ntq_get_alu_parent(src);
796 if (!compare)
797 goto out;
798
799 enum v3d_qpu_cond cond;
800 if (ntq_emit_comparison(c, compare, &cond))
801 return cond;
802
803 out:
804 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), ntq_get_src(c, src, 0)),
805 V3D_QPU_PF_PUSHZ);
806 return V3D_QPU_COND_IFNA;
807 }
808
809 static void
810 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
811 {
812 /* This should always be lowered to ALU operations for V3D. */
813 assert(!instr->dest.saturate);
814
815 /* Vectors are special in that they have non-scalarized writemasks,
816 * and just take the first swizzle channel for each argument in order
817 * into each writemask channel.
818 */
819 if (instr->op == nir_op_vec2 ||
820 instr->op == nir_op_vec3 ||
821 instr->op == nir_op_vec4) {
822 struct qreg srcs[4];
823 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
824 srcs[i] = ntq_get_src(c, instr->src[i].src,
825 instr->src[i].swizzle[0]);
826 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
827 ntq_store_dest(c, &instr->dest.dest, i,
828 vir_MOV(c, srcs[i]));
829 return;
830 }
831
832 /* General case: We can just grab the one used channel per src. */
833 struct qreg src[nir_op_infos[instr->op].num_inputs];
834 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
835 src[i] = ntq_get_alu_src(c, instr, i);
836 }
837
838 struct qreg result;
839
840 switch (instr->op) {
841 case nir_op_mov:
842 result = vir_MOV(c, src[0]);
843 break;
844
845 case nir_op_fneg:
846 result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
847 break;
848 case nir_op_ineg:
849 result = vir_NEG(c, src[0]);
850 break;
851
852 case nir_op_fmul:
853 result = vir_FMUL(c, src[0], src[1]);
854 break;
855 case nir_op_fadd:
856 result = vir_FADD(c, src[0], src[1]);
857 break;
858 case nir_op_fsub:
859 result = vir_FSUB(c, src[0], src[1]);
860 break;
861 case nir_op_fmin:
862 result = vir_FMIN(c, src[0], src[1]);
863 break;
864 case nir_op_fmax:
865 result = vir_FMAX(c, src[0], src[1]);
866 break;
867
868 case nir_op_f2i32: {
869 nir_alu_instr *src0_alu = ntq_get_alu_parent(instr->src[0].src);
870 if (src0_alu && src0_alu->op == nir_op_fround_even) {
871 result = vir_FTOIN(c, ntq_get_alu_src(c, src0_alu, 0));
872 } else {
873 result = vir_FTOIZ(c, src[0]);
874 }
875 break;
876 }
877
878 case nir_op_f2u32:
879 result = vir_FTOUZ(c, src[0]);
880 break;
881 case nir_op_i2f32:
882 result = vir_ITOF(c, src[0]);
883 break;
884 case nir_op_u2f32:
885 result = vir_UTOF(c, src[0]);
886 break;
887 case nir_op_b2f32:
888 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
889 break;
890 case nir_op_b2i32:
891 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
892 break;
893
894 case nir_op_iadd:
895 result = vir_ADD(c, src[0], src[1]);
896 break;
897 case nir_op_ushr:
898 result = vir_SHR(c, src[0], src[1]);
899 break;
900 case nir_op_isub:
901 result = vir_SUB(c, src[0], src[1]);
902 break;
903 case nir_op_ishr:
904 result = vir_ASR(c, src[0], src[1]);
905 break;
906 case nir_op_ishl:
907 result = vir_SHL(c, src[0], src[1]);
908 break;
909 case nir_op_imin:
910 result = vir_MIN(c, src[0], src[1]);
911 break;
912 case nir_op_umin:
913 result = vir_UMIN(c, src[0], src[1]);
914 break;
915 case nir_op_imax:
916 result = vir_MAX(c, src[0], src[1]);
917 break;
918 case nir_op_umax:
919 result = vir_UMAX(c, src[0], src[1]);
920 break;
921 case nir_op_iand:
922 result = vir_AND(c, src[0], src[1]);
923 break;
924 case nir_op_ior:
925 result = vir_OR(c, src[0], src[1]);
926 break;
927 case nir_op_ixor:
928 result = vir_XOR(c, src[0], src[1]);
929 break;
930 case nir_op_inot:
931 result = vir_NOT(c, src[0]);
932 break;
933
934 case nir_op_ufind_msb:
935 result = vir_SUB(c, vir_uniform_ui(c, 31), vir_CLZ(c, src[0]));
936 break;
937
938 case nir_op_imul:
939 result = vir_UMUL(c, src[0], src[1]);
940 break;
941
942 case nir_op_seq:
943 case nir_op_sne:
944 case nir_op_sge:
945 case nir_op_slt: {
946 enum v3d_qpu_cond cond;
947 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
948 assert(ok);
949 result = vir_MOV(c, vir_SEL(c, cond,
950 vir_uniform_f(c, 1.0),
951 vir_uniform_f(c, 0.0)));
952 break;
953 }
954
955 case nir_op_i2b32:
956 case nir_op_f2b32:
957 case nir_op_feq32:
958 case nir_op_fne32:
959 case nir_op_fge32:
960 case nir_op_flt32:
961 case nir_op_ieq32:
962 case nir_op_ine32:
963 case nir_op_ige32:
964 case nir_op_uge32:
965 case nir_op_ilt32:
966 case nir_op_ult32: {
967 enum v3d_qpu_cond cond;
968 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
969 assert(ok);
970 result = vir_MOV(c, vir_SEL(c, cond,
971 vir_uniform_ui(c, ~0),
972 vir_uniform_ui(c, 0)));
973 break;
974 }
975
976 case nir_op_b32csel:
977 result = vir_MOV(c,
978 vir_SEL(c,
979 ntq_emit_bool_to_cond(c, instr->src[0].src),
980 src[1], src[2]));
981 break;
982
983 case nir_op_fcsel:
984 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), src[0]),
985 V3D_QPU_PF_PUSHZ);
986 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
987 src[1], src[2]));
988 break;
989
990 case nir_op_frcp:
991 result = vir_RECIP(c, src[0]);
992 break;
993 case nir_op_frsq:
994 result = vir_RSQRT(c, src[0]);
995 break;
996 case nir_op_fexp2:
997 result = vir_EXP(c, src[0]);
998 break;
999 case nir_op_flog2:
1000 result = vir_LOG(c, src[0]);
1001 break;
1002
1003 case nir_op_fceil:
1004 result = vir_FCEIL(c, src[0]);
1005 break;
1006 case nir_op_ffloor:
1007 result = vir_FFLOOR(c, src[0]);
1008 break;
1009 case nir_op_fround_even:
1010 result = vir_FROUND(c, src[0]);
1011 break;
1012 case nir_op_ftrunc:
1013 result = vir_FTRUNC(c, src[0]);
1014 break;
1015
1016 case nir_op_fsin:
1017 result = ntq_fsincos(c, src[0], false);
1018 break;
1019 case nir_op_fcos:
1020 result = ntq_fsincos(c, src[0], true);
1021 break;
1022
1023 case nir_op_fsign:
1024 result = ntq_fsign(c, src[0]);
1025 break;
1026
1027 case nir_op_fabs: {
1028 result = vir_FMOV(c, src[0]);
1029 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
1030 break;
1031 }
1032
1033 case nir_op_iabs:
1034 result = vir_MAX(c, src[0], vir_NEG(c, src[0]));
1035 break;
1036
1037 case nir_op_fddx:
1038 case nir_op_fddx_coarse:
1039 case nir_op_fddx_fine:
1040 result = vir_FDX(c, src[0]);
1041 break;
1042
1043 case nir_op_fddy:
1044 case nir_op_fddy_coarse:
1045 case nir_op_fddy_fine:
1046 result = vir_FDY(c, src[0]);
1047 break;
1048
1049 case nir_op_uadd_carry:
1050 vir_set_pf(vir_ADD_dest(c, vir_nop_reg(), src[0], src[1]),
1051 V3D_QPU_PF_PUSHC);
1052 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1053 vir_uniform_ui(c, ~0),
1054 vir_uniform_ui(c, 0)));
1055 break;
1056
1057 case nir_op_pack_half_2x16_split:
1058 result = vir_VFPACK(c, src[0], src[1]);
1059 break;
1060
1061 case nir_op_unpack_half_2x16_split_x:
1062 result = vir_FMOV(c, src[0]);
1063 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_L);
1064 break;
1065
1066 case nir_op_unpack_half_2x16_split_y:
1067 result = vir_FMOV(c, src[0]);
1068 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_H);
1069 break;
1070
1071 default:
1072 fprintf(stderr, "unknown NIR ALU inst: ");
1073 nir_print_instr(&instr->instr, stderr);
1074 fprintf(stderr, "\n");
1075 abort();
1076 }
1077
1078 /* We have a scalar result, so the instruction should only have a
1079 * single channel written to.
1080 */
1081 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
1082 ntq_store_dest(c, &instr->dest.dest,
1083 ffs(instr->dest.write_mask) - 1, result);
1084 }
1085
1086 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
1087 * specifier. They come from a register that's preloaded with 0xffffffff
1088 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
1089 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
1090 */
1091 #define TLB_TYPE_F16_COLOR (3 << 6)
1092 #define TLB_TYPE_I32_COLOR (1 << 6)
1093 #define TLB_TYPE_F32_COLOR (0 << 6)
1094 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
1095 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
1096 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
1097 #define TLB_F16_SWAP_HI_LO (1 << 1)
1098 #define TLB_VEC_SIZE_4_F16 (1 << 0)
1099 #define TLB_VEC_SIZE_2_F16 (0 << 0)
1100 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
1101
1102 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
1103 * flag is set.
1104 */
1105 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
1106 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
1107 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
1108 #define TLB_V42_DEPTH_TYPE_INVARIANT (0 << 3) /* Unmodified sideband input used */
1109 #define TLB_V42_DEPTH_TYPE_PER_PIXEL (1 << 3) /* QPU result used */
1110
1111 /* Stencil is a single 32-bit write. */
1112 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1113
1114 static void
1115 vir_emit_tlb_color_write(struct v3d_compile *c, unsigned rt)
1116 {
1117 if (!(c->fs_key->cbufs & (1 << rt)) || !c->output_color_var[rt])
1118 return;
1119
1120 struct qreg tlb_reg = vir_magic_reg(V3D_QPU_WADDR_TLB);
1121 struct qreg tlbu_reg = vir_magic_reg(V3D_QPU_WADDR_TLBU);
1122
1123 nir_variable *var = c->output_color_var[rt];
1124 int num_components = glsl_get_vector_elements(var->type);
1125 uint32_t conf = 0xffffff00;
1126 struct qinst *inst;
1127
1128 conf |= c->msaa_per_sample_output ? TLB_SAMPLE_MODE_PER_SAMPLE :
1129 TLB_SAMPLE_MODE_PER_PIXEL;
1130 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1131
1132 if (c->fs_key->swap_color_rb & (1 << rt))
1133 num_components = MAX2(num_components, 3);
1134 assert(num_components != 0);
1135
1136 enum glsl_base_type type = glsl_get_base_type(var->type);
1137 bool is_int_format = type == GLSL_TYPE_INT || type == GLSL_TYPE_UINT;
1138 bool is_32b_tlb_format = is_int_format ||
1139 (c->fs_key->f32_color_rb & (1 << rt));
1140
1141 if (is_int_format) {
1142 /* The F32 vs I32 distinction was dropped in 4.2. */
1143 if (c->devinfo->ver < 42)
1144 conf |= TLB_TYPE_I32_COLOR;
1145 else
1146 conf |= TLB_TYPE_F32_COLOR;
1147 conf |= ((num_components - 1) << TLB_VEC_SIZE_MINUS_1_SHIFT);
1148 } else {
1149 if (c->fs_key->f32_color_rb & (1 << rt)) {
1150 conf |= TLB_TYPE_F32_COLOR;
1151 conf |= ((num_components - 1) <<
1152 TLB_VEC_SIZE_MINUS_1_SHIFT);
1153 } else {
1154 conf |= TLB_TYPE_F16_COLOR;
1155 conf |= TLB_F16_SWAP_HI_LO;
1156 if (num_components >= 3)
1157 conf |= TLB_VEC_SIZE_4_F16;
1158 else
1159 conf |= TLB_VEC_SIZE_2_F16;
1160 }
1161 }
1162
1163 int num_samples = c->msaa_per_sample_output ? V3D_MAX_SAMPLES : 1;
1164 for (int i = 0; i < num_samples; i++) {
1165 struct qreg *color = c->msaa_per_sample_output ?
1166 &c->sample_colors[(rt * V3D_MAX_SAMPLES + i) * 4] :
1167 &c->outputs[var->data.driver_location * 4];
1168
1169 struct qreg r = color[0];
1170 struct qreg g = color[1];
1171 struct qreg b = color[2];
1172 struct qreg a = color[3];
1173
1174 if (c->fs_key->swap_color_rb & (1 << rt)) {
1175 r = color[2];
1176 b = color[0];
1177 }
1178
1179 if (c->fs_key->sample_alpha_to_one)
1180 a = vir_uniform_f(c, 1.0);
1181
1182 if (is_32b_tlb_format) {
1183 if (i == 0) {
1184 inst = vir_MOV_dest(c, tlbu_reg, r);
1185 inst->uniform =
1186 vir_get_uniform_index(c,
1187 QUNIFORM_CONSTANT,
1188 conf);
1189 } else {
1190 inst = vir_MOV_dest(c, tlb_reg, r);
1191 }
1192
1193 if (num_components >= 2)
1194 vir_MOV_dest(c, tlb_reg, g);
1195 if (num_components >= 3)
1196 vir_MOV_dest(c, tlb_reg, b);
1197 if (num_components >= 4)
1198 vir_MOV_dest(c, tlb_reg, a);
1199 } else {
1200 inst = vir_VFPACK_dest(c, tlb_reg, r, g);
1201 if (conf != ~0 && i == 0) {
1202 inst->dst = tlbu_reg;
1203 inst->uniform =
1204 vir_get_uniform_index(c,
1205 QUNIFORM_CONSTANT,
1206 conf);
1207 }
1208
1209 if (num_components >= 3)
1210 inst = vir_VFPACK_dest(c, tlb_reg, b, a);
1211 }
1212 }
1213 }
1214
1215 static void
1216 emit_frag_end(struct v3d_compile *c)
1217 {
1218 /* XXX
1219 if (c->output_sample_mask_index != -1) {
1220 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1221 }
1222 */
1223
1224 bool has_any_tlb_color_write = false;
1225 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1226 if (c->fs_key->cbufs & (1 << rt) && c->output_color_var[rt])
1227 has_any_tlb_color_write = true;
1228 }
1229
1230 if (c->fs_key->sample_alpha_to_coverage && c->output_color_var[0]) {
1231 struct nir_variable *var = c->output_color_var[0];
1232 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1233
1234 vir_SETMSF_dest(c, vir_nop_reg(),
1235 vir_AND(c,
1236 vir_MSF(c),
1237 vir_FTOC(c, color[3])));
1238 }
1239
1240 struct qreg tlbu_reg = vir_magic_reg(V3D_QPU_WADDR_TLBU);
1241 if (c->output_position_index != -1) {
1242 struct qinst *inst = vir_MOV_dest(c, tlbu_reg,
1243 c->outputs[c->output_position_index]);
1244 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1245
1246 if (c->devinfo->ver >= 42) {
1247 tlb_specifier |= (TLB_V42_DEPTH_TYPE_PER_PIXEL |
1248 TLB_SAMPLE_MODE_PER_PIXEL);
1249 } else
1250 tlb_specifier |= TLB_DEPTH_TYPE_PER_PIXEL;
1251
1252 inst->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT,
1253 tlb_specifier |
1254 0xffffff00);
1255 c->writes_z = true;
1256 } else if (c->s->info.fs.uses_discard ||
1257 !c->s->info.fs.early_fragment_tests ||
1258 c->fs_key->sample_alpha_to_coverage ||
1259 !has_any_tlb_color_write) {
1260 /* Emit passthrough Z if it needed to be delayed until shader
1261 * end due to potential discards.
1262 *
1263 * Since (single-threaded) fragment shaders always need a TLB
1264 * write, emit passthrouh Z if we didn't have any color
1265 * buffers and flag us as potentially discarding, so that we
1266 * can use Z as the TLB write.
1267 */
1268 c->s->info.fs.uses_discard = true;
1269
1270 struct qinst *inst = vir_MOV_dest(c, tlbu_reg,
1271 vir_nop_reg());
1272 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1273
1274 if (c->devinfo->ver >= 42) {
1275 /* The spec says the PER_PIXEL flag is ignored for
1276 * invariant writes, but the simulator demands it.
1277 */
1278 tlb_specifier |= (TLB_V42_DEPTH_TYPE_INVARIANT |
1279 TLB_SAMPLE_MODE_PER_PIXEL);
1280 } else {
1281 tlb_specifier |= TLB_DEPTH_TYPE_INVARIANT;
1282 }
1283
1284 inst->uniform = vir_get_uniform_index(c,
1285 QUNIFORM_CONSTANT,
1286 tlb_specifier |
1287 0xffffff00);
1288 c->writes_z = true;
1289 }
1290
1291 /* XXX: Performance improvement: Merge Z write and color writes TLB
1292 * uniform setup
1293 */
1294 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++)
1295 vir_emit_tlb_color_write(c, rt);
1296 }
1297
1298 static void
1299 vir_VPM_WRITE(struct v3d_compile *c, struct qreg val, uint32_t vpm_index)
1300 {
1301 if (c->devinfo->ver >= 40) {
1302 vir_STVPMV(c, vir_uniform_ui(c, vpm_index), val);
1303 } else {
1304 /* XXX: v3d33_vir_vpm_write_setup(c); */
1305 vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM), val);
1306 }
1307 }
1308
1309 static void
1310 emit_vert_end(struct v3d_compile *c)
1311 {
1312 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1313 */
1314 if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
1315 vir_VPMWT(c);
1316 }
1317
1318 void
1319 v3d_optimize_nir(struct nir_shader *s)
1320 {
1321 bool progress;
1322 unsigned lower_flrp =
1323 (s->options->lower_flrp16 ? 16 : 0) |
1324 (s->options->lower_flrp32 ? 32 : 0) |
1325 (s->options->lower_flrp64 ? 64 : 0);
1326
1327 do {
1328 progress = false;
1329
1330 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1331 NIR_PASS(progress, s, nir_lower_alu_to_scalar, NULL);
1332 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1333 NIR_PASS(progress, s, nir_copy_prop);
1334 NIR_PASS(progress, s, nir_opt_remove_phis);
1335 NIR_PASS(progress, s, nir_opt_dce);
1336 NIR_PASS(progress, s, nir_opt_dead_cf);
1337 NIR_PASS(progress, s, nir_opt_cse);
1338 NIR_PASS(progress, s, nir_opt_peephole_select, 8, true, true);
1339 NIR_PASS(progress, s, nir_opt_algebraic);
1340 NIR_PASS(progress, s, nir_opt_constant_folding);
1341
1342 if (lower_flrp != 0) {
1343 bool lower_flrp_progress = false;
1344
1345 NIR_PASS(lower_flrp_progress, s, nir_lower_flrp,
1346 lower_flrp,
1347 false /* always_precise */,
1348 s->options->lower_ffma);
1349 if (lower_flrp_progress) {
1350 NIR_PASS(progress, s, nir_opt_constant_folding);
1351 progress = true;
1352 }
1353
1354 /* Nothing should rematerialize any flrps, so we only
1355 * need to do this lowering once.
1356 */
1357 lower_flrp = 0;
1358 }
1359
1360 NIR_PASS(progress, s, nir_opt_undef);
1361 } while (progress);
1362
1363 NIR_PASS(progress, s, nir_opt_move_load_ubo);
1364 }
1365
1366 static int
1367 driver_location_compare(const void *in_a, const void *in_b)
1368 {
1369 const nir_variable *const *a = in_a;
1370 const nir_variable *const *b = in_b;
1371
1372 return (*a)->data.driver_location - (*b)->data.driver_location;
1373 }
1374
1375 static struct qreg
1376 ntq_emit_vpm_read(struct v3d_compile *c,
1377 uint32_t *num_components_queued,
1378 uint32_t *remaining,
1379 uint32_t vpm_index)
1380 {
1381 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1382
1383 if (c->devinfo->ver >= 40 ) {
1384 return vir_LDVPMV_IN(c,
1385 vir_uniform_ui(c,
1386 (*num_components_queued)++));
1387 }
1388
1389 if (*num_components_queued != 0) {
1390 (*num_components_queued)--;
1391 return vir_MOV(c, vpm);
1392 }
1393
1394 uint32_t num_components = MIN2(*remaining, 32);
1395
1396 v3d33_vir_vpm_read_setup(c, num_components);
1397
1398 *num_components_queued = num_components - 1;
1399 *remaining -= num_components;
1400
1401 return vir_MOV(c, vpm);
1402 }
1403
1404 static void
1405 ntq_setup_vpm_inputs(struct v3d_compile *c)
1406 {
1407 /* Figure out how many components of each vertex attribute the shader
1408 * uses. Each variable should have been split to individual
1409 * components and unused ones DCEed. The vertex fetcher will load
1410 * from the start of the attribute to the number of components we
1411 * declare we need in c->vattr_sizes[].
1412 */
1413 nir_foreach_variable(var, &c->s->inputs) {
1414 /* No VS attribute array support. */
1415 assert(MAX2(glsl_get_length(var->type), 1) == 1);
1416
1417 unsigned loc = var->data.driver_location;
1418 int start_component = var->data.location_frac;
1419 int num_components = glsl_get_components(var->type);
1420
1421 c->vattr_sizes[loc] = MAX2(c->vattr_sizes[loc],
1422 start_component + num_components);
1423 }
1424
1425 unsigned num_components = 0;
1426 uint32_t vpm_components_queued = 0;
1427 bool uses_iid = c->s->info.system_values_read &
1428 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1429 bool uses_vid = c->s->info.system_values_read &
1430 (1ull << SYSTEM_VALUE_VERTEX_ID);
1431 num_components += uses_iid;
1432 num_components += uses_vid;
1433
1434 for (int i = 0; i < ARRAY_SIZE(c->vattr_sizes); i++)
1435 num_components += c->vattr_sizes[i];
1436
1437 if (uses_iid) {
1438 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1439 &num_components, ~0);
1440 }
1441
1442 if (uses_vid) {
1443 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1444 &num_components, ~0);
1445 }
1446
1447 /* The actual loads will happen directly in nir_intrinsic_load_input
1448 * on newer versions.
1449 */
1450 if (c->devinfo->ver >= 40)
1451 return;
1452
1453 for (int loc = 0; loc < ARRAY_SIZE(c->vattr_sizes); loc++) {
1454 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1455 (loc + 1) * 4);
1456
1457 for (int i = 0; i < c->vattr_sizes[loc]; i++) {
1458 c->inputs[loc * 4 + i] =
1459 ntq_emit_vpm_read(c,
1460 &vpm_components_queued,
1461 &num_components,
1462 loc * 4 + i);
1463
1464 }
1465 }
1466
1467 if (c->devinfo->ver >= 40) {
1468 assert(vpm_components_queued == num_components);
1469 } else {
1470 assert(vpm_components_queued == 0);
1471 assert(num_components == 0);
1472 }
1473 }
1474
1475 static bool
1476 var_needs_point_coord(struct v3d_compile *c, nir_variable *var)
1477 {
1478 return (var->data.location == VARYING_SLOT_PNTC ||
1479 (var->data.location >= VARYING_SLOT_VAR0 &&
1480 (c->fs_key->point_sprite_mask &
1481 (1 << (var->data.location - VARYING_SLOT_VAR0)))));
1482 }
1483
1484 static bool
1485 program_reads_point_coord(struct v3d_compile *c)
1486 {
1487 nir_foreach_variable(var, &c->s->inputs) {
1488 if (var_needs_point_coord(c, var))
1489 return true;
1490 }
1491
1492 return false;
1493 }
1494
1495 static void
1496 ntq_setup_fs_inputs(struct v3d_compile *c)
1497 {
1498 unsigned num_entries = 0;
1499 unsigned num_components = 0;
1500 nir_foreach_variable(var, &c->s->inputs) {
1501 num_entries++;
1502 num_components += glsl_get_components(var->type);
1503 }
1504
1505 nir_variable *vars[num_entries];
1506
1507 unsigned i = 0;
1508 nir_foreach_variable(var, &c->s->inputs)
1509 vars[i++] = var;
1510
1511 /* Sort the variables so that we emit the input setup in
1512 * driver_location order. This is required for VPM reads, whose data
1513 * is fetched into the VPM in driver_location (TGSI register index)
1514 * order.
1515 */
1516 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1517
1518 for (unsigned i = 0; i < num_entries; i++) {
1519 nir_variable *var = vars[i];
1520 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1521 unsigned loc = var->data.driver_location;
1522
1523 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1524 (loc + array_len) * 4);
1525
1526 if (var->data.location == VARYING_SLOT_POS) {
1527 emit_fragcoord_input(c, loc);
1528 } else if (var_needs_point_coord(c, var)) {
1529 c->inputs[loc * 4 + 0] = c->point_x;
1530 c->inputs[loc * 4 + 1] = c->point_y;
1531 } else {
1532 for (int j = 0; j < array_len; j++)
1533 emit_fragment_input(c, loc + j, var, j);
1534 }
1535 }
1536 }
1537
1538 static void
1539 ntq_setup_outputs(struct v3d_compile *c)
1540 {
1541 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
1542 return;
1543
1544 nir_foreach_variable(var, &c->s->outputs) {
1545 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1546 unsigned loc = var->data.driver_location * 4;
1547
1548 assert(array_len == 1);
1549 (void)array_len;
1550
1551 for (int i = 0; i < 4 - var->data.location_frac; i++) {
1552 add_output(c, loc + var->data.location_frac + i,
1553 var->data.location,
1554 var->data.location_frac + i);
1555 }
1556
1557 switch (var->data.location) {
1558 case FRAG_RESULT_COLOR:
1559 c->output_color_var[0] = var;
1560 c->output_color_var[1] = var;
1561 c->output_color_var[2] = var;
1562 c->output_color_var[3] = var;
1563 break;
1564 case FRAG_RESULT_DATA0:
1565 case FRAG_RESULT_DATA1:
1566 case FRAG_RESULT_DATA2:
1567 case FRAG_RESULT_DATA3:
1568 c->output_color_var[var->data.location -
1569 FRAG_RESULT_DATA0] = var;
1570 break;
1571 case FRAG_RESULT_DEPTH:
1572 c->output_position_index = loc;
1573 break;
1574 case FRAG_RESULT_SAMPLE_MASK:
1575 c->output_sample_mask_index = loc;
1576 break;
1577 }
1578 }
1579 }
1580
1581 /**
1582 * Sets up the mapping from nir_register to struct qreg *.
1583 *
1584 * Each nir_register gets a struct qreg per 32-bit component being stored.
1585 */
1586 static void
1587 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1588 {
1589 foreach_list_typed(nir_register, nir_reg, node, list) {
1590 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1591 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1592 array_len *
1593 nir_reg->num_components);
1594
1595 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1596
1597 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1598 qregs[i] = vir_get_temp(c);
1599 }
1600 }
1601
1602 static void
1603 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1604 {
1605 /* XXX perf: Experiment with using immediate loads to avoid having
1606 * these end up in the uniform stream. Watch out for breaking the
1607 * small immediates optimization in the process!
1608 */
1609 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1610 for (int i = 0; i < instr->def.num_components; i++)
1611 qregs[i] = vir_uniform_ui(c, instr->value[i].u32);
1612
1613 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1614 }
1615
1616 static void
1617 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1618 {
1619 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1620
1621 /* VIR needs there to be *some* value, so pick 0 (same as for
1622 * ntq_setup_registers().
1623 */
1624 for (int i = 0; i < instr->def.num_components; i++)
1625 qregs[i] = vir_uniform_ui(c, 0);
1626 }
1627
1628 static void
1629 ntq_emit_image_size(struct v3d_compile *c, nir_intrinsic_instr *instr)
1630 {
1631 assert(instr->intrinsic == nir_intrinsic_image_deref_size);
1632 nir_variable *var = nir_intrinsic_get_var(instr, 0);
1633 unsigned image_index = var->data.driver_location;
1634 const struct glsl_type *sampler_type = glsl_without_array(var->type);
1635 bool is_array = glsl_sampler_type_is_array(sampler_type);
1636
1637 ntq_store_dest(c, &instr->dest, 0,
1638 vir_uniform(c, QUNIFORM_IMAGE_WIDTH, image_index));
1639 if (instr->num_components > 1) {
1640 ntq_store_dest(c, &instr->dest, 1,
1641 vir_uniform(c, QUNIFORM_IMAGE_HEIGHT,
1642 image_index));
1643 }
1644 if (instr->num_components > 2) {
1645 ntq_store_dest(c, &instr->dest, 2,
1646 vir_uniform(c,
1647 is_array ?
1648 QUNIFORM_IMAGE_ARRAY_SIZE :
1649 QUNIFORM_IMAGE_DEPTH,
1650 image_index));
1651 }
1652 }
1653
1654 static void
1655 vir_emit_tlb_color_read(struct v3d_compile *c, nir_intrinsic_instr *instr)
1656 {
1657 assert(c->s->info.stage == MESA_SHADER_FRAGMENT);
1658
1659 int rt = nir_src_as_uint(instr->src[0]);
1660 assert(rt < V3D_MAX_DRAW_BUFFERS);
1661
1662 int sample_index = nir_intrinsic_base(instr) ;
1663 assert(sample_index < V3D_MAX_SAMPLES);
1664
1665 int component = nir_intrinsic_component(instr);
1666 assert(component < 4);
1667
1668 /* We need to emit our TLB reads after we have acquired the scoreboard
1669 * lock, or the GPU will hang. Usually, we do our scoreboard locking on
1670 * the last thread switch to improve parallelism, however, that is only
1671 * guaranteed to happen before the tlb color writes.
1672 *
1673 * To fix that, we make sure we always emit a thread switch before the
1674 * first tlb color read. If that happens to be the last thread switch
1675 * we emit, then everything is fine, but otherwsie, if any code after
1676 * this point needs to emit additional thread switches, then we will
1677 * switch the strategy to locking the scoreboard on the first thread
1678 * switch instead -- see vir_emit_thrsw().
1679 */
1680 if (!c->emitted_tlb_load) {
1681 if (!c->last_thrsw_at_top_level) {
1682 assert(c->devinfo->ver >= 41);
1683 vir_emit_thrsw(c);
1684 }
1685
1686 c->emitted_tlb_load = true;
1687 }
1688
1689 struct qreg *color_reads_for_sample =
1690 &c->color_reads[(rt * V3D_MAX_SAMPLES + sample_index) * 4];
1691
1692 if (color_reads_for_sample[component].file == QFILE_NULL) {
1693 enum pipe_format rt_format = c->fs_key->color_fmt[rt].format;
1694 int num_components =
1695 util_format_get_nr_components(rt_format);
1696
1697 const bool swap_rb = c->fs_key->swap_color_rb & (1 << rt);
1698 if (swap_rb)
1699 num_components = MAX2(num_components, 3);
1700
1701 nir_variable *var = c->output_color_var[rt];
1702 enum glsl_base_type type = glsl_get_base_type(var->type);
1703
1704 bool is_int_format = type == GLSL_TYPE_INT ||
1705 type == GLSL_TYPE_UINT;
1706
1707 bool is_32b_tlb_format = is_int_format ||
1708 (c->fs_key->f32_color_rb & (1 << rt));
1709
1710 int num_samples = c->fs_key->msaa ? V3D_MAX_SAMPLES : 1;
1711
1712 uint32_t conf = 0xffffff00;
1713 conf |= c->fs_key->msaa ? TLB_SAMPLE_MODE_PER_SAMPLE :
1714 TLB_SAMPLE_MODE_PER_PIXEL;
1715 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1716
1717 if (is_32b_tlb_format) {
1718 /* The F32 vs I32 distinction was dropped in 4.2. */
1719 conf |= (c->devinfo->ver < 42 && is_int_format) ?
1720 TLB_TYPE_I32_COLOR : TLB_TYPE_F32_COLOR;
1721
1722 conf |= ((num_components - 1) <<
1723 TLB_VEC_SIZE_MINUS_1_SHIFT);
1724 } else {
1725 conf |= TLB_TYPE_F16_COLOR;
1726 conf |= TLB_F16_SWAP_HI_LO;
1727
1728 if (num_components >= 3)
1729 conf |= TLB_VEC_SIZE_4_F16;
1730 else
1731 conf |= TLB_VEC_SIZE_2_F16;
1732 }
1733
1734
1735 for (int i = 0; i < num_samples; i++) {
1736 struct qreg r, g, b, a;
1737 if (is_32b_tlb_format) {
1738 r = conf != 0xffffffff && i == 0?
1739 vir_TLBU_COLOR_READ(c, conf) :
1740 vir_TLB_COLOR_READ(c);
1741 if (num_components >= 2)
1742 g = vir_TLB_COLOR_READ(c);
1743 if (num_components >= 3)
1744 b = vir_TLB_COLOR_READ(c);
1745 if (num_components >= 4)
1746 a = vir_TLB_COLOR_READ(c);
1747 } else {
1748 struct qreg rg = conf != 0xffffffff && i == 0 ?
1749 vir_TLBU_COLOR_READ(c, conf) :
1750 vir_TLB_COLOR_READ(c);
1751 r = vir_FMOV(c, rg);
1752 vir_set_unpack(c->defs[r.index], 0,
1753 V3D_QPU_UNPACK_L);
1754 g = vir_FMOV(c, rg);
1755 vir_set_unpack(c->defs[g.index], 0,
1756 V3D_QPU_UNPACK_H);
1757
1758 if (num_components > 2) {
1759 struct qreg ba = vir_TLB_COLOR_READ(c);
1760 b = vir_FMOV(c, ba);
1761 vir_set_unpack(c->defs[b.index], 0,
1762 V3D_QPU_UNPACK_L);
1763 a = vir_FMOV(c, ba);
1764 vir_set_unpack(c->defs[a.index], 0,
1765 V3D_QPU_UNPACK_H);
1766 }
1767 }
1768
1769 struct qreg *color_reads =
1770 &c->color_reads[(rt * V3D_MAX_SAMPLES + i) * 4];
1771
1772 color_reads[0] = swap_rb ? b : r;
1773 if (num_components >= 2)
1774 color_reads[1] = g;
1775 if (num_components >= 3)
1776 color_reads[2] = swap_rb ? r : b;
1777 if (num_components >= 4)
1778 color_reads[3] = a;
1779 }
1780 }
1781
1782 assert(color_reads_for_sample[component].file != QFILE_NULL);
1783 ntq_store_dest(c, &instr->dest, 0,
1784 vir_MOV(c, color_reads_for_sample[component]));
1785 }
1786
1787 static void
1788 ntq_emit_load_uniform(struct v3d_compile *c, nir_intrinsic_instr *instr)
1789 {
1790 if (nir_src_is_const(instr->src[0])) {
1791 int offset = (nir_intrinsic_base(instr) +
1792 nir_src_as_uint(instr->src[0]));
1793 assert(offset % 4 == 0);
1794 /* We need dwords */
1795 offset = offset / 4;
1796 for (int i = 0; i < instr->num_components; i++) {
1797 ntq_store_dest(c, &instr->dest, i,
1798 vir_uniform(c, QUNIFORM_UNIFORM,
1799 offset + i));
1800 }
1801 } else {
1802 ntq_emit_tmu_general(c, instr, false);
1803 }
1804 }
1805
1806 static void
1807 ntq_emit_load_input(struct v3d_compile *c, nir_intrinsic_instr *instr)
1808 {
1809 /* XXX: Use ldvpmv (uniform offset) or ldvpmd (non-uniform offset)
1810 * and enable PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR.
1811 */
1812 unsigned offset =
1813 nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[0]);
1814
1815 if (c->s->info.stage != MESA_SHADER_FRAGMENT && c->devinfo->ver >= 40) {
1816 /* Emit the LDVPM directly now, rather than at the top
1817 * of the shader like we did for V3D 3.x (which needs
1818 * vpmsetup when not just taking the next offset).
1819 *
1820 * Note that delaying like this may introduce stalls,
1821 * as LDVPMV takes a minimum of 1 instruction but may
1822 * be slower if the VPM unit is busy with another QPU.
1823 */
1824 int index = 0;
1825 if (c->s->info.system_values_read &
1826 (1ull << SYSTEM_VALUE_INSTANCE_ID)) {
1827 index++;
1828 }
1829 if (c->s->info.system_values_read &
1830 (1ull << SYSTEM_VALUE_VERTEX_ID)) {
1831 index++;
1832 }
1833 for (int i = 0; i < offset; i++)
1834 index += c->vattr_sizes[i];
1835 index += nir_intrinsic_component(instr);
1836 for (int i = 0; i < instr->num_components; i++) {
1837 struct qreg vpm_offset = vir_uniform_ui(c, index++);
1838 ntq_store_dest(c, &instr->dest, i,
1839 vir_LDVPMV_IN(c, vpm_offset));
1840 }
1841 } else {
1842 for (int i = 0; i < instr->num_components; i++) {
1843 int comp = nir_intrinsic_component(instr) + i;
1844 ntq_store_dest(c, &instr->dest, i,
1845 vir_MOV(c, c->inputs[offset * 4 + comp]));
1846 }
1847 }
1848 }
1849
1850 static void
1851 ntq_emit_per_sample_color_write(struct v3d_compile *c,
1852 nir_intrinsic_instr *instr)
1853 {
1854 assert(instr->intrinsic == nir_intrinsic_store_tlb_sample_color_v3d);
1855
1856 unsigned rt = nir_src_as_uint(instr->src[1]);
1857 assert(rt < V3D_MAX_DRAW_BUFFERS);
1858
1859 unsigned sample_idx = nir_intrinsic_base(instr);
1860 assert(sample_idx < V3D_MAX_SAMPLES);
1861
1862 unsigned offset = (rt * V3D_MAX_SAMPLES + sample_idx) * 4;
1863 for (int i = 0; i < instr->num_components; i++) {
1864 c->sample_colors[offset + i] =
1865 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
1866 }
1867 }
1868
1869 static void
1870 ntq_emit_color_write(struct v3d_compile *c,
1871 nir_intrinsic_instr *instr)
1872 {
1873 unsigned offset = (nir_intrinsic_base(instr) +
1874 nir_src_as_uint(instr->src[1])) * 4 +
1875 nir_intrinsic_component(instr);
1876 for (int i = 0; i < instr->num_components; i++) {
1877 c->outputs[offset + i] =
1878 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
1879 }
1880 }
1881
1882 static void
1883 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
1884 {
1885 switch (instr->intrinsic) {
1886 case nir_intrinsic_load_uniform:
1887 ntq_emit_load_uniform(c, instr);
1888 break;
1889
1890 case nir_intrinsic_load_ubo:
1891 ntq_emit_tmu_general(c, instr, false);
1892 break;
1893
1894 case nir_intrinsic_ssbo_atomic_add:
1895 case nir_intrinsic_ssbo_atomic_imin:
1896 case nir_intrinsic_ssbo_atomic_umin:
1897 case nir_intrinsic_ssbo_atomic_imax:
1898 case nir_intrinsic_ssbo_atomic_umax:
1899 case nir_intrinsic_ssbo_atomic_and:
1900 case nir_intrinsic_ssbo_atomic_or:
1901 case nir_intrinsic_ssbo_atomic_xor:
1902 case nir_intrinsic_ssbo_atomic_exchange:
1903 case nir_intrinsic_ssbo_atomic_comp_swap:
1904 case nir_intrinsic_load_ssbo:
1905 case nir_intrinsic_store_ssbo:
1906 ntq_emit_tmu_general(c, instr, false);
1907 break;
1908
1909 case nir_intrinsic_shared_atomic_add:
1910 case nir_intrinsic_shared_atomic_imin:
1911 case nir_intrinsic_shared_atomic_umin:
1912 case nir_intrinsic_shared_atomic_imax:
1913 case nir_intrinsic_shared_atomic_umax:
1914 case nir_intrinsic_shared_atomic_and:
1915 case nir_intrinsic_shared_atomic_or:
1916 case nir_intrinsic_shared_atomic_xor:
1917 case nir_intrinsic_shared_atomic_exchange:
1918 case nir_intrinsic_shared_atomic_comp_swap:
1919 case nir_intrinsic_load_shared:
1920 case nir_intrinsic_store_shared:
1921 case nir_intrinsic_load_scratch:
1922 case nir_intrinsic_store_scratch:
1923 ntq_emit_tmu_general(c, instr, true);
1924 break;
1925
1926 case nir_intrinsic_image_deref_load:
1927 case nir_intrinsic_image_deref_store:
1928 case nir_intrinsic_image_deref_atomic_add:
1929 case nir_intrinsic_image_deref_atomic_min:
1930 case nir_intrinsic_image_deref_atomic_max:
1931 case nir_intrinsic_image_deref_atomic_and:
1932 case nir_intrinsic_image_deref_atomic_or:
1933 case nir_intrinsic_image_deref_atomic_xor:
1934 case nir_intrinsic_image_deref_atomic_exchange:
1935 case nir_intrinsic_image_deref_atomic_comp_swap:
1936 v3d40_vir_emit_image_load_store(c, instr);
1937 break;
1938
1939 case nir_intrinsic_get_buffer_size:
1940 ntq_store_dest(c, &instr->dest, 0,
1941 vir_uniform(c, QUNIFORM_GET_BUFFER_SIZE,
1942 nir_src_as_uint(instr->src[0])));
1943 break;
1944
1945 case nir_intrinsic_load_user_clip_plane:
1946 for (int i = 0; i < instr->num_components; i++) {
1947 ntq_store_dest(c, &instr->dest, i,
1948 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1949 nir_intrinsic_ucp_id(instr) *
1950 4 + i));
1951 }
1952 break;
1953
1954 case nir_intrinsic_load_viewport_x_scale:
1955 ntq_store_dest(c, &instr->dest, 0,
1956 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE, 0));
1957 break;
1958
1959 case nir_intrinsic_load_viewport_y_scale:
1960 ntq_store_dest(c, &instr->dest, 0,
1961 vir_uniform(c, QUNIFORM_VIEWPORT_Y_SCALE, 0));
1962 break;
1963
1964 case nir_intrinsic_load_viewport_z_scale:
1965 ntq_store_dest(c, &instr->dest, 0,
1966 vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0));
1967 break;
1968
1969 case nir_intrinsic_load_viewport_z_offset:
1970 ntq_store_dest(c, &instr->dest, 0,
1971 vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0));
1972 break;
1973
1974 case nir_intrinsic_load_alpha_ref_float:
1975 ntq_store_dest(c, &instr->dest, 0,
1976 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1977 break;
1978
1979 case nir_intrinsic_load_sample_mask_in:
1980 ntq_store_dest(c, &instr->dest, 0, vir_MSF(c));
1981 break;
1982
1983 case nir_intrinsic_load_helper_invocation:
1984 vir_set_pf(vir_MSF_dest(c, vir_nop_reg()), V3D_QPU_PF_PUSHZ);
1985 ntq_store_dest(c, &instr->dest, 0,
1986 vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1987 vir_uniform_ui(c, ~0),
1988 vir_uniform_ui(c, 0))));
1989 break;
1990
1991 case nir_intrinsic_load_front_face:
1992 /* The register contains 0 (front) or 1 (back), and we need to
1993 * turn it into a NIR bool where true means front.
1994 */
1995 ntq_store_dest(c, &instr->dest, 0,
1996 vir_ADD(c,
1997 vir_uniform_ui(c, -1),
1998 vir_REVF(c)));
1999 break;
2000
2001 case nir_intrinsic_load_instance_id:
2002 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
2003 break;
2004
2005 case nir_intrinsic_load_vertex_id:
2006 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
2007 break;
2008
2009 case nir_intrinsic_load_tlb_color_v3d:
2010 vir_emit_tlb_color_read(c, instr);
2011 break;
2012
2013 case nir_intrinsic_load_input:
2014 ntq_emit_load_input(c, instr);
2015 break;
2016
2017 case nir_intrinsic_store_tlb_sample_color_v3d:
2018 ntq_emit_per_sample_color_write(c, instr);
2019 break;
2020
2021 case nir_intrinsic_store_output:
2022 /* XXX perf: Use stvpmv with uniform non-constant offsets and
2023 * stvpmd with non-uniform offsets and enable
2024 * PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR.
2025 */
2026 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
2027 ntq_emit_color_write(c, instr);
2028 } else {
2029 assert(instr->num_components == 1);
2030
2031 vir_VPM_WRITE(c,
2032 ntq_get_src(c, instr->src[0], 0),
2033 nir_intrinsic_base(instr));
2034 }
2035 break;
2036
2037 case nir_intrinsic_image_deref_size:
2038 ntq_emit_image_size(c, instr);
2039 break;
2040
2041 case nir_intrinsic_discard:
2042 if (vir_in_nonuniform_control_flow(c)) {
2043 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2044 V3D_QPU_PF_PUSHZ);
2045 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
2046 vir_uniform_ui(c, 0)),
2047 V3D_QPU_COND_IFA);
2048 } else {
2049 vir_SETMSF_dest(c, vir_nop_reg(),
2050 vir_uniform_ui(c, 0));
2051 }
2052 break;
2053
2054 case nir_intrinsic_discard_if: {
2055 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, instr->src[0]);
2056
2057 if (vir_in_nonuniform_control_flow(c)) {
2058 struct qinst *exec_flag = vir_MOV_dest(c, vir_nop_reg(),
2059 c->execute);
2060 if (cond == V3D_QPU_COND_IFA) {
2061 vir_set_uf(exec_flag, V3D_QPU_UF_ANDZ);
2062 } else {
2063 vir_set_uf(exec_flag, V3D_QPU_UF_NORNZ);
2064 cond = V3D_QPU_COND_IFA;
2065 }
2066 }
2067
2068 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
2069 vir_uniform_ui(c, 0)), cond);
2070
2071 break;
2072 }
2073
2074 case nir_intrinsic_memory_barrier:
2075 case nir_intrinsic_memory_barrier_atomic_counter:
2076 case nir_intrinsic_memory_barrier_buffer:
2077 case nir_intrinsic_memory_barrier_image:
2078 case nir_intrinsic_memory_barrier_shared:
2079 case nir_intrinsic_group_memory_barrier:
2080 /* We don't do any instruction scheduling of these NIR
2081 * instructions between each other, so we just need to make
2082 * sure that the TMU operations before the barrier are flushed
2083 * before the ones after the barrier. That is currently
2084 * handled by having a THRSW in each of them and a LDTMU
2085 * series or a TMUWT after.
2086 */
2087 break;
2088
2089 case nir_intrinsic_barrier:
2090 /* Emit a TSY op to get all invocations in the workgroup
2091 * (actually supergroup) to block until the last invocation
2092 * reaches the TSY op.
2093 */
2094 if (c->devinfo->ver >= 42) {
2095 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
2096 V3D_QPU_WADDR_SYNCB));
2097 } else {
2098 struct qinst *sync =
2099 vir_BARRIERID_dest(c,
2100 vir_reg(QFILE_MAGIC,
2101 V3D_QPU_WADDR_SYNCU));
2102 sync->uniform =
2103 vir_get_uniform_index(c, QUNIFORM_CONSTANT,
2104 0xffffff00 |
2105 V3D_TSY_WAIT_INC_CHECK);
2106
2107 }
2108
2109 /* The blocking of a TSY op only happens at the next thread
2110 * switch. No texturing may be outstanding at the time of a
2111 * TSY blocking operation.
2112 */
2113 vir_emit_thrsw(c);
2114 break;
2115
2116 case nir_intrinsic_load_num_work_groups:
2117 for (int i = 0; i < 3; i++) {
2118 ntq_store_dest(c, &instr->dest, i,
2119 vir_uniform(c, QUNIFORM_NUM_WORK_GROUPS,
2120 i));
2121 }
2122 break;
2123
2124 case nir_intrinsic_load_local_invocation_index:
2125 ntq_store_dest(c, &instr->dest, 0,
2126 vir_SHR(c, c->cs_payload[1],
2127 vir_uniform_ui(c, 32 - c->local_invocation_index_bits)));
2128 break;
2129
2130 case nir_intrinsic_load_work_group_id:
2131 ntq_store_dest(c, &instr->dest, 0,
2132 vir_AND(c, c->cs_payload[0],
2133 vir_uniform_ui(c, 0xffff)));
2134 ntq_store_dest(c, &instr->dest, 1,
2135 vir_SHR(c, c->cs_payload[0],
2136 vir_uniform_ui(c, 16)));
2137 ntq_store_dest(c, &instr->dest, 2,
2138 vir_AND(c, c->cs_payload[1],
2139 vir_uniform_ui(c, 0xffff)));
2140 break;
2141
2142 case nir_intrinsic_load_subgroup_id:
2143 ntq_store_dest(c, &instr->dest, 0, vir_EIDX(c));
2144 break;
2145
2146 default:
2147 fprintf(stderr, "Unknown intrinsic: ");
2148 nir_print_instr(&instr->instr, stderr);
2149 fprintf(stderr, "\n");
2150 break;
2151 }
2152 }
2153
2154 /* Clears (activates) the execute flags for any channels whose jump target
2155 * matches this block.
2156 *
2157 * XXX perf: Could we be using flpush/flpop somehow for our execution channel
2158 * enabling?
2159 *
2160 * XXX perf: For uniform control flow, we should be able to skip c->execute
2161 * handling entirely.
2162 */
2163 static void
2164 ntq_activate_execute_for_block(struct v3d_compile *c)
2165 {
2166 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
2167 c->execute, vir_uniform_ui(c, c->cur_block->index)),
2168 V3D_QPU_PF_PUSHZ);
2169
2170 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2171 }
2172
2173 static void
2174 ntq_emit_uniform_if(struct v3d_compile *c, nir_if *if_stmt)
2175 {
2176 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2177 bool empty_else_block =
2178 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2179 exec_list_is_empty(&nir_else_block->instr_list));
2180
2181 struct qblock *then_block = vir_new_block(c);
2182 struct qblock *after_block = vir_new_block(c);
2183 struct qblock *else_block;
2184 if (empty_else_block)
2185 else_block = after_block;
2186 else
2187 else_block = vir_new_block(c);
2188
2189 /* Set up the flags for the IF condition (taking the THEN branch). */
2190 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
2191
2192 /* Jump to ELSE. */
2193 vir_BRANCH(c, cond == V3D_QPU_COND_IFA ?
2194 V3D_QPU_BRANCH_COND_ALLNA :
2195 V3D_QPU_BRANCH_COND_ALLA);
2196 vir_link_blocks(c->cur_block, else_block);
2197 vir_link_blocks(c->cur_block, then_block);
2198
2199 /* Process the THEN block. */
2200 vir_set_emit_block(c, then_block);
2201 ntq_emit_cf_list(c, &if_stmt->then_list);
2202
2203 if (!empty_else_block) {
2204 /* At the end of the THEN block, jump to ENDIF */
2205 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALWAYS);
2206 vir_link_blocks(c->cur_block, after_block);
2207
2208 /* Emit the else block. */
2209 vir_set_emit_block(c, else_block);
2210 ntq_emit_cf_list(c, &if_stmt->else_list);
2211 }
2212
2213 vir_link_blocks(c->cur_block, after_block);
2214
2215 vir_set_emit_block(c, after_block);
2216 }
2217
2218 static void
2219 ntq_emit_nonuniform_if(struct v3d_compile *c, nir_if *if_stmt)
2220 {
2221 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2222 bool empty_else_block =
2223 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2224 exec_list_is_empty(&nir_else_block->instr_list));
2225
2226 struct qblock *then_block = vir_new_block(c);
2227 struct qblock *after_block = vir_new_block(c);
2228 struct qblock *else_block;
2229 if (empty_else_block)
2230 else_block = after_block;
2231 else
2232 else_block = vir_new_block(c);
2233
2234 bool was_uniform_control_flow = false;
2235 if (!vir_in_nonuniform_control_flow(c)) {
2236 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2237 was_uniform_control_flow = true;
2238 }
2239
2240 /* Set up the flags for the IF condition (taking the THEN branch). */
2241 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
2242
2243 /* Update the flags+cond to mean "Taking the ELSE branch (!cond) and
2244 * was previously active (execute Z) for updating the exec flags.
2245 */
2246 if (was_uniform_control_flow) {
2247 cond = v3d_qpu_cond_invert(cond);
2248 } else {
2249 struct qinst *inst = vir_MOV_dest(c, vir_nop_reg(), c->execute);
2250 if (cond == V3D_QPU_COND_IFA) {
2251 vir_set_uf(inst, V3D_QPU_UF_NORNZ);
2252 } else {
2253 vir_set_uf(inst, V3D_QPU_UF_ANDZ);
2254 cond = V3D_QPU_COND_IFA;
2255 }
2256 }
2257
2258 vir_MOV_cond(c, cond,
2259 c->execute,
2260 vir_uniform_ui(c, else_block->index));
2261
2262 /* Jump to ELSE if nothing is active for THEN, otherwise fall
2263 * through.
2264 */
2265 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ);
2266 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
2267 vir_link_blocks(c->cur_block, else_block);
2268 vir_link_blocks(c->cur_block, then_block);
2269
2270 /* Process the THEN block. */
2271 vir_set_emit_block(c, then_block);
2272 ntq_emit_cf_list(c, &if_stmt->then_list);
2273
2274 if (!empty_else_block) {
2275 /* Handle the end of the THEN block. First, all currently
2276 * active channels update their execute flags to point to
2277 * ENDIF
2278 */
2279 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2280 V3D_QPU_PF_PUSHZ);
2281 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2282 vir_uniform_ui(c, after_block->index));
2283
2284 /* If everything points at ENDIF, then jump there immediately. */
2285 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
2286 c->execute,
2287 vir_uniform_ui(c, after_block->index)),
2288 V3D_QPU_PF_PUSHZ);
2289 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
2290 vir_link_blocks(c->cur_block, after_block);
2291 vir_link_blocks(c->cur_block, else_block);
2292
2293 vir_set_emit_block(c, else_block);
2294 ntq_activate_execute_for_block(c);
2295 ntq_emit_cf_list(c, &if_stmt->else_list);
2296 }
2297
2298 vir_link_blocks(c->cur_block, after_block);
2299
2300 vir_set_emit_block(c, after_block);
2301 if (was_uniform_control_flow)
2302 c->execute = c->undef;
2303 else
2304 ntq_activate_execute_for_block(c);
2305 }
2306
2307 static void
2308 ntq_emit_if(struct v3d_compile *c, nir_if *nif)
2309 {
2310 bool was_in_control_flow = c->in_control_flow;
2311 c->in_control_flow = true;
2312 if (!vir_in_nonuniform_control_flow(c) &&
2313 nir_src_is_dynamically_uniform(nif->condition)) {
2314 ntq_emit_uniform_if(c, nif);
2315 } else {
2316 ntq_emit_nonuniform_if(c, nif);
2317 }
2318 c->in_control_flow = was_in_control_flow;
2319 }
2320
2321 static void
2322 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
2323 {
2324 switch (jump->type) {
2325 case nir_jump_break:
2326 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2327 V3D_QPU_PF_PUSHZ);
2328 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2329 vir_uniform_ui(c, c->loop_break_block->index));
2330 break;
2331
2332 case nir_jump_continue:
2333 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2334 V3D_QPU_PF_PUSHZ);
2335 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2336 vir_uniform_ui(c, c->loop_cont_block->index));
2337 break;
2338
2339 case nir_jump_return:
2340 unreachable("All returns shouold be lowered\n");
2341 }
2342 }
2343
2344 static void
2345 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
2346 {
2347 switch (instr->type) {
2348 case nir_instr_type_deref:
2349 /* ignored, will be walked by the intrinsic using it. */
2350 break;
2351
2352 case nir_instr_type_alu:
2353 ntq_emit_alu(c, nir_instr_as_alu(instr));
2354 break;
2355
2356 case nir_instr_type_intrinsic:
2357 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
2358 break;
2359
2360 case nir_instr_type_load_const:
2361 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
2362 break;
2363
2364 case nir_instr_type_ssa_undef:
2365 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
2366 break;
2367
2368 case nir_instr_type_tex:
2369 ntq_emit_tex(c, nir_instr_as_tex(instr));
2370 break;
2371
2372 case nir_instr_type_jump:
2373 ntq_emit_jump(c, nir_instr_as_jump(instr));
2374 break;
2375
2376 default:
2377 fprintf(stderr, "Unknown NIR instr type: ");
2378 nir_print_instr(instr, stderr);
2379 fprintf(stderr, "\n");
2380 abort();
2381 }
2382 }
2383
2384 static void
2385 ntq_emit_block(struct v3d_compile *c, nir_block *block)
2386 {
2387 nir_foreach_instr(instr, block) {
2388 ntq_emit_instr(c, instr);
2389 }
2390 }
2391
2392 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
2393
2394 static void
2395 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
2396 {
2397 bool was_in_control_flow = c->in_control_flow;
2398 c->in_control_flow = true;
2399
2400 bool was_uniform_control_flow = false;
2401 if (!vir_in_nonuniform_control_flow(c)) {
2402 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2403 was_uniform_control_flow = true;
2404 }
2405
2406 struct qblock *save_loop_cont_block = c->loop_cont_block;
2407 struct qblock *save_loop_break_block = c->loop_break_block;
2408
2409 c->loop_cont_block = vir_new_block(c);
2410 c->loop_break_block = vir_new_block(c);
2411
2412 vir_link_blocks(c->cur_block, c->loop_cont_block);
2413 vir_set_emit_block(c, c->loop_cont_block);
2414 ntq_activate_execute_for_block(c);
2415
2416 ntq_emit_cf_list(c, &loop->body);
2417
2418 /* Re-enable any previous continues now, so our ANYA check below
2419 * works.
2420 *
2421 * XXX: Use the .ORZ flags update, instead.
2422 */
2423 vir_set_pf(vir_XOR_dest(c,
2424 vir_nop_reg(),
2425 c->execute,
2426 vir_uniform_ui(c, c->loop_cont_block->index)),
2427 V3D_QPU_PF_PUSHZ);
2428 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2429
2430 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ);
2431
2432 struct qinst *branch = vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
2433 /* Pixels that were not dispatched or have been discarded should not
2434 * contribute to looping again.
2435 */
2436 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P;
2437 vir_link_blocks(c->cur_block, c->loop_cont_block);
2438 vir_link_blocks(c->cur_block, c->loop_break_block);
2439
2440 vir_set_emit_block(c, c->loop_break_block);
2441 if (was_uniform_control_flow)
2442 c->execute = c->undef;
2443 else
2444 ntq_activate_execute_for_block(c);
2445
2446 c->loop_break_block = save_loop_break_block;
2447 c->loop_cont_block = save_loop_cont_block;
2448
2449 c->loops++;
2450
2451 c->in_control_flow = was_in_control_flow;
2452 }
2453
2454 static void
2455 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
2456 {
2457 fprintf(stderr, "FUNCTIONS not handled.\n");
2458 abort();
2459 }
2460
2461 static void
2462 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
2463 {
2464 foreach_list_typed(nir_cf_node, node, node, list) {
2465 switch (node->type) {
2466 case nir_cf_node_block:
2467 ntq_emit_block(c, nir_cf_node_as_block(node));
2468 break;
2469
2470 case nir_cf_node_if:
2471 ntq_emit_if(c, nir_cf_node_as_if(node));
2472 break;
2473
2474 case nir_cf_node_loop:
2475 ntq_emit_loop(c, nir_cf_node_as_loop(node));
2476 break;
2477
2478 case nir_cf_node_function:
2479 ntq_emit_function(c, nir_cf_node_as_function(node));
2480 break;
2481
2482 default:
2483 fprintf(stderr, "Unknown NIR node type\n");
2484 abort();
2485 }
2486 }
2487 }
2488
2489 static void
2490 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
2491 {
2492 ntq_setup_registers(c, &impl->registers);
2493 ntq_emit_cf_list(c, &impl->body);
2494 }
2495
2496 static void
2497 nir_to_vir(struct v3d_compile *c)
2498 {
2499 switch (c->s->info.stage) {
2500 case MESA_SHADER_FRAGMENT:
2501 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
2502 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
2503 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
2504
2505 /* V3D 4.x can disable implicit point coordinate varyings if
2506 * they are not used.
2507 */
2508 if (c->fs_key->is_points &&
2509 (c->devinfo->ver < 40 || program_reads_point_coord(c))) {
2510 c->point_x = emit_fragment_varying(c, NULL, 0, 0);
2511 c->point_y = emit_fragment_varying(c, NULL, 0, 0);
2512 c->uses_implicit_point_line_varyings = true;
2513 } else if (c->fs_key->is_lines && c->devinfo->ver < 40) {
2514 c->line_x = emit_fragment_varying(c, NULL, 0, 0);
2515 c->uses_implicit_point_line_varyings = true;
2516 }
2517 break;
2518 case MESA_SHADER_COMPUTE:
2519 /* Set up the TSO for barriers, assuming we do some. */
2520 if (c->devinfo->ver < 42) {
2521 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
2522 V3D_QPU_WADDR_SYNC));
2523 }
2524
2525 c->cs_payload[0] = vir_MOV(c, vir_reg(QFILE_REG, 0));
2526 c->cs_payload[1] = vir_MOV(c, vir_reg(QFILE_REG, 2));
2527
2528 /* Set up the division between gl_LocalInvocationIndex and
2529 * wg_in_mem in the payload reg.
2530 */
2531 int wg_size = (c->s->info.cs.local_size[0] *
2532 c->s->info.cs.local_size[1] *
2533 c->s->info.cs.local_size[2]);
2534 c->local_invocation_index_bits =
2535 ffs(util_next_power_of_two(MAX2(wg_size, 64))) - 1;
2536 assert(c->local_invocation_index_bits <= 8);
2537
2538 if (c->s->info.cs.shared_size) {
2539 struct qreg wg_in_mem = vir_SHR(c, c->cs_payload[1],
2540 vir_uniform_ui(c, 16));
2541 if (c->s->info.cs.local_size[0] != 1 ||
2542 c->s->info.cs.local_size[1] != 1 ||
2543 c->s->info.cs.local_size[2] != 1) {
2544 int wg_bits = (16 -
2545 c->local_invocation_index_bits);
2546 int wg_mask = (1 << wg_bits) - 1;
2547 wg_in_mem = vir_AND(c, wg_in_mem,
2548 vir_uniform_ui(c, wg_mask));
2549 }
2550 struct qreg shared_per_wg =
2551 vir_uniform_ui(c, c->s->info.cs.shared_size);
2552
2553 c->cs_shared_offset =
2554 vir_ADD(c,
2555 vir_uniform(c, QUNIFORM_SHARED_OFFSET,0),
2556 vir_UMUL(c, wg_in_mem, shared_per_wg));
2557 }
2558 break;
2559 default:
2560 break;
2561 }
2562
2563 if (c->s->scratch_size) {
2564 v3d_setup_spill_base(c);
2565 c->spill_size += V3D_CHANNELS * c->s->scratch_size;
2566 }
2567
2568 if (c->s->info.stage == MESA_SHADER_FRAGMENT)
2569 ntq_setup_fs_inputs(c);
2570 else
2571 ntq_setup_vpm_inputs(c);
2572
2573 ntq_setup_outputs(c);
2574
2575 /* Find the main function and emit the body. */
2576 nir_foreach_function(function, c->s) {
2577 assert(strcmp(function->name, "main") == 0);
2578 assert(function->impl);
2579 ntq_emit_impl(c, function->impl);
2580 }
2581 }
2582
2583 const nir_shader_compiler_options v3d_nir_options = {
2584 .lower_all_io_to_temps = true,
2585 .lower_extract_byte = true,
2586 .lower_extract_word = true,
2587 .lower_bitfield_insert_to_shifts = true,
2588 .lower_bitfield_extract_to_shifts = true,
2589 .lower_bitfield_reverse = true,
2590 .lower_bit_count = true,
2591 .lower_cs_local_id_from_index = true,
2592 .lower_ffract = true,
2593 .lower_fmod = true,
2594 .lower_pack_unorm_2x16 = true,
2595 .lower_pack_snorm_2x16 = true,
2596 .lower_pack_unorm_4x8 = true,
2597 .lower_pack_snorm_4x8 = true,
2598 .lower_unpack_unorm_4x8 = true,
2599 .lower_unpack_snorm_4x8 = true,
2600 .lower_pack_half_2x16 = true,
2601 .lower_unpack_half_2x16 = true,
2602 .lower_fdiv = true,
2603 .lower_find_lsb = true,
2604 .lower_ffma = true,
2605 .lower_flrp32 = true,
2606 .lower_fpow = true,
2607 .lower_fsat = true,
2608 .lower_fsqrt = true,
2609 .lower_ifind_msb = true,
2610 .lower_isign = true,
2611 .lower_ldexp = true,
2612 .lower_mul_high = true,
2613 .lower_wpos_pntc = true,
2614 .lower_rotate = true,
2615 };
2616
2617 /**
2618 * When demoting a shader down to single-threaded, removes the THRSW
2619 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
2620 * program end).
2621 */
2622 static void
2623 vir_remove_thrsw(struct v3d_compile *c)
2624 {
2625 vir_for_each_block(block, c) {
2626 vir_for_each_inst_safe(inst, block) {
2627 if (inst->qpu.sig.thrsw)
2628 vir_remove_instruction(c, inst);
2629 }
2630 }
2631
2632 c->last_thrsw = NULL;
2633 }
2634
2635 void
2636 vir_emit_last_thrsw(struct v3d_compile *c)
2637 {
2638 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
2639 * switching, so disable threads if we didn't do any TMU ops (each of
2640 * which would have emitted a THRSW).
2641 */
2642 if (!c->last_thrsw_at_top_level && c->devinfo->ver < 41) {
2643 c->threads = 1;
2644 if (c->last_thrsw)
2645 vir_remove_thrsw(c);
2646 return;
2647 }
2648
2649 /* If we're threaded and the last THRSW was in conditional code, then
2650 * we need to emit another one so that we can flag it as the last
2651 * thrsw.
2652 */
2653 if (c->last_thrsw && !c->last_thrsw_at_top_level) {
2654 assert(c->devinfo->ver >= 41);
2655 vir_emit_thrsw(c);
2656 }
2657
2658 /* If we're threaded, then we need to mark the last THRSW instruction
2659 * so we can emit a pair of them at QPU emit time.
2660 *
2661 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2662 * post-last-THRSW state, so we can skip this.
2663 */
2664 if (!c->last_thrsw && c->s->info.stage == MESA_SHADER_FRAGMENT) {
2665 assert(c->devinfo->ver >= 41);
2666 vir_emit_thrsw(c);
2667 }
2668
2669 if (c->last_thrsw)
2670 c->last_thrsw->is_last_thrsw = true;
2671 }
2672
2673 /* There's a flag in the shader for "center W is needed for reasons other than
2674 * non-centroid varyings", so we just walk the program after VIR optimization
2675 * to see if it's used. It should be harmless to set even if we only use
2676 * center W for varyings.
2677 */
2678 static void
2679 vir_check_payload_w(struct v3d_compile *c)
2680 {
2681 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
2682 return;
2683
2684 vir_for_each_inst_inorder(inst, c) {
2685 for (int i = 0; i < vir_get_nsrc(inst); i++) {
2686 if (inst->src[i].file == QFILE_REG &&
2687 inst->src[i].index == 0) {
2688 c->uses_center_w = true;
2689 return;
2690 }
2691 }
2692 }
2693
2694 }
2695
2696 void
2697 v3d_nir_to_vir(struct v3d_compile *c)
2698 {
2699 if (V3D_DEBUG & (V3D_DEBUG_NIR |
2700 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2701 fprintf(stderr, "%s prog %d/%d NIR:\n",
2702 vir_get_stage_name(c),
2703 c->program_id, c->variant_id);
2704 nir_print_shader(c->s, stderr);
2705 }
2706
2707 nir_to_vir(c);
2708
2709 /* Emit the last THRSW before STVPM and TLB writes. */
2710 vir_emit_last_thrsw(c);
2711
2712 switch (c->s->info.stage) {
2713 case MESA_SHADER_FRAGMENT:
2714 emit_frag_end(c);
2715 break;
2716 case MESA_SHADER_VERTEX:
2717 emit_vert_end(c);
2718 break;
2719 case MESA_SHADER_COMPUTE:
2720 break;
2721 default:
2722 unreachable("bad stage");
2723 }
2724
2725 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2726 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2727 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
2728 vir_get_stage_name(c),
2729 c->program_id, c->variant_id);
2730 vir_dump(c);
2731 fprintf(stderr, "\n");
2732 }
2733
2734 vir_optimize(c);
2735
2736 vir_check_payload_w(c);
2737
2738 /* XXX perf: On VC4, we do a VIR-level instruction scheduling here.
2739 * We used that on that platform to pipeline TMU writes and reduce the
2740 * number of thread switches, as well as try (mostly successfully) to
2741 * reduce maximum register pressure to allow more threads. We should
2742 * do something of that sort for V3D -- either instruction scheduling
2743 * here, or delay the the THRSW and LDTMUs from our texture
2744 * instructions until the results are needed.
2745 */
2746
2747 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2748 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2749 fprintf(stderr, "%s prog %d/%d VIR:\n",
2750 vir_get_stage_name(c),
2751 c->program_id, c->variant_id);
2752 vir_dump(c);
2753 fprintf(stderr, "\n");
2754 }
2755
2756 /* Attempt to allocate registers for the temporaries. If we fail,
2757 * reduce thread count and try again.
2758 */
2759 int min_threads = (c->devinfo->ver >= 41) ? 2 : 1;
2760 struct qpu_reg *temp_registers;
2761 while (true) {
2762 bool spilled;
2763 temp_registers = v3d_register_allocate(c, &spilled);
2764 if (spilled)
2765 continue;
2766
2767 if (temp_registers)
2768 break;
2769
2770 if (c->threads == min_threads) {
2771 fprintf(stderr, "Failed to register allocate at %d threads:\n",
2772 c->threads);
2773 vir_dump(c);
2774 c->failed = true;
2775 return;
2776 }
2777
2778 c->threads /= 2;
2779
2780 if (c->threads == 1)
2781 vir_remove_thrsw(c);
2782 }
2783
2784 if (c->spills &&
2785 (V3D_DEBUG & (V3D_DEBUG_VIR |
2786 v3d_debug_flag_for_shader_stage(c->s->info.stage)))) {
2787 fprintf(stderr, "%s prog %d/%d spilled VIR:\n",
2788 vir_get_stage_name(c),
2789 c->program_id, c->variant_id);
2790 vir_dump(c);
2791 fprintf(stderr, "\n");
2792 }
2793
2794 v3d_vir_to_qpu(c, temp_registers);
2795 }