vc4: Enable PIPE_CAP_TGSI_TEXCOORD.
[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/format/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
34
35 /* We don't do any address packing. */
36 #define __gen_user_data void
37 #define __gen_address_type uint32_t
38 #define __gen_address_offset(reloc) (*reloc)
39 #define __gen_emit_reloc(cl, reloc)
40 #include "cle/v3d_packet_v41_pack.h"
41
42 #define GENERAL_TMU_LOOKUP_PER_QUAD (0 << 7)
43 #define GENERAL_TMU_LOOKUP_PER_PIXEL (1 << 7)
44 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_I (0 << 0)
45 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_I (1 << 0)
46 #define GENERAL_TMU_LOOKUP_TYPE_VEC2 (2 << 0)
47 #define GENERAL_TMU_LOOKUP_TYPE_VEC3 (3 << 0)
48 #define GENERAL_TMU_LOOKUP_TYPE_VEC4 (4 << 0)
49 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_UI (5 << 0)
50 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_UI (6 << 0)
51 #define GENERAL_TMU_LOOKUP_TYPE_32BIT_UI (7 << 0)
52
53 #define V3D_TSY_SET_QUORUM 0
54 #define V3D_TSY_INC_WAITERS 1
55 #define V3D_TSY_DEC_WAITERS 2
56 #define V3D_TSY_INC_QUORUM 3
57 #define V3D_TSY_DEC_QUORUM 4
58 #define V3D_TSY_FREE_ALL 5
59 #define V3D_TSY_RELEASE 6
60 #define V3D_TSY_ACQUIRE 7
61 #define V3D_TSY_WAIT 8
62 #define V3D_TSY_WAIT_INC 9
63 #define V3D_TSY_WAIT_CHECK 10
64 #define V3D_TSY_WAIT_INC_CHECK 11
65 #define V3D_TSY_WAIT_CV 12
66 #define V3D_TSY_INC_SEMAPHORE 13
67 #define V3D_TSY_DEC_SEMAPHORE 14
68 #define V3D_TSY_SET_QUORUM_FREE_ALL 15
69
70 static void
71 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
72
73 static void
74 resize_qreg_array(struct v3d_compile *c,
75 struct qreg **regs,
76 uint32_t *size,
77 uint32_t decl_size)
78 {
79 if (*size >= decl_size)
80 return;
81
82 uint32_t old_size = *size;
83 *size = MAX2(*size * 2, decl_size);
84 *regs = reralloc(c, *regs, struct qreg, *size);
85 if (!*regs) {
86 fprintf(stderr, "Malloc failure\n");
87 abort();
88 }
89
90 for (uint32_t i = old_size; i < *size; i++)
91 (*regs)[i] = c->undef;
92 }
93
94 void
95 vir_emit_thrsw(struct v3d_compile *c)
96 {
97 if (c->threads == 1)
98 return;
99
100 /* Always thread switch after each texture operation for now.
101 *
102 * We could do better by batching a bunch of texture fetches up and
103 * then doing one thread switch and collecting all their results
104 * afterward.
105 */
106 c->last_thrsw = vir_NOP(c);
107 c->last_thrsw->qpu.sig.thrsw = true;
108 c->last_thrsw_at_top_level = !c->in_control_flow;
109
110 /* We need to lock the scoreboard before any tlb acess happens. If this
111 * thread switch comes after we have emitted a tlb load, then it means
112 * that we can't lock on the last thread switch any more.
113 */
114 if (c->emitted_tlb_load)
115 c->lock_scoreboard_on_first_thrsw = true;
116 }
117
118 uint32_t
119 v3d_get_op_for_atomic_add(nir_intrinsic_instr *instr, unsigned src)
120 {
121 if (nir_src_is_const(instr->src[src])) {
122 int64_t add_val = nir_src_as_int(instr->src[src]);
123 if (add_val == 1)
124 return V3D_TMU_OP_WRITE_AND_READ_INC;
125 else if (add_val == -1)
126 return V3D_TMU_OP_WRITE_OR_READ_DEC;
127 }
128
129 return V3D_TMU_OP_WRITE_ADD_READ_PREFETCH;
130 }
131
132 static uint32_t
133 v3d_general_tmu_op(nir_intrinsic_instr *instr)
134 {
135 switch (instr->intrinsic) {
136 case nir_intrinsic_load_ssbo:
137 case nir_intrinsic_load_ubo:
138 case nir_intrinsic_load_uniform:
139 case nir_intrinsic_load_shared:
140 case nir_intrinsic_load_scratch:
141 case nir_intrinsic_store_ssbo:
142 case nir_intrinsic_store_shared:
143 case nir_intrinsic_store_scratch:
144 return V3D_TMU_OP_REGULAR;
145 case nir_intrinsic_ssbo_atomic_add:
146 return v3d_get_op_for_atomic_add(instr, 2);
147 case nir_intrinsic_shared_atomic_add:
148 return v3d_get_op_for_atomic_add(instr, 1);
149 case nir_intrinsic_ssbo_atomic_imin:
150 case nir_intrinsic_shared_atomic_imin:
151 return V3D_TMU_OP_WRITE_SMIN;
152 case nir_intrinsic_ssbo_atomic_umin:
153 case nir_intrinsic_shared_atomic_umin:
154 return V3D_TMU_OP_WRITE_UMIN_FULL_L1_CLEAR;
155 case nir_intrinsic_ssbo_atomic_imax:
156 case nir_intrinsic_shared_atomic_imax:
157 return V3D_TMU_OP_WRITE_SMAX;
158 case nir_intrinsic_ssbo_atomic_umax:
159 case nir_intrinsic_shared_atomic_umax:
160 return V3D_TMU_OP_WRITE_UMAX;
161 case nir_intrinsic_ssbo_atomic_and:
162 case nir_intrinsic_shared_atomic_and:
163 return V3D_TMU_OP_WRITE_AND_READ_INC;
164 case nir_intrinsic_ssbo_atomic_or:
165 case nir_intrinsic_shared_atomic_or:
166 return V3D_TMU_OP_WRITE_OR_READ_DEC;
167 case nir_intrinsic_ssbo_atomic_xor:
168 case nir_intrinsic_shared_atomic_xor:
169 return V3D_TMU_OP_WRITE_XOR_READ_NOT;
170 case nir_intrinsic_ssbo_atomic_exchange:
171 case nir_intrinsic_shared_atomic_exchange:
172 return V3D_TMU_OP_WRITE_XCHG_READ_FLUSH;
173 case nir_intrinsic_ssbo_atomic_comp_swap:
174 case nir_intrinsic_shared_atomic_comp_swap:
175 return V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH;
176 default:
177 unreachable("unknown intrinsic op");
178 }
179 }
180
181 /**
182 * Implements indirect uniform loads and SSBO accesses through the TMU general
183 * memory access interface.
184 */
185 static void
186 ntq_emit_tmu_general(struct v3d_compile *c, nir_intrinsic_instr *instr,
187 bool is_shared_or_scratch)
188 {
189 uint32_t tmu_op = v3d_general_tmu_op(instr);
190
191 /* If we were able to replace atomic_add for an inc/dec, then we
192 * need/can to do things slightly different, like not loading the
193 * amount to add/sub, as that is implicit.
194 */
195 bool atomic_add_replaced =
196 ((instr->intrinsic == nir_intrinsic_ssbo_atomic_add ||
197 instr->intrinsic == nir_intrinsic_shared_atomic_add) &&
198 (tmu_op == V3D_TMU_OP_WRITE_AND_READ_INC ||
199 tmu_op == V3D_TMU_OP_WRITE_OR_READ_DEC));
200
201 bool is_store = (instr->intrinsic == nir_intrinsic_store_ssbo ||
202 instr->intrinsic == nir_intrinsic_store_scratch ||
203 instr->intrinsic == nir_intrinsic_store_shared);
204
205 bool is_load = (instr->intrinsic == nir_intrinsic_load_uniform ||
206 instr->intrinsic == nir_intrinsic_load_ubo ||
207 instr->intrinsic == nir_intrinsic_load_ssbo ||
208 instr->intrinsic == nir_intrinsic_load_scratch ||
209 instr->intrinsic == nir_intrinsic_load_shared);
210
211 if (!is_load)
212 c->tmu_dirty_rcl = true;
213
214 bool has_index = !is_shared_or_scratch;
215
216 int offset_src;
217 if (instr->intrinsic == nir_intrinsic_load_uniform) {
218 offset_src = 0;
219 } else if (instr->intrinsic == nir_intrinsic_load_ssbo ||
220 instr->intrinsic == nir_intrinsic_load_ubo ||
221 instr->intrinsic == nir_intrinsic_load_scratch ||
222 instr->intrinsic == nir_intrinsic_load_shared ||
223 atomic_add_replaced) {
224 offset_src = 0 + has_index;
225 } else if (is_store) {
226 offset_src = 1 + has_index;
227 } else {
228 offset_src = 0 + has_index;
229 }
230
231 bool dynamic_src = !nir_src_is_const(instr->src[offset_src]);
232 uint32_t const_offset = 0;
233 if (!dynamic_src)
234 const_offset = nir_src_as_uint(instr->src[offset_src]);
235
236 struct qreg base_offset;
237 if (instr->intrinsic == nir_intrinsic_load_uniform) {
238 const_offset += nir_intrinsic_base(instr);
239 base_offset = vir_uniform(c, QUNIFORM_UBO_ADDR,
240 v3d_unit_data_create(0, const_offset));
241 const_offset = 0;
242 } else if (instr->intrinsic == nir_intrinsic_load_ubo) {
243 uint32_t index = nir_src_as_uint(instr->src[0]) + 1;
244 /* Note that QUNIFORM_UBO_ADDR takes a UBO index shifted up by
245 * 1 (0 is gallium's constant buffer 0).
246 */
247 base_offset =
248 vir_uniform(c, QUNIFORM_UBO_ADDR,
249 v3d_unit_data_create(index, const_offset));
250 const_offset = 0;
251 } else if (is_shared_or_scratch) {
252 /* Shared and scratch variables have no buffer index, and all
253 * start from a common base that we set up at the start of
254 * dispatch.
255 */
256 if (instr->intrinsic == nir_intrinsic_load_scratch ||
257 instr->intrinsic == nir_intrinsic_store_scratch) {
258 base_offset = c->spill_base;
259 } else {
260 base_offset = c->cs_shared_offset;
261 const_offset += nir_intrinsic_base(instr);
262 }
263 } else {
264 base_offset = vir_uniform(c, QUNIFORM_SSBO_OFFSET,
265 nir_src_as_uint(instr->src[is_store ?
266 1 : 0]));
267 }
268
269 struct qreg tmud = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD);
270 unsigned writemask = is_store ? nir_intrinsic_write_mask(instr) : 0;
271 uint32_t base_const_offset = const_offset;
272 int first_component = -1;
273 int last_component = -1;
274 do {
275 int tmu_writes = 1; /* address */
276
277 if (is_store) {
278 /* Find the first set of consecutive components that
279 * are enabled in the writemask and emit the TMUD
280 * instructions for them.
281 */
282 first_component = ffs(writemask) - 1;
283 last_component = first_component;
284 while (writemask & BITFIELD_BIT(last_component + 1))
285 last_component++;
286
287 assert(first_component >= 0 &&
288 first_component <= last_component &&
289 last_component < instr->num_components);
290
291 struct qreg tmud = vir_reg(QFILE_MAGIC,
292 V3D_QPU_WADDR_TMUD);
293 for (int i = first_component; i <= last_component; i++) {
294 struct qreg data =
295 ntq_get_src(c, instr->src[0], i);
296 vir_MOV_dest(c, tmud, data);
297 tmu_writes++;
298 }
299
300 /* Update the offset for the TMU write based on the
301 * the first component we are writing.
302 */
303 const_offset = base_const_offset + first_component * 4;
304
305 /* Clear these components from the writemask */
306 uint32_t written_mask =
307 BITFIELD_RANGE(first_component, tmu_writes - 1);
308 writemask &= ~written_mask;
309 } else if (!is_load && !atomic_add_replaced) {
310 struct qreg data =
311 ntq_get_src(c, instr->src[1 + has_index], 0);
312 vir_MOV_dest(c, tmud, data);
313 tmu_writes++;
314 if (tmu_op == V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH) {
315 data = ntq_get_src(c, instr->src[2 + has_index],
316 0);
317 vir_MOV_dest(c, tmud, data);
318 tmu_writes++;
319 }
320 }
321
322 /* Make sure we won't exceed the 16-entry TMU fifo if each
323 * thread is storing at the same time.
324 */
325 while (tmu_writes > 16 / c->threads)
326 c->threads /= 2;
327
328 /* The spec says that for atomics, the TYPE field is ignored,
329 * but that doesn't seem to be the case for CMPXCHG. Just use
330 * the number of tmud writes we did to decide the type (or
331 * choose "32bit" for atomic reads, which has been fine).
332 */
333 uint32_t num_components;
334 if (is_load || atomic_add_replaced) {
335 num_components = instr->num_components;
336 } else {
337 assert(tmu_writes > 1);
338 num_components = tmu_writes - 1;
339 }
340
341 uint32_t config = (0xffffff00 |
342 tmu_op << 3|
343 GENERAL_TMU_LOOKUP_PER_PIXEL);
344 if (num_components == 1) {
345 config |= GENERAL_TMU_LOOKUP_TYPE_32BIT_UI;
346 } else {
347 config |= GENERAL_TMU_LOOKUP_TYPE_VEC2 +
348 num_components - 2;
349 }
350
351 if (vir_in_nonuniform_control_flow(c)) {
352 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
353 V3D_QPU_PF_PUSHZ);
354 }
355
356 struct qreg tmua;
357 if (config == ~0)
358 tmua = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA);
359 else
360 tmua = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUAU);
361
362 struct qinst *tmu;
363 if (dynamic_src) {
364 struct qreg offset = base_offset;
365 if (const_offset != 0) {
366 offset = vir_ADD(c, offset,
367 vir_uniform_ui(c, const_offset));
368 }
369 struct qreg data =
370 ntq_get_src(c, instr->src[offset_src], 0);
371 tmu = vir_ADD_dest(c, tmua, offset, data);
372 } else {
373 if (const_offset != 0) {
374 tmu = vir_ADD_dest(c, tmua, base_offset,
375 vir_uniform_ui(c, const_offset));
376 } else {
377 tmu = vir_MOV_dest(c, tmua, base_offset);
378 }
379 }
380
381 if (config != ~0) {
382 tmu->uniform =
383 vir_get_uniform_index(c, QUNIFORM_CONSTANT,
384 config);
385 }
386
387 if (vir_in_nonuniform_control_flow(c))
388 vir_set_cond(tmu, V3D_QPU_COND_IFA);
389
390 vir_emit_thrsw(c);
391
392 /* Read the result, or wait for the TMU op to complete. */
393 for (int i = 0; i < nir_intrinsic_dest_components(instr); i++) {
394 ntq_store_dest(c, &instr->dest, i,
395 vir_MOV(c, vir_LDTMU(c)));
396 }
397
398 if (nir_intrinsic_dest_components(instr) == 0)
399 vir_TMUWT(c);
400 } while (is_store && writemask != 0);
401 }
402
403 static struct qreg *
404 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
405 {
406 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
407 def->num_components);
408 _mesa_hash_table_insert(c->def_ht, def, qregs);
409 return qregs;
410 }
411
412 static bool
413 is_ld_signal(const struct v3d_qpu_sig *sig)
414 {
415 return (sig->ldunif ||
416 sig->ldunifa ||
417 sig->ldunifrf ||
418 sig->ldunifarf ||
419 sig->ldtmu ||
420 sig->ldvary ||
421 sig->ldvpm ||
422 sig->ldtlb ||
423 sig->ldtlbu);
424 }
425
426 /**
427 * This function is responsible for getting VIR results into the associated
428 * storage for a NIR instruction.
429 *
430 * If it's a NIR SSA def, then we just set the associated hash table entry to
431 * the new result.
432 *
433 * If it's a NIR reg, then we need to update the existing qreg assigned to the
434 * NIR destination with the incoming value. To do that without introducing
435 * new MOVs, we require that the incoming qreg either be a uniform, or be
436 * SSA-defined by the previous VIR instruction in the block and rewritable by
437 * this function. That lets us sneak ahead and insert the SF flag beforehand
438 * (knowing that the previous instruction doesn't depend on flags) and rewrite
439 * its destination to be the NIR reg's destination
440 */
441 void
442 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
443 struct qreg result)
444 {
445 struct qinst *last_inst = NULL;
446 if (!list_is_empty(&c->cur_block->instructions))
447 last_inst = (struct qinst *)c->cur_block->instructions.prev;
448
449 assert((result.file == QFILE_TEMP &&
450 last_inst && last_inst == c->defs[result.index]));
451
452 if (dest->is_ssa) {
453 assert(chan < dest->ssa.num_components);
454
455 struct qreg *qregs;
456 struct hash_entry *entry =
457 _mesa_hash_table_search(c->def_ht, &dest->ssa);
458
459 if (entry)
460 qregs = entry->data;
461 else
462 qregs = ntq_init_ssa_def(c, &dest->ssa);
463
464 qregs[chan] = result;
465 } else {
466 nir_register *reg = dest->reg.reg;
467 assert(dest->reg.base_offset == 0);
468 assert(reg->num_array_elems == 0);
469 struct hash_entry *entry =
470 _mesa_hash_table_search(c->def_ht, reg);
471 struct qreg *qregs = entry->data;
472
473 /* If the previous instruction can't be predicated for
474 * the store into the nir_register, then emit a MOV
475 * that can be.
476 */
477 if (vir_in_nonuniform_control_flow(c) &&
478 is_ld_signal(&c->defs[last_inst->dst.index]->qpu.sig)) {
479 result = vir_MOV(c, result);
480 last_inst = c->defs[result.index];
481 }
482
483 /* We know they're both temps, so just rewrite index. */
484 c->defs[last_inst->dst.index] = NULL;
485 last_inst->dst.index = qregs[chan].index;
486
487 /* If we're in control flow, then make this update of the reg
488 * conditional on the execution mask.
489 */
490 if (vir_in_nonuniform_control_flow(c)) {
491 last_inst->dst.index = qregs[chan].index;
492
493 /* Set the flags to the current exec mask.
494 */
495 c->cursor = vir_before_inst(last_inst);
496 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
497 V3D_QPU_PF_PUSHZ);
498 c->cursor = vir_after_inst(last_inst);
499
500 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
501 }
502 }
503 }
504
505 struct qreg
506 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
507 {
508 struct hash_entry *entry;
509 if (src.is_ssa) {
510 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
511 assert(i < src.ssa->num_components);
512 } else {
513 nir_register *reg = src.reg.reg;
514 entry = _mesa_hash_table_search(c->def_ht, reg);
515 assert(reg->num_array_elems == 0);
516 assert(src.reg.base_offset == 0);
517 assert(i < reg->num_components);
518 }
519
520 struct qreg *qregs = entry->data;
521 return qregs[i];
522 }
523
524 static struct qreg
525 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
526 unsigned src)
527 {
528 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
529 unsigned chan = ffs(instr->dest.write_mask) - 1;
530 struct qreg r = ntq_get_src(c, instr->src[src].src,
531 instr->src[src].swizzle[chan]);
532
533 assert(!instr->src[src].abs);
534 assert(!instr->src[src].negate);
535
536 return r;
537 };
538
539 static struct qreg
540 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
541 {
542 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
543 }
544
545 static void
546 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
547 {
548 unsigned unit = instr->texture_index;
549 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
550 int dest_size = nir_tex_instr_dest_size(instr);
551
552 struct qreg lod = c->undef;
553 if (lod_index != -1)
554 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
555
556 for (int i = 0; i < dest_size; i++) {
557 assert(i < 3);
558 enum quniform_contents contents;
559
560 if (instr->is_array && i == dest_size - 1)
561 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
562 else
563 contents = QUNIFORM_TEXTURE_WIDTH + i;
564
565 struct qreg size = vir_uniform(c, contents, unit);
566
567 switch (instr->sampler_dim) {
568 case GLSL_SAMPLER_DIM_1D:
569 case GLSL_SAMPLER_DIM_2D:
570 case GLSL_SAMPLER_DIM_MS:
571 case GLSL_SAMPLER_DIM_3D:
572 case GLSL_SAMPLER_DIM_CUBE:
573 /* Don't minify the array size. */
574 if (!(instr->is_array && i == dest_size - 1)) {
575 size = ntq_minify(c, size, lod);
576 }
577 break;
578
579 case GLSL_SAMPLER_DIM_RECT:
580 /* There's no LOD field for rects */
581 break;
582
583 default:
584 unreachable("Bad sampler type");
585 }
586
587 ntq_store_dest(c, &instr->dest, i, size);
588 }
589 }
590
591 static void
592 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
593 {
594 unsigned unit = instr->texture_index;
595
596 /* Since each texture sampling op requires uploading uniforms to
597 * reference the texture, there's no HW support for texture size and
598 * you just upload uniforms containing the size.
599 */
600 switch (instr->op) {
601 case nir_texop_query_levels:
602 ntq_store_dest(c, &instr->dest, 0,
603 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
604 return;
605 case nir_texop_txs:
606 ntq_emit_txs(c, instr);
607 return;
608 default:
609 break;
610 }
611
612 if (c->devinfo->ver >= 40)
613 v3d40_vir_emit_tex(c, instr);
614 else
615 v3d33_vir_emit_tex(c, instr);
616 }
617
618 static struct qreg
619 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
620 {
621 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
622 if (is_cos)
623 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
624
625 struct qreg periods = vir_FROUND(c, input);
626 struct qreg sin_output = vir_SIN(c, vir_FSUB(c, input, periods));
627 return vir_XOR(c, sin_output, vir_SHL(c,
628 vir_FTOIN(c, periods),
629 vir_uniform_ui(c, -1)));
630 }
631
632 static struct qreg
633 ntq_fsign(struct v3d_compile *c, struct qreg src)
634 {
635 struct qreg t = vir_get_temp(c);
636
637 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
638 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHZ);
639 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
640 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHN);
641 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
642 return vir_MOV(c, t);
643 }
644
645 static void
646 emit_fragcoord_input(struct v3d_compile *c, int attr)
647 {
648 c->inputs[attr * 4 + 0] = vir_FXCD(c);
649 c->inputs[attr * 4 + 1] = vir_FYCD(c);
650 c->inputs[attr * 4 + 2] = c->payload_z;
651 c->inputs[attr * 4 + 3] = vir_RECIP(c, c->payload_w);
652 }
653
654 static struct qreg
655 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
656 uint8_t swizzle, int array_index)
657 {
658 struct qreg r3 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R3);
659 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
660
661 struct qreg vary;
662 if (c->devinfo->ver >= 41) {
663 struct qinst *ldvary = vir_add_inst(V3D_QPU_A_NOP, c->undef,
664 c->undef, c->undef);
665 ldvary->qpu.sig.ldvary = true;
666 vary = vir_emit_def(c, ldvary);
667 } else {
668 vir_NOP(c)->qpu.sig.ldvary = true;
669 vary = r3;
670 }
671
672 /* For gl_PointCoord input or distance along a line, we'll be called
673 * with no nir_variable, and we don't count toward VPM size so we
674 * don't track an input slot.
675 */
676 if (!var) {
677 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
678 }
679
680 int i = c->num_inputs++;
681 c->input_slots[i] =
682 v3d_slot_from_slot_and_component(var->data.location +
683 array_index, swizzle);
684
685 switch (var->data.interpolation) {
686 case INTERP_MODE_NONE:
687 /* If a gl_FrontColor or gl_BackColor input has no interp
688 * qualifier, then if we're using glShadeModel(GL_FLAT) it
689 * needs to be flat shaded.
690 */
691 switch (var->data.location + array_index) {
692 case VARYING_SLOT_COL0:
693 case VARYING_SLOT_COL1:
694 case VARYING_SLOT_BFC0:
695 case VARYING_SLOT_BFC1:
696 if (c->fs_key->shade_model_flat) {
697 BITSET_SET(c->flat_shade_flags, i);
698 vir_MOV_dest(c, c->undef, vary);
699 return vir_MOV(c, r5);
700 } else {
701 return vir_FADD(c, vir_FMUL(c, vary,
702 c->payload_w), r5);
703 }
704 default:
705 break;
706 }
707 /* FALLTHROUGH */
708 case INTERP_MODE_SMOOTH:
709 if (var->data.centroid) {
710 BITSET_SET(c->centroid_flags, i);
711 return vir_FADD(c, vir_FMUL(c, vary,
712 c->payload_w_centroid), r5);
713 } else {
714 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
715 }
716 case INTERP_MODE_NOPERSPECTIVE:
717 BITSET_SET(c->noperspective_flags, i);
718 return vir_FADD(c, vir_MOV(c, vary), r5);
719 case INTERP_MODE_FLAT:
720 BITSET_SET(c->flat_shade_flags, i);
721 vir_MOV_dest(c, c->undef, vary);
722 return vir_MOV(c, r5);
723 default:
724 unreachable("Bad interp mode");
725 }
726 }
727
728 static void
729 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var,
730 int array_index)
731 {
732 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
733 int chan = var->data.location_frac + i;
734 c->inputs[attr * 4 + chan] =
735 emit_fragment_varying(c, var, chan, array_index);
736 }
737 }
738
739 static void
740 add_output(struct v3d_compile *c,
741 uint32_t decl_offset,
742 uint8_t slot,
743 uint8_t swizzle)
744 {
745 uint32_t old_array_size = c->outputs_array_size;
746 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
747 decl_offset + 1);
748
749 if (old_array_size != c->outputs_array_size) {
750 c->output_slots = reralloc(c,
751 c->output_slots,
752 struct v3d_varying_slot,
753 c->outputs_array_size);
754 }
755
756 c->output_slots[decl_offset] =
757 v3d_slot_from_slot_and_component(slot, swizzle);
758 }
759
760 /**
761 * If compare_instr is a valid comparison instruction, emits the
762 * compare_instr's comparison and returns the sel_instr's return value based
763 * on the compare_instr's result.
764 */
765 static bool
766 ntq_emit_comparison(struct v3d_compile *c,
767 nir_alu_instr *compare_instr,
768 enum v3d_qpu_cond *out_cond)
769 {
770 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
771 struct qreg src1;
772 if (nir_op_infos[compare_instr->op].num_inputs > 1)
773 src1 = ntq_get_alu_src(c, compare_instr, 1);
774 bool cond_invert = false;
775 struct qreg nop = vir_nop_reg();
776
777 switch (compare_instr->op) {
778 case nir_op_feq32:
779 case nir_op_seq:
780 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
781 break;
782 case nir_op_ieq32:
783 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
784 break;
785
786 case nir_op_fne32:
787 case nir_op_sne:
788 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
789 cond_invert = true;
790 break;
791 case nir_op_ine32:
792 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
793 cond_invert = true;
794 break;
795
796 case nir_op_fge32:
797 case nir_op_sge:
798 vir_set_pf(vir_FCMP_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
799 break;
800 case nir_op_ige32:
801 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
802 cond_invert = true;
803 break;
804 case nir_op_uge32:
805 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
806 cond_invert = true;
807 break;
808
809 case nir_op_slt:
810 case nir_op_flt32:
811 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHN);
812 break;
813 case nir_op_ilt32:
814 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
815 break;
816 case nir_op_ult32:
817 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
818 break;
819
820 case nir_op_i2b32:
821 vir_set_pf(vir_MOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ);
822 cond_invert = true;
823 break;
824
825 case nir_op_f2b32:
826 vir_set_pf(vir_FMOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ);
827 cond_invert = true;
828 break;
829
830 default:
831 return false;
832 }
833
834 *out_cond = cond_invert ? V3D_QPU_COND_IFNA : V3D_QPU_COND_IFA;
835
836 return true;
837 }
838
839 /* Finds an ALU instruction that generates our src value that could
840 * (potentially) be greedily emitted in the consuming instruction.
841 */
842 static struct nir_alu_instr *
843 ntq_get_alu_parent(nir_src src)
844 {
845 if (!src.is_ssa || src.ssa->parent_instr->type != nir_instr_type_alu)
846 return NULL;
847 nir_alu_instr *instr = nir_instr_as_alu(src.ssa->parent_instr);
848 if (!instr)
849 return NULL;
850
851 /* If the ALU instr's srcs are non-SSA, then we would have to avoid
852 * moving emission of the ALU instr down past another write of the
853 * src.
854 */
855 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
856 if (!instr->src[i].src.is_ssa)
857 return NULL;
858 }
859
860 return instr;
861 }
862
863 /* Turns a NIR bool into a condition code to predicate on. */
864 static enum v3d_qpu_cond
865 ntq_emit_bool_to_cond(struct v3d_compile *c, nir_src src)
866 {
867 nir_alu_instr *compare = ntq_get_alu_parent(src);
868 if (!compare)
869 goto out;
870
871 enum v3d_qpu_cond cond;
872 if (ntq_emit_comparison(c, compare, &cond))
873 return cond;
874
875 out:
876 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), ntq_get_src(c, src, 0)),
877 V3D_QPU_PF_PUSHZ);
878 return V3D_QPU_COND_IFNA;
879 }
880
881 static void
882 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
883 {
884 /* This should always be lowered to ALU operations for V3D. */
885 assert(!instr->dest.saturate);
886
887 /* Vectors are special in that they have non-scalarized writemasks,
888 * and just take the first swizzle channel for each argument in order
889 * into each writemask channel.
890 */
891 if (instr->op == nir_op_vec2 ||
892 instr->op == nir_op_vec3 ||
893 instr->op == nir_op_vec4) {
894 struct qreg srcs[4];
895 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
896 srcs[i] = ntq_get_src(c, instr->src[i].src,
897 instr->src[i].swizzle[0]);
898 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
899 ntq_store_dest(c, &instr->dest.dest, i,
900 vir_MOV(c, srcs[i]));
901 return;
902 }
903
904 /* General case: We can just grab the one used channel per src. */
905 struct qreg src[nir_op_infos[instr->op].num_inputs];
906 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
907 src[i] = ntq_get_alu_src(c, instr, i);
908 }
909
910 struct qreg result;
911
912 switch (instr->op) {
913 case nir_op_mov:
914 result = vir_MOV(c, src[0]);
915 break;
916
917 case nir_op_fneg:
918 result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
919 break;
920 case nir_op_ineg:
921 result = vir_NEG(c, src[0]);
922 break;
923
924 case nir_op_fmul:
925 result = vir_FMUL(c, src[0], src[1]);
926 break;
927 case nir_op_fadd:
928 result = vir_FADD(c, src[0], src[1]);
929 break;
930 case nir_op_fsub:
931 result = vir_FSUB(c, src[0], src[1]);
932 break;
933 case nir_op_fmin:
934 result = vir_FMIN(c, src[0], src[1]);
935 break;
936 case nir_op_fmax:
937 result = vir_FMAX(c, src[0], src[1]);
938 break;
939
940 case nir_op_f2i32: {
941 nir_alu_instr *src0_alu = ntq_get_alu_parent(instr->src[0].src);
942 if (src0_alu && src0_alu->op == nir_op_fround_even) {
943 result = vir_FTOIN(c, ntq_get_alu_src(c, src0_alu, 0));
944 } else {
945 result = vir_FTOIZ(c, src[0]);
946 }
947 break;
948 }
949
950 case nir_op_f2u32:
951 result = vir_FTOUZ(c, src[0]);
952 break;
953 case nir_op_i2f32:
954 result = vir_ITOF(c, src[0]);
955 break;
956 case nir_op_u2f32:
957 result = vir_UTOF(c, src[0]);
958 break;
959 case nir_op_b2f32:
960 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
961 break;
962 case nir_op_b2i32:
963 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
964 break;
965
966 case nir_op_iadd:
967 result = vir_ADD(c, src[0], src[1]);
968 break;
969 case nir_op_ushr:
970 result = vir_SHR(c, src[0], src[1]);
971 break;
972 case nir_op_isub:
973 result = vir_SUB(c, src[0], src[1]);
974 break;
975 case nir_op_ishr:
976 result = vir_ASR(c, src[0], src[1]);
977 break;
978 case nir_op_ishl:
979 result = vir_SHL(c, src[0], src[1]);
980 break;
981 case nir_op_imin:
982 result = vir_MIN(c, src[0], src[1]);
983 break;
984 case nir_op_umin:
985 result = vir_UMIN(c, src[0], src[1]);
986 break;
987 case nir_op_imax:
988 result = vir_MAX(c, src[0], src[1]);
989 break;
990 case nir_op_umax:
991 result = vir_UMAX(c, src[0], src[1]);
992 break;
993 case nir_op_iand:
994 result = vir_AND(c, src[0], src[1]);
995 break;
996 case nir_op_ior:
997 result = vir_OR(c, src[0], src[1]);
998 break;
999 case nir_op_ixor:
1000 result = vir_XOR(c, src[0], src[1]);
1001 break;
1002 case nir_op_inot:
1003 result = vir_NOT(c, src[0]);
1004 break;
1005
1006 case nir_op_ufind_msb:
1007 result = vir_SUB(c, vir_uniform_ui(c, 31), vir_CLZ(c, src[0]));
1008 break;
1009
1010 case nir_op_imul:
1011 result = vir_UMUL(c, src[0], src[1]);
1012 break;
1013
1014 case nir_op_seq:
1015 case nir_op_sne:
1016 case nir_op_sge:
1017 case nir_op_slt: {
1018 enum v3d_qpu_cond cond;
1019 ASSERTED bool ok = ntq_emit_comparison(c, instr, &cond);
1020 assert(ok);
1021 result = vir_MOV(c, vir_SEL(c, cond,
1022 vir_uniform_f(c, 1.0),
1023 vir_uniform_f(c, 0.0)));
1024 break;
1025 }
1026
1027 case nir_op_i2b32:
1028 case nir_op_f2b32:
1029 case nir_op_feq32:
1030 case nir_op_fne32:
1031 case nir_op_fge32:
1032 case nir_op_flt32:
1033 case nir_op_ieq32:
1034 case nir_op_ine32:
1035 case nir_op_ige32:
1036 case nir_op_uge32:
1037 case nir_op_ilt32:
1038 case nir_op_ult32: {
1039 enum v3d_qpu_cond cond;
1040 ASSERTED bool ok = ntq_emit_comparison(c, instr, &cond);
1041 assert(ok);
1042 result = vir_MOV(c, vir_SEL(c, cond,
1043 vir_uniform_ui(c, ~0),
1044 vir_uniform_ui(c, 0)));
1045 break;
1046 }
1047
1048 case nir_op_b32csel:
1049 result = vir_MOV(c,
1050 vir_SEL(c,
1051 ntq_emit_bool_to_cond(c, instr->src[0].src),
1052 src[1], src[2]));
1053 break;
1054
1055 case nir_op_fcsel:
1056 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), src[0]),
1057 V3D_QPU_PF_PUSHZ);
1058 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
1059 src[1], src[2]));
1060 break;
1061
1062 case nir_op_frcp:
1063 result = vir_RECIP(c, src[0]);
1064 break;
1065 case nir_op_frsq:
1066 result = vir_RSQRT(c, src[0]);
1067 break;
1068 case nir_op_fexp2:
1069 result = vir_EXP(c, src[0]);
1070 break;
1071 case nir_op_flog2:
1072 result = vir_LOG(c, src[0]);
1073 break;
1074
1075 case nir_op_fceil:
1076 result = vir_FCEIL(c, src[0]);
1077 break;
1078 case nir_op_ffloor:
1079 result = vir_FFLOOR(c, src[0]);
1080 break;
1081 case nir_op_fround_even:
1082 result = vir_FROUND(c, src[0]);
1083 break;
1084 case nir_op_ftrunc:
1085 result = vir_FTRUNC(c, src[0]);
1086 break;
1087
1088 case nir_op_fsin:
1089 result = ntq_fsincos(c, src[0], false);
1090 break;
1091 case nir_op_fcos:
1092 result = ntq_fsincos(c, src[0], true);
1093 break;
1094
1095 case nir_op_fsign:
1096 result = ntq_fsign(c, src[0]);
1097 break;
1098
1099 case nir_op_fabs: {
1100 result = vir_FMOV(c, src[0]);
1101 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
1102 break;
1103 }
1104
1105 case nir_op_iabs:
1106 result = vir_MAX(c, src[0], vir_NEG(c, src[0]));
1107 break;
1108
1109 case nir_op_fddx:
1110 case nir_op_fddx_coarse:
1111 case nir_op_fddx_fine:
1112 result = vir_FDX(c, src[0]);
1113 break;
1114
1115 case nir_op_fddy:
1116 case nir_op_fddy_coarse:
1117 case nir_op_fddy_fine:
1118 result = vir_FDY(c, src[0]);
1119 break;
1120
1121 case nir_op_uadd_carry:
1122 vir_set_pf(vir_ADD_dest(c, vir_nop_reg(), src[0], src[1]),
1123 V3D_QPU_PF_PUSHC);
1124 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1125 vir_uniform_ui(c, ~0),
1126 vir_uniform_ui(c, 0)));
1127 break;
1128
1129 case nir_op_pack_half_2x16_split:
1130 result = vir_VFPACK(c, src[0], src[1]);
1131 break;
1132
1133 case nir_op_unpack_half_2x16_split_x:
1134 result = vir_FMOV(c, src[0]);
1135 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_L);
1136 break;
1137
1138 case nir_op_unpack_half_2x16_split_y:
1139 result = vir_FMOV(c, src[0]);
1140 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_H);
1141 break;
1142
1143 default:
1144 fprintf(stderr, "unknown NIR ALU inst: ");
1145 nir_print_instr(&instr->instr, stderr);
1146 fprintf(stderr, "\n");
1147 abort();
1148 }
1149
1150 /* We have a scalar result, so the instruction should only have a
1151 * single channel written to.
1152 */
1153 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
1154 ntq_store_dest(c, &instr->dest.dest,
1155 ffs(instr->dest.write_mask) - 1, result);
1156 }
1157
1158 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
1159 * specifier. They come from a register that's preloaded with 0xffffffff
1160 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
1161 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
1162 */
1163 #define TLB_TYPE_F16_COLOR (3 << 6)
1164 #define TLB_TYPE_I32_COLOR (1 << 6)
1165 #define TLB_TYPE_F32_COLOR (0 << 6)
1166 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
1167 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
1168 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
1169 #define TLB_F16_SWAP_HI_LO (1 << 1)
1170 #define TLB_VEC_SIZE_4_F16 (1 << 0)
1171 #define TLB_VEC_SIZE_2_F16 (0 << 0)
1172 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
1173
1174 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
1175 * flag is set.
1176 */
1177 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
1178 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
1179 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
1180 #define TLB_V42_DEPTH_TYPE_INVARIANT (0 << 3) /* Unmodified sideband input used */
1181 #define TLB_V42_DEPTH_TYPE_PER_PIXEL (1 << 3) /* QPU result used */
1182
1183 /* Stencil is a single 32-bit write. */
1184 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1185
1186 static void
1187 vir_emit_tlb_color_write(struct v3d_compile *c, unsigned rt)
1188 {
1189 if (!(c->fs_key->cbufs & (1 << rt)) || !c->output_color_var[rt])
1190 return;
1191
1192 struct qreg tlb_reg = vir_magic_reg(V3D_QPU_WADDR_TLB);
1193 struct qreg tlbu_reg = vir_magic_reg(V3D_QPU_WADDR_TLBU);
1194
1195 nir_variable *var = c->output_color_var[rt];
1196 int num_components = glsl_get_vector_elements(var->type);
1197 uint32_t conf = 0xffffff00;
1198 struct qinst *inst;
1199
1200 conf |= c->msaa_per_sample_output ? TLB_SAMPLE_MODE_PER_SAMPLE :
1201 TLB_SAMPLE_MODE_PER_PIXEL;
1202 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1203
1204 if (c->fs_key->swap_color_rb & (1 << rt))
1205 num_components = MAX2(num_components, 3);
1206 assert(num_components != 0);
1207
1208 enum glsl_base_type type = glsl_get_base_type(var->type);
1209 bool is_int_format = type == GLSL_TYPE_INT || type == GLSL_TYPE_UINT;
1210 bool is_32b_tlb_format = is_int_format ||
1211 (c->fs_key->f32_color_rb & (1 << rt));
1212
1213 if (is_int_format) {
1214 /* The F32 vs I32 distinction was dropped in 4.2. */
1215 if (c->devinfo->ver < 42)
1216 conf |= TLB_TYPE_I32_COLOR;
1217 else
1218 conf |= TLB_TYPE_F32_COLOR;
1219 conf |= ((num_components - 1) << TLB_VEC_SIZE_MINUS_1_SHIFT);
1220 } else {
1221 if (c->fs_key->f32_color_rb & (1 << rt)) {
1222 conf |= TLB_TYPE_F32_COLOR;
1223 conf |= ((num_components - 1) <<
1224 TLB_VEC_SIZE_MINUS_1_SHIFT);
1225 } else {
1226 conf |= TLB_TYPE_F16_COLOR;
1227 conf |= TLB_F16_SWAP_HI_LO;
1228 if (num_components >= 3)
1229 conf |= TLB_VEC_SIZE_4_F16;
1230 else
1231 conf |= TLB_VEC_SIZE_2_F16;
1232 }
1233 }
1234
1235 int num_samples = c->msaa_per_sample_output ? V3D_MAX_SAMPLES : 1;
1236 for (int i = 0; i < num_samples; i++) {
1237 struct qreg *color = c->msaa_per_sample_output ?
1238 &c->sample_colors[(rt * V3D_MAX_SAMPLES + i) * 4] :
1239 &c->outputs[var->data.driver_location * 4];
1240
1241 struct qreg r = color[0];
1242 struct qreg g = color[1];
1243 struct qreg b = color[2];
1244 struct qreg a = color[3];
1245
1246 if (c->fs_key->swap_color_rb & (1 << rt)) {
1247 r = color[2];
1248 b = color[0];
1249 }
1250
1251 if (c->fs_key->sample_alpha_to_one)
1252 a = vir_uniform_f(c, 1.0);
1253
1254 if (is_32b_tlb_format) {
1255 if (i == 0) {
1256 inst = vir_MOV_dest(c, tlbu_reg, r);
1257 inst->uniform =
1258 vir_get_uniform_index(c,
1259 QUNIFORM_CONSTANT,
1260 conf);
1261 } else {
1262 inst = vir_MOV_dest(c, tlb_reg, r);
1263 }
1264
1265 if (num_components >= 2)
1266 vir_MOV_dest(c, tlb_reg, g);
1267 if (num_components >= 3)
1268 vir_MOV_dest(c, tlb_reg, b);
1269 if (num_components >= 4)
1270 vir_MOV_dest(c, tlb_reg, a);
1271 } else {
1272 inst = vir_VFPACK_dest(c, tlb_reg, r, g);
1273 if (conf != ~0 && i == 0) {
1274 inst->dst = tlbu_reg;
1275 inst->uniform =
1276 vir_get_uniform_index(c,
1277 QUNIFORM_CONSTANT,
1278 conf);
1279 }
1280
1281 if (num_components >= 3)
1282 inst = vir_VFPACK_dest(c, tlb_reg, b, a);
1283 }
1284 }
1285 }
1286
1287 static void
1288 emit_frag_end(struct v3d_compile *c)
1289 {
1290 /* XXX
1291 if (c->output_sample_mask_index != -1) {
1292 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1293 }
1294 */
1295
1296 bool has_any_tlb_color_write = false;
1297 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1298 if (c->fs_key->cbufs & (1 << rt) && c->output_color_var[rt])
1299 has_any_tlb_color_write = true;
1300 }
1301
1302 if (c->fs_key->sample_alpha_to_coverage && c->output_color_var[0]) {
1303 struct nir_variable *var = c->output_color_var[0];
1304 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1305
1306 vir_SETMSF_dest(c, vir_nop_reg(),
1307 vir_AND(c,
1308 vir_MSF(c),
1309 vir_FTOC(c, color[3])));
1310 }
1311
1312 struct qreg tlbu_reg = vir_magic_reg(V3D_QPU_WADDR_TLBU);
1313 if (c->output_position_index != -1) {
1314 struct qinst *inst = vir_MOV_dest(c, tlbu_reg,
1315 c->outputs[c->output_position_index]);
1316 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1317
1318 if (c->devinfo->ver >= 42) {
1319 tlb_specifier |= (TLB_V42_DEPTH_TYPE_PER_PIXEL |
1320 TLB_SAMPLE_MODE_PER_PIXEL);
1321 } else
1322 tlb_specifier |= TLB_DEPTH_TYPE_PER_PIXEL;
1323
1324 inst->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT,
1325 tlb_specifier |
1326 0xffffff00);
1327 c->writes_z = true;
1328 } else if (c->s->info.fs.uses_discard ||
1329 !c->s->info.fs.early_fragment_tests ||
1330 c->fs_key->sample_alpha_to_coverage ||
1331 !has_any_tlb_color_write) {
1332 /* Emit passthrough Z if it needed to be delayed until shader
1333 * end due to potential discards.
1334 *
1335 * Since (single-threaded) fragment shaders always need a TLB
1336 * write, emit passthrouh Z if we didn't have any color
1337 * buffers and flag us as potentially discarding, so that we
1338 * can use Z as the TLB write.
1339 */
1340 c->s->info.fs.uses_discard = true;
1341
1342 struct qinst *inst = vir_MOV_dest(c, tlbu_reg,
1343 vir_nop_reg());
1344 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1345
1346 if (c->devinfo->ver >= 42) {
1347 /* The spec says the PER_PIXEL flag is ignored for
1348 * invariant writes, but the simulator demands it.
1349 */
1350 tlb_specifier |= (TLB_V42_DEPTH_TYPE_INVARIANT |
1351 TLB_SAMPLE_MODE_PER_PIXEL);
1352 } else {
1353 tlb_specifier |= TLB_DEPTH_TYPE_INVARIANT;
1354 }
1355
1356 inst->uniform = vir_get_uniform_index(c,
1357 QUNIFORM_CONSTANT,
1358 tlb_specifier |
1359 0xffffff00);
1360 c->writes_z = true;
1361 }
1362
1363 /* XXX: Performance improvement: Merge Z write and color writes TLB
1364 * uniform setup
1365 */
1366 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++)
1367 vir_emit_tlb_color_write(c, rt);
1368 }
1369
1370 static inline void
1371 vir_VPM_WRITE_indirect(struct v3d_compile *c,
1372 struct qreg val,
1373 struct qreg vpm_index)
1374 {
1375 assert(c->devinfo->ver >= 40);
1376 vir_STVPMV(c, vpm_index, val);
1377 }
1378
1379 static void
1380 vir_VPM_WRITE(struct v3d_compile *c, struct qreg val, uint32_t vpm_index)
1381 {
1382 if (c->devinfo->ver >= 40) {
1383 vir_VPM_WRITE_indirect(c, val, vir_uniform_ui(c, vpm_index));
1384 } else {
1385 /* XXX: v3d33_vir_vpm_write_setup(c); */
1386 vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM), val);
1387 }
1388 }
1389
1390 static void
1391 emit_vert_end(struct v3d_compile *c)
1392 {
1393 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1394 */
1395 if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
1396 vir_VPMWT(c);
1397 }
1398
1399 static void
1400 emit_geom_end(struct v3d_compile *c)
1401 {
1402 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1403 */
1404 if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
1405 vir_VPMWT(c);
1406 }
1407
1408 void
1409 v3d_optimize_nir(struct nir_shader *s)
1410 {
1411 bool progress;
1412 unsigned lower_flrp =
1413 (s->options->lower_flrp16 ? 16 : 0) |
1414 (s->options->lower_flrp32 ? 32 : 0) |
1415 (s->options->lower_flrp64 ? 64 : 0);
1416
1417 do {
1418 progress = false;
1419
1420 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1421 NIR_PASS(progress, s, nir_lower_alu_to_scalar, NULL, NULL);
1422 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1423 NIR_PASS(progress, s, nir_copy_prop);
1424 NIR_PASS(progress, s, nir_opt_remove_phis);
1425 NIR_PASS(progress, s, nir_opt_dce);
1426 NIR_PASS(progress, s, nir_opt_dead_cf);
1427 NIR_PASS(progress, s, nir_opt_cse);
1428 NIR_PASS(progress, s, nir_opt_peephole_select, 8, true, true);
1429 NIR_PASS(progress, s, nir_opt_algebraic);
1430 NIR_PASS(progress, s, nir_opt_constant_folding);
1431
1432 if (lower_flrp != 0) {
1433 bool lower_flrp_progress = false;
1434
1435 NIR_PASS(lower_flrp_progress, s, nir_lower_flrp,
1436 lower_flrp,
1437 false /* always_precise */,
1438 s->options->lower_ffma);
1439 if (lower_flrp_progress) {
1440 NIR_PASS(progress, s, nir_opt_constant_folding);
1441 progress = true;
1442 }
1443
1444 /* Nothing should rematerialize any flrps, so we only
1445 * need to do this lowering once.
1446 */
1447 lower_flrp = 0;
1448 }
1449
1450 NIR_PASS(progress, s, nir_opt_undef);
1451 } while (progress);
1452
1453 NIR_PASS(progress, s, nir_opt_move, nir_move_load_ubo);
1454 }
1455
1456 static int
1457 driver_location_compare(const void *in_a, const void *in_b)
1458 {
1459 const nir_variable *const *a = in_a;
1460 const nir_variable *const *b = in_b;
1461
1462 return (*a)->data.driver_location - (*b)->data.driver_location;
1463 }
1464
1465 static struct qreg
1466 ntq_emit_vpm_read(struct v3d_compile *c,
1467 uint32_t *num_components_queued,
1468 uint32_t *remaining,
1469 uint32_t vpm_index)
1470 {
1471 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1472
1473 if (c->devinfo->ver >= 40 ) {
1474 return vir_LDVPMV_IN(c,
1475 vir_uniform_ui(c,
1476 (*num_components_queued)++));
1477 }
1478
1479 if (*num_components_queued != 0) {
1480 (*num_components_queued)--;
1481 return vir_MOV(c, vpm);
1482 }
1483
1484 uint32_t num_components = MIN2(*remaining, 32);
1485
1486 v3d33_vir_vpm_read_setup(c, num_components);
1487
1488 *num_components_queued = num_components - 1;
1489 *remaining -= num_components;
1490
1491 return vir_MOV(c, vpm);
1492 }
1493
1494 static void
1495 ntq_setup_vs_inputs(struct v3d_compile *c)
1496 {
1497 /* Figure out how many components of each vertex attribute the shader
1498 * uses. Each variable should have been split to individual
1499 * components and unused ones DCEed. The vertex fetcher will load
1500 * from the start of the attribute to the number of components we
1501 * declare we need in c->vattr_sizes[].
1502 */
1503 nir_foreach_variable(var, &c->s->inputs) {
1504 /* No VS attribute array support. */
1505 assert(MAX2(glsl_get_length(var->type), 1) == 1);
1506
1507 unsigned loc = var->data.driver_location;
1508 int start_component = var->data.location_frac;
1509 int num_components = glsl_get_components(var->type);
1510
1511 c->vattr_sizes[loc] = MAX2(c->vattr_sizes[loc],
1512 start_component + num_components);
1513 }
1514
1515 unsigned num_components = 0;
1516 uint32_t vpm_components_queued = 0;
1517 bool uses_iid = c->s->info.system_values_read &
1518 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1519 bool uses_vid = c->s->info.system_values_read &
1520 (1ull << SYSTEM_VALUE_VERTEX_ID);
1521 num_components += uses_iid;
1522 num_components += uses_vid;
1523
1524 for (int i = 0; i < ARRAY_SIZE(c->vattr_sizes); i++)
1525 num_components += c->vattr_sizes[i];
1526
1527 if (uses_iid) {
1528 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1529 &num_components, ~0);
1530 }
1531
1532 if (uses_vid) {
1533 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1534 &num_components, ~0);
1535 }
1536
1537 /* The actual loads will happen directly in nir_intrinsic_load_input
1538 * on newer versions.
1539 */
1540 if (c->devinfo->ver >= 40)
1541 return;
1542
1543 for (int loc = 0; loc < ARRAY_SIZE(c->vattr_sizes); loc++) {
1544 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1545 (loc + 1) * 4);
1546
1547 for (int i = 0; i < c->vattr_sizes[loc]; i++) {
1548 c->inputs[loc * 4 + i] =
1549 ntq_emit_vpm_read(c,
1550 &vpm_components_queued,
1551 &num_components,
1552 loc * 4 + i);
1553
1554 }
1555 }
1556
1557 if (c->devinfo->ver >= 40) {
1558 assert(vpm_components_queued == num_components);
1559 } else {
1560 assert(vpm_components_queued == 0);
1561 assert(num_components == 0);
1562 }
1563 }
1564
1565 static bool
1566 var_needs_point_coord(struct v3d_compile *c, nir_variable *var)
1567 {
1568 return (var->data.location == VARYING_SLOT_PNTC ||
1569 (var->data.location >= VARYING_SLOT_VAR0 &&
1570 (c->fs_key->point_sprite_mask &
1571 (1 << (var->data.location - VARYING_SLOT_VAR0)))));
1572 }
1573
1574 static bool
1575 program_reads_point_coord(struct v3d_compile *c)
1576 {
1577 nir_foreach_variable(var, &c->s->inputs) {
1578 if (var_needs_point_coord(c, var))
1579 return true;
1580 }
1581
1582 return false;
1583 }
1584
1585 static void
1586 get_sorted_input_variables(struct v3d_compile *c,
1587 unsigned *num_entries,
1588 nir_variable ***vars)
1589 {
1590 *num_entries = 0;
1591 nir_foreach_variable(var, &c->s->inputs)
1592 (*num_entries)++;
1593
1594 *vars = ralloc_array(c, nir_variable *, *num_entries);
1595
1596 unsigned i = 0;
1597 nir_foreach_variable(var, &c->s->inputs)
1598 (*vars)[i++] = var;
1599
1600 /* Sort the variables so that we emit the input setup in
1601 * driver_location order. This is required for VPM reads, whose data
1602 * is fetched into the VPM in driver_location (TGSI register index)
1603 * order.
1604 */
1605 qsort(*vars, *num_entries, sizeof(**vars), driver_location_compare);
1606 }
1607
1608 static void
1609 ntq_setup_gs_inputs(struct v3d_compile *c)
1610 {
1611 nir_variable **vars;
1612 unsigned num_entries;
1613 get_sorted_input_variables(c, &num_entries, &vars);
1614
1615 for (unsigned i = 0; i < num_entries; i++) {
1616 nir_variable *var = vars[i];
1617
1618 /* All GS inputs are arrays with as many entries as vertices
1619 * in the input primitive, but here we only care about the
1620 * per-vertex input type.
1621 */
1622 const struct glsl_type *type = glsl_without_array(var->type);
1623 unsigned array_len = MAX2(glsl_get_length(type), 1);
1624 unsigned loc = var->data.driver_location;
1625
1626 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1627 (loc + array_len) * 4);
1628
1629 for (unsigned j = 0; j < array_len; j++) {
1630 unsigned num_elements = glsl_get_vector_elements(type);
1631 for (unsigned k = 0; k < num_elements; k++) {
1632 unsigned chan = var->data.location_frac + k;
1633 unsigned input_idx = c->num_inputs++;
1634 struct v3d_varying_slot slot =
1635 v3d_slot_from_slot_and_component(var->data.location + j, chan);
1636 c->input_slots[input_idx] = slot;
1637 }
1638 }
1639 }
1640 }
1641
1642
1643 static void
1644 ntq_setup_fs_inputs(struct v3d_compile *c)
1645 {
1646 nir_variable **vars;
1647 unsigned num_entries;
1648 get_sorted_input_variables(c, &num_entries, &vars);
1649
1650 for (unsigned i = 0; i < num_entries; i++) {
1651 nir_variable *var = vars[i];
1652 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1653 unsigned loc = var->data.driver_location;
1654
1655 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1656 (loc + array_len) * 4);
1657
1658 if (var->data.location == VARYING_SLOT_POS) {
1659 emit_fragcoord_input(c, loc);
1660 } else if (var_needs_point_coord(c, var)) {
1661 c->inputs[loc * 4 + 0] = c->point_x;
1662 c->inputs[loc * 4 + 1] = c->point_y;
1663 } else {
1664 for (int j = 0; j < array_len; j++)
1665 emit_fragment_input(c, loc + j, var, j);
1666 }
1667 }
1668 }
1669
1670 static void
1671 ntq_setup_outputs(struct v3d_compile *c)
1672 {
1673 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
1674 return;
1675
1676 nir_foreach_variable(var, &c->s->outputs) {
1677 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1678 unsigned loc = var->data.driver_location * 4;
1679
1680 assert(array_len == 1);
1681 (void)array_len;
1682
1683 for (int i = 0; i < 4 - var->data.location_frac; i++) {
1684 add_output(c, loc + var->data.location_frac + i,
1685 var->data.location,
1686 var->data.location_frac + i);
1687 }
1688
1689 switch (var->data.location) {
1690 case FRAG_RESULT_COLOR:
1691 c->output_color_var[0] = var;
1692 c->output_color_var[1] = var;
1693 c->output_color_var[2] = var;
1694 c->output_color_var[3] = var;
1695 break;
1696 case FRAG_RESULT_DATA0:
1697 case FRAG_RESULT_DATA1:
1698 case FRAG_RESULT_DATA2:
1699 case FRAG_RESULT_DATA3:
1700 c->output_color_var[var->data.location -
1701 FRAG_RESULT_DATA0] = var;
1702 break;
1703 case FRAG_RESULT_DEPTH:
1704 c->output_position_index = loc;
1705 break;
1706 case FRAG_RESULT_SAMPLE_MASK:
1707 c->output_sample_mask_index = loc;
1708 break;
1709 }
1710 }
1711 }
1712
1713 /**
1714 * Sets up the mapping from nir_register to struct qreg *.
1715 *
1716 * Each nir_register gets a struct qreg per 32-bit component being stored.
1717 */
1718 static void
1719 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1720 {
1721 foreach_list_typed(nir_register, nir_reg, node, list) {
1722 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1723 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1724 array_len *
1725 nir_reg->num_components);
1726
1727 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1728
1729 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1730 qregs[i] = vir_get_temp(c);
1731 }
1732 }
1733
1734 static void
1735 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1736 {
1737 /* XXX perf: Experiment with using immediate loads to avoid having
1738 * these end up in the uniform stream. Watch out for breaking the
1739 * small immediates optimization in the process!
1740 */
1741 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1742 for (int i = 0; i < instr->def.num_components; i++)
1743 qregs[i] = vir_uniform_ui(c, instr->value[i].u32);
1744
1745 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1746 }
1747
1748 static void
1749 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1750 {
1751 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1752
1753 /* VIR needs there to be *some* value, so pick 0 (same as for
1754 * ntq_setup_registers().
1755 */
1756 for (int i = 0; i < instr->def.num_components; i++)
1757 qregs[i] = vir_uniform_ui(c, 0);
1758 }
1759
1760 static void
1761 ntq_emit_image_size(struct v3d_compile *c, nir_intrinsic_instr *instr)
1762 {
1763 unsigned image_index = nir_src_as_uint(instr->src[0]);
1764 bool is_array = nir_intrinsic_image_array(instr);
1765
1766 ntq_store_dest(c, &instr->dest, 0,
1767 vir_uniform(c, QUNIFORM_IMAGE_WIDTH, image_index));
1768 if (instr->num_components > 1) {
1769 ntq_store_dest(c, &instr->dest, 1,
1770 vir_uniform(c, QUNIFORM_IMAGE_HEIGHT,
1771 image_index));
1772 }
1773 if (instr->num_components > 2) {
1774 ntq_store_dest(c, &instr->dest, 2,
1775 vir_uniform(c,
1776 is_array ?
1777 QUNIFORM_IMAGE_ARRAY_SIZE :
1778 QUNIFORM_IMAGE_DEPTH,
1779 image_index));
1780 }
1781 }
1782
1783 static void
1784 vir_emit_tlb_color_read(struct v3d_compile *c, nir_intrinsic_instr *instr)
1785 {
1786 assert(c->s->info.stage == MESA_SHADER_FRAGMENT);
1787
1788 int rt = nir_src_as_uint(instr->src[0]);
1789 assert(rt < V3D_MAX_DRAW_BUFFERS);
1790
1791 int sample_index = nir_intrinsic_base(instr) ;
1792 assert(sample_index < V3D_MAX_SAMPLES);
1793
1794 int component = nir_intrinsic_component(instr);
1795 assert(component < 4);
1796
1797 /* We need to emit our TLB reads after we have acquired the scoreboard
1798 * lock, or the GPU will hang. Usually, we do our scoreboard locking on
1799 * the last thread switch to improve parallelism, however, that is only
1800 * guaranteed to happen before the tlb color writes.
1801 *
1802 * To fix that, we make sure we always emit a thread switch before the
1803 * first tlb color read. If that happens to be the last thread switch
1804 * we emit, then everything is fine, but otherwsie, if any code after
1805 * this point needs to emit additional thread switches, then we will
1806 * switch the strategy to locking the scoreboard on the first thread
1807 * switch instead -- see vir_emit_thrsw().
1808 */
1809 if (!c->emitted_tlb_load) {
1810 if (!c->last_thrsw_at_top_level) {
1811 assert(c->devinfo->ver >= 41);
1812 vir_emit_thrsw(c);
1813 }
1814
1815 c->emitted_tlb_load = true;
1816 }
1817
1818 struct qreg *color_reads_for_sample =
1819 &c->color_reads[(rt * V3D_MAX_SAMPLES + sample_index) * 4];
1820
1821 if (color_reads_for_sample[component].file == QFILE_NULL) {
1822 enum pipe_format rt_format = c->fs_key->color_fmt[rt].format;
1823 int num_components =
1824 util_format_get_nr_components(rt_format);
1825
1826 const bool swap_rb = c->fs_key->swap_color_rb & (1 << rt);
1827 if (swap_rb)
1828 num_components = MAX2(num_components, 3);
1829
1830 nir_variable *var = c->output_color_var[rt];
1831 enum glsl_base_type type = glsl_get_base_type(var->type);
1832
1833 bool is_int_format = type == GLSL_TYPE_INT ||
1834 type == GLSL_TYPE_UINT;
1835
1836 bool is_32b_tlb_format = is_int_format ||
1837 (c->fs_key->f32_color_rb & (1 << rt));
1838
1839 int num_samples = c->fs_key->msaa ? V3D_MAX_SAMPLES : 1;
1840
1841 uint32_t conf = 0xffffff00;
1842 conf |= c->fs_key->msaa ? TLB_SAMPLE_MODE_PER_SAMPLE :
1843 TLB_SAMPLE_MODE_PER_PIXEL;
1844 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1845
1846 if (is_32b_tlb_format) {
1847 /* The F32 vs I32 distinction was dropped in 4.2. */
1848 conf |= (c->devinfo->ver < 42 && is_int_format) ?
1849 TLB_TYPE_I32_COLOR : TLB_TYPE_F32_COLOR;
1850
1851 conf |= ((num_components - 1) <<
1852 TLB_VEC_SIZE_MINUS_1_SHIFT);
1853 } else {
1854 conf |= TLB_TYPE_F16_COLOR;
1855 conf |= TLB_F16_SWAP_HI_LO;
1856
1857 if (num_components >= 3)
1858 conf |= TLB_VEC_SIZE_4_F16;
1859 else
1860 conf |= TLB_VEC_SIZE_2_F16;
1861 }
1862
1863
1864 for (int i = 0; i < num_samples; i++) {
1865 struct qreg r, g, b, a;
1866 if (is_32b_tlb_format) {
1867 r = conf != 0xffffffff && i == 0?
1868 vir_TLBU_COLOR_READ(c, conf) :
1869 vir_TLB_COLOR_READ(c);
1870 if (num_components >= 2)
1871 g = vir_TLB_COLOR_READ(c);
1872 if (num_components >= 3)
1873 b = vir_TLB_COLOR_READ(c);
1874 if (num_components >= 4)
1875 a = vir_TLB_COLOR_READ(c);
1876 } else {
1877 struct qreg rg = conf != 0xffffffff && i == 0 ?
1878 vir_TLBU_COLOR_READ(c, conf) :
1879 vir_TLB_COLOR_READ(c);
1880 r = vir_FMOV(c, rg);
1881 vir_set_unpack(c->defs[r.index], 0,
1882 V3D_QPU_UNPACK_L);
1883 g = vir_FMOV(c, rg);
1884 vir_set_unpack(c->defs[g.index], 0,
1885 V3D_QPU_UNPACK_H);
1886
1887 if (num_components > 2) {
1888 struct qreg ba = vir_TLB_COLOR_READ(c);
1889 b = vir_FMOV(c, ba);
1890 vir_set_unpack(c->defs[b.index], 0,
1891 V3D_QPU_UNPACK_L);
1892 a = vir_FMOV(c, ba);
1893 vir_set_unpack(c->defs[a.index], 0,
1894 V3D_QPU_UNPACK_H);
1895 }
1896 }
1897
1898 struct qreg *color_reads =
1899 &c->color_reads[(rt * V3D_MAX_SAMPLES + i) * 4];
1900
1901 color_reads[0] = swap_rb ? b : r;
1902 if (num_components >= 2)
1903 color_reads[1] = g;
1904 if (num_components >= 3)
1905 color_reads[2] = swap_rb ? r : b;
1906 if (num_components >= 4)
1907 color_reads[3] = a;
1908 }
1909 }
1910
1911 assert(color_reads_for_sample[component].file != QFILE_NULL);
1912 ntq_store_dest(c, &instr->dest, 0,
1913 vir_MOV(c, color_reads_for_sample[component]));
1914 }
1915
1916 static void
1917 ntq_emit_load_uniform(struct v3d_compile *c, nir_intrinsic_instr *instr)
1918 {
1919 if (nir_src_is_const(instr->src[0])) {
1920 int offset = (nir_intrinsic_base(instr) +
1921 nir_src_as_uint(instr->src[0]));
1922 assert(offset % 4 == 0);
1923 /* We need dwords */
1924 offset = offset / 4;
1925 for (int i = 0; i < instr->num_components; i++) {
1926 ntq_store_dest(c, &instr->dest, i,
1927 vir_uniform(c, QUNIFORM_UNIFORM,
1928 offset + i));
1929 }
1930 } else {
1931 ntq_emit_tmu_general(c, instr, false);
1932 }
1933 }
1934
1935 static void
1936 ntq_emit_load_input(struct v3d_compile *c, nir_intrinsic_instr *instr)
1937 {
1938 /* XXX: Use ldvpmv (uniform offset) or ldvpmd (non-uniform offset)
1939 * and enable PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR.
1940 */
1941 unsigned offset =
1942 nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[0]);
1943
1944 if (c->s->info.stage != MESA_SHADER_FRAGMENT && c->devinfo->ver >= 40) {
1945 /* Emit the LDVPM directly now, rather than at the top
1946 * of the shader like we did for V3D 3.x (which needs
1947 * vpmsetup when not just taking the next offset).
1948 *
1949 * Note that delaying like this may introduce stalls,
1950 * as LDVPMV takes a minimum of 1 instruction but may
1951 * be slower if the VPM unit is busy with another QPU.
1952 */
1953 int index = 0;
1954 if (c->s->info.system_values_read &
1955 (1ull << SYSTEM_VALUE_INSTANCE_ID)) {
1956 index++;
1957 }
1958 if (c->s->info.system_values_read &
1959 (1ull << SYSTEM_VALUE_VERTEX_ID)) {
1960 index++;
1961 }
1962 for (int i = 0; i < offset; i++)
1963 index += c->vattr_sizes[i];
1964 index += nir_intrinsic_component(instr);
1965 for (int i = 0; i < instr->num_components; i++) {
1966 struct qreg vpm_offset = vir_uniform_ui(c, index++);
1967 ntq_store_dest(c, &instr->dest, i,
1968 vir_LDVPMV_IN(c, vpm_offset));
1969 }
1970 } else {
1971 for (int i = 0; i < instr->num_components; i++) {
1972 int comp = nir_intrinsic_component(instr) + i;
1973 ntq_store_dest(c, &instr->dest, i,
1974 vir_MOV(c, c->inputs[offset * 4 + comp]));
1975 }
1976 }
1977 }
1978
1979 static void
1980 ntq_emit_per_sample_color_write(struct v3d_compile *c,
1981 nir_intrinsic_instr *instr)
1982 {
1983 assert(instr->intrinsic == nir_intrinsic_store_tlb_sample_color_v3d);
1984
1985 unsigned rt = nir_src_as_uint(instr->src[1]);
1986 assert(rt < V3D_MAX_DRAW_BUFFERS);
1987
1988 unsigned sample_idx = nir_intrinsic_base(instr);
1989 assert(sample_idx < V3D_MAX_SAMPLES);
1990
1991 unsigned offset = (rt * V3D_MAX_SAMPLES + sample_idx) * 4;
1992 for (int i = 0; i < instr->num_components; i++) {
1993 c->sample_colors[offset + i] =
1994 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
1995 }
1996 }
1997
1998 static void
1999 ntq_emit_color_write(struct v3d_compile *c,
2000 nir_intrinsic_instr *instr)
2001 {
2002 unsigned offset = (nir_intrinsic_base(instr) +
2003 nir_src_as_uint(instr->src[1])) * 4 +
2004 nir_intrinsic_component(instr);
2005 for (int i = 0; i < instr->num_components; i++) {
2006 c->outputs[offset + i] =
2007 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
2008 }
2009 }
2010
2011 static void
2012 emit_store_output_gs(struct v3d_compile *c, nir_intrinsic_instr *instr)
2013 {
2014 assert(instr->num_components == 1);
2015
2016 uint32_t base_offset = nir_intrinsic_base(instr);
2017 struct qreg src_offset = ntq_get_src(c, instr->src[1], 0);
2018 struct qreg offset =
2019 vir_ADD(c, vir_uniform_ui(c, base_offset), src_offset);
2020
2021 /* Usually, for VS or FS, we only emit outputs once at program end so
2022 * our VPM writes are never in non-uniform control flow, but this
2023 * is not true for GS, where we are emitting multiple vertices.
2024 */
2025 if (vir_in_nonuniform_control_flow(c)) {
2026 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2027 V3D_QPU_PF_PUSHZ);
2028 }
2029
2030 struct qreg val = ntq_get_src(c, instr->src[0], 0);
2031
2032 /* The offset isn’t necessarily dynamically uniform for a geometry
2033 * shader. This can happen if the shader sometimes doesn’t emit one of
2034 * the vertices. In that case subsequent vertices will be written to
2035 * different offsets in the VPM and we need to use the scatter write
2036 * instruction to have a different offset for each lane.
2037 */
2038 if (nir_src_is_dynamically_uniform(instr->src[1]))
2039 vir_VPM_WRITE_indirect(c, val, offset);
2040 else
2041 vir_STVPMD(c, offset, val);
2042
2043 if (vir_in_nonuniform_control_flow(c)) {
2044 struct qinst *last_inst =
2045 (struct qinst *)c->cur_block->instructions.prev;
2046 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
2047 }
2048 }
2049
2050 static void
2051 ntq_emit_store_output(struct v3d_compile *c, nir_intrinsic_instr *instr)
2052 {
2053 /* XXX perf: Use stvpmv with uniform non-constant offsets and
2054 * stvpmd with non-uniform offsets and enable
2055 * PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR.
2056 */
2057 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
2058 ntq_emit_color_write(c, instr);
2059 } else if (c->s->info.stage == MESA_SHADER_GEOMETRY) {
2060 emit_store_output_gs(c, instr);
2061 } else {
2062 assert(c->s->info.stage == MESA_SHADER_VERTEX);
2063 assert(instr->num_components == 1);
2064
2065 vir_VPM_WRITE(c,
2066 ntq_get_src(c, instr->src[0], 0),
2067 nir_intrinsic_base(instr));
2068 }
2069 }
2070
2071 static void
2072 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
2073 {
2074 switch (instr->intrinsic) {
2075 case nir_intrinsic_load_uniform:
2076 ntq_emit_load_uniform(c, instr);
2077 break;
2078
2079 case nir_intrinsic_load_ubo:
2080 ntq_emit_tmu_general(c, instr, false);
2081 break;
2082
2083 case nir_intrinsic_ssbo_atomic_add:
2084 case nir_intrinsic_ssbo_atomic_imin:
2085 case nir_intrinsic_ssbo_atomic_umin:
2086 case nir_intrinsic_ssbo_atomic_imax:
2087 case nir_intrinsic_ssbo_atomic_umax:
2088 case nir_intrinsic_ssbo_atomic_and:
2089 case nir_intrinsic_ssbo_atomic_or:
2090 case nir_intrinsic_ssbo_atomic_xor:
2091 case nir_intrinsic_ssbo_atomic_exchange:
2092 case nir_intrinsic_ssbo_atomic_comp_swap:
2093 case nir_intrinsic_load_ssbo:
2094 case nir_intrinsic_store_ssbo:
2095 ntq_emit_tmu_general(c, instr, false);
2096 break;
2097
2098 case nir_intrinsic_shared_atomic_add:
2099 case nir_intrinsic_shared_atomic_imin:
2100 case nir_intrinsic_shared_atomic_umin:
2101 case nir_intrinsic_shared_atomic_imax:
2102 case nir_intrinsic_shared_atomic_umax:
2103 case nir_intrinsic_shared_atomic_and:
2104 case nir_intrinsic_shared_atomic_or:
2105 case nir_intrinsic_shared_atomic_xor:
2106 case nir_intrinsic_shared_atomic_exchange:
2107 case nir_intrinsic_shared_atomic_comp_swap:
2108 case nir_intrinsic_load_shared:
2109 case nir_intrinsic_store_shared:
2110 case nir_intrinsic_load_scratch:
2111 case nir_intrinsic_store_scratch:
2112 ntq_emit_tmu_general(c, instr, true);
2113 break;
2114
2115 case nir_intrinsic_image_load:
2116 case nir_intrinsic_image_store:
2117 case nir_intrinsic_image_atomic_add:
2118 case nir_intrinsic_image_atomic_imin:
2119 case nir_intrinsic_image_atomic_umin:
2120 case nir_intrinsic_image_atomic_imax:
2121 case nir_intrinsic_image_atomic_umax:
2122 case nir_intrinsic_image_atomic_and:
2123 case nir_intrinsic_image_atomic_or:
2124 case nir_intrinsic_image_atomic_xor:
2125 case nir_intrinsic_image_atomic_exchange:
2126 case nir_intrinsic_image_atomic_comp_swap:
2127 v3d40_vir_emit_image_load_store(c, instr);
2128 break;
2129
2130 case nir_intrinsic_get_buffer_size:
2131 ntq_store_dest(c, &instr->dest, 0,
2132 vir_uniform(c, QUNIFORM_GET_BUFFER_SIZE,
2133 nir_src_as_uint(instr->src[0])));
2134 break;
2135
2136 case nir_intrinsic_load_user_clip_plane:
2137 for (int i = 0; i < nir_intrinsic_dest_components(instr); i++) {
2138 ntq_store_dest(c, &instr->dest, i,
2139 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
2140 nir_intrinsic_ucp_id(instr) *
2141 4 + i));
2142 }
2143 break;
2144
2145 case nir_intrinsic_load_viewport_x_scale:
2146 ntq_store_dest(c, &instr->dest, 0,
2147 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE, 0));
2148 break;
2149
2150 case nir_intrinsic_load_viewport_y_scale:
2151 ntq_store_dest(c, &instr->dest, 0,
2152 vir_uniform(c, QUNIFORM_VIEWPORT_Y_SCALE, 0));
2153 break;
2154
2155 case nir_intrinsic_load_viewport_z_scale:
2156 ntq_store_dest(c, &instr->dest, 0,
2157 vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0));
2158 break;
2159
2160 case nir_intrinsic_load_viewport_z_offset:
2161 ntq_store_dest(c, &instr->dest, 0,
2162 vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0));
2163 break;
2164
2165 case nir_intrinsic_load_alpha_ref_float:
2166 ntq_store_dest(c, &instr->dest, 0,
2167 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
2168 break;
2169
2170 case nir_intrinsic_load_sample_mask_in:
2171 ntq_store_dest(c, &instr->dest, 0, vir_MSF(c));
2172 break;
2173
2174 case nir_intrinsic_load_helper_invocation:
2175 vir_set_pf(vir_MSF_dest(c, vir_nop_reg()), V3D_QPU_PF_PUSHZ);
2176 ntq_store_dest(c, &instr->dest, 0,
2177 vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
2178 vir_uniform_ui(c, ~0),
2179 vir_uniform_ui(c, 0))));
2180 break;
2181
2182 case nir_intrinsic_load_front_face:
2183 /* The register contains 0 (front) or 1 (back), and we need to
2184 * turn it into a NIR bool where true means front.
2185 */
2186 ntq_store_dest(c, &instr->dest, 0,
2187 vir_ADD(c,
2188 vir_uniform_ui(c, -1),
2189 vir_REVF(c)));
2190 break;
2191
2192 case nir_intrinsic_load_instance_id:
2193 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
2194 break;
2195
2196 case nir_intrinsic_load_vertex_id:
2197 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
2198 break;
2199
2200 case nir_intrinsic_load_tlb_color_v3d:
2201 vir_emit_tlb_color_read(c, instr);
2202 break;
2203
2204 case nir_intrinsic_load_input:
2205 ntq_emit_load_input(c, instr);
2206 break;
2207
2208 case nir_intrinsic_store_tlb_sample_color_v3d:
2209 ntq_emit_per_sample_color_write(c, instr);
2210 break;
2211
2212 case nir_intrinsic_store_output:
2213 ntq_emit_store_output(c, instr);
2214 break;
2215
2216 case nir_intrinsic_image_size:
2217 ntq_emit_image_size(c, instr);
2218 break;
2219
2220 case nir_intrinsic_discard:
2221 if (vir_in_nonuniform_control_flow(c)) {
2222 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2223 V3D_QPU_PF_PUSHZ);
2224 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
2225 vir_uniform_ui(c, 0)),
2226 V3D_QPU_COND_IFA);
2227 } else {
2228 vir_SETMSF_dest(c, vir_nop_reg(),
2229 vir_uniform_ui(c, 0));
2230 }
2231 break;
2232
2233 case nir_intrinsic_discard_if: {
2234 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, instr->src[0]);
2235
2236 if (vir_in_nonuniform_control_flow(c)) {
2237 struct qinst *exec_flag = vir_MOV_dest(c, vir_nop_reg(),
2238 c->execute);
2239 if (cond == V3D_QPU_COND_IFA) {
2240 vir_set_uf(exec_flag, V3D_QPU_UF_ANDZ);
2241 } else {
2242 vir_set_uf(exec_flag, V3D_QPU_UF_NORNZ);
2243 cond = V3D_QPU_COND_IFA;
2244 }
2245 }
2246
2247 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
2248 vir_uniform_ui(c, 0)), cond);
2249
2250 break;
2251 }
2252
2253 case nir_intrinsic_memory_barrier:
2254 case nir_intrinsic_memory_barrier_buffer:
2255 case nir_intrinsic_memory_barrier_image:
2256 case nir_intrinsic_memory_barrier_shared:
2257 case nir_intrinsic_memory_barrier_tcs_patch:
2258 case nir_intrinsic_group_memory_barrier:
2259 /* We don't do any instruction scheduling of these NIR
2260 * instructions between each other, so we just need to make
2261 * sure that the TMU operations before the barrier are flushed
2262 * before the ones after the barrier. That is currently
2263 * handled by having a THRSW in each of them and a LDTMU
2264 * series or a TMUWT after.
2265 */
2266 break;
2267
2268 case nir_intrinsic_control_barrier:
2269 /* Emit a TSY op to get all invocations in the workgroup
2270 * (actually supergroup) to block until the last invocation
2271 * reaches the TSY op.
2272 */
2273 if (c->devinfo->ver >= 42) {
2274 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
2275 V3D_QPU_WADDR_SYNCB));
2276 } else {
2277 struct qinst *sync =
2278 vir_BARRIERID_dest(c,
2279 vir_reg(QFILE_MAGIC,
2280 V3D_QPU_WADDR_SYNCU));
2281 sync->uniform =
2282 vir_get_uniform_index(c, QUNIFORM_CONSTANT,
2283 0xffffff00 |
2284 V3D_TSY_WAIT_INC_CHECK);
2285
2286 }
2287
2288 /* The blocking of a TSY op only happens at the next thread
2289 * switch. No texturing may be outstanding at the time of a
2290 * TSY blocking operation.
2291 */
2292 vir_emit_thrsw(c);
2293 break;
2294
2295 case nir_intrinsic_load_num_work_groups:
2296 for (int i = 0; i < 3; i++) {
2297 ntq_store_dest(c, &instr->dest, i,
2298 vir_uniform(c, QUNIFORM_NUM_WORK_GROUPS,
2299 i));
2300 }
2301 break;
2302
2303 case nir_intrinsic_load_local_invocation_index:
2304 ntq_store_dest(c, &instr->dest, 0,
2305 vir_SHR(c, c->cs_payload[1],
2306 vir_uniform_ui(c, 32 - c->local_invocation_index_bits)));
2307 break;
2308
2309 case nir_intrinsic_load_work_group_id:
2310 ntq_store_dest(c, &instr->dest, 0,
2311 vir_AND(c, c->cs_payload[0],
2312 vir_uniform_ui(c, 0xffff)));
2313 ntq_store_dest(c, &instr->dest, 1,
2314 vir_SHR(c, c->cs_payload[0],
2315 vir_uniform_ui(c, 16)));
2316 ntq_store_dest(c, &instr->dest, 2,
2317 vir_AND(c, c->cs_payload[1],
2318 vir_uniform_ui(c, 0xffff)));
2319 break;
2320
2321 case nir_intrinsic_load_subgroup_id:
2322 ntq_store_dest(c, &instr->dest, 0, vir_EIDX(c));
2323 break;
2324
2325 case nir_intrinsic_load_per_vertex_input: {
2326 /* col: vertex index, row = varying index */
2327 struct qreg col = ntq_get_src(c, instr->src[0], 0);
2328 uint32_t row_idx = nir_intrinsic_base(instr) * 4 +
2329 nir_intrinsic_component(instr);
2330 for (int i = 0; i < instr->num_components; i++) {
2331 struct qreg row = vir_uniform_ui(c, row_idx++);
2332 ntq_store_dest(c, &instr->dest, i,
2333 vir_LDVPMG_IN(c, row, col));
2334 }
2335 break;
2336 }
2337
2338 case nir_intrinsic_emit_vertex:
2339 case nir_intrinsic_end_primitive:
2340 unreachable("Should have been lowered in v3d_nir_lower_io");
2341 break;
2342
2343 case nir_intrinsic_load_primitive_id: {
2344 /* gl_PrimitiveIdIn is written by the GBG in the first word of
2345 * VPM output header. According to docs, we should read this
2346 * using ldvpm(v,d)_in (See Table 71).
2347 */
2348 ntq_store_dest(c, &instr->dest, 0,
2349 vir_LDVPMV_IN(c, vir_uniform_ui(c, 0)));
2350 break;
2351 }
2352
2353 case nir_intrinsic_load_invocation_id:
2354 ntq_store_dest(c, &instr->dest, 0, vir_IID(c));
2355 break;
2356
2357 case nir_intrinsic_load_fb_layers_v3d:
2358 ntq_store_dest(c, &instr->dest, 0,
2359 vir_uniform(c, QUNIFORM_FB_LAYERS, 0));
2360 break;
2361
2362 default:
2363 fprintf(stderr, "Unknown intrinsic: ");
2364 nir_print_instr(&instr->instr, stderr);
2365 fprintf(stderr, "\n");
2366 break;
2367 }
2368 }
2369
2370 /* Clears (activates) the execute flags for any channels whose jump target
2371 * matches this block.
2372 *
2373 * XXX perf: Could we be using flpush/flpop somehow for our execution channel
2374 * enabling?
2375 *
2376 * XXX perf: For uniform control flow, we should be able to skip c->execute
2377 * handling entirely.
2378 */
2379 static void
2380 ntq_activate_execute_for_block(struct v3d_compile *c)
2381 {
2382 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
2383 c->execute, vir_uniform_ui(c, c->cur_block->index)),
2384 V3D_QPU_PF_PUSHZ);
2385
2386 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2387 }
2388
2389 static void
2390 ntq_emit_uniform_if(struct v3d_compile *c, nir_if *if_stmt)
2391 {
2392 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2393 bool empty_else_block =
2394 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2395 exec_list_is_empty(&nir_else_block->instr_list));
2396
2397 struct qblock *then_block = vir_new_block(c);
2398 struct qblock *after_block = vir_new_block(c);
2399 struct qblock *else_block;
2400 if (empty_else_block)
2401 else_block = after_block;
2402 else
2403 else_block = vir_new_block(c);
2404
2405 /* Set up the flags for the IF condition (taking the THEN branch). */
2406 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
2407
2408 /* Jump to ELSE. */
2409 vir_BRANCH(c, cond == V3D_QPU_COND_IFA ?
2410 V3D_QPU_BRANCH_COND_ALLNA :
2411 V3D_QPU_BRANCH_COND_ALLA);
2412 vir_link_blocks(c->cur_block, else_block);
2413 vir_link_blocks(c->cur_block, then_block);
2414
2415 /* Process the THEN block. */
2416 vir_set_emit_block(c, then_block);
2417 ntq_emit_cf_list(c, &if_stmt->then_list);
2418
2419 if (!empty_else_block) {
2420 /* At the end of the THEN block, jump to ENDIF */
2421 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALWAYS);
2422 vir_link_blocks(c->cur_block, after_block);
2423
2424 /* Emit the else block. */
2425 vir_set_emit_block(c, else_block);
2426 ntq_emit_cf_list(c, &if_stmt->else_list);
2427 }
2428
2429 vir_link_blocks(c->cur_block, after_block);
2430
2431 vir_set_emit_block(c, after_block);
2432 }
2433
2434 static void
2435 ntq_emit_nonuniform_if(struct v3d_compile *c, nir_if *if_stmt)
2436 {
2437 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2438 bool empty_else_block =
2439 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2440 exec_list_is_empty(&nir_else_block->instr_list));
2441
2442 struct qblock *then_block = vir_new_block(c);
2443 struct qblock *after_block = vir_new_block(c);
2444 struct qblock *else_block;
2445 if (empty_else_block)
2446 else_block = after_block;
2447 else
2448 else_block = vir_new_block(c);
2449
2450 bool was_uniform_control_flow = false;
2451 if (!vir_in_nonuniform_control_flow(c)) {
2452 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2453 was_uniform_control_flow = true;
2454 }
2455
2456 /* Set up the flags for the IF condition (taking the THEN branch). */
2457 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
2458
2459 /* Update the flags+cond to mean "Taking the ELSE branch (!cond) and
2460 * was previously active (execute Z) for updating the exec flags.
2461 */
2462 if (was_uniform_control_flow) {
2463 cond = v3d_qpu_cond_invert(cond);
2464 } else {
2465 struct qinst *inst = vir_MOV_dest(c, vir_nop_reg(), c->execute);
2466 if (cond == V3D_QPU_COND_IFA) {
2467 vir_set_uf(inst, V3D_QPU_UF_NORNZ);
2468 } else {
2469 vir_set_uf(inst, V3D_QPU_UF_ANDZ);
2470 cond = V3D_QPU_COND_IFA;
2471 }
2472 }
2473
2474 vir_MOV_cond(c, cond,
2475 c->execute,
2476 vir_uniform_ui(c, else_block->index));
2477
2478 /* Jump to ELSE if nothing is active for THEN, otherwise fall
2479 * through.
2480 */
2481 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ);
2482 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
2483 vir_link_blocks(c->cur_block, else_block);
2484 vir_link_blocks(c->cur_block, then_block);
2485
2486 /* Process the THEN block. */
2487 vir_set_emit_block(c, then_block);
2488 ntq_emit_cf_list(c, &if_stmt->then_list);
2489
2490 if (!empty_else_block) {
2491 /* Handle the end of the THEN block. First, all currently
2492 * active channels update their execute flags to point to
2493 * ENDIF
2494 */
2495 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2496 V3D_QPU_PF_PUSHZ);
2497 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2498 vir_uniform_ui(c, after_block->index));
2499
2500 /* If everything points at ENDIF, then jump there immediately. */
2501 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
2502 c->execute,
2503 vir_uniform_ui(c, after_block->index)),
2504 V3D_QPU_PF_PUSHZ);
2505 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
2506 vir_link_blocks(c->cur_block, after_block);
2507 vir_link_blocks(c->cur_block, else_block);
2508
2509 vir_set_emit_block(c, else_block);
2510 ntq_activate_execute_for_block(c);
2511 ntq_emit_cf_list(c, &if_stmt->else_list);
2512 }
2513
2514 vir_link_blocks(c->cur_block, after_block);
2515
2516 vir_set_emit_block(c, after_block);
2517 if (was_uniform_control_flow)
2518 c->execute = c->undef;
2519 else
2520 ntq_activate_execute_for_block(c);
2521 }
2522
2523 static void
2524 ntq_emit_if(struct v3d_compile *c, nir_if *nif)
2525 {
2526 bool was_in_control_flow = c->in_control_flow;
2527 c->in_control_flow = true;
2528 if (!vir_in_nonuniform_control_flow(c) &&
2529 nir_src_is_dynamically_uniform(nif->condition)) {
2530 ntq_emit_uniform_if(c, nif);
2531 } else {
2532 ntq_emit_nonuniform_if(c, nif);
2533 }
2534 c->in_control_flow = was_in_control_flow;
2535 }
2536
2537 static void
2538 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
2539 {
2540 switch (jump->type) {
2541 case nir_jump_break:
2542 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2543 V3D_QPU_PF_PUSHZ);
2544 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2545 vir_uniform_ui(c, c->loop_break_block->index));
2546 break;
2547
2548 case nir_jump_continue:
2549 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2550 V3D_QPU_PF_PUSHZ);
2551 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2552 vir_uniform_ui(c, c->loop_cont_block->index));
2553 break;
2554
2555 case nir_jump_return:
2556 unreachable("All returns shouold be lowered\n");
2557 }
2558 }
2559
2560 static void
2561 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
2562 {
2563 switch (instr->type) {
2564 case nir_instr_type_alu:
2565 ntq_emit_alu(c, nir_instr_as_alu(instr));
2566 break;
2567
2568 case nir_instr_type_intrinsic:
2569 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
2570 break;
2571
2572 case nir_instr_type_load_const:
2573 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
2574 break;
2575
2576 case nir_instr_type_ssa_undef:
2577 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
2578 break;
2579
2580 case nir_instr_type_tex:
2581 ntq_emit_tex(c, nir_instr_as_tex(instr));
2582 break;
2583
2584 case nir_instr_type_jump:
2585 ntq_emit_jump(c, nir_instr_as_jump(instr));
2586 break;
2587
2588 default:
2589 fprintf(stderr, "Unknown NIR instr type: ");
2590 nir_print_instr(instr, stderr);
2591 fprintf(stderr, "\n");
2592 abort();
2593 }
2594 }
2595
2596 static void
2597 ntq_emit_block(struct v3d_compile *c, nir_block *block)
2598 {
2599 nir_foreach_instr(instr, block) {
2600 ntq_emit_instr(c, instr);
2601 }
2602 }
2603
2604 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
2605
2606 static void
2607 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
2608 {
2609 bool was_in_control_flow = c->in_control_flow;
2610 c->in_control_flow = true;
2611
2612 bool was_uniform_control_flow = false;
2613 if (!vir_in_nonuniform_control_flow(c)) {
2614 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2615 was_uniform_control_flow = true;
2616 }
2617
2618 struct qblock *save_loop_cont_block = c->loop_cont_block;
2619 struct qblock *save_loop_break_block = c->loop_break_block;
2620
2621 c->loop_cont_block = vir_new_block(c);
2622 c->loop_break_block = vir_new_block(c);
2623
2624 vir_link_blocks(c->cur_block, c->loop_cont_block);
2625 vir_set_emit_block(c, c->loop_cont_block);
2626 ntq_activate_execute_for_block(c);
2627
2628 ntq_emit_cf_list(c, &loop->body);
2629
2630 /* Re-enable any previous continues now, so our ANYA check below
2631 * works.
2632 *
2633 * XXX: Use the .ORZ flags update, instead.
2634 */
2635 vir_set_pf(vir_XOR_dest(c,
2636 vir_nop_reg(),
2637 c->execute,
2638 vir_uniform_ui(c, c->loop_cont_block->index)),
2639 V3D_QPU_PF_PUSHZ);
2640 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2641
2642 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ);
2643
2644 struct qinst *branch = vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
2645 /* Pixels that were not dispatched or have been discarded should not
2646 * contribute to looping again.
2647 */
2648 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P;
2649 vir_link_blocks(c->cur_block, c->loop_cont_block);
2650 vir_link_blocks(c->cur_block, c->loop_break_block);
2651
2652 vir_set_emit_block(c, c->loop_break_block);
2653 if (was_uniform_control_flow)
2654 c->execute = c->undef;
2655 else
2656 ntq_activate_execute_for_block(c);
2657
2658 c->loop_break_block = save_loop_break_block;
2659 c->loop_cont_block = save_loop_cont_block;
2660
2661 c->loops++;
2662
2663 c->in_control_flow = was_in_control_flow;
2664 }
2665
2666 static void
2667 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
2668 {
2669 fprintf(stderr, "FUNCTIONS not handled.\n");
2670 abort();
2671 }
2672
2673 static void
2674 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
2675 {
2676 foreach_list_typed(nir_cf_node, node, node, list) {
2677 switch (node->type) {
2678 case nir_cf_node_block:
2679 ntq_emit_block(c, nir_cf_node_as_block(node));
2680 break;
2681
2682 case nir_cf_node_if:
2683 ntq_emit_if(c, nir_cf_node_as_if(node));
2684 break;
2685
2686 case nir_cf_node_loop:
2687 ntq_emit_loop(c, nir_cf_node_as_loop(node));
2688 break;
2689
2690 case nir_cf_node_function:
2691 ntq_emit_function(c, nir_cf_node_as_function(node));
2692 break;
2693
2694 default:
2695 fprintf(stderr, "Unknown NIR node type\n");
2696 abort();
2697 }
2698 }
2699 }
2700
2701 static void
2702 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
2703 {
2704 ntq_setup_registers(c, &impl->registers);
2705 ntq_emit_cf_list(c, &impl->body);
2706 }
2707
2708 static void
2709 nir_to_vir(struct v3d_compile *c)
2710 {
2711 switch (c->s->info.stage) {
2712 case MESA_SHADER_FRAGMENT:
2713 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
2714 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
2715 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
2716
2717 /* V3D 4.x can disable implicit point coordinate varyings if
2718 * they are not used.
2719 */
2720 if (c->fs_key->is_points &&
2721 (c->devinfo->ver < 40 || program_reads_point_coord(c))) {
2722 c->point_x = emit_fragment_varying(c, NULL, 0, 0);
2723 c->point_y = emit_fragment_varying(c, NULL, 0, 0);
2724 c->uses_implicit_point_line_varyings = true;
2725 } else if (c->fs_key->is_lines && c->devinfo->ver < 40) {
2726 c->line_x = emit_fragment_varying(c, NULL, 0, 0);
2727 c->uses_implicit_point_line_varyings = true;
2728 }
2729 break;
2730 case MESA_SHADER_COMPUTE:
2731 /* Set up the TSO for barriers, assuming we do some. */
2732 if (c->devinfo->ver < 42) {
2733 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
2734 V3D_QPU_WADDR_SYNC));
2735 }
2736
2737 c->cs_payload[0] = vir_MOV(c, vir_reg(QFILE_REG, 0));
2738 c->cs_payload[1] = vir_MOV(c, vir_reg(QFILE_REG, 2));
2739
2740 /* Set up the division between gl_LocalInvocationIndex and
2741 * wg_in_mem in the payload reg.
2742 */
2743 int wg_size = (c->s->info.cs.local_size[0] *
2744 c->s->info.cs.local_size[1] *
2745 c->s->info.cs.local_size[2]);
2746 c->local_invocation_index_bits =
2747 ffs(util_next_power_of_two(MAX2(wg_size, 64))) - 1;
2748 assert(c->local_invocation_index_bits <= 8);
2749
2750 if (c->s->info.cs.shared_size) {
2751 struct qreg wg_in_mem = vir_SHR(c, c->cs_payload[1],
2752 vir_uniform_ui(c, 16));
2753 if (c->s->info.cs.local_size[0] != 1 ||
2754 c->s->info.cs.local_size[1] != 1 ||
2755 c->s->info.cs.local_size[2] != 1) {
2756 int wg_bits = (16 -
2757 c->local_invocation_index_bits);
2758 int wg_mask = (1 << wg_bits) - 1;
2759 wg_in_mem = vir_AND(c, wg_in_mem,
2760 vir_uniform_ui(c, wg_mask));
2761 }
2762 struct qreg shared_per_wg =
2763 vir_uniform_ui(c, c->s->info.cs.shared_size);
2764
2765 c->cs_shared_offset =
2766 vir_ADD(c,
2767 vir_uniform(c, QUNIFORM_SHARED_OFFSET,0),
2768 vir_UMUL(c, wg_in_mem, shared_per_wg));
2769 }
2770 break;
2771 default:
2772 break;
2773 }
2774
2775 if (c->s->scratch_size) {
2776 v3d_setup_spill_base(c);
2777 c->spill_size += V3D_CHANNELS * c->s->scratch_size;
2778 }
2779
2780 switch (c->s->info.stage) {
2781 case MESA_SHADER_VERTEX:
2782 ntq_setup_vs_inputs(c);
2783 break;
2784 case MESA_SHADER_GEOMETRY:
2785 ntq_setup_gs_inputs(c);
2786 break;
2787 case MESA_SHADER_FRAGMENT:
2788 ntq_setup_fs_inputs(c);
2789 break;
2790 case MESA_SHADER_COMPUTE:
2791 break;
2792 default:
2793 unreachable("unsupported shader stage");
2794 }
2795
2796 ntq_setup_outputs(c);
2797
2798 /* Find the main function and emit the body. */
2799 nir_foreach_function(function, c->s) {
2800 assert(strcmp(function->name, "main") == 0);
2801 assert(function->impl);
2802 ntq_emit_impl(c, function->impl);
2803 }
2804 }
2805
2806 const nir_shader_compiler_options v3d_nir_options = {
2807 .lower_all_io_to_temps = true,
2808 .lower_extract_byte = true,
2809 .lower_extract_word = true,
2810 .lower_bitfield_insert_to_shifts = true,
2811 .lower_bitfield_extract_to_shifts = true,
2812 .lower_bitfield_reverse = true,
2813 .lower_bit_count = true,
2814 .lower_cs_local_id_from_index = true,
2815 .lower_ffract = true,
2816 .lower_fmod = true,
2817 .lower_pack_unorm_2x16 = true,
2818 .lower_pack_snorm_2x16 = true,
2819 .lower_pack_unorm_4x8 = true,
2820 .lower_pack_snorm_4x8 = true,
2821 .lower_unpack_unorm_4x8 = true,
2822 .lower_unpack_snorm_4x8 = true,
2823 .lower_pack_half_2x16 = true,
2824 .lower_unpack_half_2x16 = true,
2825 .lower_fdiv = true,
2826 .lower_find_lsb = true,
2827 .lower_ffma = true,
2828 .lower_flrp32 = true,
2829 .lower_fpow = true,
2830 .lower_fsat = true,
2831 .lower_fsqrt = true,
2832 .lower_ifind_msb = true,
2833 .lower_isign = true,
2834 .lower_ldexp = true,
2835 .lower_mul_high = true,
2836 .lower_wpos_pntc = true,
2837 .lower_rotate = true,
2838 .lower_to_scalar = true,
2839 };
2840
2841 /**
2842 * When demoting a shader down to single-threaded, removes the THRSW
2843 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
2844 * program end).
2845 */
2846 static void
2847 vir_remove_thrsw(struct v3d_compile *c)
2848 {
2849 vir_for_each_block(block, c) {
2850 vir_for_each_inst_safe(inst, block) {
2851 if (inst->qpu.sig.thrsw)
2852 vir_remove_instruction(c, inst);
2853 }
2854 }
2855
2856 c->last_thrsw = NULL;
2857 }
2858
2859 void
2860 vir_emit_last_thrsw(struct v3d_compile *c)
2861 {
2862 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
2863 * switching, so disable threads if we didn't do any TMU ops (each of
2864 * which would have emitted a THRSW).
2865 */
2866 if (!c->last_thrsw_at_top_level && c->devinfo->ver < 41) {
2867 c->threads = 1;
2868 if (c->last_thrsw)
2869 vir_remove_thrsw(c);
2870 return;
2871 }
2872
2873 /* If we're threaded and the last THRSW was in conditional code, then
2874 * we need to emit another one so that we can flag it as the last
2875 * thrsw.
2876 */
2877 if (c->last_thrsw && !c->last_thrsw_at_top_level) {
2878 assert(c->devinfo->ver >= 41);
2879 vir_emit_thrsw(c);
2880 }
2881
2882 /* If we're threaded, then we need to mark the last THRSW instruction
2883 * so we can emit a pair of them at QPU emit time.
2884 *
2885 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2886 * post-last-THRSW state, so we can skip this.
2887 */
2888 if (!c->last_thrsw && c->s->info.stage == MESA_SHADER_FRAGMENT) {
2889 assert(c->devinfo->ver >= 41);
2890 vir_emit_thrsw(c);
2891 }
2892
2893 if (c->last_thrsw)
2894 c->last_thrsw->is_last_thrsw = true;
2895 }
2896
2897 /* There's a flag in the shader for "center W is needed for reasons other than
2898 * non-centroid varyings", so we just walk the program after VIR optimization
2899 * to see if it's used. It should be harmless to set even if we only use
2900 * center W for varyings.
2901 */
2902 static void
2903 vir_check_payload_w(struct v3d_compile *c)
2904 {
2905 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
2906 return;
2907
2908 vir_for_each_inst_inorder(inst, c) {
2909 for (int i = 0; i < vir_get_nsrc(inst); i++) {
2910 if (inst->src[i].file == QFILE_REG &&
2911 inst->src[i].index == 0) {
2912 c->uses_center_w = true;
2913 return;
2914 }
2915 }
2916 }
2917
2918 }
2919
2920 void
2921 v3d_nir_to_vir(struct v3d_compile *c)
2922 {
2923 if (V3D_DEBUG & (V3D_DEBUG_NIR |
2924 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2925 fprintf(stderr, "%s prog %d/%d NIR:\n",
2926 vir_get_stage_name(c),
2927 c->program_id, c->variant_id);
2928 nir_print_shader(c->s, stderr);
2929 }
2930
2931 nir_to_vir(c);
2932
2933 /* Emit the last THRSW before STVPM and TLB writes. */
2934 vir_emit_last_thrsw(c);
2935
2936 switch (c->s->info.stage) {
2937 case MESA_SHADER_FRAGMENT:
2938 emit_frag_end(c);
2939 break;
2940 case MESA_SHADER_GEOMETRY:
2941 emit_geom_end(c);
2942 break;
2943 case MESA_SHADER_VERTEX:
2944 emit_vert_end(c);
2945 break;
2946 case MESA_SHADER_COMPUTE:
2947 break;
2948 default:
2949 unreachable("bad stage");
2950 }
2951
2952 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2953 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2954 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
2955 vir_get_stage_name(c),
2956 c->program_id, c->variant_id);
2957 vir_dump(c);
2958 fprintf(stderr, "\n");
2959 }
2960
2961 vir_optimize(c);
2962
2963 vir_check_payload_w(c);
2964
2965 /* XXX perf: On VC4, we do a VIR-level instruction scheduling here.
2966 * We used that on that platform to pipeline TMU writes and reduce the
2967 * number of thread switches, as well as try (mostly successfully) to
2968 * reduce maximum register pressure to allow more threads. We should
2969 * do something of that sort for V3D -- either instruction scheduling
2970 * here, or delay the the THRSW and LDTMUs from our texture
2971 * instructions until the results are needed.
2972 */
2973
2974 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2975 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2976 fprintf(stderr, "%s prog %d/%d VIR:\n",
2977 vir_get_stage_name(c),
2978 c->program_id, c->variant_id);
2979 vir_dump(c);
2980 fprintf(stderr, "\n");
2981 }
2982
2983 /* Attempt to allocate registers for the temporaries. If we fail,
2984 * reduce thread count and try again.
2985 */
2986 int min_threads = (c->devinfo->ver >= 41) ? 2 : 1;
2987 struct qpu_reg *temp_registers;
2988 while (true) {
2989 bool spilled;
2990 temp_registers = v3d_register_allocate(c, &spilled);
2991 if (spilled)
2992 continue;
2993
2994 if (temp_registers)
2995 break;
2996
2997 if (c->threads == min_threads) {
2998 fprintf(stderr, "Failed to register allocate at %d threads:\n",
2999 c->threads);
3000 vir_dump(c);
3001 c->failed = true;
3002 return;
3003 }
3004
3005 c->threads /= 2;
3006
3007 if (c->threads == 1)
3008 vir_remove_thrsw(c);
3009 }
3010
3011 if (c->spills &&
3012 (V3D_DEBUG & (V3D_DEBUG_VIR |
3013 v3d_debug_flag_for_shader_stage(c->s->info.stage)))) {
3014 fprintf(stderr, "%s prog %d/%d spilled VIR:\n",
3015 vir_get_stage_name(c),
3016 c->program_id, c->variant_id);
3017 vir_dump(c);
3018 fprintf(stderr, "\n");
3019 }
3020
3021 v3d_vir_to_qpu(c, temp_registers);
3022 }