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v3d: Delay emitting ldvpm on V3D 4.x until it's actually used.
[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
34
35 #define GENERAL_TMU_LOOKUP_PER_QUAD (0 << 7)
36 #define GENERAL_TMU_LOOKUP_PER_PIXEL (1 << 7)
37 #define GENERAL_TMU_READ_OP_PREFETCH (0 << 3)
38 #define GENERAL_TMU_READ_OP_CACHE_CLEAR (1 << 3)
39 #define GENERAL_TMU_READ_OP_CACHE_FLUSH (3 << 3)
40 #define GENERAL_TMU_READ_OP_CACHE_CLEAN (3 << 3)
41 #define GENERAL_TMU_READ_OP_CACHE_L1T_CLEAR (4 << 3)
42 #define GENERAL_TMU_READ_OP_CACHE_L1T_FLUSH_AGGREGATION (5 << 3)
43 #define GENERAL_TMU_READ_OP_ATOMIC_INC (8 << 3)
44 #define GENERAL_TMU_READ_OP_ATOMIC_DEC (9 << 3)
45 #define GENERAL_TMU_READ_OP_ATOMIC_NOT (10 << 3)
46 #define GENERAL_TMU_READ_OP_READ (15 << 3)
47 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_I (0 << 0)
48 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_I (1 << 0)
49 #define GENERAL_TMU_LOOKUP_TYPE_VEC2 (2 << 0)
50 #define GENERAL_TMU_LOOKUP_TYPE_VEC3 (3 << 0)
51 #define GENERAL_TMU_LOOKUP_TYPE_VEC4 (4 << 0)
52 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_UI (5 << 0)
53 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_UI (6 << 0)
54 #define GENERAL_TMU_LOOKUP_TYPE_32BIT_UI (7 << 0)
55
56 #define GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP (0 << 3)
57 #define GENERAL_TMU_WRITE_OP_ATOMIC_SUB_WRAP (1 << 3)
58 #define GENERAL_TMU_WRITE_OP_ATOMIC_XCHG (2 << 3)
59 #define GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG (3 << 3)
60 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMIN (4 << 3)
61 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMAX (5 << 3)
62 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMIN (6 << 3)
63 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMAX (7 << 3)
64 #define GENERAL_TMU_WRITE_OP_ATOMIC_AND (8 << 3)
65 #define GENERAL_TMU_WRITE_OP_ATOMIC_OR (9 << 3)
66 #define GENERAL_TMU_WRITE_OP_ATOMIC_XOR (10 << 3)
67 #define GENERAL_TMU_WRITE_OP_WRITE (15 << 3)
68
69 #define V3D_TSY_SET_QUORUM 0
70 #define V3D_TSY_INC_WAITERS 1
71 #define V3D_TSY_DEC_WAITERS 2
72 #define V3D_TSY_INC_QUORUM 3
73 #define V3D_TSY_DEC_QUORUM 4
74 #define V3D_TSY_FREE_ALL 5
75 #define V3D_TSY_RELEASE 6
76 #define V3D_TSY_ACQUIRE 7
77 #define V3D_TSY_WAIT 8
78 #define V3D_TSY_WAIT_INC 9
79 #define V3D_TSY_WAIT_CHECK 10
80 #define V3D_TSY_WAIT_INC_CHECK 11
81 #define V3D_TSY_WAIT_CV 12
82 #define V3D_TSY_INC_SEMAPHORE 13
83 #define V3D_TSY_DEC_SEMAPHORE 14
84 #define V3D_TSY_SET_QUORUM_FREE_ALL 15
85
86 static void
87 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
88
89 static void
90 resize_qreg_array(struct v3d_compile *c,
91 struct qreg **regs,
92 uint32_t *size,
93 uint32_t decl_size)
94 {
95 if (*size >= decl_size)
96 return;
97
98 uint32_t old_size = *size;
99 *size = MAX2(*size * 2, decl_size);
100 *regs = reralloc(c, *regs, struct qreg, *size);
101 if (!*regs) {
102 fprintf(stderr, "Malloc failure\n");
103 abort();
104 }
105
106 for (uint32_t i = old_size; i < *size; i++)
107 (*regs)[i] = c->undef;
108 }
109
110 void
111 vir_emit_thrsw(struct v3d_compile *c)
112 {
113 if (c->threads == 1)
114 return;
115
116 /* Always thread switch after each texture operation for now.
117 *
118 * We could do better by batching a bunch of texture fetches up and
119 * then doing one thread switch and collecting all their results
120 * afterward.
121 */
122 c->last_thrsw = vir_NOP(c);
123 c->last_thrsw->qpu.sig.thrsw = true;
124 c->last_thrsw_at_top_level = !c->in_control_flow;
125 }
126
127 static uint32_t
128 v3d_general_tmu_op(nir_intrinsic_instr *instr)
129 {
130 switch (instr->intrinsic) {
131 case nir_intrinsic_load_ssbo:
132 case nir_intrinsic_load_ubo:
133 case nir_intrinsic_load_uniform:
134 case nir_intrinsic_load_shared:
135 return GENERAL_TMU_READ_OP_READ;
136 case nir_intrinsic_store_ssbo:
137 case nir_intrinsic_store_shared:
138 return GENERAL_TMU_WRITE_OP_WRITE;
139 case nir_intrinsic_ssbo_atomic_add:
140 case nir_intrinsic_shared_atomic_add:
141 return GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP;
142 case nir_intrinsic_ssbo_atomic_imin:
143 case nir_intrinsic_shared_atomic_imin:
144 return GENERAL_TMU_WRITE_OP_ATOMIC_SMIN;
145 case nir_intrinsic_ssbo_atomic_umin:
146 case nir_intrinsic_shared_atomic_umin:
147 return GENERAL_TMU_WRITE_OP_ATOMIC_UMIN;
148 case nir_intrinsic_ssbo_atomic_imax:
149 case nir_intrinsic_shared_atomic_imax:
150 return GENERAL_TMU_WRITE_OP_ATOMIC_SMAX;
151 case nir_intrinsic_ssbo_atomic_umax:
152 case nir_intrinsic_shared_atomic_umax:
153 return GENERAL_TMU_WRITE_OP_ATOMIC_UMAX;
154 case nir_intrinsic_ssbo_atomic_and:
155 case nir_intrinsic_shared_atomic_and:
156 return GENERAL_TMU_WRITE_OP_ATOMIC_AND;
157 case nir_intrinsic_ssbo_atomic_or:
158 case nir_intrinsic_shared_atomic_or:
159 return GENERAL_TMU_WRITE_OP_ATOMIC_OR;
160 case nir_intrinsic_ssbo_atomic_xor:
161 case nir_intrinsic_shared_atomic_xor:
162 return GENERAL_TMU_WRITE_OP_ATOMIC_XOR;
163 case nir_intrinsic_ssbo_atomic_exchange:
164 case nir_intrinsic_shared_atomic_exchange:
165 return GENERAL_TMU_WRITE_OP_ATOMIC_XCHG;
166 case nir_intrinsic_ssbo_atomic_comp_swap:
167 case nir_intrinsic_shared_atomic_comp_swap:
168 return GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG;
169 default:
170 unreachable("unknown intrinsic op");
171 }
172 }
173
174 /**
175 * Implements indirect uniform loads and SSBO accesses through the TMU general
176 * memory access interface.
177 */
178 static void
179 ntq_emit_tmu_general(struct v3d_compile *c, nir_intrinsic_instr *instr,
180 bool is_shared)
181 {
182 /* XXX perf: We should turn add/sub of 1 to inc/dec. Perhaps NIR
183 * wants to have support for inc/dec?
184 */
185
186 uint32_t tmu_op = v3d_general_tmu_op(instr);
187 bool is_store = (instr->intrinsic == nir_intrinsic_store_ssbo ||
188 instr->intrinsic == nir_intrinsic_store_shared);
189 bool has_index = !is_shared;
190
191 int offset_src;
192 int tmu_writes = 1; /* address */
193 if (instr->intrinsic == nir_intrinsic_load_uniform) {
194 offset_src = 0;
195 } else if (instr->intrinsic == nir_intrinsic_load_ssbo ||
196 instr->intrinsic == nir_intrinsic_load_ubo ||
197 instr->intrinsic == nir_intrinsic_load_shared) {
198 offset_src = 0 + has_index;
199 } else if (is_store) {
200 offset_src = 1 + has_index;
201 for (int i = 0; i < instr->num_components; i++) {
202 vir_MOV_dest(c,
203 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
204 ntq_get_src(c, instr->src[0], i));
205 tmu_writes++;
206 }
207 } else {
208 offset_src = 0 + has_index;
209 vir_MOV_dest(c,
210 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
211 ntq_get_src(c, instr->src[1 + has_index], 0));
212 tmu_writes++;
213 if (tmu_op == GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG) {
214 vir_MOV_dest(c,
215 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
216 ntq_get_src(c, instr->src[2 + has_index],
217 0));
218 tmu_writes++;
219 }
220 }
221
222 /* Make sure we won't exceed the 16-entry TMU fifo if each thread is
223 * storing at the same time.
224 */
225 while (tmu_writes > 16 / c->threads)
226 c->threads /= 2;
227
228 struct qreg offset;
229 if (instr->intrinsic == nir_intrinsic_load_uniform) {
230 offset = vir_uniform(c, QUNIFORM_UBO_ADDR, 0);
231
232 /* Find what variable in the default uniform block this
233 * uniform load is coming from.
234 */
235 uint32_t base = nir_intrinsic_base(instr);
236 int i;
237 struct v3d_ubo_range *range = NULL;
238 for (i = 0; i < c->num_ubo_ranges; i++) {
239 range = &c->ubo_ranges[i];
240 if (base >= range->src_offset &&
241 base < range->src_offset + range->size) {
242 break;
243 }
244 }
245 /* The driver-location-based offset always has to be within a
246 * declared uniform range.
247 */
248 assert(i != c->num_ubo_ranges);
249 if (!c->ubo_range_used[i]) {
250 c->ubo_range_used[i] = true;
251 range->dst_offset = c->next_ubo_dst_offset;
252 c->next_ubo_dst_offset += range->size;
253 }
254
255 base = base - range->src_offset + range->dst_offset;
256
257 if (base != 0)
258 offset = vir_ADD(c, offset, vir_uniform_ui(c, base));
259 } else if (instr->intrinsic == nir_intrinsic_load_ubo) {
260 /* Note that QUNIFORM_UBO_ADDR takes a UBO index shifted up by
261 * 1 (0 is gallium's constant buffer 0).
262 */
263 offset = vir_uniform(c, QUNIFORM_UBO_ADDR,
264 nir_src_as_uint(instr->src[0]) + 1);
265 } else if (is_shared) {
266 /* Shared variables have no buffer index, and all start from a
267 * common base that we set up at the start of dispatch
268 */
269 offset = c->cs_shared_offset;
270 } else {
271 offset = vir_uniform(c, QUNIFORM_SSBO_OFFSET,
272 nir_src_as_uint(instr->src[is_store ?
273 1 : 0]));
274 }
275
276 uint32_t config = (0xffffff00 |
277 tmu_op |
278 GENERAL_TMU_LOOKUP_PER_PIXEL);
279 if (instr->num_components == 1) {
280 config |= GENERAL_TMU_LOOKUP_TYPE_32BIT_UI;
281 } else {
282 config |= (GENERAL_TMU_LOOKUP_TYPE_VEC2 +
283 instr->num_components - 2);
284 }
285
286 if (vir_in_nonuniform_control_flow(c)) {
287 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
288 V3D_QPU_PF_PUSHZ);
289 }
290
291 struct qreg dest;
292 if (config == ~0)
293 dest = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA);
294 else
295 dest = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUAU);
296
297 struct qinst *tmu;
298 if (nir_src_is_const(instr->src[offset_src]) &&
299 nir_src_as_uint(instr->src[offset_src]) == 0) {
300 tmu = vir_MOV_dest(c, dest, offset);
301 } else {
302 tmu = vir_ADD_dest(c, dest,
303 offset,
304 ntq_get_src(c, instr->src[offset_src], 0));
305 }
306
307 if (config != ~0) {
308 tmu->src[vir_get_implicit_uniform_src(tmu)] =
309 vir_uniform_ui(c, config);
310 }
311
312 if (vir_in_nonuniform_control_flow(c))
313 vir_set_cond(tmu, V3D_QPU_COND_IFA);
314
315 vir_emit_thrsw(c);
316
317 /* Read the result, or wait for the TMU op to complete. */
318 for (int i = 0; i < nir_intrinsic_dest_components(instr); i++)
319 ntq_store_dest(c, &instr->dest, i, vir_MOV(c, vir_LDTMU(c)));
320
321 if (nir_intrinsic_dest_components(instr) == 0)
322 vir_TMUWT(c);
323 }
324
325 static struct qreg *
326 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
327 {
328 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
329 def->num_components);
330 _mesa_hash_table_insert(c->def_ht, def, qregs);
331 return qregs;
332 }
333
334 /**
335 * This function is responsible for getting VIR results into the associated
336 * storage for a NIR instruction.
337 *
338 * If it's a NIR SSA def, then we just set the associated hash table entry to
339 * the new result.
340 *
341 * If it's a NIR reg, then we need to update the existing qreg assigned to the
342 * NIR destination with the incoming value. To do that without introducing
343 * new MOVs, we require that the incoming qreg either be a uniform, or be
344 * SSA-defined by the previous VIR instruction in the block and rewritable by
345 * this function. That lets us sneak ahead and insert the SF flag beforehand
346 * (knowing that the previous instruction doesn't depend on flags) and rewrite
347 * its destination to be the NIR reg's destination
348 */
349 void
350 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
351 struct qreg result)
352 {
353 struct qinst *last_inst = NULL;
354 if (!list_empty(&c->cur_block->instructions))
355 last_inst = (struct qinst *)c->cur_block->instructions.prev;
356
357 assert(result.file == QFILE_UNIF ||
358 (result.file == QFILE_TEMP &&
359 last_inst && last_inst == c->defs[result.index]));
360
361 if (dest->is_ssa) {
362 assert(chan < dest->ssa.num_components);
363
364 struct qreg *qregs;
365 struct hash_entry *entry =
366 _mesa_hash_table_search(c->def_ht, &dest->ssa);
367
368 if (entry)
369 qregs = entry->data;
370 else
371 qregs = ntq_init_ssa_def(c, &dest->ssa);
372
373 qregs[chan] = result;
374 } else {
375 nir_register *reg = dest->reg.reg;
376 assert(dest->reg.base_offset == 0);
377 assert(reg->num_array_elems == 0);
378 struct hash_entry *entry =
379 _mesa_hash_table_search(c->def_ht, reg);
380 struct qreg *qregs = entry->data;
381
382 /* Insert a MOV if the source wasn't an SSA def in the
383 * previous instruction.
384 */
385 if (result.file == QFILE_UNIF) {
386 result = vir_MOV(c, result);
387 last_inst = c->defs[result.index];
388 }
389
390 /* We know they're both temps, so just rewrite index. */
391 c->defs[last_inst->dst.index] = NULL;
392 last_inst->dst.index = qregs[chan].index;
393
394 /* If we're in control flow, then make this update of the reg
395 * conditional on the execution mask.
396 */
397 if (vir_in_nonuniform_control_flow(c)) {
398 last_inst->dst.index = qregs[chan].index;
399
400 /* Set the flags to the current exec mask.
401 */
402 c->cursor = vir_before_inst(last_inst);
403 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
404 V3D_QPU_PF_PUSHZ);
405 c->cursor = vir_after_inst(last_inst);
406
407 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
408 last_inst->cond_is_exec_mask = true;
409 }
410 }
411 }
412
413 struct qreg
414 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
415 {
416 struct hash_entry *entry;
417 if (src.is_ssa) {
418 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
419 assert(i < src.ssa->num_components);
420 } else {
421 nir_register *reg = src.reg.reg;
422 entry = _mesa_hash_table_search(c->def_ht, reg);
423 assert(reg->num_array_elems == 0);
424 assert(src.reg.base_offset == 0);
425 assert(i < reg->num_components);
426 }
427
428 struct qreg *qregs = entry->data;
429 return qregs[i];
430 }
431
432 static struct qreg
433 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
434 unsigned src)
435 {
436 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
437 unsigned chan = ffs(instr->dest.write_mask) - 1;
438 struct qreg r = ntq_get_src(c, instr->src[src].src,
439 instr->src[src].swizzle[chan]);
440
441 assert(!instr->src[src].abs);
442 assert(!instr->src[src].negate);
443
444 return r;
445 };
446
447 static struct qreg
448 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
449 {
450 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
451 }
452
453 static void
454 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
455 {
456 unsigned unit = instr->texture_index;
457 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
458 int dest_size = nir_tex_instr_dest_size(instr);
459
460 struct qreg lod = c->undef;
461 if (lod_index != -1)
462 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
463
464 for (int i = 0; i < dest_size; i++) {
465 assert(i < 3);
466 enum quniform_contents contents;
467
468 if (instr->is_array && i == dest_size - 1)
469 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
470 else
471 contents = QUNIFORM_TEXTURE_WIDTH + i;
472
473 struct qreg size = vir_uniform(c, contents, unit);
474
475 switch (instr->sampler_dim) {
476 case GLSL_SAMPLER_DIM_1D:
477 case GLSL_SAMPLER_DIM_2D:
478 case GLSL_SAMPLER_DIM_MS:
479 case GLSL_SAMPLER_DIM_3D:
480 case GLSL_SAMPLER_DIM_CUBE:
481 /* Don't minify the array size. */
482 if (!(instr->is_array && i == dest_size - 1)) {
483 size = ntq_minify(c, size, lod);
484 }
485 break;
486
487 case GLSL_SAMPLER_DIM_RECT:
488 /* There's no LOD field for rects */
489 break;
490
491 default:
492 unreachable("Bad sampler type");
493 }
494
495 ntq_store_dest(c, &instr->dest, i, size);
496 }
497 }
498
499 static void
500 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
501 {
502 unsigned unit = instr->texture_index;
503
504 /* Since each texture sampling op requires uploading uniforms to
505 * reference the texture, there's no HW support for texture size and
506 * you just upload uniforms containing the size.
507 */
508 switch (instr->op) {
509 case nir_texop_query_levels:
510 ntq_store_dest(c, &instr->dest, 0,
511 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
512 return;
513 case nir_texop_txs:
514 ntq_emit_txs(c, instr);
515 return;
516 default:
517 break;
518 }
519
520 if (c->devinfo->ver >= 40)
521 v3d40_vir_emit_tex(c, instr);
522 else
523 v3d33_vir_emit_tex(c, instr);
524 }
525
526 static struct qreg
527 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
528 {
529 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
530 if (is_cos)
531 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
532
533 struct qreg periods = vir_FROUND(c, input);
534 struct qreg sin_output = vir_SIN(c, vir_FSUB(c, input, periods));
535 return vir_XOR(c, sin_output, vir_SHL(c,
536 vir_FTOIN(c, periods),
537 vir_uniform_ui(c, -1)));
538 }
539
540 static struct qreg
541 ntq_fsign(struct v3d_compile *c, struct qreg src)
542 {
543 struct qreg t = vir_get_temp(c);
544
545 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
546 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHZ);
547 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
548 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHN);
549 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
550 return vir_MOV(c, t);
551 }
552
553 static void
554 emit_fragcoord_input(struct v3d_compile *c, int attr)
555 {
556 c->inputs[attr * 4 + 0] = vir_FXCD(c);
557 c->inputs[attr * 4 + 1] = vir_FYCD(c);
558 c->inputs[attr * 4 + 2] = c->payload_z;
559 c->inputs[attr * 4 + 3] = vir_RECIP(c, c->payload_w);
560 }
561
562 static struct qreg
563 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
564 uint8_t swizzle, int array_index)
565 {
566 struct qreg r3 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R3);
567 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
568
569 struct qreg vary;
570 if (c->devinfo->ver >= 41) {
571 struct qinst *ldvary = vir_add_inst(V3D_QPU_A_NOP, c->undef,
572 c->undef, c->undef);
573 ldvary->qpu.sig.ldvary = true;
574 vary = vir_emit_def(c, ldvary);
575 } else {
576 vir_NOP(c)->qpu.sig.ldvary = true;
577 vary = r3;
578 }
579
580 /* For gl_PointCoord input or distance along a line, we'll be called
581 * with no nir_variable, and we don't count toward VPM size so we
582 * don't track an input slot.
583 */
584 if (!var) {
585 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
586 }
587
588 int i = c->num_inputs++;
589 c->input_slots[i] =
590 v3d_slot_from_slot_and_component(var->data.location +
591 array_index, swizzle);
592
593 switch (var->data.interpolation) {
594 case INTERP_MODE_NONE:
595 /* If a gl_FrontColor or gl_BackColor input has no interp
596 * qualifier, then if we're using glShadeModel(GL_FLAT) it
597 * needs to be flat shaded.
598 */
599 switch (var->data.location + array_index) {
600 case VARYING_SLOT_COL0:
601 case VARYING_SLOT_COL1:
602 case VARYING_SLOT_BFC0:
603 case VARYING_SLOT_BFC1:
604 if (c->fs_key->shade_model_flat) {
605 BITSET_SET(c->flat_shade_flags, i);
606 vir_MOV_dest(c, c->undef, vary);
607 return vir_MOV(c, r5);
608 } else {
609 return vir_FADD(c, vir_FMUL(c, vary,
610 c->payload_w), r5);
611 }
612 default:
613 break;
614 }
615 /* FALLTHROUGH */
616 case INTERP_MODE_SMOOTH:
617 if (var->data.centroid) {
618 BITSET_SET(c->centroid_flags, i);
619 return vir_FADD(c, vir_FMUL(c, vary,
620 c->payload_w_centroid), r5);
621 } else {
622 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
623 }
624 case INTERP_MODE_NOPERSPECTIVE:
625 BITSET_SET(c->noperspective_flags, i);
626 return vir_FADD(c, vir_MOV(c, vary), r5);
627 case INTERP_MODE_FLAT:
628 BITSET_SET(c->flat_shade_flags, i);
629 vir_MOV_dest(c, c->undef, vary);
630 return vir_MOV(c, r5);
631 default:
632 unreachable("Bad interp mode");
633 }
634 }
635
636 static void
637 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var,
638 int array_index)
639 {
640 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
641 int chan = var->data.location_frac + i;
642 c->inputs[attr * 4 + chan] =
643 emit_fragment_varying(c, var, chan, array_index);
644 }
645 }
646
647 static void
648 add_output(struct v3d_compile *c,
649 uint32_t decl_offset,
650 uint8_t slot,
651 uint8_t swizzle)
652 {
653 uint32_t old_array_size = c->outputs_array_size;
654 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
655 decl_offset + 1);
656
657 if (old_array_size != c->outputs_array_size) {
658 c->output_slots = reralloc(c,
659 c->output_slots,
660 struct v3d_varying_slot,
661 c->outputs_array_size);
662 }
663
664 c->output_slots[decl_offset] =
665 v3d_slot_from_slot_and_component(slot, swizzle);
666 }
667
668 static void
669 declare_uniform_range(struct v3d_compile *c, uint32_t start, uint32_t size)
670 {
671 unsigned array_id = c->num_ubo_ranges++;
672 if (array_id >= c->ubo_ranges_array_size) {
673 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
674 array_id + 1);
675 c->ubo_ranges = reralloc(c, c->ubo_ranges,
676 struct v3d_ubo_range,
677 c->ubo_ranges_array_size);
678 c->ubo_range_used = reralloc(c, c->ubo_range_used,
679 bool,
680 c->ubo_ranges_array_size);
681 }
682
683 c->ubo_ranges[array_id].dst_offset = 0;
684 c->ubo_ranges[array_id].src_offset = start;
685 c->ubo_ranges[array_id].size = size;
686 c->ubo_range_used[array_id] = false;
687 }
688
689 /**
690 * If compare_instr is a valid comparison instruction, emits the
691 * compare_instr's comparison and returns the sel_instr's return value based
692 * on the compare_instr's result.
693 */
694 static bool
695 ntq_emit_comparison(struct v3d_compile *c,
696 nir_alu_instr *compare_instr,
697 enum v3d_qpu_cond *out_cond)
698 {
699 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
700 struct qreg src1;
701 if (nir_op_infos[compare_instr->op].num_inputs > 1)
702 src1 = ntq_get_alu_src(c, compare_instr, 1);
703 bool cond_invert = false;
704 struct qreg nop = vir_nop_reg();
705
706 switch (compare_instr->op) {
707 case nir_op_feq32:
708 case nir_op_seq:
709 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
710 break;
711 case nir_op_ieq32:
712 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
713 break;
714
715 case nir_op_fne32:
716 case nir_op_sne:
717 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
718 cond_invert = true;
719 break;
720 case nir_op_ine32:
721 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
722 cond_invert = true;
723 break;
724
725 case nir_op_fge32:
726 case nir_op_sge:
727 vir_set_pf(vir_FCMP_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
728 break;
729 case nir_op_ige32:
730 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
731 cond_invert = true;
732 break;
733 case nir_op_uge32:
734 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
735 cond_invert = true;
736 break;
737
738 case nir_op_slt:
739 case nir_op_flt32:
740 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHN);
741 break;
742 case nir_op_ilt32:
743 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
744 break;
745 case nir_op_ult32:
746 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
747 break;
748
749 default:
750 return false;
751 }
752
753 *out_cond = cond_invert ? V3D_QPU_COND_IFNA : V3D_QPU_COND_IFA;
754
755 return true;
756 }
757
758 /* Finds an ALU instruction that generates our src value that could
759 * (potentially) be greedily emitted in the consuming instruction.
760 */
761 static struct nir_alu_instr *
762 ntq_get_alu_parent(nir_src src)
763 {
764 if (!src.is_ssa || src.ssa->parent_instr->type != nir_instr_type_alu)
765 return NULL;
766 nir_alu_instr *instr = nir_instr_as_alu(src.ssa->parent_instr);
767 if (!instr)
768 return NULL;
769
770 /* If the ALU instr's srcs are non-SSA, then we would have to avoid
771 * moving emission of the ALU instr down past another write of the
772 * src.
773 */
774 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
775 if (!instr->src[i].src.is_ssa)
776 return NULL;
777 }
778
779 return instr;
780 }
781
782 /* Turns a NIR bool into a condition code to predicate on. */
783 static enum v3d_qpu_cond
784 ntq_emit_bool_to_cond(struct v3d_compile *c, nir_src src)
785 {
786 nir_alu_instr *compare = ntq_get_alu_parent(src);
787 if (!compare)
788 goto out;
789
790 enum v3d_qpu_cond cond;
791 if (ntq_emit_comparison(c, compare, &cond))
792 return cond;
793
794 out:
795 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), ntq_get_src(c, src, 0)),
796 V3D_QPU_PF_PUSHZ);
797 return V3D_QPU_COND_IFNA;
798 }
799
800 static void
801 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
802 {
803 /* This should always be lowered to ALU operations for V3D. */
804 assert(!instr->dest.saturate);
805
806 /* Vectors are special in that they have non-scalarized writemasks,
807 * and just take the first swizzle channel for each argument in order
808 * into each writemask channel.
809 */
810 if (instr->op == nir_op_vec2 ||
811 instr->op == nir_op_vec3 ||
812 instr->op == nir_op_vec4) {
813 struct qreg srcs[4];
814 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
815 srcs[i] = ntq_get_src(c, instr->src[i].src,
816 instr->src[i].swizzle[0]);
817 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
818 ntq_store_dest(c, &instr->dest.dest, i,
819 vir_MOV(c, srcs[i]));
820 return;
821 }
822
823 /* General case: We can just grab the one used channel per src. */
824 struct qreg src[nir_op_infos[instr->op].num_inputs];
825 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
826 src[i] = ntq_get_alu_src(c, instr, i);
827 }
828
829 struct qreg result;
830
831 switch (instr->op) {
832 case nir_op_fmov:
833 case nir_op_imov:
834 result = vir_MOV(c, src[0]);
835 break;
836
837 case nir_op_fneg:
838 result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
839 break;
840 case nir_op_ineg:
841 result = vir_NEG(c, src[0]);
842 break;
843
844 case nir_op_fmul:
845 result = vir_FMUL(c, src[0], src[1]);
846 break;
847 case nir_op_fadd:
848 result = vir_FADD(c, src[0], src[1]);
849 break;
850 case nir_op_fsub:
851 result = vir_FSUB(c, src[0], src[1]);
852 break;
853 case nir_op_fmin:
854 result = vir_FMIN(c, src[0], src[1]);
855 break;
856 case nir_op_fmax:
857 result = vir_FMAX(c, src[0], src[1]);
858 break;
859
860 case nir_op_f2i32:
861 result = vir_FTOIZ(c, src[0]);
862 break;
863 case nir_op_f2u32:
864 result = vir_FTOUZ(c, src[0]);
865 break;
866 case nir_op_i2f32:
867 result = vir_ITOF(c, src[0]);
868 break;
869 case nir_op_u2f32:
870 result = vir_UTOF(c, src[0]);
871 break;
872 case nir_op_b2f32:
873 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
874 break;
875 case nir_op_b2i32:
876 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
877 break;
878 case nir_op_i2b32:
879 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), src[0]),
880 V3D_QPU_PF_PUSHZ);
881 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
882 vir_uniform_ui(c, ~0),
883 vir_uniform_ui(c, 0)));
884 case nir_op_f2b32:
885 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src[0]),
886 V3D_QPU_PF_PUSHZ);
887 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
888 vir_uniform_ui(c, ~0),
889 vir_uniform_ui(c, 0)));
890 break;
891
892 case nir_op_iadd:
893 result = vir_ADD(c, src[0], src[1]);
894 break;
895 case nir_op_ushr:
896 result = vir_SHR(c, src[0], src[1]);
897 break;
898 case nir_op_isub:
899 result = vir_SUB(c, src[0], src[1]);
900 break;
901 case nir_op_ishr:
902 result = vir_ASR(c, src[0], src[1]);
903 break;
904 case nir_op_ishl:
905 result = vir_SHL(c, src[0], src[1]);
906 break;
907 case nir_op_imin:
908 result = vir_MIN(c, src[0], src[1]);
909 break;
910 case nir_op_umin:
911 result = vir_UMIN(c, src[0], src[1]);
912 break;
913 case nir_op_imax:
914 result = vir_MAX(c, src[0], src[1]);
915 break;
916 case nir_op_umax:
917 result = vir_UMAX(c, src[0], src[1]);
918 break;
919 case nir_op_iand:
920 result = vir_AND(c, src[0], src[1]);
921 break;
922 case nir_op_ior:
923 result = vir_OR(c, src[0], src[1]);
924 break;
925 case nir_op_ixor:
926 result = vir_XOR(c, src[0], src[1]);
927 break;
928 case nir_op_inot:
929 result = vir_NOT(c, src[0]);
930 break;
931
932 case nir_op_ufind_msb:
933 result = vir_SUB(c, vir_uniform_ui(c, 31), vir_CLZ(c, src[0]));
934 break;
935
936 case nir_op_imul:
937 result = vir_UMUL(c, src[0], src[1]);
938 break;
939
940 case nir_op_seq:
941 case nir_op_sne:
942 case nir_op_sge:
943 case nir_op_slt: {
944 enum v3d_qpu_cond cond;
945 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
946 assert(ok);
947 result = vir_MOV(c, vir_SEL(c, cond,
948 vir_uniform_f(c, 1.0),
949 vir_uniform_f(c, 0.0)));
950 break;
951 }
952
953 case nir_op_feq32:
954 case nir_op_fne32:
955 case nir_op_fge32:
956 case nir_op_flt32:
957 case nir_op_ieq32:
958 case nir_op_ine32:
959 case nir_op_ige32:
960 case nir_op_uge32:
961 case nir_op_ilt32:
962 case nir_op_ult32: {
963 enum v3d_qpu_cond cond;
964 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
965 assert(ok);
966 result = vir_MOV(c, vir_SEL(c, cond,
967 vir_uniform_ui(c, ~0),
968 vir_uniform_ui(c, 0)));
969 break;
970 }
971
972 case nir_op_b32csel:
973 result = vir_MOV(c,
974 vir_SEL(c,
975 ntq_emit_bool_to_cond(c, instr->src[0].src),
976 src[1], src[2]));
977 break;
978
979 case nir_op_fcsel:
980 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), src[0]),
981 V3D_QPU_PF_PUSHZ);
982 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
983 src[1], src[2]));
984 break;
985
986 case nir_op_frcp:
987 result = vir_RECIP(c, src[0]);
988 break;
989 case nir_op_frsq:
990 result = vir_RSQRT(c, src[0]);
991 break;
992 case nir_op_fexp2:
993 result = vir_EXP(c, src[0]);
994 break;
995 case nir_op_flog2:
996 result = vir_LOG(c, src[0]);
997 break;
998
999 case nir_op_fceil:
1000 result = vir_FCEIL(c, src[0]);
1001 break;
1002 case nir_op_ffloor:
1003 result = vir_FFLOOR(c, src[0]);
1004 break;
1005 case nir_op_fround_even:
1006 result = vir_FROUND(c, src[0]);
1007 break;
1008 case nir_op_ftrunc:
1009 result = vir_FTRUNC(c, src[0]);
1010 break;
1011
1012 case nir_op_fsin:
1013 result = ntq_fsincos(c, src[0], false);
1014 break;
1015 case nir_op_fcos:
1016 result = ntq_fsincos(c, src[0], true);
1017 break;
1018
1019 case nir_op_fsign:
1020 result = ntq_fsign(c, src[0]);
1021 break;
1022
1023 case nir_op_fabs: {
1024 result = vir_FMOV(c, src[0]);
1025 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
1026 break;
1027 }
1028
1029 case nir_op_iabs:
1030 result = vir_MAX(c, src[0],
1031 vir_SUB(c, vir_uniform_ui(c, 0), src[0]));
1032 break;
1033
1034 case nir_op_fddx:
1035 case nir_op_fddx_coarse:
1036 case nir_op_fddx_fine:
1037 result = vir_FDX(c, src[0]);
1038 break;
1039
1040 case nir_op_fddy:
1041 case nir_op_fddy_coarse:
1042 case nir_op_fddy_fine:
1043 result = vir_FDY(c, src[0]);
1044 break;
1045
1046 case nir_op_uadd_carry:
1047 vir_set_pf(vir_ADD_dest(c, vir_nop_reg(), src[0], src[1]),
1048 V3D_QPU_PF_PUSHC);
1049 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1050 vir_uniform_ui(c, ~0),
1051 vir_uniform_ui(c, 0)));
1052 break;
1053
1054 case nir_op_pack_half_2x16_split:
1055 result = vir_VFPACK(c, src[0], src[1]);
1056 break;
1057
1058 case nir_op_unpack_half_2x16_split_x:
1059 result = vir_FMOV(c, src[0]);
1060 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_L);
1061 break;
1062
1063 case nir_op_unpack_half_2x16_split_y:
1064 result = vir_FMOV(c, src[0]);
1065 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_H);
1066 break;
1067
1068 default:
1069 fprintf(stderr, "unknown NIR ALU inst: ");
1070 nir_print_instr(&instr->instr, stderr);
1071 fprintf(stderr, "\n");
1072 abort();
1073 }
1074
1075 /* We have a scalar result, so the instruction should only have a
1076 * single channel written to.
1077 */
1078 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
1079 ntq_store_dest(c, &instr->dest.dest,
1080 ffs(instr->dest.write_mask) - 1, result);
1081 }
1082
1083 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
1084 * specifier. They come from a register that's preloaded with 0xffffffff
1085 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
1086 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
1087 */
1088 #define TLB_TYPE_F16_COLOR (3 << 6)
1089 #define TLB_TYPE_I32_COLOR (1 << 6)
1090 #define TLB_TYPE_F32_COLOR (0 << 6)
1091 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
1092 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
1093 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
1094 #define TLB_F16_SWAP_HI_LO (1 << 1)
1095 #define TLB_VEC_SIZE_4_F16 (1 << 0)
1096 #define TLB_VEC_SIZE_2_F16 (0 << 0)
1097 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
1098
1099 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
1100 * flag is set.
1101 */
1102 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
1103 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
1104 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
1105 #define TLB_V42_DEPTH_TYPE_INVARIANT (0 << 3) /* Unmodified sideband input used */
1106 #define TLB_V42_DEPTH_TYPE_PER_PIXEL (1 << 3) /* QPU result used */
1107
1108 /* Stencil is a single 32-bit write. */
1109 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1110
1111 static void
1112 emit_frag_end(struct v3d_compile *c)
1113 {
1114 /* XXX
1115 if (c->output_sample_mask_index != -1) {
1116 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1117 }
1118 */
1119
1120 bool has_any_tlb_color_write = false;
1121 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1122 if (c->fs_key->cbufs & (1 << rt) && c->output_color_var[rt])
1123 has_any_tlb_color_write = true;
1124 }
1125
1126 if (c->fs_key->sample_alpha_to_coverage && c->output_color_var[0]) {
1127 struct nir_variable *var = c->output_color_var[0];
1128 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1129
1130 vir_SETMSF_dest(c, vir_nop_reg(),
1131 vir_AND(c,
1132 vir_MSF(c),
1133 vir_FTOC(c, color[3])));
1134 }
1135
1136 if (c->output_position_index != -1) {
1137 struct qinst *inst = vir_MOV_dest(c,
1138 vir_reg(QFILE_TLBU, 0),
1139 c->outputs[c->output_position_index]);
1140 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1141
1142 if (c->devinfo->ver >= 42) {
1143 tlb_specifier |= (TLB_V42_DEPTH_TYPE_PER_PIXEL |
1144 TLB_SAMPLE_MODE_PER_PIXEL);
1145 } else
1146 tlb_specifier |= TLB_DEPTH_TYPE_PER_PIXEL;
1147
1148 inst->src[vir_get_implicit_uniform_src(inst)] =
1149 vir_uniform_ui(c, tlb_specifier | 0xffffff00);
1150 c->writes_z = true;
1151 } else if (c->s->info.fs.uses_discard ||
1152 !c->s->info.fs.early_fragment_tests ||
1153 c->fs_key->sample_alpha_to_coverage ||
1154 !has_any_tlb_color_write) {
1155 /* Emit passthrough Z if it needed to be delayed until shader
1156 * end due to potential discards.
1157 *
1158 * Since (single-threaded) fragment shaders always need a TLB
1159 * write, emit passthrouh Z if we didn't have any color
1160 * buffers and flag us as potentially discarding, so that we
1161 * can use Z as the TLB write.
1162 */
1163 c->s->info.fs.uses_discard = true;
1164
1165 struct qinst *inst = vir_MOV_dest(c,
1166 vir_reg(QFILE_TLBU, 0),
1167 vir_nop_reg());
1168 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1169
1170 if (c->devinfo->ver >= 42) {
1171 /* The spec says the PER_PIXEL flag is ignored for
1172 * invariant writes, but the simulator demands it.
1173 */
1174 tlb_specifier |= (TLB_V42_DEPTH_TYPE_INVARIANT |
1175 TLB_SAMPLE_MODE_PER_PIXEL);
1176 } else {
1177 tlb_specifier |= TLB_DEPTH_TYPE_INVARIANT;
1178 }
1179
1180 inst->src[vir_get_implicit_uniform_src(inst)] =
1181 vir_uniform_ui(c, tlb_specifier | 0xffffff00);
1182 c->writes_z = true;
1183 }
1184
1185 /* XXX: Performance improvement: Merge Z write and color writes TLB
1186 * uniform setup
1187 */
1188
1189 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1190 if (!(c->fs_key->cbufs & (1 << rt)) || !c->output_color_var[rt])
1191 continue;
1192
1193 nir_variable *var = c->output_color_var[rt];
1194 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1195 int num_components = glsl_get_vector_elements(var->type);
1196 uint32_t conf = 0xffffff00;
1197 struct qinst *inst;
1198
1199 conf |= TLB_SAMPLE_MODE_PER_PIXEL;
1200 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1201
1202 if (c->fs_key->swap_color_rb & (1 << rt))
1203 num_components = MAX2(num_components, 3);
1204
1205 assert(num_components != 0);
1206 switch (glsl_get_base_type(var->type)) {
1207 case GLSL_TYPE_UINT:
1208 case GLSL_TYPE_INT:
1209 /* The F32 vs I32 distinction was dropped in 4.2. */
1210 if (c->devinfo->ver < 42)
1211 conf |= TLB_TYPE_I32_COLOR;
1212 else
1213 conf |= TLB_TYPE_F32_COLOR;
1214 conf |= ((num_components - 1) <<
1215 TLB_VEC_SIZE_MINUS_1_SHIFT);
1216
1217 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
1218 inst->src[vir_get_implicit_uniform_src(inst)] =
1219 vir_uniform_ui(c, conf);
1220
1221 for (int i = 1; i < num_components; i++) {
1222 inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
1223 color[i]);
1224 }
1225 break;
1226
1227 default: {
1228 struct qreg r = color[0];
1229 struct qreg g = color[1];
1230 struct qreg b = color[2];
1231 struct qreg a = color[3];
1232
1233 if (c->fs_key->f32_color_rb & (1 << rt)) {
1234 conf |= TLB_TYPE_F32_COLOR;
1235 conf |= ((num_components - 1) <<
1236 TLB_VEC_SIZE_MINUS_1_SHIFT);
1237 } else {
1238 conf |= TLB_TYPE_F16_COLOR;
1239 conf |= TLB_F16_SWAP_HI_LO;
1240 if (num_components >= 3)
1241 conf |= TLB_VEC_SIZE_4_F16;
1242 else
1243 conf |= TLB_VEC_SIZE_2_F16;
1244 }
1245
1246 if (c->fs_key->swap_color_rb & (1 << rt)) {
1247 r = color[2];
1248 b = color[0];
1249 }
1250
1251 if (c->fs_key->sample_alpha_to_one)
1252 a = vir_uniform_f(c, 1.0);
1253
1254 if (c->fs_key->f32_color_rb & (1 << rt)) {
1255 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), r);
1256 inst->src[vir_get_implicit_uniform_src(inst)] =
1257 vir_uniform_ui(c, conf);
1258
1259 if (num_components >= 2)
1260 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), g);
1261 if (num_components >= 3)
1262 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), b);
1263 if (num_components >= 4)
1264 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), a);
1265 } else {
1266 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), r, g);
1267 if (conf != ~0) {
1268 inst->dst.file = QFILE_TLBU;
1269 inst->src[vir_get_implicit_uniform_src(inst)] =
1270 vir_uniform_ui(c, conf);
1271 }
1272
1273 if (num_components >= 3)
1274 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), b, a);
1275 }
1276 break;
1277 }
1278 }
1279 }
1280 }
1281
1282 static void
1283 vir_VPM_WRITE(struct v3d_compile *c, struct qreg val, uint32_t *vpm_index)
1284 {
1285 if (c->devinfo->ver >= 40) {
1286 vir_STVPMV(c, vir_uniform_ui(c, *vpm_index), val);
1287 *vpm_index = *vpm_index + 1;
1288 } else {
1289 vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM), val);
1290 }
1291
1292 c->num_vpm_writes++;
1293 }
1294
1295 static void
1296 emit_scaled_viewport_write(struct v3d_compile *c, struct qreg rcp_w,
1297 uint32_t *vpm_index)
1298 {
1299 for (int i = 0; i < 2; i++) {
1300 struct qreg coord = c->outputs[c->output_position_index + i];
1301 coord = vir_FMUL(c, coord,
1302 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i,
1303 0));
1304 coord = vir_FMUL(c, coord, rcp_w);
1305 vir_VPM_WRITE(c, vir_FTOIN(c, coord), vpm_index);
1306 }
1307
1308 }
1309
1310 static void
1311 emit_zs_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index)
1312 {
1313 struct qreg zscale = vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1314 struct qreg zoffset = vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1315
1316 struct qreg z = c->outputs[c->output_position_index + 2];
1317 z = vir_FMUL(c, z, zscale);
1318 z = vir_FMUL(c, z, rcp_w);
1319 z = vir_FADD(c, z, zoffset);
1320 vir_VPM_WRITE(c, z, vpm_index);
1321 }
1322
1323 static void
1324 emit_rcp_wc_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index)
1325 {
1326 vir_VPM_WRITE(c, rcp_w, vpm_index);
1327 }
1328
1329 static void
1330 emit_point_size_write(struct v3d_compile *c, uint32_t *vpm_index)
1331 {
1332 struct qreg point_size;
1333
1334 if (c->output_point_size_index != -1)
1335 point_size = c->outputs[c->output_point_size_index];
1336 else
1337 point_size = vir_uniform_f(c, 1.0);
1338
1339 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1340 * BCM21553).
1341 */
1342 point_size = vir_FMAX(c, point_size, vir_uniform_f(c, .125));
1343
1344 vir_VPM_WRITE(c, point_size, vpm_index);
1345 }
1346
1347 static void
1348 emit_vpm_write_setup(struct v3d_compile *c)
1349 {
1350 if (c->devinfo->ver >= 40)
1351 return;
1352
1353 v3d33_vir_vpm_write_setup(c);
1354 }
1355
1356 /**
1357 * Sets up c->outputs[c->output_position_index] for the vertex shader
1358 * epilogue, if an output vertex position wasn't specified in the user's
1359 * shader. This may be the case for transform feedback with rasterizer
1360 * discard enabled.
1361 */
1362 static void
1363 setup_default_position(struct v3d_compile *c)
1364 {
1365 if (c->output_position_index != -1)
1366 return;
1367
1368 c->output_position_index = c->outputs_array_size;
1369 for (int i = 0; i < 4; i++) {
1370 add_output(c,
1371 c->output_position_index + i,
1372 VARYING_SLOT_POS, i);
1373 }
1374 }
1375
1376 static void
1377 emit_vert_end(struct v3d_compile *c)
1378 {
1379 setup_default_position(c);
1380
1381 uint32_t vpm_index = 0;
1382 struct qreg rcp_w = vir_RECIP(c,
1383 c->outputs[c->output_position_index + 3]);
1384
1385 emit_vpm_write_setup(c);
1386
1387 if (c->vs_key->is_coord) {
1388 for (int i = 0; i < 4; i++)
1389 vir_VPM_WRITE(c, c->outputs[c->output_position_index + i],
1390 &vpm_index);
1391 emit_scaled_viewport_write(c, rcp_w, &vpm_index);
1392 if (c->vs_key->per_vertex_point_size) {
1393 emit_point_size_write(c, &vpm_index);
1394 /* emit_rcp_wc_write(c, rcp_w); */
1395 }
1396 /* XXX: Z-only rendering */
1397 if (0)
1398 emit_zs_write(c, rcp_w, &vpm_index);
1399 } else {
1400 emit_scaled_viewport_write(c, rcp_w, &vpm_index);
1401 emit_zs_write(c, rcp_w, &vpm_index);
1402 emit_rcp_wc_write(c, rcp_w, &vpm_index);
1403 if (c->vs_key->per_vertex_point_size)
1404 emit_point_size_write(c, &vpm_index);
1405 }
1406
1407 for (int i = 0; i < c->vs_key->num_fs_inputs; i++) {
1408 struct v3d_varying_slot input = c->vs_key->fs_inputs[i];
1409 int j;
1410
1411 for (j = 0; j < c->num_outputs; j++) {
1412 struct v3d_varying_slot output = c->output_slots[j];
1413
1414 if (!memcmp(&input, &output, sizeof(input))) {
1415 vir_VPM_WRITE(c, c->outputs[j],
1416 &vpm_index);
1417 break;
1418 }
1419 }
1420 /* Emit padding if we didn't find a declared VS output for
1421 * this FS input.
1422 */
1423 if (j == c->num_outputs)
1424 vir_VPM_WRITE(c, vir_uniform_f(c, 0.0),
1425 &vpm_index);
1426 }
1427
1428 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1429 */
1430 if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
1431 vir_VPMWT(c);
1432 }
1433
1434 void
1435 v3d_optimize_nir(struct nir_shader *s)
1436 {
1437 bool progress;
1438
1439 do {
1440 progress = false;
1441
1442 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1443 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1444 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1445 NIR_PASS(progress, s, nir_copy_prop);
1446 NIR_PASS(progress, s, nir_opt_remove_phis);
1447 NIR_PASS(progress, s, nir_opt_dce);
1448 NIR_PASS(progress, s, nir_opt_dead_cf);
1449 NIR_PASS(progress, s, nir_opt_cse);
1450 NIR_PASS(progress, s, nir_opt_peephole_select, 8, true, true);
1451 NIR_PASS(progress, s, nir_opt_algebraic);
1452 NIR_PASS(progress, s, nir_opt_constant_folding);
1453 NIR_PASS(progress, s, nir_opt_undef);
1454 } while (progress);
1455
1456 NIR_PASS(progress, s, nir_opt_move_load_ubo);
1457 }
1458
1459 static int
1460 driver_location_compare(const void *in_a, const void *in_b)
1461 {
1462 const nir_variable *const *a = in_a;
1463 const nir_variable *const *b = in_b;
1464
1465 return (*a)->data.driver_location - (*b)->data.driver_location;
1466 }
1467
1468 static struct qreg
1469 ntq_emit_vpm_read(struct v3d_compile *c,
1470 uint32_t *num_components_queued,
1471 uint32_t *remaining,
1472 uint32_t vpm_index)
1473 {
1474 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1475
1476 if (c->devinfo->ver >= 40 ) {
1477 return vir_LDVPMV_IN(c,
1478 vir_uniform_ui(c,
1479 (*num_components_queued)++));
1480 }
1481
1482 if (*num_components_queued != 0) {
1483 (*num_components_queued)--;
1484 return vir_MOV(c, vpm);
1485 }
1486
1487 uint32_t num_components = MIN2(*remaining, 32);
1488
1489 v3d33_vir_vpm_read_setup(c, num_components);
1490
1491 *num_components_queued = num_components - 1;
1492 *remaining -= num_components;
1493
1494 return vir_MOV(c, vpm);
1495 }
1496
1497 static void
1498 ntq_setup_vpm_inputs(struct v3d_compile *c)
1499 {
1500 /* Figure out how many components of each vertex attribute the shader
1501 * uses. Each variable should have been split to individual
1502 * components and unused ones DCEed. The vertex fetcher will load
1503 * from the start of the attribute to the number of components we
1504 * declare we need in c->vattr_sizes[].
1505 */
1506 nir_foreach_variable(var, &c->s->inputs) {
1507 /* No VS attribute array support. */
1508 assert(MAX2(glsl_get_length(var->type), 1) == 1);
1509
1510 unsigned loc = var->data.driver_location;
1511 int start_component = var->data.location_frac;
1512 int num_components = glsl_get_components(var->type);
1513
1514 c->vattr_sizes[loc] = MAX2(c->vattr_sizes[loc],
1515 start_component + num_components);
1516 }
1517
1518 unsigned num_components = 0;
1519 uint32_t vpm_components_queued = 0;
1520 bool uses_iid = c->s->info.system_values_read &
1521 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1522 bool uses_vid = c->s->info.system_values_read &
1523 (1ull << SYSTEM_VALUE_VERTEX_ID);
1524 num_components += uses_iid;
1525 num_components += uses_vid;
1526
1527 for (int i = 0; i < ARRAY_SIZE(c->vattr_sizes); i++)
1528 num_components += c->vattr_sizes[i];
1529
1530 if (uses_iid) {
1531 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1532 &num_components, ~0);
1533 }
1534
1535 if (uses_vid) {
1536 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1537 &num_components, ~0);
1538 }
1539
1540 /* The actual loads will happen directly in nir_intrinsic_load_input
1541 * on newer versions.
1542 */
1543 if (c->devinfo->ver >= 40)
1544 return;
1545
1546 for (int loc = 0; loc < ARRAY_SIZE(c->vattr_sizes); loc++) {
1547 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1548 (loc + 1) * 4);
1549
1550 for (int i = 0; i < c->vattr_sizes[loc]; i++) {
1551 c->inputs[loc * 4 + i] =
1552 ntq_emit_vpm_read(c,
1553 &vpm_components_queued,
1554 &num_components,
1555 loc * 4 + i);
1556
1557 }
1558 }
1559
1560 if (c->devinfo->ver >= 40) {
1561 assert(vpm_components_queued == num_components);
1562 } else {
1563 assert(vpm_components_queued == 0);
1564 assert(num_components == 0);
1565 }
1566 }
1567
1568 static void
1569 ntq_setup_fs_inputs(struct v3d_compile *c)
1570 {
1571 unsigned num_entries = 0;
1572 unsigned num_components = 0;
1573 nir_foreach_variable(var, &c->s->inputs) {
1574 num_entries++;
1575 num_components += glsl_get_components(var->type);
1576 }
1577
1578 nir_variable *vars[num_entries];
1579
1580 unsigned i = 0;
1581 nir_foreach_variable(var, &c->s->inputs)
1582 vars[i++] = var;
1583
1584 /* Sort the variables so that we emit the input setup in
1585 * driver_location order. This is required for VPM reads, whose data
1586 * is fetched into the VPM in driver_location (TGSI register index)
1587 * order.
1588 */
1589 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1590
1591 for (unsigned i = 0; i < num_entries; i++) {
1592 nir_variable *var = vars[i];
1593 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1594 unsigned loc = var->data.driver_location;
1595
1596 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1597 (loc + array_len) * 4);
1598
1599 if (var->data.location == VARYING_SLOT_POS) {
1600 emit_fragcoord_input(c, loc);
1601 } else if (var->data.location == VARYING_SLOT_PNTC ||
1602 (var->data.location >= VARYING_SLOT_VAR0 &&
1603 (c->fs_key->point_sprite_mask &
1604 (1 << (var->data.location -
1605 VARYING_SLOT_VAR0))))) {
1606 c->inputs[loc * 4 + 0] = c->point_x;
1607 c->inputs[loc * 4 + 1] = c->point_y;
1608 } else {
1609 for (int j = 0; j < array_len; j++)
1610 emit_fragment_input(c, loc + j, var, j);
1611 }
1612 }
1613 }
1614
1615 static void
1616 ntq_setup_outputs(struct v3d_compile *c)
1617 {
1618 nir_foreach_variable(var, &c->s->outputs) {
1619 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1620 unsigned loc = var->data.driver_location * 4;
1621
1622 assert(array_len == 1);
1623 (void)array_len;
1624
1625 for (int i = 0; i < 4 - var->data.location_frac; i++) {
1626 add_output(c, loc + var->data.location_frac + i,
1627 var->data.location,
1628 var->data.location_frac + i);
1629 }
1630
1631 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1632 switch (var->data.location) {
1633 case FRAG_RESULT_COLOR:
1634 c->output_color_var[0] = var;
1635 c->output_color_var[1] = var;
1636 c->output_color_var[2] = var;
1637 c->output_color_var[3] = var;
1638 break;
1639 case FRAG_RESULT_DATA0:
1640 case FRAG_RESULT_DATA1:
1641 case FRAG_RESULT_DATA2:
1642 case FRAG_RESULT_DATA3:
1643 c->output_color_var[var->data.location -
1644 FRAG_RESULT_DATA0] = var;
1645 break;
1646 case FRAG_RESULT_DEPTH:
1647 c->output_position_index = loc;
1648 break;
1649 case FRAG_RESULT_SAMPLE_MASK:
1650 c->output_sample_mask_index = loc;
1651 break;
1652 }
1653 } else {
1654 switch (var->data.location) {
1655 case VARYING_SLOT_POS:
1656 c->output_position_index = loc;
1657 break;
1658 case VARYING_SLOT_PSIZ:
1659 c->output_point_size_index = loc;
1660 break;
1661 }
1662 }
1663 }
1664 }
1665
1666 static void
1667 ntq_setup_uniforms(struct v3d_compile *c)
1668 {
1669 nir_foreach_variable(var, &c->s->uniforms) {
1670 uint32_t vec4_count = glsl_count_attribute_slots(var->type,
1671 false);
1672 unsigned vec4_size = 4 * sizeof(float);
1673
1674 if (var->data.mode != nir_var_uniform)
1675 continue;
1676
1677 declare_uniform_range(c, var->data.driver_location * vec4_size,
1678 vec4_count * vec4_size);
1679
1680 }
1681 }
1682
1683 /**
1684 * Sets up the mapping from nir_register to struct qreg *.
1685 *
1686 * Each nir_register gets a struct qreg per 32-bit component being stored.
1687 */
1688 static void
1689 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1690 {
1691 foreach_list_typed(nir_register, nir_reg, node, list) {
1692 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1693 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1694 array_len *
1695 nir_reg->num_components);
1696
1697 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1698
1699 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1700 qregs[i] = vir_get_temp(c);
1701 }
1702 }
1703
1704 static void
1705 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1706 {
1707 /* XXX perf: Experiment with using immediate loads to avoid having
1708 * these end up in the uniform stream. Watch out for breaking the
1709 * small immediates optimization in the process!
1710 */
1711 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1712 for (int i = 0; i < instr->def.num_components; i++)
1713 qregs[i] = vir_uniform_ui(c, instr->value.u32[i]);
1714
1715 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1716 }
1717
1718 static void
1719 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1720 {
1721 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1722
1723 /* VIR needs there to be *some* value, so pick 0 (same as for
1724 * ntq_setup_registers().
1725 */
1726 for (int i = 0; i < instr->def.num_components; i++)
1727 qregs[i] = vir_uniform_ui(c, 0);
1728 }
1729
1730 static void
1731 ntq_emit_image_size(struct v3d_compile *c, nir_intrinsic_instr *instr)
1732 {
1733 assert(instr->intrinsic == nir_intrinsic_image_deref_size);
1734 nir_variable *var = nir_intrinsic_get_var(instr, 0);
1735 unsigned image_index = var->data.driver_location;
1736 const struct glsl_type *sampler_type = glsl_without_array(var->type);
1737 bool is_array = glsl_sampler_type_is_array(sampler_type);
1738
1739 ntq_store_dest(c, &instr->dest, 0,
1740 vir_uniform(c, QUNIFORM_IMAGE_WIDTH, image_index));
1741 if (instr->num_components > 1) {
1742 ntq_store_dest(c, &instr->dest, 1,
1743 vir_uniform(c, QUNIFORM_IMAGE_HEIGHT,
1744 image_index));
1745 }
1746 if (instr->num_components > 2) {
1747 ntq_store_dest(c, &instr->dest, 2,
1748 vir_uniform(c,
1749 is_array ?
1750 QUNIFORM_IMAGE_ARRAY_SIZE :
1751 QUNIFORM_IMAGE_DEPTH,
1752 image_index));
1753 }
1754 }
1755
1756 static void
1757 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
1758 {
1759 unsigned offset;
1760
1761 switch (instr->intrinsic) {
1762 case nir_intrinsic_load_uniform:
1763 if (nir_src_is_const(instr->src[0])) {
1764 int offset = (nir_intrinsic_base(instr) +
1765 nir_src_as_uint(instr->src[0]));
1766 assert(offset % 4 == 0);
1767 /* We need dwords */
1768 offset = offset / 4;
1769 for (int i = 0; i < instr->num_components; i++) {
1770 ntq_store_dest(c, &instr->dest, i,
1771 vir_uniform(c, QUNIFORM_UNIFORM,
1772 offset + i));
1773 }
1774 } else {
1775 ntq_emit_tmu_general(c, instr, false);
1776 }
1777 break;
1778
1779 case nir_intrinsic_load_ubo:
1780 ntq_emit_tmu_general(c, instr, false);
1781 break;
1782
1783 case nir_intrinsic_ssbo_atomic_add:
1784 case nir_intrinsic_ssbo_atomic_imin:
1785 case nir_intrinsic_ssbo_atomic_umin:
1786 case nir_intrinsic_ssbo_atomic_imax:
1787 case nir_intrinsic_ssbo_atomic_umax:
1788 case nir_intrinsic_ssbo_atomic_and:
1789 case nir_intrinsic_ssbo_atomic_or:
1790 case nir_intrinsic_ssbo_atomic_xor:
1791 case nir_intrinsic_ssbo_atomic_exchange:
1792 case nir_intrinsic_ssbo_atomic_comp_swap:
1793 case nir_intrinsic_load_ssbo:
1794 case nir_intrinsic_store_ssbo:
1795 ntq_emit_tmu_general(c, instr, false);
1796 break;
1797
1798 case nir_intrinsic_shared_atomic_add:
1799 case nir_intrinsic_shared_atomic_imin:
1800 case nir_intrinsic_shared_atomic_umin:
1801 case nir_intrinsic_shared_atomic_imax:
1802 case nir_intrinsic_shared_atomic_umax:
1803 case nir_intrinsic_shared_atomic_and:
1804 case nir_intrinsic_shared_atomic_or:
1805 case nir_intrinsic_shared_atomic_xor:
1806 case nir_intrinsic_shared_atomic_exchange:
1807 case nir_intrinsic_shared_atomic_comp_swap:
1808 case nir_intrinsic_load_shared:
1809 case nir_intrinsic_store_shared:
1810 ntq_emit_tmu_general(c, instr, true);
1811 break;
1812
1813 case nir_intrinsic_image_deref_load:
1814 case nir_intrinsic_image_deref_store:
1815 case nir_intrinsic_image_deref_atomic_add:
1816 case nir_intrinsic_image_deref_atomic_min:
1817 case nir_intrinsic_image_deref_atomic_max:
1818 case nir_intrinsic_image_deref_atomic_and:
1819 case nir_intrinsic_image_deref_atomic_or:
1820 case nir_intrinsic_image_deref_atomic_xor:
1821 case nir_intrinsic_image_deref_atomic_exchange:
1822 case nir_intrinsic_image_deref_atomic_comp_swap:
1823 v3d40_vir_emit_image_load_store(c, instr);
1824 break;
1825
1826 case nir_intrinsic_get_buffer_size:
1827 ntq_store_dest(c, &instr->dest, 0,
1828 vir_uniform(c, QUNIFORM_GET_BUFFER_SIZE,
1829 nir_src_as_uint(instr->src[0])));
1830 break;
1831
1832 case nir_intrinsic_load_user_clip_plane:
1833 for (int i = 0; i < instr->num_components; i++) {
1834 ntq_store_dest(c, &instr->dest, i,
1835 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1836 nir_intrinsic_ucp_id(instr) *
1837 4 + i));
1838 }
1839 break;
1840
1841 case nir_intrinsic_load_alpha_ref_float:
1842 ntq_store_dest(c, &instr->dest, 0,
1843 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1844 break;
1845
1846 case nir_intrinsic_load_sample_mask_in:
1847 ntq_store_dest(c, &instr->dest, 0, vir_MSF(c));
1848 break;
1849
1850 case nir_intrinsic_load_helper_invocation:
1851 vir_set_pf(vir_MSF_dest(c, vir_nop_reg()), V3D_QPU_PF_PUSHZ);
1852 ntq_store_dest(c, &instr->dest, 0,
1853 vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1854 vir_uniform_ui(c, ~0),
1855 vir_uniform_ui(c, 0))));
1856 break;
1857
1858 case nir_intrinsic_load_front_face:
1859 /* The register contains 0 (front) or 1 (back), and we need to
1860 * turn it into a NIR bool where true means front.
1861 */
1862 ntq_store_dest(c, &instr->dest, 0,
1863 vir_ADD(c,
1864 vir_uniform_ui(c, -1),
1865 vir_REVF(c)));
1866 break;
1867
1868 case nir_intrinsic_load_instance_id:
1869 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
1870 break;
1871
1872 case nir_intrinsic_load_vertex_id:
1873 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
1874 break;
1875
1876 case nir_intrinsic_load_input:
1877 offset = (nir_intrinsic_base(instr) +
1878 nir_src_as_uint(instr->src[0]));
1879 if (c->s->info.stage != MESA_SHADER_FRAGMENT &&
1880 c->devinfo->ver >= 40) {
1881 /* Emit the LDVPM directly now, rather than at the top
1882 * of the shader like we did for V3D 3.x (which needs
1883 * vpmsetup when not just taking the next offset).
1884 *
1885 * Note that delaying like this may introduce stalls,
1886 * as LDVPMV takes a minimum of 1 instruction but may
1887 * be slower if the VPM unit is busy with another QPU.
1888 */
1889 int index = 0;
1890 if (c->s->info.system_values_read &
1891 (1ull << SYSTEM_VALUE_INSTANCE_ID)) {
1892 index++;
1893 }
1894 if (c->s->info.system_values_read &
1895 (1ull << SYSTEM_VALUE_VERTEX_ID)) {
1896 index++;
1897 }
1898 for (int i = 0; i < offset; i++)
1899 index += c->vattr_sizes[i];
1900 index += nir_intrinsic_component(instr);
1901 for (int i = 0; i < instr->num_components; i++) {
1902 struct qreg vpm_offset =
1903 vir_uniform_ui(c, index++);
1904 ntq_store_dest(c, &instr->dest, i,
1905 vir_LDVPMV_IN(c, vpm_offset));
1906 }
1907 } else {
1908 for (int i = 0; i < instr->num_components; i++) {
1909 int comp = nir_intrinsic_component(instr) + i;
1910 ntq_store_dest(c, &instr->dest, i,
1911 vir_MOV(c, c->inputs[offset * 4 +
1912 comp]));
1913 }
1914 }
1915 break;
1916
1917 case nir_intrinsic_store_output:
1918 offset = ((nir_intrinsic_base(instr) +
1919 nir_src_as_uint(instr->src[1])) * 4 +
1920 nir_intrinsic_component(instr));
1921
1922 for (int i = 0; i < instr->num_components; i++) {
1923 c->outputs[offset + i] =
1924 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
1925 }
1926 c->num_outputs = MAX2(c->num_outputs,
1927 offset + instr->num_components);
1928 break;
1929
1930 case nir_intrinsic_image_deref_size:
1931 ntq_emit_image_size(c, instr);
1932 break;
1933
1934 case nir_intrinsic_discard:
1935 if (vir_in_nonuniform_control_flow(c)) {
1936 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
1937 V3D_QPU_PF_PUSHZ);
1938 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
1939 vir_uniform_ui(c, 0)),
1940 V3D_QPU_COND_IFA);
1941 } else {
1942 vir_SETMSF_dest(c, vir_nop_reg(),
1943 vir_uniform_ui(c, 0));
1944 }
1945 break;
1946
1947 case nir_intrinsic_discard_if: {
1948 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, instr->src[0]);
1949
1950 if (vir_in_nonuniform_control_flow(c)) {
1951 struct qinst *exec_flag = vir_MOV_dest(c, vir_nop_reg(),
1952 c->execute);
1953 if (cond == V3D_QPU_COND_IFA) {
1954 vir_set_uf(exec_flag, V3D_QPU_UF_ANDZ);
1955 } else {
1956 vir_set_uf(exec_flag, V3D_QPU_UF_NORNZ);
1957 cond = V3D_QPU_COND_IFA;
1958 }
1959 }
1960
1961 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
1962 vir_uniform_ui(c, 0)), cond);
1963
1964 break;
1965 }
1966
1967 case nir_intrinsic_memory_barrier:
1968 case nir_intrinsic_memory_barrier_atomic_counter:
1969 case nir_intrinsic_memory_barrier_buffer:
1970 case nir_intrinsic_memory_barrier_image:
1971 case nir_intrinsic_memory_barrier_shared:
1972 /* We don't do any instruction scheduling of these NIR
1973 * instructions between each other, so we just need to make
1974 * sure that the TMU operations before the barrier are flushed
1975 * before the ones after the barrier. That is currently
1976 * handled by having a THRSW in each of them and a LDTMU
1977 * series or a TMUWT after.
1978 */
1979 break;
1980
1981 case nir_intrinsic_barrier:
1982 /* Emit a TSY op to get all invocations in the workgroup
1983 * (actually supergroup) to block until the last invocation
1984 * reaches the TSY op.
1985 */
1986 if (c->devinfo->ver >= 42) {
1987 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
1988 V3D_QPU_WADDR_SYNCB));
1989 } else {
1990 struct qinst *sync =
1991 vir_BARRIERID_dest(c,
1992 vir_reg(QFILE_MAGIC,
1993 V3D_QPU_WADDR_SYNCU));
1994 sync->src[vir_get_implicit_uniform_src(sync)] =
1995 vir_uniform_ui(c,
1996 0xffffff00 |
1997 V3D_TSY_WAIT_INC_CHECK);
1998
1999 }
2000
2001 /* The blocking of a TSY op only happens at the next thread
2002 * switch. No texturing may be outstanding at the time of a
2003 * TSY blocking operation.
2004 */
2005 vir_emit_thrsw(c);
2006 break;
2007
2008 case nir_intrinsic_load_num_work_groups:
2009 for (int i = 0; i < 3; i++) {
2010 ntq_store_dest(c, &instr->dest, i,
2011 vir_uniform(c, QUNIFORM_NUM_WORK_GROUPS,
2012 i));
2013 }
2014 break;
2015
2016 case nir_intrinsic_load_local_invocation_index:
2017 ntq_store_dest(c, &instr->dest, 0,
2018 vir_SHR(c, c->cs_payload[1],
2019 vir_uniform_ui(c, 32 - c->local_invocation_index_bits)));
2020 break;
2021
2022 case nir_intrinsic_load_work_group_id:
2023 ntq_store_dest(c, &instr->dest, 0,
2024 vir_AND(c, c->cs_payload[0],
2025 vir_uniform_ui(c, 0xffff)));
2026 ntq_store_dest(c, &instr->dest, 1,
2027 vir_SHR(c, c->cs_payload[0],
2028 vir_uniform_ui(c, 16)));
2029 ntq_store_dest(c, &instr->dest, 2,
2030 vir_AND(c, c->cs_payload[1],
2031 vir_uniform_ui(c, 0xffff)));
2032 break;
2033
2034 default:
2035 fprintf(stderr, "Unknown intrinsic: ");
2036 nir_print_instr(&instr->instr, stderr);
2037 fprintf(stderr, "\n");
2038 break;
2039 }
2040 }
2041
2042 /* Clears (activates) the execute flags for any channels whose jump target
2043 * matches this block.
2044 *
2045 * XXX perf: Could we be using flpush/flpop somehow for our execution channel
2046 * enabling?
2047 *
2048 * XXX perf: For uniform control flow, we should be able to skip c->execute
2049 * handling entirely.
2050 */
2051 static void
2052 ntq_activate_execute_for_block(struct v3d_compile *c)
2053 {
2054 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
2055 c->execute, vir_uniform_ui(c, c->cur_block->index)),
2056 V3D_QPU_PF_PUSHZ);
2057
2058 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2059 }
2060
2061 static void
2062 ntq_emit_uniform_if(struct v3d_compile *c, nir_if *if_stmt)
2063 {
2064 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2065 bool empty_else_block =
2066 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2067 exec_list_is_empty(&nir_else_block->instr_list));
2068
2069 struct qblock *then_block = vir_new_block(c);
2070 struct qblock *after_block = vir_new_block(c);
2071 struct qblock *else_block;
2072 if (empty_else_block)
2073 else_block = after_block;
2074 else
2075 else_block = vir_new_block(c);
2076
2077 /* Set up the flags for the IF condition (taking the THEN branch). */
2078 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
2079
2080 /* Jump to ELSE. */
2081 vir_BRANCH(c, cond == V3D_QPU_COND_IFA ?
2082 V3D_QPU_BRANCH_COND_ALLNA :
2083 V3D_QPU_BRANCH_COND_ALLA);
2084 vir_link_blocks(c->cur_block, else_block);
2085 vir_link_blocks(c->cur_block, then_block);
2086
2087 /* Process the THEN block. */
2088 vir_set_emit_block(c, then_block);
2089 ntq_emit_cf_list(c, &if_stmt->then_list);
2090
2091 if (!empty_else_block) {
2092 /* At the end of the THEN block, jump to ENDIF */
2093 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALWAYS);
2094 vir_link_blocks(c->cur_block, after_block);
2095
2096 /* Emit the else block. */
2097 vir_set_emit_block(c, else_block);
2098 ntq_activate_execute_for_block(c);
2099 ntq_emit_cf_list(c, &if_stmt->else_list);
2100 }
2101
2102 vir_link_blocks(c->cur_block, after_block);
2103
2104 vir_set_emit_block(c, after_block);
2105 }
2106
2107 static void
2108 ntq_emit_nonuniform_if(struct v3d_compile *c, nir_if *if_stmt)
2109 {
2110 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2111 bool empty_else_block =
2112 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2113 exec_list_is_empty(&nir_else_block->instr_list));
2114
2115 struct qblock *then_block = vir_new_block(c);
2116 struct qblock *after_block = vir_new_block(c);
2117 struct qblock *else_block;
2118 if (empty_else_block)
2119 else_block = after_block;
2120 else
2121 else_block = vir_new_block(c);
2122
2123 bool was_uniform_control_flow = false;
2124 if (!vir_in_nonuniform_control_flow(c)) {
2125 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2126 was_uniform_control_flow = true;
2127 }
2128
2129 /* Set up the flags for the IF condition (taking the THEN branch). */
2130 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
2131
2132 /* Update the flags+cond to mean "Taking the ELSE branch (!cond) and
2133 * was previously active (execute Z) for updating the exec flags.
2134 */
2135 if (was_uniform_control_flow) {
2136 cond = v3d_qpu_cond_invert(cond);
2137 } else {
2138 struct qinst *inst = vir_MOV_dest(c, vir_nop_reg(), c->execute);
2139 if (cond == V3D_QPU_COND_IFA) {
2140 vir_set_uf(inst, V3D_QPU_UF_NORNZ);
2141 } else {
2142 vir_set_uf(inst, V3D_QPU_UF_ANDZ);
2143 cond = V3D_QPU_COND_IFA;
2144 }
2145 }
2146
2147 vir_MOV_cond(c, cond,
2148 c->execute,
2149 vir_uniform_ui(c, else_block->index));
2150
2151 /* Jump to ELSE if nothing is active for THEN, otherwise fall
2152 * through.
2153 */
2154 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ);
2155 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
2156 vir_link_blocks(c->cur_block, else_block);
2157 vir_link_blocks(c->cur_block, then_block);
2158
2159 /* Process the THEN block. */
2160 vir_set_emit_block(c, then_block);
2161 ntq_emit_cf_list(c, &if_stmt->then_list);
2162
2163 if (!empty_else_block) {
2164 /* Handle the end of the THEN block. First, all currently
2165 * active channels update their execute flags to point to
2166 * ENDIF
2167 */
2168 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2169 V3D_QPU_PF_PUSHZ);
2170 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2171 vir_uniform_ui(c, after_block->index));
2172
2173 /* If everything points at ENDIF, then jump there immediately. */
2174 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
2175 c->execute,
2176 vir_uniform_ui(c, after_block->index)),
2177 V3D_QPU_PF_PUSHZ);
2178 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
2179 vir_link_blocks(c->cur_block, after_block);
2180 vir_link_blocks(c->cur_block, else_block);
2181
2182 vir_set_emit_block(c, else_block);
2183 ntq_activate_execute_for_block(c);
2184 ntq_emit_cf_list(c, &if_stmt->else_list);
2185 }
2186
2187 vir_link_blocks(c->cur_block, after_block);
2188
2189 vir_set_emit_block(c, after_block);
2190 if (was_uniform_control_flow)
2191 c->execute = c->undef;
2192 else
2193 ntq_activate_execute_for_block(c);
2194 }
2195
2196 static void
2197 ntq_emit_if(struct v3d_compile *c, nir_if *nif)
2198 {
2199 bool was_in_control_flow = c->in_control_flow;
2200 c->in_control_flow = true;
2201 if (!vir_in_nonuniform_control_flow(c) &&
2202 nir_src_is_dynamically_uniform(nif->condition)) {
2203 ntq_emit_uniform_if(c, nif);
2204 } else {
2205 ntq_emit_nonuniform_if(c, nif);
2206 }
2207 c->in_control_flow = was_in_control_flow;
2208 }
2209
2210 static void
2211 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
2212 {
2213 switch (jump->type) {
2214 case nir_jump_break:
2215 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2216 V3D_QPU_PF_PUSHZ);
2217 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2218 vir_uniform_ui(c, c->loop_break_block->index));
2219 break;
2220
2221 case nir_jump_continue:
2222 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2223 V3D_QPU_PF_PUSHZ);
2224 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2225 vir_uniform_ui(c, c->loop_cont_block->index));
2226 break;
2227
2228 case nir_jump_return:
2229 unreachable("All returns shouold be lowered\n");
2230 }
2231 }
2232
2233 static void
2234 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
2235 {
2236 switch (instr->type) {
2237 case nir_instr_type_deref:
2238 /* ignored, will be walked by the intrinsic using it. */
2239 break;
2240
2241 case nir_instr_type_alu:
2242 ntq_emit_alu(c, nir_instr_as_alu(instr));
2243 break;
2244
2245 case nir_instr_type_intrinsic:
2246 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
2247 break;
2248
2249 case nir_instr_type_load_const:
2250 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
2251 break;
2252
2253 case nir_instr_type_ssa_undef:
2254 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
2255 break;
2256
2257 case nir_instr_type_tex:
2258 ntq_emit_tex(c, nir_instr_as_tex(instr));
2259 break;
2260
2261 case nir_instr_type_jump:
2262 ntq_emit_jump(c, nir_instr_as_jump(instr));
2263 break;
2264
2265 default:
2266 fprintf(stderr, "Unknown NIR instr type: ");
2267 nir_print_instr(instr, stderr);
2268 fprintf(stderr, "\n");
2269 abort();
2270 }
2271 }
2272
2273 static void
2274 ntq_emit_block(struct v3d_compile *c, nir_block *block)
2275 {
2276 nir_foreach_instr(instr, block) {
2277 ntq_emit_instr(c, instr);
2278 }
2279 }
2280
2281 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
2282
2283 static void
2284 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
2285 {
2286 bool was_in_control_flow = c->in_control_flow;
2287 c->in_control_flow = true;
2288
2289 bool was_uniform_control_flow = false;
2290 if (!vir_in_nonuniform_control_flow(c)) {
2291 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2292 was_uniform_control_flow = true;
2293 }
2294
2295 struct qblock *save_loop_cont_block = c->loop_cont_block;
2296 struct qblock *save_loop_break_block = c->loop_break_block;
2297
2298 c->loop_cont_block = vir_new_block(c);
2299 c->loop_break_block = vir_new_block(c);
2300
2301 vir_link_blocks(c->cur_block, c->loop_cont_block);
2302 vir_set_emit_block(c, c->loop_cont_block);
2303 ntq_activate_execute_for_block(c);
2304
2305 ntq_emit_cf_list(c, &loop->body);
2306
2307 /* Re-enable any previous continues now, so our ANYA check below
2308 * works.
2309 *
2310 * XXX: Use the .ORZ flags update, instead.
2311 */
2312 vir_set_pf(vir_XOR_dest(c,
2313 vir_nop_reg(),
2314 c->execute,
2315 vir_uniform_ui(c, c->loop_cont_block->index)),
2316 V3D_QPU_PF_PUSHZ);
2317 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2318
2319 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ);
2320
2321 struct qinst *branch = vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
2322 /* Pixels that were not dispatched or have been discarded should not
2323 * contribute to looping again.
2324 */
2325 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P;
2326 vir_link_blocks(c->cur_block, c->loop_cont_block);
2327 vir_link_blocks(c->cur_block, c->loop_break_block);
2328
2329 vir_set_emit_block(c, c->loop_break_block);
2330 if (was_uniform_control_flow)
2331 c->execute = c->undef;
2332 else
2333 ntq_activate_execute_for_block(c);
2334
2335 c->loop_break_block = save_loop_break_block;
2336 c->loop_cont_block = save_loop_cont_block;
2337
2338 c->loops++;
2339
2340 c->in_control_flow = was_in_control_flow;
2341 }
2342
2343 static void
2344 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
2345 {
2346 fprintf(stderr, "FUNCTIONS not handled.\n");
2347 abort();
2348 }
2349
2350 static void
2351 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
2352 {
2353 foreach_list_typed(nir_cf_node, node, node, list) {
2354 switch (node->type) {
2355 case nir_cf_node_block:
2356 ntq_emit_block(c, nir_cf_node_as_block(node));
2357 break;
2358
2359 case nir_cf_node_if:
2360 ntq_emit_if(c, nir_cf_node_as_if(node));
2361 break;
2362
2363 case nir_cf_node_loop:
2364 ntq_emit_loop(c, nir_cf_node_as_loop(node));
2365 break;
2366
2367 case nir_cf_node_function:
2368 ntq_emit_function(c, nir_cf_node_as_function(node));
2369 break;
2370
2371 default:
2372 fprintf(stderr, "Unknown NIR node type\n");
2373 abort();
2374 }
2375 }
2376 }
2377
2378 static void
2379 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
2380 {
2381 ntq_setup_registers(c, &impl->registers);
2382 ntq_emit_cf_list(c, &impl->body);
2383 }
2384
2385 static void
2386 nir_to_vir(struct v3d_compile *c)
2387 {
2388 switch (c->s->info.stage) {
2389 case MESA_SHADER_FRAGMENT:
2390 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
2391 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
2392 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
2393
2394 /* XXX perf: We could set the "disable implicit point/line
2395 * varyings" field in the shader record and not emit these, if
2396 * they're not going to be used.
2397 */
2398 if (c->fs_key->is_points) {
2399 c->point_x = emit_fragment_varying(c, NULL, 0, 0);
2400 c->point_y = emit_fragment_varying(c, NULL, 0, 0);
2401 } else if (c->fs_key->is_lines) {
2402 c->line_x = emit_fragment_varying(c, NULL, 0, 0);
2403 }
2404 break;
2405 case MESA_SHADER_COMPUTE:
2406 /* Set up the TSO for barriers, assuming we do some. */
2407 if (c->devinfo->ver < 42) {
2408 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
2409 V3D_QPU_WADDR_SYNC));
2410 }
2411
2412 if (c->s->info.system_values_read &
2413 ((1ull << SYSTEM_VALUE_LOCAL_INVOCATION_INDEX) |
2414 (1ull << SYSTEM_VALUE_WORK_GROUP_ID))) {
2415 c->cs_payload[0] = vir_MOV(c, vir_reg(QFILE_REG, 0));
2416 }
2417 if ((c->s->info.system_values_read &
2418 ((1ull << SYSTEM_VALUE_WORK_GROUP_ID))) ||
2419 c->s->info.cs.shared_size) {
2420 c->cs_payload[1] = vir_MOV(c, vir_reg(QFILE_REG, 2));
2421 }
2422
2423 /* Set up the division between gl_LocalInvocationIndex and
2424 * wg_in_mem in the payload reg.
2425 */
2426 int wg_size = (c->s->info.cs.local_size[0] *
2427 c->s->info.cs.local_size[1] *
2428 c->s->info.cs.local_size[2]);
2429 c->local_invocation_index_bits =
2430 ffs(util_next_power_of_two(MAX2(wg_size, 64))) - 1;
2431 assert(c->local_invocation_index_bits <= 8);
2432
2433 if (c->s->info.cs.shared_size) {
2434 struct qreg wg_in_mem = vir_SHR(c, c->cs_payload[1],
2435 vir_uniform_ui(c, 16));
2436 if (c->s->info.cs.local_size[0] != 1 ||
2437 c->s->info.cs.local_size[1] != 1 ||
2438 c->s->info.cs.local_size[2] != 1) {
2439 int wg_bits = (16 -
2440 c->local_invocation_index_bits);
2441 int wg_mask = (1 << wg_bits) - 1;
2442 wg_in_mem = vir_AND(c, wg_in_mem,
2443 vir_uniform_ui(c, wg_mask));
2444 }
2445 struct qreg shared_per_wg =
2446 vir_uniform_ui(c, c->s->info.cs.shared_size);
2447
2448 c->cs_shared_offset =
2449 vir_ADD(c,
2450 vir_uniform(c, QUNIFORM_SHARED_OFFSET,0),
2451 vir_UMUL(c, wg_in_mem, shared_per_wg));
2452 }
2453 break;
2454 default:
2455 break;
2456 }
2457
2458 if (c->s->info.stage == MESA_SHADER_FRAGMENT)
2459 ntq_setup_fs_inputs(c);
2460 else
2461 ntq_setup_vpm_inputs(c);
2462
2463 ntq_setup_outputs(c);
2464 ntq_setup_uniforms(c);
2465 ntq_setup_registers(c, &c->s->registers);
2466
2467 /* Find the main function and emit the body. */
2468 nir_foreach_function(function, c->s) {
2469 assert(strcmp(function->name, "main") == 0);
2470 assert(function->impl);
2471 ntq_emit_impl(c, function->impl);
2472 }
2473 }
2474
2475 const nir_shader_compiler_options v3d_nir_options = {
2476 .lower_all_io_to_temps = true,
2477 .lower_extract_byte = true,
2478 .lower_extract_word = true,
2479 .lower_bfm = true,
2480 .lower_bitfield_insert_to_shifts = true,
2481 .lower_bitfield_extract_to_shifts = true,
2482 .lower_bitfield_reverse = true,
2483 .lower_bit_count = true,
2484 .lower_cs_local_id_from_index = true,
2485 .lower_ffract = true,
2486 .lower_pack_unorm_2x16 = true,
2487 .lower_pack_snorm_2x16 = true,
2488 .lower_pack_unorm_4x8 = true,
2489 .lower_pack_snorm_4x8 = true,
2490 .lower_unpack_unorm_4x8 = true,
2491 .lower_unpack_snorm_4x8 = true,
2492 .lower_pack_half_2x16 = true,
2493 .lower_unpack_half_2x16 = true,
2494 .lower_fdiv = true,
2495 .lower_find_lsb = true,
2496 .lower_ffma = true,
2497 .lower_flrp32 = true,
2498 .lower_fpow = true,
2499 .lower_fsat = true,
2500 .lower_fsqrt = true,
2501 .lower_ifind_msb = true,
2502 .lower_isign = true,
2503 .lower_ldexp = true,
2504 .lower_mul_high = true,
2505 .lower_wpos_pntc = true,
2506 .native_integers = true,
2507 };
2508
2509 /**
2510 * When demoting a shader down to single-threaded, removes the THRSW
2511 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
2512 * program end).
2513 */
2514 static void
2515 vir_remove_thrsw(struct v3d_compile *c)
2516 {
2517 vir_for_each_block(block, c) {
2518 vir_for_each_inst_safe(inst, block) {
2519 if (inst->qpu.sig.thrsw)
2520 vir_remove_instruction(c, inst);
2521 }
2522 }
2523
2524 c->last_thrsw = NULL;
2525 }
2526
2527 void
2528 vir_emit_last_thrsw(struct v3d_compile *c)
2529 {
2530 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
2531 * switching, so disable threads if we didn't do any TMU ops (each of
2532 * which would have emitted a THRSW).
2533 */
2534 if (!c->last_thrsw_at_top_level && c->devinfo->ver < 41) {
2535 c->threads = 1;
2536 if (c->last_thrsw)
2537 vir_remove_thrsw(c);
2538 return;
2539 }
2540
2541 /* If we're threaded and the last THRSW was in conditional code, then
2542 * we need to emit another one so that we can flag it as the last
2543 * thrsw.
2544 */
2545 if (c->last_thrsw && !c->last_thrsw_at_top_level) {
2546 assert(c->devinfo->ver >= 41);
2547 vir_emit_thrsw(c);
2548 }
2549
2550 /* If we're threaded, then we need to mark the last THRSW instruction
2551 * so we can emit a pair of them at QPU emit time.
2552 *
2553 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2554 * post-last-THRSW state, so we can skip this.
2555 */
2556 if (!c->last_thrsw && c->s->info.stage == MESA_SHADER_FRAGMENT) {
2557 assert(c->devinfo->ver >= 41);
2558 vir_emit_thrsw(c);
2559 }
2560
2561 if (c->last_thrsw)
2562 c->last_thrsw->is_last_thrsw = true;
2563 }
2564
2565 /* There's a flag in the shader for "center W is needed for reasons other than
2566 * non-centroid varyings", so we just walk the program after VIR optimization
2567 * to see if it's used. It should be harmless to set even if we only use
2568 * center W for varyings.
2569 */
2570 static void
2571 vir_check_payload_w(struct v3d_compile *c)
2572 {
2573 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
2574 return;
2575
2576 vir_for_each_inst_inorder(inst, c) {
2577 for (int i = 0; i < vir_get_nsrc(inst); i++) {
2578 if (inst->src[i].file == QFILE_REG &&
2579 inst->src[i].index == 0) {
2580 c->uses_center_w = true;
2581 return;
2582 }
2583 }
2584 }
2585
2586 }
2587
2588 void
2589 v3d_nir_to_vir(struct v3d_compile *c)
2590 {
2591 if (V3D_DEBUG & (V3D_DEBUG_NIR |
2592 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2593 fprintf(stderr, "%s prog %d/%d NIR:\n",
2594 vir_get_stage_name(c),
2595 c->program_id, c->variant_id);
2596 nir_print_shader(c->s, stderr);
2597 }
2598
2599 nir_to_vir(c);
2600
2601 /* Emit the last THRSW before STVPM and TLB writes. */
2602 vir_emit_last_thrsw(c);
2603
2604 switch (c->s->info.stage) {
2605 case MESA_SHADER_FRAGMENT:
2606 emit_frag_end(c);
2607 break;
2608 case MESA_SHADER_VERTEX:
2609 emit_vert_end(c);
2610 break;
2611 default:
2612 unreachable("bad stage");
2613 }
2614
2615 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2616 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2617 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
2618 vir_get_stage_name(c),
2619 c->program_id, c->variant_id);
2620 vir_dump(c);
2621 fprintf(stderr, "\n");
2622 }
2623
2624 vir_optimize(c);
2625 vir_lower_uniforms(c);
2626
2627 vir_check_payload_w(c);
2628
2629 /* XXX perf: On VC4, we do a VIR-level instruction scheduling here.
2630 * We used that on that platform to pipeline TMU writes and reduce the
2631 * number of thread switches, as well as try (mostly successfully) to
2632 * reduce maximum register pressure to allow more threads. We should
2633 * do something of that sort for V3D -- either instruction scheduling
2634 * here, or delay the the THRSW and LDTMUs from our texture
2635 * instructions until the results are needed.
2636 */
2637
2638 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2639 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2640 fprintf(stderr, "%s prog %d/%d VIR:\n",
2641 vir_get_stage_name(c),
2642 c->program_id, c->variant_id);
2643 vir_dump(c);
2644 fprintf(stderr, "\n");
2645 }
2646
2647 /* Attempt to allocate registers for the temporaries. If we fail,
2648 * reduce thread count and try again.
2649 */
2650 int min_threads = (c->devinfo->ver >= 41) ? 2 : 1;
2651 struct qpu_reg *temp_registers;
2652 while (true) {
2653 bool spilled;
2654 temp_registers = v3d_register_allocate(c, &spilled);
2655 if (spilled)
2656 continue;
2657
2658 if (temp_registers)
2659 break;
2660
2661 if (c->threads == min_threads) {
2662 fprintf(stderr, "Failed to register allocate at %d threads:\n",
2663 c->threads);
2664 vir_dump(c);
2665 c->failed = true;
2666 return;
2667 }
2668
2669 c->threads /= 2;
2670
2671 if (c->threads == 1)
2672 vir_remove_thrsw(c);
2673 }
2674
2675 v3d_vir_to_qpu(c, temp_registers);
2676 }