2 * Copyright © 2016 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
36 ntq_emit_cf_list(struct v3d_compile
*c
, struct exec_list
*list
);
39 resize_qreg_array(struct v3d_compile
*c
,
44 if (*size
>= decl_size
)
47 uint32_t old_size
= *size
;
48 *size
= MAX2(*size
* 2, decl_size
);
49 *regs
= reralloc(c
, *regs
, struct qreg
, *size
);
51 fprintf(stderr
, "Malloc failure\n");
55 for (uint32_t i
= old_size
; i
< *size
; i
++)
56 (*regs
)[i
] = c
->undef
;
60 vir_emit_thrsw(struct v3d_compile
*c
)
65 /* Always thread switch after each texture operation for now.
67 * We could do better by batching a bunch of texture fetches up and
68 * then doing one thread switch and collecting all their results
71 c
->last_thrsw
= vir_NOP(c
);
72 c
->last_thrsw
->qpu
.sig
.thrsw
= true;
73 c
->last_thrsw_at_top_level
= (c
->execute
.file
== QFILE_NULL
);
77 indirect_uniform_load(struct v3d_compile
*c
, nir_intrinsic_instr
*intr
)
79 struct qreg indirect_offset
= ntq_get_src(c
, intr
->src
[0], 0);
80 uint32_t offset
= nir_intrinsic_base(intr
);
81 struct v3d_ubo_range
*range
= NULL
;
84 for (i
= 0; i
< c
->num_ubo_ranges
; i
++) {
85 range
= &c
->ubo_ranges
[i
];
86 if (offset
>= range
->src_offset
&&
87 offset
< range
->src_offset
+ range
->size
) {
91 /* The driver-location-based offset always has to be within a declared
94 assert(i
!= c
->num_ubo_ranges
);
95 if (!c
->ubo_range_used
[i
]) {
96 c
->ubo_range_used
[i
] = true;
97 range
->dst_offset
= c
->next_ubo_dst_offset
;
98 c
->next_ubo_dst_offset
+= range
->size
;
101 offset
-= range
->src_offset
;
103 if (range
->dst_offset
+ offset
!= 0) {
104 indirect_offset
= vir_ADD(c
, indirect_offset
,
105 vir_uniform_ui(c
, range
->dst_offset
+
109 /* Adjust for where we stored the TGSI register base. */
111 vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_TMUA
),
112 vir_uniform(c
, QUNIFORM_UBO_ADDR
, 0),
120 ntq_init_ssa_def(struct v3d_compile
*c
, nir_ssa_def
*def
)
122 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
123 def
->num_components
);
124 _mesa_hash_table_insert(c
->def_ht
, def
, qregs
);
129 * This function is responsible for getting VIR results into the associated
130 * storage for a NIR instruction.
132 * If it's a NIR SSA def, then we just set the associated hash table entry to
135 * If it's a NIR reg, then we need to update the existing qreg assigned to the
136 * NIR destination with the incoming value. To do that without introducing
137 * new MOVs, we require that the incoming qreg either be a uniform, or be
138 * SSA-defined by the previous VIR instruction in the block and rewritable by
139 * this function. That lets us sneak ahead and insert the SF flag beforehand
140 * (knowing that the previous instruction doesn't depend on flags) and rewrite
141 * its destination to be the NIR reg's destination
144 ntq_store_dest(struct v3d_compile
*c
, nir_dest
*dest
, int chan
,
147 struct qinst
*last_inst
= NULL
;
148 if (!list_empty(&c
->cur_block
->instructions
))
149 last_inst
= (struct qinst
*)c
->cur_block
->instructions
.prev
;
151 assert(result
.file
== QFILE_UNIF
||
152 (result
.file
== QFILE_TEMP
&&
153 last_inst
&& last_inst
== c
->defs
[result
.index
]));
156 assert(chan
< dest
->ssa
.num_components
);
159 struct hash_entry
*entry
=
160 _mesa_hash_table_search(c
->def_ht
, &dest
->ssa
);
165 qregs
= ntq_init_ssa_def(c
, &dest
->ssa
);
167 qregs
[chan
] = result
;
169 nir_register
*reg
= dest
->reg
.reg
;
170 assert(dest
->reg
.base_offset
== 0);
171 assert(reg
->num_array_elems
== 0);
172 struct hash_entry
*entry
=
173 _mesa_hash_table_search(c
->def_ht
, reg
);
174 struct qreg
*qregs
= entry
->data
;
176 /* Insert a MOV if the source wasn't an SSA def in the
177 * previous instruction.
179 if (result
.file
== QFILE_UNIF
) {
180 result
= vir_MOV(c
, result
);
181 last_inst
= c
->defs
[result
.index
];
184 /* We know they're both temps, so just rewrite index. */
185 c
->defs
[last_inst
->dst
.index
] = NULL
;
186 last_inst
->dst
.index
= qregs
[chan
].index
;
188 /* If we're in control flow, then make this update of the reg
189 * conditional on the execution mask.
191 if (c
->execute
.file
!= QFILE_NULL
) {
192 last_inst
->dst
.index
= qregs
[chan
].index
;
194 /* Set the flags to the current exec mask.
196 c
->cursor
= vir_before_inst(last_inst
);
197 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
198 c
->cursor
= vir_after_inst(last_inst
);
200 vir_set_cond(last_inst
, V3D_QPU_COND_IFA
);
201 last_inst
->cond_is_exec_mask
= true;
207 ntq_get_src(struct v3d_compile
*c
, nir_src src
, int i
)
209 struct hash_entry
*entry
;
211 entry
= _mesa_hash_table_search(c
->def_ht
, src
.ssa
);
212 assert(i
< src
.ssa
->num_components
);
214 nir_register
*reg
= src
.reg
.reg
;
215 entry
= _mesa_hash_table_search(c
->def_ht
, reg
);
216 assert(reg
->num_array_elems
== 0);
217 assert(src
.reg
.base_offset
== 0);
218 assert(i
< reg
->num_components
);
221 struct qreg
*qregs
= entry
->data
;
226 ntq_get_alu_src(struct v3d_compile
*c
, nir_alu_instr
*instr
,
229 assert(util_is_power_of_two_or_zero(instr
->dest
.write_mask
));
230 unsigned chan
= ffs(instr
->dest
.write_mask
) - 1;
231 struct qreg r
= ntq_get_src(c
, instr
->src
[src
].src
,
232 instr
->src
[src
].swizzle
[chan
]);
234 assert(!instr
->src
[src
].abs
);
235 assert(!instr
->src
[src
].negate
);
241 ntq_minify(struct v3d_compile
*c
, struct qreg size
, struct qreg level
)
243 return vir_MAX(c
, vir_SHR(c
, size
, level
), vir_uniform_ui(c
, 1));
247 ntq_emit_txs(struct v3d_compile
*c
, nir_tex_instr
*instr
)
249 unsigned unit
= instr
->texture_index
;
250 int lod_index
= nir_tex_instr_src_index(instr
, nir_tex_src_lod
);
251 int dest_size
= nir_tex_instr_dest_size(instr
);
253 struct qreg lod
= c
->undef
;
255 lod
= ntq_get_src(c
, instr
->src
[lod_index
].src
, 0);
257 for (int i
= 0; i
< dest_size
; i
++) {
259 enum quniform_contents contents
;
261 if (instr
->is_array
&& i
== dest_size
- 1)
262 contents
= QUNIFORM_TEXTURE_ARRAY_SIZE
;
264 contents
= QUNIFORM_TEXTURE_WIDTH
+ i
;
266 struct qreg size
= vir_uniform(c
, contents
, unit
);
268 switch (instr
->sampler_dim
) {
269 case GLSL_SAMPLER_DIM_1D
:
270 case GLSL_SAMPLER_DIM_2D
:
271 case GLSL_SAMPLER_DIM_MS
:
272 case GLSL_SAMPLER_DIM_3D
:
273 case GLSL_SAMPLER_DIM_CUBE
:
274 /* Don't minify the array size. */
275 if (!(instr
->is_array
&& i
== dest_size
- 1)) {
276 size
= ntq_minify(c
, size
, lod
);
280 case GLSL_SAMPLER_DIM_RECT
:
281 /* There's no LOD field for rects */
285 unreachable("Bad sampler type");
288 ntq_store_dest(c
, &instr
->dest
, i
, size
);
293 ntq_emit_tex(struct v3d_compile
*c
, nir_tex_instr
*instr
)
295 unsigned unit
= instr
->texture_index
;
297 /* Since each texture sampling op requires uploading uniforms to
298 * reference the texture, there's no HW support for texture size and
299 * you just upload uniforms containing the size.
302 case nir_texop_query_levels
:
303 ntq_store_dest(c
, &instr
->dest
, 0,
304 vir_uniform(c
, QUNIFORM_TEXTURE_LEVELS
, unit
));
307 ntq_emit_txs(c
, instr
);
313 if (c
->devinfo
->ver
>= 40)
314 v3d40_vir_emit_tex(c
, instr
);
316 v3d33_vir_emit_tex(c
, instr
);
320 ntq_fsincos(struct v3d_compile
*c
, struct qreg src
, bool is_cos
)
322 struct qreg input
= vir_FMUL(c
, src
, vir_uniform_f(c
, 1.0f
/ M_PI
));
324 input
= vir_FADD(c
, input
, vir_uniform_f(c
, 0.5));
326 struct qreg periods
= vir_FROUND(c
, input
);
327 struct qreg sin_output
= vir_SIN(c
, vir_FSUB(c
, input
, periods
));
328 return vir_XOR(c
, sin_output
, vir_SHL(c
,
329 vir_FTOIN(c
, periods
),
330 vir_uniform_ui(c
, -1)));
334 ntq_fsign(struct v3d_compile
*c
, struct qreg src
)
336 struct qreg t
= vir_get_temp(c
);
338 vir_MOV_dest(c
, t
, vir_uniform_f(c
, 0.0));
339 vir_PF(c
, vir_FMOV(c
, src
), V3D_QPU_PF_PUSHZ
);
340 vir_MOV_cond(c
, V3D_QPU_COND_IFNA
, t
, vir_uniform_f(c
, 1.0));
341 vir_PF(c
, vir_FMOV(c
, src
), V3D_QPU_PF_PUSHN
);
342 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, t
, vir_uniform_f(c
, -1.0));
343 return vir_MOV(c
, t
);
347 ntq_isign(struct v3d_compile
*c
, struct qreg src
)
349 struct qreg t
= vir_get_temp(c
);
351 vir_MOV_dest(c
, t
, vir_uniform_ui(c
, 0));
352 vir_PF(c
, vir_MOV(c
, src
), V3D_QPU_PF_PUSHZ
);
353 vir_MOV_cond(c
, V3D_QPU_COND_IFNA
, t
, vir_uniform_ui(c
, 1));
354 vir_PF(c
, vir_MOV(c
, src
), V3D_QPU_PF_PUSHN
);
355 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, t
, vir_uniform_ui(c
, -1));
356 return vir_MOV(c
, t
);
360 emit_fragcoord_input(struct v3d_compile
*c
, int attr
)
362 c
->inputs
[attr
* 4 + 0] = vir_FXCD(c
);
363 c
->inputs
[attr
* 4 + 1] = vir_FYCD(c
);
364 c
->inputs
[attr
* 4 + 2] = c
->payload_z
;
365 c
->inputs
[attr
* 4 + 3] = vir_RECIP(c
, c
->payload_w
);
369 emit_fragment_varying(struct v3d_compile
*c
, nir_variable
*var
,
372 struct qreg r3
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_R3
);
373 struct qreg r5
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_R5
);
376 if (c
->devinfo
->ver
>= 41) {
377 struct qinst
*ldvary
= vir_add_inst(V3D_QPU_A_NOP
, c
->undef
,
379 ldvary
->qpu
.sig
.ldvary
= true;
380 vary
= vir_emit_def(c
, ldvary
);
382 vir_NOP(c
)->qpu
.sig
.ldvary
= true;
386 /* For gl_PointCoord input or distance along a line, we'll be called
387 * with no nir_variable, and we don't count toward VPM size so we
388 * don't track an input slot.
391 return vir_FADD(c
, vir_FMUL(c
, vary
, c
->payload_w
), r5
);
394 int i
= c
->num_inputs
++;
395 c
->input_slots
[i
] = v3d_slot_from_slot_and_component(var
->data
.location
,
398 switch (var
->data
.interpolation
) {
399 case INTERP_MODE_NONE
:
400 /* If a gl_FrontColor or gl_BackColor input has no interp
401 * qualifier, then if we're using glShadeModel(GL_FLAT) it
402 * needs to be flat shaded.
404 switch (var
->data
.location
) {
405 case VARYING_SLOT_COL0
:
406 case VARYING_SLOT_COL1
:
407 case VARYING_SLOT_BFC0
:
408 case VARYING_SLOT_BFC1
:
409 if (c
->fs_key
->shade_model_flat
) {
410 BITSET_SET(c
->flat_shade_flags
, i
);
411 vir_MOV_dest(c
, c
->undef
, vary
);
412 return vir_MOV(c
, r5
);
414 return vir_FADD(c
, vir_FMUL(c
, vary
,
421 case INTERP_MODE_SMOOTH
:
422 if (var
->data
.centroid
) {
423 BITSET_SET(c
->centroid_flags
, i
);
424 return vir_FADD(c
, vir_FMUL(c
, vary
,
425 c
->payload_w_centroid
), r5
);
427 return vir_FADD(c
, vir_FMUL(c
, vary
, c
->payload_w
), r5
);
429 case INTERP_MODE_NOPERSPECTIVE
:
430 BITSET_SET(c
->noperspective_flags
, i
);
431 return vir_FADD(c
, vir_MOV(c
, vary
), r5
);
432 case INTERP_MODE_FLAT
:
433 BITSET_SET(c
->flat_shade_flags
, i
);
434 vir_MOV_dest(c
, c
->undef
, vary
);
435 return vir_MOV(c
, r5
);
437 unreachable("Bad interp mode");
442 emit_fragment_input(struct v3d_compile
*c
, int attr
, nir_variable
*var
)
444 for (int i
= 0; i
< glsl_get_vector_elements(var
->type
); i
++) {
445 int chan
= var
->data
.location_frac
+ i
;
446 c
->inputs
[attr
* 4 + chan
] =
447 emit_fragment_varying(c
, var
, chan
);
452 add_output(struct v3d_compile
*c
,
453 uint32_t decl_offset
,
457 uint32_t old_array_size
= c
->outputs_array_size
;
458 resize_qreg_array(c
, &c
->outputs
, &c
->outputs_array_size
,
461 if (old_array_size
!= c
->outputs_array_size
) {
462 c
->output_slots
= reralloc(c
,
464 struct v3d_varying_slot
,
465 c
->outputs_array_size
);
468 c
->output_slots
[decl_offset
] =
469 v3d_slot_from_slot_and_component(slot
, swizzle
);
473 declare_uniform_range(struct v3d_compile
*c
, uint32_t start
, uint32_t size
)
475 unsigned array_id
= c
->num_ubo_ranges
++;
476 if (array_id
>= c
->ubo_ranges_array_size
) {
477 c
->ubo_ranges_array_size
= MAX2(c
->ubo_ranges_array_size
* 2,
479 c
->ubo_ranges
= reralloc(c
, c
->ubo_ranges
,
480 struct v3d_ubo_range
,
481 c
->ubo_ranges_array_size
);
482 c
->ubo_range_used
= reralloc(c
, c
->ubo_range_used
,
484 c
->ubo_ranges_array_size
);
487 c
->ubo_ranges
[array_id
].dst_offset
= 0;
488 c
->ubo_ranges
[array_id
].src_offset
= start
;
489 c
->ubo_ranges
[array_id
].size
= size
;
490 c
->ubo_range_used
[array_id
] = false;
494 * If compare_instr is a valid comparison instruction, emits the
495 * compare_instr's comparison and returns the sel_instr's return value based
496 * on the compare_instr's result.
499 ntq_emit_comparison(struct v3d_compile
*c
, struct qreg
*dest
,
500 nir_alu_instr
*compare_instr
,
501 nir_alu_instr
*sel_instr
)
503 struct qreg src0
= ntq_get_alu_src(c
, compare_instr
, 0);
505 if (nir_op_infos
[compare_instr
->op
].num_inputs
> 1)
506 src1
= ntq_get_alu_src(c
, compare_instr
, 1);
507 bool cond_invert
= false;
508 struct qreg nop
= vir_reg(QFILE_NULL
, 0);
510 switch (compare_instr
->op
) {
513 vir_set_pf(vir_FCMP_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
516 vir_set_pf(vir_XOR_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
521 vir_set_pf(vir_FCMP_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
525 vir_set_pf(vir_XOR_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
531 vir_set_pf(vir_FCMP_dest(c
, nop
, src1
, src0
), V3D_QPU_PF_PUSHC
);
534 vir_set_pf(vir_MIN_dest(c
, nop
, src1
, src0
), V3D_QPU_PF_PUSHC
);
538 vir_set_pf(vir_SUB_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHC
);
544 vir_set_pf(vir_FCMP_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHN
);
547 vir_set_pf(vir_MIN_dest(c
, nop
, src1
, src0
), V3D_QPU_PF_PUSHC
);
550 vir_set_pf(vir_SUB_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHC
);
557 enum v3d_qpu_cond cond
= (cond_invert
?
561 switch (sel_instr
->op
) {
566 *dest
= vir_SEL(c
, cond
,
567 vir_uniform_f(c
, 1.0), vir_uniform_f(c
, 0.0));
571 *dest
= vir_SEL(c
, cond
,
572 ntq_get_alu_src(c
, sel_instr
, 1),
573 ntq_get_alu_src(c
, sel_instr
, 2));
577 *dest
= vir_SEL(c
, cond
,
578 vir_uniform_ui(c
, ~0), vir_uniform_ui(c
, 0));
582 /* Make the temporary for nir_store_dest(). */
583 *dest
= vir_MOV(c
, *dest
);
589 * Attempts to fold a comparison generating a boolean result into the
590 * condition code for selecting between two values, instead of comparing the
591 * boolean result against 0 to generate the condition code.
593 static struct qreg
ntq_emit_bcsel(struct v3d_compile
*c
, nir_alu_instr
*instr
,
596 if (!instr
->src
[0].src
.is_ssa
)
598 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
600 nir_alu_instr
*compare
=
601 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
606 if (ntq_emit_comparison(c
, &dest
, compare
, instr
))
610 vir_PF(c
, src
[0], V3D_QPU_PF_PUSHZ
);
611 return vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFNA
, src
[1], src
[2]));
616 ntq_emit_alu(struct v3d_compile
*c
, nir_alu_instr
*instr
)
618 /* This should always be lowered to ALU operations for V3D. */
619 assert(!instr
->dest
.saturate
);
621 /* Vectors are special in that they have non-scalarized writemasks,
622 * and just take the first swizzle channel for each argument in order
623 * into each writemask channel.
625 if (instr
->op
== nir_op_vec2
||
626 instr
->op
== nir_op_vec3
||
627 instr
->op
== nir_op_vec4
) {
629 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
630 srcs
[i
] = ntq_get_src(c
, instr
->src
[i
].src
,
631 instr
->src
[i
].swizzle
[0]);
632 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
633 ntq_store_dest(c
, &instr
->dest
.dest
, i
,
634 vir_MOV(c
, srcs
[i
]));
638 /* General case: We can just grab the one used channel per src. */
639 struct qreg src
[nir_op_infos
[instr
->op
].num_inputs
];
640 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
641 src
[i
] = ntq_get_alu_src(c
, instr
, i
);
649 result
= vir_MOV(c
, src
[0]);
653 result
= vir_XOR(c
, src
[0], vir_uniform_ui(c
, 1 << 31));
656 result
= vir_NEG(c
, src
[0]);
660 result
= vir_FMUL(c
, src
[0], src
[1]);
663 result
= vir_FADD(c
, src
[0], src
[1]);
666 result
= vir_FSUB(c
, src
[0], src
[1]);
669 result
= vir_FMIN(c
, src
[0], src
[1]);
672 result
= vir_FMAX(c
, src
[0], src
[1]);
676 result
= vir_FTOIZ(c
, src
[0]);
679 result
= vir_FTOUZ(c
, src
[0]);
682 result
= vir_ITOF(c
, src
[0]);
685 result
= vir_UTOF(c
, src
[0]);
688 result
= vir_AND(c
, src
[0], vir_uniform_f(c
, 1.0));
691 result
= vir_AND(c
, src
[0], vir_uniform_ui(c
, 1));
695 vir_PF(c
, src
[0], V3D_QPU_PF_PUSHZ
);
696 result
= vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFNA
,
697 vir_uniform_ui(c
, ~0),
698 vir_uniform_ui(c
, 0)));
702 result
= vir_ADD(c
, src
[0], src
[1]);
705 result
= vir_SHR(c
, src
[0], src
[1]);
708 result
= vir_SUB(c
, src
[0], src
[1]);
711 result
= vir_ASR(c
, src
[0], src
[1]);
714 result
= vir_SHL(c
, src
[0], src
[1]);
717 result
= vir_MIN(c
, src
[0], src
[1]);
720 result
= vir_UMIN(c
, src
[0], src
[1]);
723 result
= vir_MAX(c
, src
[0], src
[1]);
726 result
= vir_UMAX(c
, src
[0], src
[1]);
729 result
= vir_AND(c
, src
[0], src
[1]);
732 result
= vir_OR(c
, src
[0], src
[1]);
735 result
= vir_XOR(c
, src
[0], src
[1]);
738 result
= vir_NOT(c
, src
[0]);
741 case nir_op_ufind_msb
:
742 result
= vir_SUB(c
, vir_uniform_ui(c
, 31), vir_CLZ(c
, src
[0]));
746 result
= vir_UMUL(c
, src
[0], src
[1]);
763 if (!ntq_emit_comparison(c
, &result
, instr
, instr
)) {
764 fprintf(stderr
, "Bad comparison instruction\n");
769 result
= ntq_emit_bcsel(c
, instr
, src
);
772 vir_PF(c
, src
[0], V3D_QPU_PF_PUSHZ
);
773 result
= vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFNA
,
778 result
= vir_RECIP(c
, src
[0]);
781 result
= vir_RSQRT(c
, src
[0]);
784 result
= vir_EXP(c
, src
[0]);
787 result
= vir_LOG(c
, src
[0]);
791 result
= vir_FCEIL(c
, src
[0]);
794 result
= vir_FFLOOR(c
, src
[0]);
796 case nir_op_fround_even
:
797 result
= vir_FROUND(c
, src
[0]);
800 result
= vir_FTRUNC(c
, src
[0]);
803 result
= vir_FSUB(c
, src
[0], vir_FFLOOR(c
, src
[0]));
807 result
= ntq_fsincos(c
, src
[0], false);
810 result
= ntq_fsincos(c
, src
[0], true);
814 result
= ntq_fsign(c
, src
[0]);
817 result
= ntq_isign(c
, src
[0]);
821 result
= vir_FMOV(c
, src
[0]);
822 vir_set_unpack(c
->defs
[result
.index
], 0, V3D_QPU_UNPACK_ABS
);
827 result
= vir_MAX(c
, src
[0],
828 vir_SUB(c
, vir_uniform_ui(c
, 0), src
[0]));
832 case nir_op_fddx_coarse
:
833 case nir_op_fddx_fine
:
834 result
= vir_FDX(c
, src
[0]);
838 case nir_op_fddy_coarse
:
839 case nir_op_fddy_fine
:
840 result
= vir_FDY(c
, src
[0]);
843 case nir_op_uadd_carry
:
844 vir_PF(c
, vir_ADD(c
, src
[0], src
[1]), V3D_QPU_PF_PUSHC
);
845 result
= vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFA
,
846 vir_uniform_ui(c
, ~0),
847 vir_uniform_ui(c
, 0)));
850 case nir_op_pack_half_2x16_split
:
851 result
= vir_VFPACK(c
, src
[0], src
[1]);
854 case nir_op_unpack_half_2x16_split_x
:
855 /* XXX perf: It would be good to be able to merge this unpack
856 * with whatever uses our result.
858 result
= vir_FMOV(c
, src
[0]);
859 vir_set_unpack(c
->defs
[result
.index
], 0, V3D_QPU_UNPACK_L
);
862 case nir_op_unpack_half_2x16_split_y
:
863 result
= vir_FMOV(c
, src
[0]);
864 vir_set_unpack(c
->defs
[result
.index
], 0, V3D_QPU_UNPACK_H
);
868 fprintf(stderr
, "unknown NIR ALU inst: ");
869 nir_print_instr(&instr
->instr
, stderr
);
870 fprintf(stderr
, "\n");
874 /* We have a scalar result, so the instruction should only have a
875 * single channel written to.
877 assert(util_is_power_of_two_or_zero(instr
->dest
.write_mask
));
878 ntq_store_dest(c
, &instr
->dest
.dest
,
879 ffs(instr
->dest
.write_mask
) - 1, result
);
882 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
883 * specifier. They come from a register that's preloaded with 0xffffffff
884 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
885 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
887 #define TLB_TYPE_F16_COLOR (3 << 6)
888 #define TLB_TYPE_I32_COLOR (1 << 6)
889 #define TLB_TYPE_F32_COLOR (0 << 6)
890 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
891 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
892 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
893 #define TLB_F16_SWAP_HI_LO (1 << 1)
894 #define TLB_VEC_SIZE_4_F16 (1 << 0)
895 #define TLB_VEC_SIZE_2_F16 (0 << 0)
896 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
898 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
901 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
902 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
903 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
904 #define TLB_V42_DEPTH_TYPE_INVARIANT (0 << 3) /* Unmodified sideband input used */
905 #define TLB_V42_DEPTH_TYPE_PER_PIXEL (1 << 3) /* QPU result used */
907 /* Stencil is a single 32-bit write. */
908 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
911 emit_frag_end(struct v3d_compile
*c
)
914 if (c->output_sample_mask_index != -1) {
915 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
919 bool has_any_tlb_color_write
= false;
920 for (int rt
= 0; rt
< c
->fs_key
->nr_cbufs
; rt
++) {
921 if (c
->output_color_var
[rt
])
922 has_any_tlb_color_write
= true;
925 if (c
->fs_key
->sample_alpha_to_coverage
&& c
->output_color_var
[0]) {
926 struct nir_variable
*var
= c
->output_color_var
[0];
927 struct qreg
*color
= &c
->outputs
[var
->data
.driver_location
* 4];
929 vir_SETMSF_dest(c
, vir_reg(QFILE_NULL
, 0),
932 vir_FTOC(c
, color
[3])));
935 if (c
->output_position_index
!= -1) {
936 struct qinst
*inst
= vir_MOV_dest(c
,
937 vir_reg(QFILE_TLBU
, 0),
938 c
->outputs
[c
->output_position_index
]);
939 uint8_t tlb_specifier
= TLB_TYPE_DEPTH
;
941 if (c
->devinfo
->ver
>= 42) {
942 tlb_specifier
|= (TLB_V42_DEPTH_TYPE_PER_PIXEL
|
943 TLB_SAMPLE_MODE_PER_PIXEL
);
945 tlb_specifier
|= TLB_DEPTH_TYPE_PER_PIXEL
;
947 inst
->src
[vir_get_implicit_uniform_src(inst
)] =
948 vir_uniform_ui(c
, tlb_specifier
| 0xffffff00);
949 } else if (c
->s
->info
.fs
.uses_discard
||
950 c
->fs_key
->sample_alpha_to_coverage
||
951 !has_any_tlb_color_write
) {
952 /* Emit passthrough Z if it needed to be delayed until shader
953 * end due to potential discards.
955 * Since (single-threaded) fragment shaders always need a TLB
956 * write, emit passthrouh Z if we didn't have any color
957 * buffers and flag us as potentially discarding, so that we
958 * can use Z as the TLB write.
960 c
->s
->info
.fs
.uses_discard
= true;
962 struct qinst
*inst
= vir_MOV_dest(c
,
963 vir_reg(QFILE_TLBU
, 0),
964 vir_reg(QFILE_NULL
, 0));
965 uint8_t tlb_specifier
= TLB_TYPE_DEPTH
;
967 if (c
->devinfo
->ver
>= 42) {
968 /* The spec says the PER_PIXEL flag is ignored for
969 * invariant writes, but the simulator demands it.
971 tlb_specifier
|= (TLB_V42_DEPTH_TYPE_INVARIANT
|
972 TLB_SAMPLE_MODE_PER_PIXEL
);
974 tlb_specifier
|= TLB_DEPTH_TYPE_INVARIANT
;
977 inst
->src
[vir_get_implicit_uniform_src(inst
)] =
978 vir_uniform_ui(c
, tlb_specifier
| 0xffffff00);
981 /* XXX: Performance improvement: Merge Z write and color writes TLB
985 for (int rt
= 0; rt
< c
->fs_key
->nr_cbufs
; rt
++) {
986 if (!c
->output_color_var
[rt
])
989 nir_variable
*var
= c
->output_color_var
[rt
];
990 struct qreg
*color
= &c
->outputs
[var
->data
.driver_location
* 4];
991 int num_components
= glsl_get_vector_elements(var
->type
);
992 uint32_t conf
= 0xffffff00;
995 conf
|= TLB_SAMPLE_MODE_PER_PIXEL
;
996 conf
|= (7 - rt
) << TLB_RENDER_TARGET_SHIFT
;
998 if (c
->fs_key
->swap_color_rb
& (1 << rt
))
999 num_components
= MAX2(num_components
, 3);
1001 assert(num_components
!= 0);
1002 switch (glsl_get_base_type(var
->type
)) {
1003 case GLSL_TYPE_UINT
:
1005 /* The F32 vs I32 distinction was dropped in 4.2. */
1006 if (c
->devinfo
->ver
< 42)
1007 conf
|= TLB_TYPE_I32_COLOR
;
1009 conf
|= TLB_TYPE_F32_COLOR
;
1010 conf
|= ((num_components
- 1) <<
1011 TLB_VEC_SIZE_MINUS_1_SHIFT
);
1013 inst
= vir_MOV_dest(c
, vir_reg(QFILE_TLBU
, 0), color
[0]);
1014 inst
->src
[vir_get_implicit_uniform_src(inst
)] =
1015 vir_uniform_ui(c
, conf
);
1017 for (int i
= 1; i
< num_components
; i
++) {
1018 inst
= vir_MOV_dest(c
, vir_reg(QFILE_TLB
, 0),
1024 struct qreg r
= color
[0];
1025 struct qreg g
= color
[1];
1026 struct qreg b
= color
[2];
1027 struct qreg a
= color
[3];
1029 if (c
->fs_key
->f32_color_rb
& (1 << rt
)) {
1030 conf
|= TLB_TYPE_F32_COLOR
;
1031 conf
|= ((num_components
- 1) <<
1032 TLB_VEC_SIZE_MINUS_1_SHIFT
);
1034 conf
|= TLB_TYPE_F16_COLOR
;
1035 conf
|= TLB_F16_SWAP_HI_LO
;
1036 if (num_components
>= 3)
1037 conf
|= TLB_VEC_SIZE_4_F16
;
1039 conf
|= TLB_VEC_SIZE_2_F16
;
1042 if (c
->fs_key
->swap_color_rb
& (1 << rt
)) {
1047 if (c
->fs_key
->sample_alpha_to_one
)
1048 a
= vir_uniform_f(c
, 1.0);
1050 if (c
->fs_key
->f32_color_rb
& (1 << rt
)) {
1051 inst
= vir_MOV_dest(c
, vir_reg(QFILE_TLBU
, 0), r
);
1052 inst
->src
[vir_get_implicit_uniform_src(inst
)] =
1053 vir_uniform_ui(c
, conf
);
1055 if (num_components
>= 2)
1056 vir_MOV_dest(c
, vir_reg(QFILE_TLB
, 0), g
);
1057 if (num_components
>= 3)
1058 vir_MOV_dest(c
, vir_reg(QFILE_TLB
, 0), b
);
1059 if (num_components
>= 4)
1060 vir_MOV_dest(c
, vir_reg(QFILE_TLB
, 0), a
);
1062 inst
= vir_VFPACK_dest(c
, vir_reg(QFILE_TLB
, 0), r
, g
);
1064 inst
->dst
.file
= QFILE_TLBU
;
1065 inst
->src
[vir_get_implicit_uniform_src(inst
)] =
1066 vir_uniform_ui(c
, conf
);
1069 if (num_components
>= 3)
1070 inst
= vir_VFPACK_dest(c
, vir_reg(QFILE_TLB
, 0), b
, a
);
1079 vir_VPM_WRITE(struct v3d_compile
*c
, struct qreg val
, uint32_t *vpm_index
)
1081 if (c
->devinfo
->ver
>= 40) {
1082 vir_STVPMV(c
, vir_uniform_ui(c
, *vpm_index
), val
);
1083 *vpm_index
= *vpm_index
+ 1;
1085 vir_MOV_dest(c
, vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_VPM
), val
);
1088 c
->num_vpm_writes
++;
1092 emit_scaled_viewport_write(struct v3d_compile
*c
, struct qreg rcp_w
,
1093 uint32_t *vpm_index
)
1095 for (int i
= 0; i
< 2; i
++) {
1096 struct qreg coord
= c
->outputs
[c
->output_position_index
+ i
];
1097 coord
= vir_FMUL(c
, coord
,
1098 vir_uniform(c
, QUNIFORM_VIEWPORT_X_SCALE
+ i
,
1100 coord
= vir_FMUL(c
, coord
, rcp_w
);
1101 vir_VPM_WRITE(c
, vir_FTOIN(c
, coord
), vpm_index
);
1107 emit_zs_write(struct v3d_compile
*c
, struct qreg rcp_w
, uint32_t *vpm_index
)
1109 struct qreg zscale
= vir_uniform(c
, QUNIFORM_VIEWPORT_Z_SCALE
, 0);
1110 struct qreg zoffset
= vir_uniform(c
, QUNIFORM_VIEWPORT_Z_OFFSET
, 0);
1112 struct qreg z
= c
->outputs
[c
->output_position_index
+ 2];
1113 z
= vir_FMUL(c
, z
, zscale
);
1114 z
= vir_FMUL(c
, z
, rcp_w
);
1115 z
= vir_FADD(c
, z
, zoffset
);
1116 vir_VPM_WRITE(c
, z
, vpm_index
);
1120 emit_rcp_wc_write(struct v3d_compile
*c
, struct qreg rcp_w
, uint32_t *vpm_index
)
1122 vir_VPM_WRITE(c
, rcp_w
, vpm_index
);
1126 emit_point_size_write(struct v3d_compile
*c
, uint32_t *vpm_index
)
1128 struct qreg point_size
;
1130 if (c
->output_point_size_index
!= -1)
1131 point_size
= c
->outputs
[c
->output_point_size_index
];
1133 point_size
= vir_uniform_f(c
, 1.0);
1135 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1138 point_size
= vir_FMAX(c
, point_size
, vir_uniform_f(c
, .125));
1140 vir_VPM_WRITE(c
, point_size
, vpm_index
);
1144 emit_vpm_write_setup(struct v3d_compile
*c
)
1146 if (c
->devinfo
->ver
>= 40)
1149 v3d33_vir_vpm_write_setup(c
);
1153 * Sets up c->outputs[c->output_position_index] for the vertex shader
1154 * epilogue, if an output vertex position wasn't specified in the user's
1155 * shader. This may be the case for transform feedback with rasterizer
1159 setup_default_position(struct v3d_compile
*c
)
1161 if (c
->output_position_index
!= -1)
1164 c
->output_position_index
= c
->outputs_array_size
;
1165 for (int i
= 0; i
< 4; i
++) {
1167 c
->output_position_index
+ i
,
1168 VARYING_SLOT_POS
, i
);
1173 emit_vert_end(struct v3d_compile
*c
)
1175 setup_default_position(c
);
1177 uint32_t vpm_index
= 0;
1178 struct qreg rcp_w
= vir_RECIP(c
,
1179 c
->outputs
[c
->output_position_index
+ 3]);
1181 emit_vpm_write_setup(c
);
1183 if (c
->vs_key
->is_coord
) {
1184 for (int i
= 0; i
< 4; i
++)
1185 vir_VPM_WRITE(c
, c
->outputs
[c
->output_position_index
+ i
],
1187 emit_scaled_viewport_write(c
, rcp_w
, &vpm_index
);
1188 if (c
->vs_key
->per_vertex_point_size
) {
1189 emit_point_size_write(c
, &vpm_index
);
1190 /* emit_rcp_wc_write(c, rcp_w); */
1192 /* XXX: Z-only rendering */
1194 emit_zs_write(c
, rcp_w
, &vpm_index
);
1196 emit_scaled_viewport_write(c
, rcp_w
, &vpm_index
);
1197 emit_zs_write(c
, rcp_w
, &vpm_index
);
1198 emit_rcp_wc_write(c
, rcp_w
, &vpm_index
);
1199 if (c
->vs_key
->per_vertex_point_size
)
1200 emit_point_size_write(c
, &vpm_index
);
1203 for (int i
= 0; i
< c
->vs_key
->num_fs_inputs
; i
++) {
1204 struct v3d_varying_slot input
= c
->vs_key
->fs_inputs
[i
];
1207 for (j
= 0; j
< c
->num_outputs
; j
++) {
1208 struct v3d_varying_slot output
= c
->output_slots
[j
];
1210 if (!memcmp(&input
, &output
, sizeof(input
))) {
1211 vir_VPM_WRITE(c
, c
->outputs
[j
],
1216 /* Emit padding if we didn't find a declared VS output for
1219 if (j
== c
->num_outputs
)
1220 vir_VPM_WRITE(c
, vir_uniform_f(c
, 0.0),
1224 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1226 if (c
->devinfo
->ver
>= 40 && c
->devinfo
->ver
<= 42)
1231 v3d_optimize_nir(struct nir_shader
*s
)
1238 NIR_PASS_V(s
, nir_lower_vars_to_ssa
);
1239 NIR_PASS(progress
, s
, nir_lower_alu_to_scalar
);
1240 NIR_PASS(progress
, s
, nir_lower_phis_to_scalar
);
1241 NIR_PASS(progress
, s
, nir_copy_prop
);
1242 NIR_PASS(progress
, s
, nir_opt_remove_phis
);
1243 NIR_PASS(progress
, s
, nir_opt_dce
);
1244 NIR_PASS(progress
, s
, nir_opt_dead_cf
);
1245 NIR_PASS(progress
, s
, nir_opt_cse
);
1246 NIR_PASS(progress
, s
, nir_opt_peephole_select
, 8, true, true);
1247 NIR_PASS(progress
, s
, nir_opt_algebraic
);
1248 NIR_PASS(progress
, s
, nir_opt_constant_folding
);
1249 NIR_PASS(progress
, s
, nir_opt_undef
);
1252 NIR_PASS(progress
, s
, nir_opt_move_load_ubo
);
1256 driver_location_compare(const void *in_a
, const void *in_b
)
1258 const nir_variable
*const *a
= in_a
;
1259 const nir_variable
*const *b
= in_b
;
1261 return (*a
)->data
.driver_location
- (*b
)->data
.driver_location
;
1265 ntq_emit_vpm_read(struct v3d_compile
*c
,
1266 uint32_t *num_components_queued
,
1267 uint32_t *remaining
,
1270 struct qreg vpm
= vir_reg(QFILE_VPM
, vpm_index
);
1272 if (c
->devinfo
->ver
>= 40 ) {
1273 return vir_LDVPMV_IN(c
,
1275 (*num_components_queued
)++));
1278 if (*num_components_queued
!= 0) {
1279 (*num_components_queued
)--;
1281 return vir_MOV(c
, vpm
);
1284 uint32_t num_components
= MIN2(*remaining
, 32);
1286 v3d33_vir_vpm_read_setup(c
, num_components
);
1288 *num_components_queued
= num_components
- 1;
1289 *remaining
-= num_components
;
1292 return vir_MOV(c
, vpm
);
1296 ntq_setup_vpm_inputs(struct v3d_compile
*c
)
1298 /* Figure out how many components of each vertex attribute the shader
1299 * uses. Each variable should have been split to individual
1300 * components and unused ones DCEed. The vertex fetcher will load
1301 * from the start of the attribute to the number of components we
1302 * declare we need in c->vattr_sizes[].
1304 nir_foreach_variable(var
, &c
->s
->inputs
) {
1305 /* No VS attribute array support. */
1306 assert(MAX2(glsl_get_length(var
->type
), 1) == 1);
1308 unsigned loc
= var
->data
.driver_location
;
1309 int start_component
= var
->data
.location_frac
;
1310 int num_components
= glsl_get_components(var
->type
);
1312 c
->vattr_sizes
[loc
] = MAX2(c
->vattr_sizes
[loc
],
1313 start_component
+ num_components
);
1316 unsigned num_components
= 0;
1317 uint32_t vpm_components_queued
= 0;
1318 bool uses_iid
= c
->s
->info
.system_values_read
&
1319 (1ull << SYSTEM_VALUE_INSTANCE_ID
);
1320 bool uses_vid
= c
->s
->info
.system_values_read
&
1321 (1ull << SYSTEM_VALUE_VERTEX_ID
);
1322 num_components
+= uses_iid
;
1323 num_components
+= uses_vid
;
1325 for (int i
= 0; i
< ARRAY_SIZE(c
->vattr_sizes
); i
++)
1326 num_components
+= c
->vattr_sizes
[i
];
1329 c
->iid
= ntq_emit_vpm_read(c
, &vpm_components_queued
,
1330 &num_components
, ~0);
1334 c
->vid
= ntq_emit_vpm_read(c
, &vpm_components_queued
,
1335 &num_components
, ~0);
1338 for (int loc
= 0; loc
< ARRAY_SIZE(c
->vattr_sizes
); loc
++) {
1339 resize_qreg_array(c
, &c
->inputs
, &c
->inputs_array_size
,
1342 for (int i
= 0; i
< c
->vattr_sizes
[loc
]; i
++) {
1343 c
->inputs
[loc
* 4 + i
] =
1344 ntq_emit_vpm_read(c
,
1345 &vpm_components_queued
,
1352 if (c
->devinfo
->ver
>= 40) {
1353 assert(vpm_components_queued
== num_components
);
1355 assert(vpm_components_queued
== 0);
1356 assert(num_components
== 0);
1361 ntq_setup_fs_inputs(struct v3d_compile
*c
)
1363 unsigned num_entries
= 0;
1364 unsigned num_components
= 0;
1365 nir_foreach_variable(var
, &c
->s
->inputs
) {
1367 num_components
+= glsl_get_components(var
->type
);
1370 nir_variable
*vars
[num_entries
];
1373 nir_foreach_variable(var
, &c
->s
->inputs
)
1376 /* Sort the variables so that we emit the input setup in
1377 * driver_location order. This is required for VPM reads, whose data
1378 * is fetched into the VPM in driver_location (TGSI register index)
1381 qsort(&vars
, num_entries
, sizeof(*vars
), driver_location_compare
);
1383 for (unsigned i
= 0; i
< num_entries
; i
++) {
1384 nir_variable
*var
= vars
[i
];
1385 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1386 unsigned loc
= var
->data
.driver_location
;
1388 assert(array_len
== 1);
1390 resize_qreg_array(c
, &c
->inputs
, &c
->inputs_array_size
,
1393 if (var
->data
.location
== VARYING_SLOT_POS
) {
1394 emit_fragcoord_input(c
, loc
);
1395 } else if (var
->data
.location
== VARYING_SLOT_PNTC
||
1396 (var
->data
.location
>= VARYING_SLOT_VAR0
&&
1397 (c
->fs_key
->point_sprite_mask
&
1398 (1 << (var
->data
.location
-
1399 VARYING_SLOT_VAR0
))))) {
1400 c
->inputs
[loc
* 4 + 0] = c
->point_x
;
1401 c
->inputs
[loc
* 4 + 1] = c
->point_y
;
1403 emit_fragment_input(c
, loc
, var
);
1409 ntq_setup_outputs(struct v3d_compile
*c
)
1411 nir_foreach_variable(var
, &c
->s
->outputs
) {
1412 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1413 unsigned loc
= var
->data
.driver_location
* 4;
1415 assert(array_len
== 1);
1418 for (int i
= 0; i
< 4 - var
->data
.location_frac
; i
++) {
1419 add_output(c
, loc
+ var
->data
.location_frac
+ i
,
1421 var
->data
.location_frac
+ i
);
1424 if (c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
) {
1425 switch (var
->data
.location
) {
1426 case FRAG_RESULT_COLOR
:
1427 c
->output_color_var
[0] = var
;
1428 c
->output_color_var
[1] = var
;
1429 c
->output_color_var
[2] = var
;
1430 c
->output_color_var
[3] = var
;
1432 case FRAG_RESULT_DATA0
:
1433 case FRAG_RESULT_DATA1
:
1434 case FRAG_RESULT_DATA2
:
1435 case FRAG_RESULT_DATA3
:
1436 c
->output_color_var
[var
->data
.location
-
1437 FRAG_RESULT_DATA0
] = var
;
1439 case FRAG_RESULT_DEPTH
:
1440 c
->output_position_index
= loc
;
1442 case FRAG_RESULT_SAMPLE_MASK
:
1443 c
->output_sample_mask_index
= loc
;
1447 switch (var
->data
.location
) {
1448 case VARYING_SLOT_POS
:
1449 c
->output_position_index
= loc
;
1451 case VARYING_SLOT_PSIZ
:
1452 c
->output_point_size_index
= loc
;
1460 ntq_setup_uniforms(struct v3d_compile
*c
)
1462 nir_foreach_variable(var
, &c
->s
->uniforms
) {
1463 uint32_t vec4_count
= glsl_count_attribute_slots(var
->type
,
1465 unsigned vec4_size
= 4 * sizeof(float);
1467 declare_uniform_range(c
, var
->data
.driver_location
* vec4_size
,
1468 vec4_count
* vec4_size
);
1474 * Sets up the mapping from nir_register to struct qreg *.
1476 * Each nir_register gets a struct qreg per 32-bit component being stored.
1479 ntq_setup_registers(struct v3d_compile
*c
, struct exec_list
*list
)
1481 foreach_list_typed(nir_register
, nir_reg
, node
, list
) {
1482 unsigned array_len
= MAX2(nir_reg
->num_array_elems
, 1);
1483 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
1485 nir_reg
->num_components
);
1487 _mesa_hash_table_insert(c
->def_ht
, nir_reg
, qregs
);
1489 for (int i
= 0; i
< array_len
* nir_reg
->num_components
; i
++)
1490 qregs
[i
] = vir_get_temp(c
);
1495 ntq_emit_load_const(struct v3d_compile
*c
, nir_load_const_instr
*instr
)
1497 /* XXX perf: Experiment with using immediate loads to avoid having
1498 * these end up in the uniform stream. Watch out for breaking the
1499 * small immediates optimization in the process!
1501 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1502 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1503 qregs
[i
] = vir_uniform_ui(c
, instr
->value
.u32
[i
]);
1505 _mesa_hash_table_insert(c
->def_ht
, &instr
->def
, qregs
);
1509 ntq_emit_ssa_undef(struct v3d_compile
*c
, nir_ssa_undef_instr
*instr
)
1511 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1513 /* VIR needs there to be *some* value, so pick 0 (same as for
1514 * ntq_setup_registers().
1516 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1517 qregs
[i
] = vir_uniform_ui(c
, 0);
1521 ntq_emit_intrinsic(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
)
1525 switch (instr
->intrinsic
) {
1526 case nir_intrinsic_load_uniform
:
1527 assert(instr
->num_components
== 1);
1528 if (nir_src_is_const(instr
->src
[0])) {
1529 offset
= (nir_intrinsic_base(instr
) +
1530 nir_src_as_uint(instr
->src
[0]));
1531 assert(offset
% 4 == 0);
1532 /* We need dwords */
1533 offset
= offset
/ 4;
1534 ntq_store_dest(c
, &instr
->dest
, 0,
1535 vir_uniform(c
, QUNIFORM_UNIFORM
,
1538 ntq_store_dest(c
, &instr
->dest
, 0,
1539 indirect_uniform_load(c
, instr
));
1543 case nir_intrinsic_load_ubo
:
1544 for (int i
= 0; i
< instr
->num_components
; i
++) {
1545 int ubo
= nir_src_as_uint(instr
->src
[0]);
1547 /* XXX perf: On V3D 4.x with uniform offsets, we
1548 * should probably try setting UBOs up in the A
1549 * register file and doing a sequence of loads that
1552 /* Adjust for where we stored the TGSI register base. */
1554 vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_TMUA
),
1555 vir_uniform(c
, QUNIFORM_UBO_ADDR
, 1 + ubo
),
1557 ntq_get_src(c
, instr
->src
[1], 0),
1558 vir_uniform_ui(c
, i
* 4)));
1562 ntq_store_dest(c
, &instr
->dest
, i
, vir_LDTMU(c
));
1566 if (nir_src_is_const(instr
->src
[0])) {
1567 offset
= (nir_intrinsic_base(instr
) +
1568 nir_src_as_uint(instr
->src
[0]));
1569 assert(offset
% 4 == 0);
1570 /* We need dwords */
1571 offset
= offset
/ 4;
1572 ntq_store_dest(c
, &instr
->dest
, 0,
1573 vir_uniform(c
, QUNIFORM_UNIFORM
,
1576 ntq_store_dest(c
, &instr
->dest
, 0,
1577 indirect_uniform_load(c
, instr
));
1581 case nir_intrinsic_load_user_clip_plane
:
1582 for (int i
= 0; i
< instr
->num_components
; i
++) {
1583 ntq_store_dest(c
, &instr
->dest
, i
,
1584 vir_uniform(c
, QUNIFORM_USER_CLIP_PLANE
,
1585 nir_intrinsic_ucp_id(instr
) *
1590 case nir_intrinsic_load_alpha_ref_float
:
1591 ntq_store_dest(c
, &instr
->dest
, 0,
1592 vir_uniform(c
, QUNIFORM_ALPHA_REF
, 0));
1595 case nir_intrinsic_load_sample_mask_in
:
1596 ntq_store_dest(c
, &instr
->dest
, 0, vir_MSF(c
));
1599 case nir_intrinsic_load_front_face
:
1600 /* The register contains 0 (front) or 1 (back), and we need to
1601 * turn it into a NIR bool where true means front.
1603 ntq_store_dest(c
, &instr
->dest
, 0,
1605 vir_uniform_ui(c
, -1),
1609 case nir_intrinsic_load_instance_id
:
1610 ntq_store_dest(c
, &instr
->dest
, 0, vir_MOV(c
, c
->iid
));
1613 case nir_intrinsic_load_vertex_id
:
1614 ntq_store_dest(c
, &instr
->dest
, 0, vir_MOV(c
, c
->vid
));
1617 case nir_intrinsic_load_input
:
1618 for (int i
= 0; i
< instr
->num_components
; i
++) {
1619 offset
= (nir_intrinsic_base(instr
) +
1620 nir_src_as_uint(instr
->src
[0]));
1621 int comp
= nir_intrinsic_component(instr
) + i
;
1622 ntq_store_dest(c
, &instr
->dest
, i
,
1623 vir_MOV(c
, c
->inputs
[offset
* 4 + comp
]));
1627 case nir_intrinsic_store_output
:
1628 offset
= ((nir_intrinsic_base(instr
) +
1629 nir_src_as_uint(instr
->src
[1])) * 4 +
1630 nir_intrinsic_component(instr
));
1632 for (int i
= 0; i
< instr
->num_components
; i
++) {
1633 c
->outputs
[offset
+ i
] =
1634 vir_MOV(c
, ntq_get_src(c
, instr
->src
[0], i
));
1636 c
->num_outputs
= MAX2(c
->num_outputs
,
1637 offset
+ instr
->num_components
);
1640 case nir_intrinsic_discard
:
1641 if (c
->execute
.file
!= QFILE_NULL
) {
1642 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
1643 vir_set_cond(vir_SETMSF_dest(c
, vir_reg(QFILE_NULL
, 0),
1644 vir_uniform_ui(c
, 0)),
1647 vir_SETMSF_dest(c
, vir_reg(QFILE_NULL
, 0),
1648 vir_uniform_ui(c
, 0));
1652 case nir_intrinsic_discard_if
: {
1653 /* true (~0) if we're discarding */
1654 struct qreg cond
= ntq_get_src(c
, instr
->src
[0], 0);
1656 if (c
->execute
.file
!= QFILE_NULL
) {
1657 /* execute == 0 means the channel is active. Invert
1658 * the condition so that we can use zero as "executing
1661 vir_PF(c
, vir_OR(c
, c
->execute
, vir_NOT(c
, cond
)),
1663 vir_set_cond(vir_SETMSF_dest(c
, vir_reg(QFILE_NULL
, 0),
1664 vir_uniform_ui(c
, 0)),
1667 vir_PF(c
, cond
, V3D_QPU_PF_PUSHZ
);
1668 vir_set_cond(vir_SETMSF_dest(c
, vir_reg(QFILE_NULL
, 0),
1669 vir_uniform_ui(c
, 0)),
1677 fprintf(stderr
, "Unknown intrinsic: ");
1678 nir_print_instr(&instr
->instr
, stderr
);
1679 fprintf(stderr
, "\n");
1684 /* Clears (activates) the execute flags for any channels whose jump target
1685 * matches this block.
1687 * XXX perf: Could we be using flpush/flpop somehow for our execution channel
1690 * XXX perf: For uniform control flow, we should be able to skip c->execute
1691 * handling entirely.
1694 ntq_activate_execute_for_block(struct v3d_compile
*c
)
1696 vir_set_pf(vir_XOR_dest(c
, vir_reg(QFILE_NULL
, 0),
1697 c
->execute
, vir_uniform_ui(c
, c
->cur_block
->index
)),
1700 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
, vir_uniform_ui(c
, 0));
1704 ntq_emit_if(struct v3d_compile
*c
, nir_if
*if_stmt
)
1706 nir_block
*nir_else_block
= nir_if_first_else_block(if_stmt
);
1707 bool empty_else_block
=
1708 (nir_else_block
== nir_if_last_else_block(if_stmt
) &&
1709 exec_list_is_empty(&nir_else_block
->instr_list
));
1711 struct qblock
*then_block
= vir_new_block(c
);
1712 struct qblock
*after_block
= vir_new_block(c
);
1713 struct qblock
*else_block
;
1714 if (empty_else_block
)
1715 else_block
= after_block
;
1717 else_block
= vir_new_block(c
);
1719 bool was_top_level
= false;
1720 if (c
->execute
.file
== QFILE_NULL
) {
1721 c
->execute
= vir_MOV(c
, vir_uniform_ui(c
, 0));
1722 was_top_level
= true;
1725 /* Set A for executing (execute == 0) and jumping (if->condition ==
1726 * 0) channels, and then update execute flags for those to point to
1729 * XXX perf: we could reuse ntq_emit_comparison() to generate our if
1730 * condition, and the .uf field to ignore non-executing channels, to
1731 * reduce the overhead of if statements.
1735 ntq_get_src(c
, if_stmt
->condition
, 0)),
1737 vir_MOV_cond(c
, V3D_QPU_COND_IFA
,
1739 vir_uniform_ui(c
, else_block
->index
));
1741 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1744 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
1745 vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ALLNA
);
1746 vir_link_blocks(c
->cur_block
, else_block
);
1747 vir_link_blocks(c
->cur_block
, then_block
);
1749 /* Process the THEN block. */
1750 vir_set_emit_block(c
, then_block
);
1751 ntq_emit_cf_list(c
, &if_stmt
->then_list
);
1753 if (!empty_else_block
) {
1754 /* Handle the end of the THEN block. First, all currently
1755 * active channels update their execute flags to point to
1758 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
1759 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
,
1760 vir_uniform_ui(c
, after_block
->index
));
1762 /* If everything points at ENDIF, then jump there immediately. */
1763 vir_PF(c
, vir_XOR(c
, c
->execute
,
1764 vir_uniform_ui(c
, after_block
->index
)),
1766 vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ALLA
);
1767 vir_link_blocks(c
->cur_block
, after_block
);
1768 vir_link_blocks(c
->cur_block
, else_block
);
1770 vir_set_emit_block(c
, else_block
);
1771 ntq_activate_execute_for_block(c
);
1772 ntq_emit_cf_list(c
, &if_stmt
->else_list
);
1775 vir_link_blocks(c
->cur_block
, after_block
);
1777 vir_set_emit_block(c
, after_block
);
1779 c
->execute
= c
->undef
;
1781 ntq_activate_execute_for_block(c
);
1785 ntq_emit_jump(struct v3d_compile
*c
, nir_jump_instr
*jump
)
1787 switch (jump
->type
) {
1788 case nir_jump_break
:
1789 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
1790 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
,
1791 vir_uniform_ui(c
, c
->loop_break_block
->index
));
1794 case nir_jump_continue
:
1795 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
1796 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
,
1797 vir_uniform_ui(c
, c
->loop_cont_block
->index
));
1800 case nir_jump_return
:
1801 unreachable("All returns shouold be lowered\n");
1806 ntq_emit_instr(struct v3d_compile
*c
, nir_instr
*instr
)
1808 switch (instr
->type
) {
1809 case nir_instr_type_alu
:
1810 ntq_emit_alu(c
, nir_instr_as_alu(instr
));
1813 case nir_instr_type_intrinsic
:
1814 ntq_emit_intrinsic(c
, nir_instr_as_intrinsic(instr
));
1817 case nir_instr_type_load_const
:
1818 ntq_emit_load_const(c
, nir_instr_as_load_const(instr
));
1821 case nir_instr_type_ssa_undef
:
1822 ntq_emit_ssa_undef(c
, nir_instr_as_ssa_undef(instr
));
1825 case nir_instr_type_tex
:
1826 ntq_emit_tex(c
, nir_instr_as_tex(instr
));
1829 case nir_instr_type_jump
:
1830 ntq_emit_jump(c
, nir_instr_as_jump(instr
));
1834 fprintf(stderr
, "Unknown NIR instr type: ");
1835 nir_print_instr(instr
, stderr
);
1836 fprintf(stderr
, "\n");
1842 ntq_emit_block(struct v3d_compile
*c
, nir_block
*block
)
1844 nir_foreach_instr(instr
, block
) {
1845 ntq_emit_instr(c
, instr
);
1849 static void ntq_emit_cf_list(struct v3d_compile
*c
, struct exec_list
*list
);
1852 ntq_emit_loop(struct v3d_compile
*c
, nir_loop
*loop
)
1854 bool was_top_level
= false;
1855 if (c
->execute
.file
== QFILE_NULL
) {
1856 c
->execute
= vir_MOV(c
, vir_uniform_ui(c
, 0));
1857 was_top_level
= true;
1860 struct qblock
*save_loop_cont_block
= c
->loop_cont_block
;
1861 struct qblock
*save_loop_break_block
= c
->loop_break_block
;
1863 c
->loop_cont_block
= vir_new_block(c
);
1864 c
->loop_break_block
= vir_new_block(c
);
1866 vir_link_blocks(c
->cur_block
, c
->loop_cont_block
);
1867 vir_set_emit_block(c
, c
->loop_cont_block
);
1868 ntq_activate_execute_for_block(c
);
1870 ntq_emit_cf_list(c
, &loop
->body
);
1872 /* Re-enable any previous continues now, so our ANYA check below
1875 * XXX: Use the .ORZ flags update, instead.
1877 vir_PF(c
, vir_XOR(c
,
1879 vir_uniform_ui(c
, c
->loop_cont_block
->index
)),
1881 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
, vir_uniform_ui(c
, 0));
1883 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
1885 struct qinst
*branch
= vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ANYA
);
1886 /* Pixels that were not dispatched or have been discarded should not
1887 * contribute to looping again.
1889 branch
->qpu
.branch
.msfign
= V3D_QPU_MSFIGN_P
;
1890 vir_link_blocks(c
->cur_block
, c
->loop_cont_block
);
1891 vir_link_blocks(c
->cur_block
, c
->loop_break_block
);
1893 vir_set_emit_block(c
, c
->loop_break_block
);
1895 c
->execute
= c
->undef
;
1897 ntq_activate_execute_for_block(c
);
1899 c
->loop_break_block
= save_loop_break_block
;
1900 c
->loop_cont_block
= save_loop_cont_block
;
1906 ntq_emit_function(struct v3d_compile
*c
, nir_function_impl
*func
)
1908 fprintf(stderr
, "FUNCTIONS not handled.\n");
1913 ntq_emit_cf_list(struct v3d_compile
*c
, struct exec_list
*list
)
1915 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
1916 switch (node
->type
) {
1917 case nir_cf_node_block
:
1918 ntq_emit_block(c
, nir_cf_node_as_block(node
));
1921 case nir_cf_node_if
:
1922 ntq_emit_if(c
, nir_cf_node_as_if(node
));
1925 case nir_cf_node_loop
:
1926 ntq_emit_loop(c
, nir_cf_node_as_loop(node
));
1929 case nir_cf_node_function
:
1930 ntq_emit_function(c
, nir_cf_node_as_function(node
));
1934 fprintf(stderr
, "Unknown NIR node type\n");
1941 ntq_emit_impl(struct v3d_compile
*c
, nir_function_impl
*impl
)
1943 ntq_setup_registers(c
, &impl
->registers
);
1944 ntq_emit_cf_list(c
, &impl
->body
);
1948 nir_to_vir(struct v3d_compile
*c
)
1950 if (c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
) {
1951 c
->payload_w
= vir_MOV(c
, vir_reg(QFILE_REG
, 0));
1952 c
->payload_w_centroid
= vir_MOV(c
, vir_reg(QFILE_REG
, 1));
1953 c
->payload_z
= vir_MOV(c
, vir_reg(QFILE_REG
, 2));
1955 /* XXX perf: We could set the "disable implicit point/line
1956 * varyings" field in the shader record and not emit these, if
1957 * they're not going to be used.
1959 if (c
->fs_key
->is_points
) {
1960 c
->point_x
= emit_fragment_varying(c
, NULL
, 0);
1961 c
->point_y
= emit_fragment_varying(c
, NULL
, 0);
1962 } else if (c
->fs_key
->is_lines
) {
1963 c
->line_x
= emit_fragment_varying(c
, NULL
, 0);
1967 if (c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
)
1968 ntq_setup_fs_inputs(c
);
1970 ntq_setup_vpm_inputs(c
);
1972 ntq_setup_outputs(c
);
1973 ntq_setup_uniforms(c
);
1974 ntq_setup_registers(c
, &c
->s
->registers
);
1976 /* Find the main function and emit the body. */
1977 nir_foreach_function(function
, c
->s
) {
1978 assert(strcmp(function
->name
, "main") == 0);
1979 assert(function
->impl
);
1980 ntq_emit_impl(c
, function
->impl
);
1984 const nir_shader_compiler_options v3d_nir_options
= {
1985 .lower_all_io_to_temps
= true,
1986 .lower_extract_byte
= true,
1987 .lower_extract_word
= true,
1989 .lower_bitfield_insert_to_shifts
= true,
1990 .lower_bitfield_extract_to_shifts
= true,
1991 .lower_bitfield_reverse
= true,
1992 .lower_bit_count
= true,
1993 .lower_pack_unorm_2x16
= true,
1994 .lower_pack_snorm_2x16
= true,
1995 .lower_pack_unorm_4x8
= true,
1996 .lower_pack_snorm_4x8
= true,
1997 .lower_unpack_unorm_4x8
= true,
1998 .lower_unpack_snorm_4x8
= true,
1999 .lower_pack_half_2x16
= true,
2000 .lower_unpack_half_2x16
= true,
2002 .lower_find_lsb
= true,
2004 .lower_flrp32
= true,
2007 .lower_fsqrt
= true,
2008 .lower_ifind_msb
= true,
2009 .lower_ldexp
= true,
2010 .lower_mul_high
= true,
2011 .lower_wpos_pntc
= true,
2012 .native_integers
= true,
2016 * When demoting a shader down to single-threaded, removes the THRSW
2017 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
2021 vir_remove_thrsw(struct v3d_compile
*c
)
2023 vir_for_each_block(block
, c
) {
2024 vir_for_each_inst_safe(inst
, block
) {
2025 if (inst
->qpu
.sig
.thrsw
)
2026 vir_remove_instruction(c
, inst
);
2030 c
->last_thrsw
= NULL
;
2034 vir_emit_last_thrsw(struct v3d_compile
*c
)
2036 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
2037 * switching, so disable threads if we didn't do any TMU ops (each of
2038 * which would have emitted a THRSW).
2040 if (!c
->last_thrsw_at_top_level
&& c
->devinfo
->ver
< 41) {
2043 vir_remove_thrsw(c
);
2047 /* If we're threaded and the last THRSW was in conditional code, then
2048 * we need to emit another one so that we can flag it as the last
2051 if (c
->last_thrsw
&& !c
->last_thrsw_at_top_level
) {
2052 assert(c
->devinfo
->ver
>= 41);
2056 /* If we're threaded, then we need to mark the last THRSW instruction
2057 * so we can emit a pair of them at QPU emit time.
2059 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2060 * post-last-THRSW state, so we can skip this.
2062 if (!c
->last_thrsw
&& c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
) {
2063 assert(c
->devinfo
->ver
>= 41);
2068 c
->last_thrsw
->is_last_thrsw
= true;
2071 /* There's a flag in the shader for "center W is needed for reasons other than
2072 * non-centroid varyings", so we just walk the program after VIR optimization
2073 * to see if it's used. It should be harmless to set even if we only use
2074 * center W for varyings.
2077 vir_check_payload_w(struct v3d_compile
*c
)
2079 if (c
->s
->info
.stage
!= MESA_SHADER_FRAGMENT
)
2082 vir_for_each_inst_inorder(inst
, c
) {
2083 for (int i
= 0; i
< vir_get_nsrc(inst
); i
++) {
2084 if (inst
->src
[i
].file
== QFILE_REG
&&
2085 inst
->src
[i
].index
== 0) {
2086 c
->uses_center_w
= true;
2095 v3d_nir_to_vir(struct v3d_compile
*c
)
2097 if (V3D_DEBUG
& (V3D_DEBUG_NIR
|
2098 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
))) {
2099 fprintf(stderr
, "%s prog %d/%d NIR:\n",
2100 vir_get_stage_name(c
),
2101 c
->program_id
, c
->variant_id
);
2102 nir_print_shader(c
->s
, stderr
);
2107 /* Emit the last THRSW before STVPM and TLB writes. */
2108 vir_emit_last_thrsw(c
);
2110 switch (c
->s
->info
.stage
) {
2111 case MESA_SHADER_FRAGMENT
:
2114 case MESA_SHADER_VERTEX
:
2118 unreachable("bad stage");
2121 if (V3D_DEBUG
& (V3D_DEBUG_VIR
|
2122 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
))) {
2123 fprintf(stderr
, "%s prog %d/%d pre-opt VIR:\n",
2124 vir_get_stage_name(c
),
2125 c
->program_id
, c
->variant_id
);
2127 fprintf(stderr
, "\n");
2131 vir_lower_uniforms(c
);
2133 vir_check_payload_w(c
);
2135 /* XXX perf: On VC4, we do a VIR-level instruction scheduling here.
2136 * We used that on that platform to pipeline TMU writes and reduce the
2137 * number of thread switches, as well as try (mostly successfully) to
2138 * reduce maximum register pressure to allow more threads. We should
2139 * do something of that sort for V3D -- either instruction scheduling
2140 * here, or delay the the THRSW and LDTMUs from our texture
2141 * instructions until the results are needed.
2144 if (V3D_DEBUG
& (V3D_DEBUG_VIR
|
2145 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
))) {
2146 fprintf(stderr
, "%s prog %d/%d VIR:\n",
2147 vir_get_stage_name(c
),
2148 c
->program_id
, c
->variant_id
);
2150 fprintf(stderr
, "\n");
2153 /* Attempt to allocate registers for the temporaries. If we fail,
2154 * reduce thread count and try again.
2156 int min_threads
= (c
->devinfo
->ver
>= 41) ? 2 : 1;
2157 struct qpu_reg
*temp_registers
;
2160 temp_registers
= v3d_register_allocate(c
, &spilled
);
2167 if (c
->threads
== min_threads
) {
2168 fprintf(stderr
, "Failed to register allocate at %d threads:\n",
2177 if (c
->threads
== 1)
2178 vir_remove_thrsw(c
);
2181 v3d_vir_to_qpu(c
, temp_registers
);