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v3d: Drop in a bunch of notes about performance improvement opportunities.
[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
34
35 static void
36 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
37
38 static void
39 resize_qreg_array(struct v3d_compile *c,
40 struct qreg **regs,
41 uint32_t *size,
42 uint32_t decl_size)
43 {
44 if (*size >= decl_size)
45 return;
46
47 uint32_t old_size = *size;
48 *size = MAX2(*size * 2, decl_size);
49 *regs = reralloc(c, *regs, struct qreg, *size);
50 if (!*regs) {
51 fprintf(stderr, "Malloc failure\n");
52 abort();
53 }
54
55 for (uint32_t i = old_size; i < *size; i++)
56 (*regs)[i] = c->undef;
57 }
58
59 void
60 vir_emit_thrsw(struct v3d_compile *c)
61 {
62 if (c->threads == 1)
63 return;
64
65 /* Always thread switch after each texture operation for now.
66 *
67 * We could do better by batching a bunch of texture fetches up and
68 * then doing one thread switch and collecting all their results
69 * afterward.
70 */
71 c->last_thrsw = vir_NOP(c);
72 c->last_thrsw->qpu.sig.thrsw = true;
73 c->last_thrsw_at_top_level = (c->execute.file == QFILE_NULL);
74 }
75
76 static struct qreg
77 indirect_uniform_load(struct v3d_compile *c, nir_intrinsic_instr *intr)
78 {
79 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
80 uint32_t offset = nir_intrinsic_base(intr);
81 struct v3d_ubo_range *range = NULL;
82 unsigned i;
83
84 for (i = 0; i < c->num_ubo_ranges; i++) {
85 range = &c->ubo_ranges[i];
86 if (offset >= range->src_offset &&
87 offset < range->src_offset + range->size) {
88 break;
89 }
90 }
91 /* The driver-location-based offset always has to be within a declared
92 * uniform range.
93 */
94 assert(i != c->num_ubo_ranges);
95 if (!c->ubo_range_used[i]) {
96 c->ubo_range_used[i] = true;
97 range->dst_offset = c->next_ubo_dst_offset;
98 c->next_ubo_dst_offset += range->size;
99 }
100
101 offset -= range->src_offset;
102
103 if (range->dst_offset + offset != 0) {
104 indirect_offset = vir_ADD(c, indirect_offset,
105 vir_uniform_ui(c, range->dst_offset +
106 offset));
107 }
108
109 /* Adjust for where we stored the TGSI register base. */
110 vir_ADD_dest(c,
111 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA),
112 vir_uniform(c, QUNIFORM_UBO_ADDR, 0),
113 indirect_offset);
114
115 vir_emit_thrsw(c);
116 return vir_LDTMU(c);
117 }
118
119 static struct qreg *
120 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
121 {
122 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
123 def->num_components);
124 _mesa_hash_table_insert(c->def_ht, def, qregs);
125 return qregs;
126 }
127
128 /**
129 * This function is responsible for getting VIR results into the associated
130 * storage for a NIR instruction.
131 *
132 * If it's a NIR SSA def, then we just set the associated hash table entry to
133 * the new result.
134 *
135 * If it's a NIR reg, then we need to update the existing qreg assigned to the
136 * NIR destination with the incoming value. To do that without introducing
137 * new MOVs, we require that the incoming qreg either be a uniform, or be
138 * SSA-defined by the previous VIR instruction in the block and rewritable by
139 * this function. That lets us sneak ahead and insert the SF flag beforehand
140 * (knowing that the previous instruction doesn't depend on flags) and rewrite
141 * its destination to be the NIR reg's destination
142 */
143 void
144 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
145 struct qreg result)
146 {
147 struct qinst *last_inst = NULL;
148 if (!list_empty(&c->cur_block->instructions))
149 last_inst = (struct qinst *)c->cur_block->instructions.prev;
150
151 assert(result.file == QFILE_UNIF ||
152 (result.file == QFILE_TEMP &&
153 last_inst && last_inst == c->defs[result.index]));
154
155 if (dest->is_ssa) {
156 assert(chan < dest->ssa.num_components);
157
158 struct qreg *qregs;
159 struct hash_entry *entry =
160 _mesa_hash_table_search(c->def_ht, &dest->ssa);
161
162 if (entry)
163 qregs = entry->data;
164 else
165 qregs = ntq_init_ssa_def(c, &dest->ssa);
166
167 qregs[chan] = result;
168 } else {
169 nir_register *reg = dest->reg.reg;
170 assert(dest->reg.base_offset == 0);
171 assert(reg->num_array_elems == 0);
172 struct hash_entry *entry =
173 _mesa_hash_table_search(c->def_ht, reg);
174 struct qreg *qregs = entry->data;
175
176 /* Insert a MOV if the source wasn't an SSA def in the
177 * previous instruction.
178 */
179 if (result.file == QFILE_UNIF) {
180 result = vir_MOV(c, result);
181 last_inst = c->defs[result.index];
182 }
183
184 /* We know they're both temps, so just rewrite index. */
185 c->defs[last_inst->dst.index] = NULL;
186 last_inst->dst.index = qregs[chan].index;
187
188 /* If we're in control flow, then make this update of the reg
189 * conditional on the execution mask.
190 */
191 if (c->execute.file != QFILE_NULL) {
192 last_inst->dst.index = qregs[chan].index;
193
194 /* Set the flags to the current exec mask.
195 */
196 c->cursor = vir_before_inst(last_inst);
197 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
198 c->cursor = vir_after_inst(last_inst);
199
200 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
201 last_inst->cond_is_exec_mask = true;
202 }
203 }
204 }
205
206 struct qreg
207 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
208 {
209 struct hash_entry *entry;
210 if (src.is_ssa) {
211 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
212 assert(i < src.ssa->num_components);
213 } else {
214 nir_register *reg = src.reg.reg;
215 entry = _mesa_hash_table_search(c->def_ht, reg);
216 assert(reg->num_array_elems == 0);
217 assert(src.reg.base_offset == 0);
218 assert(i < reg->num_components);
219 }
220
221 struct qreg *qregs = entry->data;
222 return qregs[i];
223 }
224
225 static struct qreg
226 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
227 unsigned src)
228 {
229 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
230 unsigned chan = ffs(instr->dest.write_mask) - 1;
231 struct qreg r = ntq_get_src(c, instr->src[src].src,
232 instr->src[src].swizzle[chan]);
233
234 assert(!instr->src[src].abs);
235 assert(!instr->src[src].negate);
236
237 return r;
238 };
239
240 static struct qreg
241 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
242 {
243 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
244 }
245
246 static void
247 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
248 {
249 unsigned unit = instr->texture_index;
250 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
251 int dest_size = nir_tex_instr_dest_size(instr);
252
253 struct qreg lod = c->undef;
254 if (lod_index != -1)
255 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
256
257 for (int i = 0; i < dest_size; i++) {
258 assert(i < 3);
259 enum quniform_contents contents;
260
261 if (instr->is_array && i == dest_size - 1)
262 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
263 else
264 contents = QUNIFORM_TEXTURE_WIDTH + i;
265
266 struct qreg size = vir_uniform(c, contents, unit);
267
268 switch (instr->sampler_dim) {
269 case GLSL_SAMPLER_DIM_1D:
270 case GLSL_SAMPLER_DIM_2D:
271 case GLSL_SAMPLER_DIM_3D:
272 case GLSL_SAMPLER_DIM_CUBE:
273 /* Don't minify the array size. */
274 if (!(instr->is_array && i == dest_size - 1)) {
275 size = ntq_minify(c, size, lod);
276 }
277 break;
278
279 case GLSL_SAMPLER_DIM_RECT:
280 /* There's no LOD field for rects */
281 break;
282
283 default:
284 unreachable("Bad sampler type");
285 }
286
287 ntq_store_dest(c, &instr->dest, i, size);
288 }
289 }
290
291 static void
292 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
293 {
294 unsigned unit = instr->texture_index;
295
296 /* Since each texture sampling op requires uploading uniforms to
297 * reference the texture, there's no HW support for texture size and
298 * you just upload uniforms containing the size.
299 */
300 switch (instr->op) {
301 case nir_texop_query_levels:
302 ntq_store_dest(c, &instr->dest, 0,
303 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
304 return;
305 case nir_texop_txs:
306 ntq_emit_txs(c, instr);
307 return;
308 default:
309 break;
310 }
311
312 if (c->devinfo->ver >= 40)
313 v3d40_vir_emit_tex(c, instr);
314 else
315 v3d33_vir_emit_tex(c, instr);
316 }
317
318 static struct qreg
319 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
320 {
321 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
322 if (is_cos)
323 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
324
325 struct qreg periods = vir_FROUND(c, input);
326 struct qreg sin_output = vir_SIN(c, vir_FSUB(c, input, periods));
327 return vir_XOR(c, sin_output, vir_SHL(c,
328 vir_FTOIN(c, periods),
329 vir_uniform_ui(c, -1)));
330 }
331
332 static struct qreg
333 ntq_fsign(struct v3d_compile *c, struct qreg src)
334 {
335 struct qreg t = vir_get_temp(c);
336
337 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
338 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHZ);
339 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
340 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHN);
341 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
342 return vir_MOV(c, t);
343 }
344
345 static struct qreg
346 ntq_isign(struct v3d_compile *c, struct qreg src)
347 {
348 struct qreg t = vir_get_temp(c);
349
350 vir_MOV_dest(c, t, vir_uniform_ui(c, 0));
351 vir_PF(c, vir_MOV(c, src), V3D_QPU_PF_PUSHZ);
352 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_ui(c, 1));
353 vir_PF(c, vir_MOV(c, src), V3D_QPU_PF_PUSHN);
354 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_ui(c, -1));
355 return vir_MOV(c, t);
356 }
357
358 static void
359 emit_fragcoord_input(struct v3d_compile *c, int attr)
360 {
361 c->inputs[attr * 4 + 0] = vir_FXCD(c);
362 c->inputs[attr * 4 + 1] = vir_FYCD(c);
363 c->inputs[attr * 4 + 2] = c->payload_z;
364 c->inputs[attr * 4 + 3] = vir_RECIP(c, c->payload_w);
365 }
366
367 static struct qreg
368 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
369 uint8_t swizzle)
370 {
371 struct qreg r3 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R3);
372 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
373
374 struct qreg vary;
375 if (c->devinfo->ver >= 41) {
376 struct qinst *ldvary = vir_add_inst(V3D_QPU_A_NOP, c->undef,
377 c->undef, c->undef);
378 ldvary->qpu.sig.ldvary = true;
379 vary = vir_emit_def(c, ldvary);
380 } else {
381 vir_NOP(c)->qpu.sig.ldvary = true;
382 vary = r3;
383 }
384
385 /* For gl_PointCoord input or distance along a line, we'll be called
386 * with no nir_variable, and we don't count toward VPM size so we
387 * don't track an input slot.
388 */
389 if (!var) {
390 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
391 }
392
393 int i = c->num_inputs++;
394 c->input_slots[i] = v3d_slot_from_slot_and_component(var->data.location,
395 swizzle);
396
397 switch (var->data.interpolation) {
398 case INTERP_MODE_NONE:
399 /* If a gl_FrontColor or gl_BackColor input has no interp
400 * qualifier, then if we're using glShadeModel(GL_FLAT) it
401 * needs to be flat shaded.
402 */
403 switch (var->data.location) {
404 case VARYING_SLOT_COL0:
405 case VARYING_SLOT_COL1:
406 case VARYING_SLOT_BFC0:
407 case VARYING_SLOT_BFC1:
408 if (c->fs_key->shade_model_flat) {
409 BITSET_SET(c->flat_shade_flags, i);
410 vir_MOV_dest(c, c->undef, vary);
411 return vir_MOV(c, r5);
412 } else {
413 return vir_FADD(c, vir_FMUL(c, vary,
414 c->payload_w), r5);
415 }
416 default:
417 break;
418 }
419 /* FALLTHROUGH */
420 case INTERP_MODE_SMOOTH:
421 if (var->data.centroid) {
422 BITSET_SET(c->centroid_flags, i);
423 return vir_FADD(c, vir_FMUL(c, vary,
424 c->payload_w_centroid), r5);
425 } else {
426 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
427 }
428 case INTERP_MODE_NOPERSPECTIVE:
429 BITSET_SET(c->noperspective_flags, i);
430 return vir_FADD(c, vir_MOV(c, vary), r5);
431 case INTERP_MODE_FLAT:
432 BITSET_SET(c->flat_shade_flags, i);
433 vir_MOV_dest(c, c->undef, vary);
434 return vir_MOV(c, r5);
435 default:
436 unreachable("Bad interp mode");
437 }
438 }
439
440 static void
441 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var)
442 {
443 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
444 int chan = var->data.location_frac + i;
445 c->inputs[attr * 4 + chan] =
446 emit_fragment_varying(c, var, chan);
447 }
448 }
449
450 static void
451 add_output(struct v3d_compile *c,
452 uint32_t decl_offset,
453 uint8_t slot,
454 uint8_t swizzle)
455 {
456 uint32_t old_array_size = c->outputs_array_size;
457 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
458 decl_offset + 1);
459
460 if (old_array_size != c->outputs_array_size) {
461 c->output_slots = reralloc(c,
462 c->output_slots,
463 struct v3d_varying_slot,
464 c->outputs_array_size);
465 }
466
467 c->output_slots[decl_offset] =
468 v3d_slot_from_slot_and_component(slot, swizzle);
469 }
470
471 static void
472 declare_uniform_range(struct v3d_compile *c, uint32_t start, uint32_t size)
473 {
474 unsigned array_id = c->num_ubo_ranges++;
475 if (array_id >= c->ubo_ranges_array_size) {
476 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
477 array_id + 1);
478 c->ubo_ranges = reralloc(c, c->ubo_ranges,
479 struct v3d_ubo_range,
480 c->ubo_ranges_array_size);
481 c->ubo_range_used = reralloc(c, c->ubo_range_used,
482 bool,
483 c->ubo_ranges_array_size);
484 }
485
486 c->ubo_ranges[array_id].dst_offset = 0;
487 c->ubo_ranges[array_id].src_offset = start;
488 c->ubo_ranges[array_id].size = size;
489 c->ubo_range_used[array_id] = false;
490 }
491
492 /**
493 * If compare_instr is a valid comparison instruction, emits the
494 * compare_instr's comparison and returns the sel_instr's return value based
495 * on the compare_instr's result.
496 */
497 static bool
498 ntq_emit_comparison(struct v3d_compile *c, struct qreg *dest,
499 nir_alu_instr *compare_instr,
500 nir_alu_instr *sel_instr)
501 {
502 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
503 struct qreg src1;
504 if (nir_op_infos[compare_instr->op].num_inputs > 1)
505 src1 = ntq_get_alu_src(c, compare_instr, 1);
506 bool cond_invert = false;
507
508 switch (compare_instr->op) {
509 case nir_op_feq:
510 case nir_op_seq:
511 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHZ);
512 break;
513 case nir_op_ieq:
514 vir_PF(c, vir_XOR(c, src0, src1), V3D_QPU_PF_PUSHZ);
515 break;
516
517 case nir_op_fne:
518 case nir_op_sne:
519 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHZ);
520 cond_invert = true;
521 break;
522 case nir_op_ine:
523 vir_PF(c, vir_XOR(c, src0, src1), V3D_QPU_PF_PUSHZ);
524 cond_invert = true;
525 break;
526
527 case nir_op_fge:
528 case nir_op_sge:
529 vir_PF(c, vir_FCMP(c, src1, src0), V3D_QPU_PF_PUSHC);
530 break;
531 case nir_op_ige:
532 vir_PF(c, vir_MIN(c, src1, src0), V3D_QPU_PF_PUSHC);
533 cond_invert = true;
534 break;
535 case nir_op_uge:
536 vir_PF(c, vir_SUB(c, src0, src1), V3D_QPU_PF_PUSHC);
537 cond_invert = true;
538 break;
539
540 case nir_op_slt:
541 case nir_op_flt:
542 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHN);
543 break;
544 case nir_op_ilt:
545 vir_PF(c, vir_MIN(c, src1, src0), V3D_QPU_PF_PUSHC);
546 break;
547 case nir_op_ult:
548 vir_PF(c, vir_SUB(c, src0, src1), V3D_QPU_PF_PUSHC);
549 break;
550
551 default:
552 return false;
553 }
554
555 enum v3d_qpu_cond cond = (cond_invert ?
556 V3D_QPU_COND_IFNA :
557 V3D_QPU_COND_IFA);
558
559 switch (sel_instr->op) {
560 case nir_op_seq:
561 case nir_op_sne:
562 case nir_op_sge:
563 case nir_op_slt:
564 *dest = vir_SEL(c, cond,
565 vir_uniform_f(c, 1.0), vir_uniform_f(c, 0.0));
566 break;
567
568 case nir_op_bcsel:
569 *dest = vir_SEL(c, cond,
570 ntq_get_alu_src(c, sel_instr, 1),
571 ntq_get_alu_src(c, sel_instr, 2));
572 break;
573
574 default:
575 *dest = vir_SEL(c, cond,
576 vir_uniform_ui(c, ~0), vir_uniform_ui(c, 0));
577 break;
578 }
579
580 /* Make the temporary for nir_store_dest(). */
581 *dest = vir_MOV(c, *dest);
582
583 return true;
584 }
585
586 /**
587 * Attempts to fold a comparison generating a boolean result into the
588 * condition code for selecting between two values, instead of comparing the
589 * boolean result against 0 to generate the condition code.
590 */
591 static struct qreg ntq_emit_bcsel(struct v3d_compile *c, nir_alu_instr *instr,
592 struct qreg *src)
593 {
594 if (!instr->src[0].src.is_ssa)
595 goto out;
596 if (instr->src[0].src.ssa->parent_instr->type != nir_instr_type_alu)
597 goto out;
598 nir_alu_instr *compare =
599 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
600 if (!compare)
601 goto out;
602
603 struct qreg dest;
604 if (ntq_emit_comparison(c, &dest, compare, instr))
605 return dest;
606
607 out:
608 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
609 return vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA, src[1], src[2]));
610 }
611
612
613 static void
614 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
615 {
616 /* This should always be lowered to ALU operations for V3D. */
617 assert(!instr->dest.saturate);
618
619 /* Vectors are special in that they have non-scalarized writemasks,
620 * and just take the first swizzle channel for each argument in order
621 * into each writemask channel.
622 */
623 if (instr->op == nir_op_vec2 ||
624 instr->op == nir_op_vec3 ||
625 instr->op == nir_op_vec4) {
626 struct qreg srcs[4];
627 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
628 srcs[i] = ntq_get_src(c, instr->src[i].src,
629 instr->src[i].swizzle[0]);
630 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
631 ntq_store_dest(c, &instr->dest.dest, i,
632 vir_MOV(c, srcs[i]));
633 return;
634 }
635
636 /* General case: We can just grab the one used channel per src. */
637 struct qreg src[nir_op_infos[instr->op].num_inputs];
638 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
639 src[i] = ntq_get_alu_src(c, instr, i);
640 }
641
642 struct qreg result;
643
644 switch (instr->op) {
645 case nir_op_fmov:
646 case nir_op_imov:
647 result = vir_MOV(c, src[0]);
648 break;
649
650 case nir_op_fneg:
651 result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
652 break;
653 case nir_op_ineg:
654 result = vir_NEG(c, src[0]);
655 break;
656
657 case nir_op_fmul:
658 result = vir_FMUL(c, src[0], src[1]);
659 break;
660 case nir_op_fadd:
661 result = vir_FADD(c, src[0], src[1]);
662 break;
663 case nir_op_fsub:
664 result = vir_FSUB(c, src[0], src[1]);
665 break;
666 case nir_op_fmin:
667 result = vir_FMIN(c, src[0], src[1]);
668 break;
669 case nir_op_fmax:
670 result = vir_FMAX(c, src[0], src[1]);
671 break;
672
673 case nir_op_f2i32:
674 result = vir_FTOIZ(c, src[0]);
675 break;
676 case nir_op_f2u32:
677 result = vir_FTOUZ(c, src[0]);
678 break;
679 case nir_op_i2f32:
680 result = vir_ITOF(c, src[0]);
681 break;
682 case nir_op_u2f32:
683 result = vir_UTOF(c, src[0]);
684 break;
685 case nir_op_b2f32:
686 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
687 break;
688 case nir_op_b2i32:
689 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
690 break;
691 case nir_op_i2b32:
692 case nir_op_f2b32:
693 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
694 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
695 vir_uniform_ui(c, ~0),
696 vir_uniform_ui(c, 0)));
697 break;
698
699 case nir_op_iadd:
700 result = vir_ADD(c, src[0], src[1]);
701 break;
702 case nir_op_ushr:
703 result = vir_SHR(c, src[0], src[1]);
704 break;
705 case nir_op_isub:
706 result = vir_SUB(c, src[0], src[1]);
707 break;
708 case nir_op_ishr:
709 result = vir_ASR(c, src[0], src[1]);
710 break;
711 case nir_op_ishl:
712 result = vir_SHL(c, src[0], src[1]);
713 break;
714 case nir_op_imin:
715 result = vir_MIN(c, src[0], src[1]);
716 break;
717 case nir_op_umin:
718 result = vir_UMIN(c, src[0], src[1]);
719 break;
720 case nir_op_imax:
721 result = vir_MAX(c, src[0], src[1]);
722 break;
723 case nir_op_umax:
724 result = vir_UMAX(c, src[0], src[1]);
725 break;
726 case nir_op_iand:
727 result = vir_AND(c, src[0], src[1]);
728 break;
729 case nir_op_ior:
730 result = vir_OR(c, src[0], src[1]);
731 break;
732 case nir_op_ixor:
733 result = vir_XOR(c, src[0], src[1]);
734 break;
735 case nir_op_inot:
736 result = vir_NOT(c, src[0]);
737 break;
738
739 case nir_op_ufind_msb:
740 result = vir_SUB(c, vir_uniform_ui(c, 31), vir_CLZ(c, src[0]));
741 break;
742
743 case nir_op_imul:
744 result = vir_UMUL(c, src[0], src[1]);
745 break;
746
747 case nir_op_seq:
748 case nir_op_sne:
749 case nir_op_sge:
750 case nir_op_slt:
751 case nir_op_feq:
752 case nir_op_fne:
753 case nir_op_fge:
754 case nir_op_flt:
755 case nir_op_ieq:
756 case nir_op_ine:
757 case nir_op_ige:
758 case nir_op_uge:
759 case nir_op_ilt:
760 case nir_op_ult:
761 if (!ntq_emit_comparison(c, &result, instr, instr)) {
762 fprintf(stderr, "Bad comparison instruction\n");
763 }
764 break;
765
766 case nir_op_bcsel:
767 result = ntq_emit_bcsel(c, instr, src);
768 break;
769 case nir_op_fcsel:
770 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
771 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
772 src[1], src[2]));
773 break;
774
775 case nir_op_frcp:
776 result = vir_RECIP(c, src[0]);
777 break;
778 case nir_op_frsq:
779 result = vir_RSQRT(c, src[0]);
780 break;
781 case nir_op_fexp2:
782 result = vir_EXP(c, src[0]);
783 break;
784 case nir_op_flog2:
785 result = vir_LOG(c, src[0]);
786 break;
787
788 case nir_op_fceil:
789 result = vir_FCEIL(c, src[0]);
790 break;
791 case nir_op_ffloor:
792 result = vir_FFLOOR(c, src[0]);
793 break;
794 case nir_op_fround_even:
795 result = vir_FROUND(c, src[0]);
796 break;
797 case nir_op_ftrunc:
798 result = vir_FTRUNC(c, src[0]);
799 break;
800 case nir_op_ffract:
801 result = vir_FSUB(c, src[0], vir_FFLOOR(c, src[0]));
802 break;
803
804 case nir_op_fsin:
805 result = ntq_fsincos(c, src[0], false);
806 break;
807 case nir_op_fcos:
808 result = ntq_fsincos(c, src[0], true);
809 break;
810
811 case nir_op_fsign:
812 result = ntq_fsign(c, src[0]);
813 break;
814 case nir_op_isign:
815 result = ntq_isign(c, src[0]);
816 break;
817
818 case nir_op_fabs: {
819 result = vir_FMOV(c, src[0]);
820 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
821 break;
822 }
823
824 case nir_op_iabs:
825 result = vir_MAX(c, src[0],
826 vir_SUB(c, vir_uniform_ui(c, 0), src[0]));
827 break;
828
829 case nir_op_fddx:
830 case nir_op_fddx_coarse:
831 case nir_op_fddx_fine:
832 result = vir_FDX(c, src[0]);
833 break;
834
835 case nir_op_fddy:
836 case nir_op_fddy_coarse:
837 case nir_op_fddy_fine:
838 result = vir_FDY(c, src[0]);
839 break;
840
841 case nir_op_uadd_carry:
842 vir_PF(c, vir_ADD(c, src[0], src[1]), V3D_QPU_PF_PUSHC);
843 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
844 vir_uniform_ui(c, ~0),
845 vir_uniform_ui(c, 0)));
846 break;
847
848 case nir_op_pack_half_2x16_split:
849 result = vir_VFPACK(c, src[0], src[1]);
850 break;
851
852 case nir_op_unpack_half_2x16_split_x:
853 /* XXX perf: It would be good to be able to merge this unpack
854 * with whatever uses our result.
855 */
856 result = vir_FMOV(c, src[0]);
857 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_L);
858 break;
859
860 case nir_op_unpack_half_2x16_split_y:
861 result = vir_FMOV(c, src[0]);
862 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_H);
863 break;
864
865 default:
866 fprintf(stderr, "unknown NIR ALU inst: ");
867 nir_print_instr(&instr->instr, stderr);
868 fprintf(stderr, "\n");
869 abort();
870 }
871
872 /* We have a scalar result, so the instruction should only have a
873 * single channel written to.
874 */
875 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
876 ntq_store_dest(c, &instr->dest.dest,
877 ffs(instr->dest.write_mask) - 1, result);
878 }
879
880 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
881 * specifier. They come from a register that's preloaded with 0xffffffff
882 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
883 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
884 */
885 #define TLB_TYPE_F16_COLOR (3 << 6)
886 #define TLB_TYPE_I32_COLOR (1 << 6)
887 #define TLB_TYPE_F32_COLOR (0 << 6)
888 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
889 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
890 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
891 #define TLB_F16_SWAP_HI_LO (1 << 1)
892 #define TLB_VEC_SIZE_4_F16 (1 << 0)
893 #define TLB_VEC_SIZE_2_F16 (0 << 0)
894 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
895
896 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
897 * flag is set.
898 */
899 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
900 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
901 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
902 #define TLB_V42_DEPTH_TYPE_INVARIANT (0 << 3) /* Unmodified sideband input used */
903 #define TLB_V42_DEPTH_TYPE_PER_PIXEL (1 << 3) /* QPU result used */
904
905 /* Stencil is a single 32-bit write. */
906 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
907
908 static void
909 emit_frag_end(struct v3d_compile *c)
910 {
911 /* XXX
912 if (c->output_sample_mask_index != -1) {
913 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
914 }
915 */
916
917 bool has_any_tlb_color_write = false;
918 for (int rt = 0; rt < c->fs_key->nr_cbufs; rt++) {
919 if (c->output_color_var[rt])
920 has_any_tlb_color_write = true;
921 }
922
923 if (c->fs_key->sample_alpha_to_coverage && c->output_color_var[0]) {
924 struct nir_variable *var = c->output_color_var[0];
925 struct qreg *color = &c->outputs[var->data.driver_location * 4];
926
927 vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
928 vir_AND(c,
929 vir_MSF(c),
930 vir_FTOC(c, color[3])));
931 }
932
933 if (c->output_position_index != -1) {
934 struct qinst *inst = vir_MOV_dest(c,
935 vir_reg(QFILE_TLBU, 0),
936 c->outputs[c->output_position_index]);
937 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
938
939 if (c->devinfo->ver >= 42) {
940 tlb_specifier |= (TLB_V42_DEPTH_TYPE_PER_PIXEL |
941 TLB_SAMPLE_MODE_PER_PIXEL);
942 } else
943 tlb_specifier |= TLB_DEPTH_TYPE_PER_PIXEL;
944
945 inst->src[vir_get_implicit_uniform_src(inst)] =
946 vir_uniform_ui(c, tlb_specifier | 0xffffff00);
947 } else if (c->s->info.fs.uses_discard ||
948 c->fs_key->sample_alpha_to_coverage ||
949 !has_any_tlb_color_write) {
950 /* Emit passthrough Z if it needed to be delayed until shader
951 * end due to potential discards.
952 *
953 * Since (single-threaded) fragment shaders always need a TLB
954 * write, emit passthrouh Z if we didn't have any color
955 * buffers and flag us as potentially discarding, so that we
956 * can use Z as the TLB write.
957 */
958 c->s->info.fs.uses_discard = true;
959
960 struct qinst *inst = vir_MOV_dest(c,
961 vir_reg(QFILE_TLBU, 0),
962 vir_reg(QFILE_NULL, 0));
963 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
964
965 if (c->devinfo->ver >= 42) {
966 /* The spec says the PER_PIXEL flag is ignored for
967 * invariant writes, but the simulator demands it.
968 */
969 tlb_specifier |= (TLB_V42_DEPTH_TYPE_INVARIANT |
970 TLB_SAMPLE_MODE_PER_PIXEL);
971 } else {
972 tlb_specifier |= TLB_DEPTH_TYPE_INVARIANT;
973 }
974
975 inst->src[vir_get_implicit_uniform_src(inst)] =
976 vir_uniform_ui(c, tlb_specifier | 0xffffff00);
977 }
978
979 /* XXX: Performance improvement: Merge Z write and color writes TLB
980 * uniform setup
981 */
982
983 for (int rt = 0; rt < c->fs_key->nr_cbufs; rt++) {
984 if (!c->output_color_var[rt])
985 continue;
986
987 nir_variable *var = c->output_color_var[rt];
988 struct qreg *color = &c->outputs[var->data.driver_location * 4];
989 int num_components = glsl_get_vector_elements(var->type);
990 uint32_t conf = 0xffffff00;
991 struct qinst *inst;
992
993 conf |= TLB_SAMPLE_MODE_PER_PIXEL;
994 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
995
996 if (c->fs_key->swap_color_rb & (1 << rt))
997 num_components = MAX2(num_components, 3);
998
999 assert(num_components != 0);
1000 switch (glsl_get_base_type(var->type)) {
1001 case GLSL_TYPE_UINT:
1002 case GLSL_TYPE_INT:
1003 /* The F32 vs I32 distinction was dropped in 4.2. */
1004 if (c->devinfo->ver < 42)
1005 conf |= TLB_TYPE_I32_COLOR;
1006 else
1007 conf |= TLB_TYPE_F32_COLOR;
1008 conf |= ((num_components - 1) <<
1009 TLB_VEC_SIZE_MINUS_1_SHIFT);
1010
1011 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
1012 inst->src[vir_get_implicit_uniform_src(inst)] =
1013 vir_uniform_ui(c, conf);
1014
1015 for (int i = 1; i < num_components; i++) {
1016 inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
1017 color[i]);
1018 }
1019 break;
1020
1021 default: {
1022 struct qreg r = color[0];
1023 struct qreg g = color[1];
1024 struct qreg b = color[2];
1025 struct qreg a = color[3];
1026
1027 if (c->fs_key->f32_color_rb & (1 << rt)) {
1028 conf |= TLB_TYPE_F32_COLOR;
1029 conf |= ((num_components - 1) <<
1030 TLB_VEC_SIZE_MINUS_1_SHIFT);
1031 } else {
1032 conf |= TLB_TYPE_F16_COLOR;
1033 conf |= TLB_F16_SWAP_HI_LO;
1034 if (num_components >= 3)
1035 conf |= TLB_VEC_SIZE_4_F16;
1036 else
1037 conf |= TLB_VEC_SIZE_2_F16;
1038 }
1039
1040 if (c->fs_key->swap_color_rb & (1 << rt)) {
1041 r = color[2];
1042 b = color[0];
1043 }
1044
1045 if (c->fs_key->sample_alpha_to_one)
1046 a = vir_uniform_f(c, 1.0);
1047
1048 if (c->fs_key->f32_color_rb & (1 << rt)) {
1049 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), r);
1050 inst->src[vir_get_implicit_uniform_src(inst)] =
1051 vir_uniform_ui(c, conf);
1052
1053 if (num_components >= 2)
1054 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), g);
1055 if (num_components >= 3)
1056 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), b);
1057 if (num_components >= 4)
1058 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), a);
1059 } else {
1060 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), r, g);
1061 if (conf != ~0) {
1062 inst->dst.file = QFILE_TLBU;
1063 inst->src[vir_get_implicit_uniform_src(inst)] =
1064 vir_uniform_ui(c, conf);
1065 }
1066
1067 if (num_components >= 3)
1068 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), b, a);
1069 }
1070 break;
1071 }
1072 }
1073 }
1074 }
1075
1076 static void
1077 vir_VPM_WRITE(struct v3d_compile *c, struct qreg val, uint32_t *vpm_index)
1078 {
1079 if (c->devinfo->ver >= 40) {
1080 vir_STVPMV(c, vir_uniform_ui(c, *vpm_index), val);
1081 *vpm_index = *vpm_index + 1;
1082 } else {
1083 vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM), val);
1084 }
1085
1086 c->num_vpm_writes++;
1087 }
1088
1089 static void
1090 emit_scaled_viewport_write(struct v3d_compile *c, struct qreg rcp_w,
1091 uint32_t *vpm_index)
1092 {
1093 for (int i = 0; i < 2; i++) {
1094 struct qreg coord = c->outputs[c->output_position_index + i];
1095 coord = vir_FMUL(c, coord,
1096 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i,
1097 0));
1098 coord = vir_FMUL(c, coord, rcp_w);
1099 vir_VPM_WRITE(c, vir_FTOIN(c, coord), vpm_index);
1100 }
1101
1102 }
1103
1104 static void
1105 emit_zs_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index)
1106 {
1107 struct qreg zscale = vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1108 struct qreg zoffset = vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1109
1110 struct qreg z = c->outputs[c->output_position_index + 2];
1111 z = vir_FMUL(c, z, zscale);
1112 z = vir_FMUL(c, z, rcp_w);
1113 z = vir_FADD(c, z, zoffset);
1114 vir_VPM_WRITE(c, z, vpm_index);
1115 }
1116
1117 static void
1118 emit_rcp_wc_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index)
1119 {
1120 vir_VPM_WRITE(c, rcp_w, vpm_index);
1121 }
1122
1123 static void
1124 emit_point_size_write(struct v3d_compile *c, uint32_t *vpm_index)
1125 {
1126 struct qreg point_size;
1127
1128 if (c->output_point_size_index != -1)
1129 point_size = c->outputs[c->output_point_size_index];
1130 else
1131 point_size = vir_uniform_f(c, 1.0);
1132
1133 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1134 * BCM21553).
1135 */
1136 point_size = vir_FMAX(c, point_size, vir_uniform_f(c, .125));
1137
1138 vir_VPM_WRITE(c, point_size, vpm_index);
1139 }
1140
1141 static void
1142 emit_vpm_write_setup(struct v3d_compile *c)
1143 {
1144 if (c->devinfo->ver >= 40)
1145 return;
1146
1147 v3d33_vir_vpm_write_setup(c);
1148 }
1149
1150 /**
1151 * Sets up c->outputs[c->output_position_index] for the vertex shader
1152 * epilogue, if an output vertex position wasn't specified in the user's
1153 * shader. This may be the case for transform feedback with rasterizer
1154 * discard enabled.
1155 */
1156 static void
1157 setup_default_position(struct v3d_compile *c)
1158 {
1159 if (c->output_position_index != -1)
1160 return;
1161
1162 c->output_position_index = c->outputs_array_size;
1163 for (int i = 0; i < 4; i++) {
1164 add_output(c,
1165 c->output_position_index + i,
1166 VARYING_SLOT_POS, i);
1167 }
1168 }
1169
1170 static void
1171 emit_vert_end(struct v3d_compile *c)
1172 {
1173 setup_default_position(c);
1174
1175 uint32_t vpm_index = 0;
1176 struct qreg rcp_w = vir_RECIP(c,
1177 c->outputs[c->output_position_index + 3]);
1178
1179 emit_vpm_write_setup(c);
1180
1181 if (c->vs_key->is_coord) {
1182 for (int i = 0; i < 4; i++)
1183 vir_VPM_WRITE(c, c->outputs[c->output_position_index + i],
1184 &vpm_index);
1185 emit_scaled_viewport_write(c, rcp_w, &vpm_index);
1186 if (c->vs_key->per_vertex_point_size) {
1187 emit_point_size_write(c, &vpm_index);
1188 /* emit_rcp_wc_write(c, rcp_w); */
1189 }
1190 /* XXX: Z-only rendering */
1191 if (0)
1192 emit_zs_write(c, rcp_w, &vpm_index);
1193 } else {
1194 emit_scaled_viewport_write(c, rcp_w, &vpm_index);
1195 emit_zs_write(c, rcp_w, &vpm_index);
1196 emit_rcp_wc_write(c, rcp_w, &vpm_index);
1197 if (c->vs_key->per_vertex_point_size)
1198 emit_point_size_write(c, &vpm_index);
1199 }
1200
1201 for (int i = 0; i < c->vs_key->num_fs_inputs; i++) {
1202 struct v3d_varying_slot input = c->vs_key->fs_inputs[i];
1203 int j;
1204
1205 for (j = 0; j < c->num_outputs; j++) {
1206 struct v3d_varying_slot output = c->output_slots[j];
1207
1208 if (!memcmp(&input, &output, sizeof(input))) {
1209 vir_VPM_WRITE(c, c->outputs[j],
1210 &vpm_index);
1211 break;
1212 }
1213 }
1214 /* Emit padding if we didn't find a declared VS output for
1215 * this FS input.
1216 */
1217 if (j == c->num_outputs)
1218 vir_VPM_WRITE(c, vir_uniform_f(c, 0.0),
1219 &vpm_index);
1220 }
1221
1222 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1223 */
1224 if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
1225 vir_VPMWT(c);
1226 }
1227
1228 void
1229 v3d_optimize_nir(struct nir_shader *s)
1230 {
1231 bool progress;
1232
1233 do {
1234 progress = false;
1235
1236 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1237 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1238 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1239 NIR_PASS(progress, s, nir_copy_prop);
1240 NIR_PASS(progress, s, nir_opt_remove_phis);
1241 NIR_PASS(progress, s, nir_opt_dce);
1242 NIR_PASS(progress, s, nir_opt_dead_cf);
1243 NIR_PASS(progress, s, nir_opt_cse);
1244 NIR_PASS(progress, s, nir_opt_peephole_select, 8);
1245 NIR_PASS(progress, s, nir_opt_algebraic);
1246 NIR_PASS(progress, s, nir_opt_constant_folding);
1247 NIR_PASS(progress, s, nir_opt_undef);
1248 } while (progress);
1249
1250 NIR_PASS(progress, s, nir_opt_move_load_ubo);
1251 }
1252
1253 static int
1254 driver_location_compare(const void *in_a, const void *in_b)
1255 {
1256 const nir_variable *const *a = in_a;
1257 const nir_variable *const *b = in_b;
1258
1259 return (*a)->data.driver_location - (*b)->data.driver_location;
1260 }
1261
1262 static struct qreg
1263 ntq_emit_vpm_read(struct v3d_compile *c,
1264 uint32_t *num_components_queued,
1265 uint32_t *remaining,
1266 uint32_t vpm_index)
1267 {
1268 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1269
1270 if (c->devinfo->ver >= 40 ) {
1271 return vir_LDVPMV_IN(c,
1272 vir_uniform_ui(c,
1273 (*num_components_queued)++));
1274 }
1275
1276 if (*num_components_queued != 0) {
1277 (*num_components_queued)--;
1278 c->num_inputs++;
1279 return vir_MOV(c, vpm);
1280 }
1281
1282 uint32_t num_components = MIN2(*remaining, 32);
1283
1284 v3d33_vir_vpm_read_setup(c, num_components);
1285
1286 *num_components_queued = num_components - 1;
1287 *remaining -= num_components;
1288 c->num_inputs++;
1289
1290 return vir_MOV(c, vpm);
1291 }
1292
1293 static void
1294 ntq_setup_vpm_inputs(struct v3d_compile *c)
1295 {
1296 /* Figure out how many components of each vertex attribute the shader
1297 * uses. Each variable should have been split to individual
1298 * components and unused ones DCEed. The vertex fetcher will load
1299 * from the start of the attribute to the number of components we
1300 * declare we need in c->vattr_sizes[].
1301 */
1302 nir_foreach_variable(var, &c->s->inputs) {
1303 /* No VS attribute array support. */
1304 assert(MAX2(glsl_get_length(var->type), 1) == 1);
1305
1306 unsigned loc = var->data.driver_location;
1307 int start_component = var->data.location_frac;
1308 int num_components = glsl_get_components(var->type);
1309
1310 c->vattr_sizes[loc] = MAX2(c->vattr_sizes[loc],
1311 start_component + num_components);
1312 }
1313
1314 unsigned num_components = 0;
1315 uint32_t vpm_components_queued = 0;
1316 bool uses_iid = c->s->info.system_values_read &
1317 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1318 bool uses_vid = c->s->info.system_values_read &
1319 (1ull << SYSTEM_VALUE_VERTEX_ID);
1320 num_components += uses_iid;
1321 num_components += uses_vid;
1322
1323 for (int i = 0; i < ARRAY_SIZE(c->vattr_sizes); i++)
1324 num_components += c->vattr_sizes[i];
1325
1326 if (uses_iid) {
1327 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1328 &num_components, ~0);
1329 }
1330
1331 if (uses_vid) {
1332 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1333 &num_components, ~0);
1334 }
1335
1336 for (int loc = 0; loc < ARRAY_SIZE(c->vattr_sizes); loc++) {
1337 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1338 (loc + 1) * 4);
1339
1340 for (int i = 0; i < c->vattr_sizes[loc]; i++) {
1341 c->inputs[loc * 4 + i] =
1342 ntq_emit_vpm_read(c,
1343 &vpm_components_queued,
1344 &num_components,
1345 loc * 4 + i);
1346
1347 }
1348 }
1349
1350 if (c->devinfo->ver >= 40) {
1351 assert(vpm_components_queued == num_components);
1352 } else {
1353 assert(vpm_components_queued == 0);
1354 assert(num_components == 0);
1355 }
1356 }
1357
1358 static void
1359 ntq_setup_fs_inputs(struct v3d_compile *c)
1360 {
1361 unsigned num_entries = 0;
1362 unsigned num_components = 0;
1363 nir_foreach_variable(var, &c->s->inputs) {
1364 num_entries++;
1365 num_components += glsl_get_components(var->type);
1366 }
1367
1368 nir_variable *vars[num_entries];
1369
1370 unsigned i = 0;
1371 nir_foreach_variable(var, &c->s->inputs)
1372 vars[i++] = var;
1373
1374 /* Sort the variables so that we emit the input setup in
1375 * driver_location order. This is required for VPM reads, whose data
1376 * is fetched into the VPM in driver_location (TGSI register index)
1377 * order.
1378 */
1379 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1380
1381 for (unsigned i = 0; i < num_entries; i++) {
1382 nir_variable *var = vars[i];
1383 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1384 unsigned loc = var->data.driver_location;
1385
1386 assert(array_len == 1);
1387 (void)array_len;
1388 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1389 (loc + 1) * 4);
1390
1391 if (var->data.location == VARYING_SLOT_POS) {
1392 emit_fragcoord_input(c, loc);
1393 } else if (var->data.location == VARYING_SLOT_PNTC ||
1394 (var->data.location >= VARYING_SLOT_VAR0 &&
1395 (c->fs_key->point_sprite_mask &
1396 (1 << (var->data.location -
1397 VARYING_SLOT_VAR0))))) {
1398 c->inputs[loc * 4 + 0] = c->point_x;
1399 c->inputs[loc * 4 + 1] = c->point_y;
1400 } else {
1401 emit_fragment_input(c, loc, var);
1402 }
1403 }
1404 }
1405
1406 static void
1407 ntq_setup_outputs(struct v3d_compile *c)
1408 {
1409 nir_foreach_variable(var, &c->s->outputs) {
1410 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1411 unsigned loc = var->data.driver_location * 4;
1412
1413 assert(array_len == 1);
1414 (void)array_len;
1415
1416 for (int i = 0; i < 4 - var->data.location_frac; i++) {
1417 add_output(c, loc + var->data.location_frac + i,
1418 var->data.location,
1419 var->data.location_frac + i);
1420 }
1421
1422 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1423 switch (var->data.location) {
1424 case FRAG_RESULT_COLOR:
1425 c->output_color_var[0] = var;
1426 c->output_color_var[1] = var;
1427 c->output_color_var[2] = var;
1428 c->output_color_var[3] = var;
1429 break;
1430 case FRAG_RESULT_DATA0:
1431 case FRAG_RESULT_DATA1:
1432 case FRAG_RESULT_DATA2:
1433 case FRAG_RESULT_DATA3:
1434 c->output_color_var[var->data.location -
1435 FRAG_RESULT_DATA0] = var;
1436 break;
1437 case FRAG_RESULT_DEPTH:
1438 c->output_position_index = loc;
1439 break;
1440 case FRAG_RESULT_SAMPLE_MASK:
1441 c->output_sample_mask_index = loc;
1442 break;
1443 }
1444 } else {
1445 switch (var->data.location) {
1446 case VARYING_SLOT_POS:
1447 c->output_position_index = loc;
1448 break;
1449 case VARYING_SLOT_PSIZ:
1450 c->output_point_size_index = loc;
1451 break;
1452 }
1453 }
1454 }
1455 }
1456
1457 static void
1458 ntq_setup_uniforms(struct v3d_compile *c)
1459 {
1460 nir_foreach_variable(var, &c->s->uniforms) {
1461 uint32_t vec4_count = glsl_count_attribute_slots(var->type,
1462 false);
1463 unsigned vec4_size = 4 * sizeof(float);
1464
1465 declare_uniform_range(c, var->data.driver_location * vec4_size,
1466 vec4_count * vec4_size);
1467
1468 }
1469 }
1470
1471 /**
1472 * Sets up the mapping from nir_register to struct qreg *.
1473 *
1474 * Each nir_register gets a struct qreg per 32-bit component being stored.
1475 */
1476 static void
1477 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1478 {
1479 foreach_list_typed(nir_register, nir_reg, node, list) {
1480 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1481 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1482 array_len *
1483 nir_reg->num_components);
1484
1485 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1486
1487 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1488 qregs[i] = vir_get_temp(c);
1489 }
1490 }
1491
1492 static void
1493 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1494 {
1495 /* XXX perf: Experiment with using immediate loads to avoid having
1496 * these end up in the uniform stream. Watch out for breaking the
1497 * small immediates optimization in the process!
1498 */
1499 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1500 for (int i = 0; i < instr->def.num_components; i++)
1501 qregs[i] = vir_uniform_ui(c, instr->value.u32[i]);
1502
1503 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1504 }
1505
1506 static void
1507 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1508 {
1509 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1510
1511 /* VIR needs there to be *some* value, so pick 0 (same as for
1512 * ntq_setup_registers().
1513 */
1514 for (int i = 0; i < instr->def.num_components; i++)
1515 qregs[i] = vir_uniform_ui(c, 0);
1516 }
1517
1518 static void
1519 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
1520 {
1521 unsigned offset;
1522
1523 switch (instr->intrinsic) {
1524 case nir_intrinsic_load_uniform:
1525 assert(instr->num_components == 1);
1526 if (nir_src_is_const(instr->src[0])) {
1527 offset = (nir_intrinsic_base(instr) +
1528 nir_src_as_uint(instr->src[0]));
1529 assert(offset % 4 == 0);
1530 /* We need dwords */
1531 offset = offset / 4;
1532 ntq_store_dest(c, &instr->dest, 0,
1533 vir_uniform(c, QUNIFORM_UNIFORM,
1534 offset));
1535 } else {
1536 ntq_store_dest(c, &instr->dest, 0,
1537 indirect_uniform_load(c, instr));
1538 }
1539 break;
1540
1541 case nir_intrinsic_load_ubo:
1542 for (int i = 0; i < instr->num_components; i++) {
1543 int ubo = nir_src_as_uint(instr->src[0]);
1544
1545 /* XXX perf: On V3D 4.x with uniform offsets, we
1546 * should probably try setting UBOs up in the A
1547 * register file and doing a sequence of loads that
1548 * way.
1549 */
1550 /* Adjust for where we stored the TGSI register base. */
1551 vir_ADD_dest(c,
1552 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA),
1553 vir_uniform(c, QUNIFORM_UBO_ADDR, 1 + ubo),
1554 vir_ADD(c,
1555 ntq_get_src(c, instr->src[1], 0),
1556 vir_uniform_ui(c, i * 4)));
1557
1558 vir_emit_thrsw(c);
1559
1560 ntq_store_dest(c, &instr->dest, i, vir_LDTMU(c));
1561 }
1562 break;
1563
1564 if (nir_src_is_const(instr->src[0])) {
1565 offset = (nir_intrinsic_base(instr) +
1566 nir_src_as_uint(instr->src[0]));
1567 assert(offset % 4 == 0);
1568 /* We need dwords */
1569 offset = offset / 4;
1570 ntq_store_dest(c, &instr->dest, 0,
1571 vir_uniform(c, QUNIFORM_UNIFORM,
1572 offset));
1573 } else {
1574 ntq_store_dest(c, &instr->dest, 0,
1575 indirect_uniform_load(c, instr));
1576 }
1577 break;
1578
1579 case nir_intrinsic_load_user_clip_plane:
1580 for (int i = 0; i < instr->num_components; i++) {
1581 ntq_store_dest(c, &instr->dest, i,
1582 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1583 nir_intrinsic_ucp_id(instr) *
1584 4 + i));
1585 }
1586 break;
1587
1588 case nir_intrinsic_load_alpha_ref_float:
1589 ntq_store_dest(c, &instr->dest, 0,
1590 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1591 break;
1592
1593 case nir_intrinsic_load_sample_mask_in:
1594 ntq_store_dest(c, &instr->dest, 0, vir_MSF(c));
1595 break;
1596
1597 case nir_intrinsic_load_front_face:
1598 /* The register contains 0 (front) or 1 (back), and we need to
1599 * turn it into a NIR bool where true means front.
1600 */
1601 ntq_store_dest(c, &instr->dest, 0,
1602 vir_ADD(c,
1603 vir_uniform_ui(c, -1),
1604 vir_REVF(c)));
1605 break;
1606
1607 case nir_intrinsic_load_instance_id:
1608 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
1609 break;
1610
1611 case nir_intrinsic_load_vertex_id:
1612 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
1613 break;
1614
1615 case nir_intrinsic_load_input:
1616 for (int i = 0; i < instr->num_components; i++) {
1617 offset = (nir_intrinsic_base(instr) +
1618 nir_src_as_uint(instr->src[0]));
1619 int comp = nir_intrinsic_component(instr) + i;
1620 ntq_store_dest(c, &instr->dest, i,
1621 vir_MOV(c, c->inputs[offset * 4 + comp]));
1622 }
1623 break;
1624
1625 case nir_intrinsic_store_output:
1626 offset = ((nir_intrinsic_base(instr) +
1627 nir_src_as_uint(instr->src[1])) * 4 +
1628 nir_intrinsic_component(instr));
1629
1630 for (int i = 0; i < instr->num_components; i++) {
1631 c->outputs[offset + i] =
1632 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
1633 }
1634 c->num_outputs = MAX2(c->num_outputs,
1635 offset + instr->num_components);
1636 break;
1637
1638 case nir_intrinsic_discard:
1639 if (c->execute.file != QFILE_NULL) {
1640 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1641 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1642 vir_uniform_ui(c, 0)),
1643 V3D_QPU_COND_IFA);
1644 } else {
1645 vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1646 vir_uniform_ui(c, 0));
1647 }
1648 break;
1649
1650 case nir_intrinsic_discard_if: {
1651 /* true (~0) if we're discarding */
1652 struct qreg cond = ntq_get_src(c, instr->src[0], 0);
1653
1654 if (c->execute.file != QFILE_NULL) {
1655 /* execute == 0 means the channel is active. Invert
1656 * the condition so that we can use zero as "executing
1657 * and discarding."
1658 */
1659 vir_PF(c, vir_OR(c, c->execute, vir_NOT(c, cond)),
1660 V3D_QPU_PF_PUSHZ);
1661 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1662 vir_uniform_ui(c, 0)),
1663 V3D_QPU_COND_IFA);
1664 } else {
1665 vir_PF(c, cond, V3D_QPU_PF_PUSHZ);
1666 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1667 vir_uniform_ui(c, 0)),
1668 V3D_QPU_COND_IFNA);
1669 }
1670
1671 break;
1672 }
1673
1674 default:
1675 fprintf(stderr, "Unknown intrinsic: ");
1676 nir_print_instr(&instr->instr, stderr);
1677 fprintf(stderr, "\n");
1678 break;
1679 }
1680 }
1681
1682 /* Clears (activates) the execute flags for any channels whose jump target
1683 * matches this block.
1684 *
1685 * XXX perf: Could we be using flpush/flpop somehow for our execution channel
1686 * enabling?
1687 *
1688 * XXX perf: For uniform control flow, we should be able to skip c->execute
1689 * handling entirely.
1690 */
1691 static void
1692 ntq_activate_execute_for_block(struct v3d_compile *c)
1693 {
1694 vir_PF(c, vir_XOR(c, c->execute, vir_uniform_ui(c, c->cur_block->index)),
1695 V3D_QPU_PF_PUSHZ);
1696
1697 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
1698 }
1699
1700 static void
1701 ntq_emit_if(struct v3d_compile *c, nir_if *if_stmt)
1702 {
1703 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
1704 bool empty_else_block =
1705 (nir_else_block == nir_if_last_else_block(if_stmt) &&
1706 exec_list_is_empty(&nir_else_block->instr_list));
1707
1708 struct qblock *then_block = vir_new_block(c);
1709 struct qblock *after_block = vir_new_block(c);
1710 struct qblock *else_block;
1711 if (empty_else_block)
1712 else_block = after_block;
1713 else
1714 else_block = vir_new_block(c);
1715
1716 bool was_top_level = false;
1717 if (c->execute.file == QFILE_NULL) {
1718 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
1719 was_top_level = true;
1720 }
1721
1722 /* Set A for executing (execute == 0) and jumping (if->condition ==
1723 * 0) channels, and then update execute flags for those to point to
1724 * the ELSE block.
1725 *
1726 * XXX perf: we could reuse ntq_emit_comparison() to generate our if
1727 * condition, and the .uf field to ignore non-executing channels, to
1728 * reduce the overhead of if statements.
1729 */
1730 vir_PF(c, vir_OR(c,
1731 c->execute,
1732 ntq_get_src(c, if_stmt->condition, 0)),
1733 V3D_QPU_PF_PUSHZ);
1734 vir_MOV_cond(c, V3D_QPU_COND_IFA,
1735 c->execute,
1736 vir_uniform_ui(c, else_block->index));
1737
1738 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1739 * through.
1740 */
1741 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1742 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
1743 vir_link_blocks(c->cur_block, else_block);
1744 vir_link_blocks(c->cur_block, then_block);
1745
1746 /* Process the THEN block. */
1747 vir_set_emit_block(c, then_block);
1748 ntq_emit_cf_list(c, &if_stmt->then_list);
1749
1750 if (!empty_else_block) {
1751 /* Handle the end of the THEN block. First, all currently
1752 * active channels update their execute flags to point to
1753 * ENDIF
1754 */
1755 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1756 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1757 vir_uniform_ui(c, after_block->index));
1758
1759 /* If everything points at ENDIF, then jump there immediately. */
1760 vir_PF(c, vir_XOR(c, c->execute,
1761 vir_uniform_ui(c, after_block->index)),
1762 V3D_QPU_PF_PUSHZ);
1763 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
1764 vir_link_blocks(c->cur_block, after_block);
1765 vir_link_blocks(c->cur_block, else_block);
1766
1767 vir_set_emit_block(c, else_block);
1768 ntq_activate_execute_for_block(c);
1769 ntq_emit_cf_list(c, &if_stmt->else_list);
1770 }
1771
1772 vir_link_blocks(c->cur_block, after_block);
1773
1774 vir_set_emit_block(c, after_block);
1775 if (was_top_level)
1776 c->execute = c->undef;
1777 else
1778 ntq_activate_execute_for_block(c);
1779 }
1780
1781 static void
1782 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
1783 {
1784 switch (jump->type) {
1785 case nir_jump_break:
1786 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1787 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1788 vir_uniform_ui(c, c->loop_break_block->index));
1789 break;
1790
1791 case nir_jump_continue:
1792 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1793 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1794 vir_uniform_ui(c, c->loop_cont_block->index));
1795 break;
1796
1797 case nir_jump_return:
1798 unreachable("All returns shouold be lowered\n");
1799 }
1800 }
1801
1802 static void
1803 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
1804 {
1805 switch (instr->type) {
1806 case nir_instr_type_alu:
1807 ntq_emit_alu(c, nir_instr_as_alu(instr));
1808 break;
1809
1810 case nir_instr_type_intrinsic:
1811 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
1812 break;
1813
1814 case nir_instr_type_load_const:
1815 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
1816 break;
1817
1818 case nir_instr_type_ssa_undef:
1819 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
1820 break;
1821
1822 case nir_instr_type_tex:
1823 ntq_emit_tex(c, nir_instr_as_tex(instr));
1824 break;
1825
1826 case nir_instr_type_jump:
1827 ntq_emit_jump(c, nir_instr_as_jump(instr));
1828 break;
1829
1830 default:
1831 fprintf(stderr, "Unknown NIR instr type: ");
1832 nir_print_instr(instr, stderr);
1833 fprintf(stderr, "\n");
1834 abort();
1835 }
1836 }
1837
1838 static void
1839 ntq_emit_block(struct v3d_compile *c, nir_block *block)
1840 {
1841 nir_foreach_instr(instr, block) {
1842 ntq_emit_instr(c, instr);
1843 }
1844 }
1845
1846 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
1847
1848 static void
1849 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
1850 {
1851 bool was_top_level = false;
1852 if (c->execute.file == QFILE_NULL) {
1853 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
1854 was_top_level = true;
1855 }
1856
1857 struct qblock *save_loop_cont_block = c->loop_cont_block;
1858 struct qblock *save_loop_break_block = c->loop_break_block;
1859
1860 c->loop_cont_block = vir_new_block(c);
1861 c->loop_break_block = vir_new_block(c);
1862
1863 vir_link_blocks(c->cur_block, c->loop_cont_block);
1864 vir_set_emit_block(c, c->loop_cont_block);
1865 ntq_activate_execute_for_block(c);
1866
1867 ntq_emit_cf_list(c, &loop->body);
1868
1869 /* Re-enable any previous continues now, so our ANYA check below
1870 * works.
1871 *
1872 * XXX: Use the .ORZ flags update, instead.
1873 */
1874 vir_PF(c, vir_XOR(c,
1875 c->execute,
1876 vir_uniform_ui(c, c->loop_cont_block->index)),
1877 V3D_QPU_PF_PUSHZ);
1878 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
1879
1880 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1881
1882 struct qinst *branch = vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
1883 /* Pixels that were not dispatched or have been discarded should not
1884 * contribute to looping again.
1885 */
1886 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P;
1887 vir_link_blocks(c->cur_block, c->loop_cont_block);
1888 vir_link_blocks(c->cur_block, c->loop_break_block);
1889
1890 vir_set_emit_block(c, c->loop_break_block);
1891 if (was_top_level)
1892 c->execute = c->undef;
1893 else
1894 ntq_activate_execute_for_block(c);
1895
1896 c->loop_break_block = save_loop_break_block;
1897 c->loop_cont_block = save_loop_cont_block;
1898 }
1899
1900 static void
1901 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
1902 {
1903 fprintf(stderr, "FUNCTIONS not handled.\n");
1904 abort();
1905 }
1906
1907 static void
1908 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
1909 {
1910 foreach_list_typed(nir_cf_node, node, node, list) {
1911 switch (node->type) {
1912 case nir_cf_node_block:
1913 ntq_emit_block(c, nir_cf_node_as_block(node));
1914 break;
1915
1916 case nir_cf_node_if:
1917 ntq_emit_if(c, nir_cf_node_as_if(node));
1918 break;
1919
1920 case nir_cf_node_loop:
1921 ntq_emit_loop(c, nir_cf_node_as_loop(node));
1922 break;
1923
1924 case nir_cf_node_function:
1925 ntq_emit_function(c, nir_cf_node_as_function(node));
1926 break;
1927
1928 default:
1929 fprintf(stderr, "Unknown NIR node type\n");
1930 abort();
1931 }
1932 }
1933 }
1934
1935 static void
1936 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
1937 {
1938 ntq_setup_registers(c, &impl->registers);
1939 ntq_emit_cf_list(c, &impl->body);
1940 }
1941
1942 static void
1943 nir_to_vir(struct v3d_compile *c)
1944 {
1945 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1946 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
1947 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
1948 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
1949
1950 /* XXX perf: We could set the "disable implicit point/line
1951 * varyings" field in the shader record and not emit these, if
1952 * they're not going to be used.
1953 */
1954 if (c->fs_key->is_points) {
1955 c->point_x = emit_fragment_varying(c, NULL, 0);
1956 c->point_y = emit_fragment_varying(c, NULL, 0);
1957 } else if (c->fs_key->is_lines) {
1958 c->line_x = emit_fragment_varying(c, NULL, 0);
1959 }
1960 }
1961
1962 if (c->s->info.stage == MESA_SHADER_FRAGMENT)
1963 ntq_setup_fs_inputs(c);
1964 else
1965 ntq_setup_vpm_inputs(c);
1966
1967 ntq_setup_outputs(c);
1968 ntq_setup_uniforms(c);
1969 ntq_setup_registers(c, &c->s->registers);
1970
1971 /* Find the main function and emit the body. */
1972 nir_foreach_function(function, c->s) {
1973 assert(strcmp(function->name, "main") == 0);
1974 assert(function->impl);
1975 ntq_emit_impl(c, function->impl);
1976 }
1977 }
1978
1979 const nir_shader_compiler_options v3d_nir_options = {
1980 .lower_all_io_to_temps = true,
1981 .lower_extract_byte = true,
1982 .lower_extract_word = true,
1983 .lower_bfm = true,
1984 .lower_bitfield_insert_to_shifts = true,
1985 .lower_bitfield_extract_to_shifts = true,
1986 .lower_bitfield_reverse = true,
1987 .lower_bit_count = true,
1988 .lower_pack_unorm_2x16 = true,
1989 .lower_pack_snorm_2x16 = true,
1990 .lower_pack_unorm_4x8 = true,
1991 .lower_pack_snorm_4x8 = true,
1992 .lower_unpack_unorm_4x8 = true,
1993 .lower_unpack_snorm_4x8 = true,
1994 .lower_pack_half_2x16 = true,
1995 .lower_unpack_half_2x16 = true,
1996 .lower_fdiv = true,
1997 .lower_find_lsb = true,
1998 .lower_ffma = true,
1999 .lower_flrp32 = true,
2000 .lower_fpow = true,
2001 .lower_fsat = true,
2002 .lower_fsqrt = true,
2003 .lower_ifind_msb = true,
2004 .lower_ldexp = true,
2005 .lower_mul_high = true,
2006 .lower_wpos_pntc = true,
2007 .native_integers = true,
2008 };
2009
2010
2011 #if 0
2012 static int
2013 count_nir_instrs(nir_shader *nir)
2014 {
2015 int count = 0;
2016 nir_foreach_function(function, nir) {
2017 if (!function->impl)
2018 continue;
2019 nir_foreach_block(block, function->impl) {
2020 nir_foreach_instr(instr, block)
2021 count++;
2022 }
2023 }
2024 return count;
2025 }
2026 #endif
2027
2028 /**
2029 * When demoting a shader down to single-threaded, removes the THRSW
2030 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
2031 * program end).
2032 */
2033 static void
2034 vir_remove_thrsw(struct v3d_compile *c)
2035 {
2036 vir_for_each_block(block, c) {
2037 vir_for_each_inst_safe(inst, block) {
2038 if (inst->qpu.sig.thrsw)
2039 vir_remove_instruction(c, inst);
2040 }
2041 }
2042
2043 c->last_thrsw = NULL;
2044 }
2045
2046 void
2047 vir_emit_last_thrsw(struct v3d_compile *c)
2048 {
2049 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
2050 * switching, so disable threads if we didn't do any TMU ops (each of
2051 * which would have emitted a THRSW).
2052 */
2053 if (!c->last_thrsw_at_top_level && c->devinfo->ver < 41) {
2054 c->threads = 1;
2055 if (c->last_thrsw)
2056 vir_remove_thrsw(c);
2057 return;
2058 }
2059
2060 /* If we're threaded and the last THRSW was in conditional code, then
2061 * we need to emit another one so that we can flag it as the last
2062 * thrsw.
2063 */
2064 if (c->last_thrsw && !c->last_thrsw_at_top_level) {
2065 assert(c->devinfo->ver >= 41);
2066 vir_emit_thrsw(c);
2067 }
2068
2069 /* If we're threaded, then we need to mark the last THRSW instruction
2070 * so we can emit a pair of them at QPU emit time.
2071 *
2072 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2073 * post-last-THRSW state, so we can skip this.
2074 */
2075 if (!c->last_thrsw && c->s->info.stage == MESA_SHADER_FRAGMENT) {
2076 assert(c->devinfo->ver >= 41);
2077 vir_emit_thrsw(c);
2078 }
2079
2080 if (c->last_thrsw)
2081 c->last_thrsw->is_last_thrsw = true;
2082 }
2083
2084 /* There's a flag in the shader for "center W is needed for reasons other than
2085 * non-centroid varyings", so we just walk the program after VIR optimization
2086 * to see if it's used. It should be harmless to set even if we only use
2087 * center W for varyings.
2088 */
2089 static void
2090 vir_check_payload_w(struct v3d_compile *c)
2091 {
2092 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
2093 return;
2094
2095 vir_for_each_inst_inorder(inst, c) {
2096 for (int i = 0; i < vir_get_nsrc(inst); i++) {
2097 if (inst->src[i].file == QFILE_REG &&
2098 inst->src[i].index == 0) {
2099 c->uses_center_w = true;
2100 return;
2101 }
2102 }
2103 }
2104
2105 }
2106
2107 void
2108 v3d_nir_to_vir(struct v3d_compile *c)
2109 {
2110 if (V3D_DEBUG & (V3D_DEBUG_NIR |
2111 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2112 fprintf(stderr, "%s prog %d/%d NIR:\n",
2113 vir_get_stage_name(c),
2114 c->program_id, c->variant_id);
2115 nir_print_shader(c->s, stderr);
2116 }
2117
2118 nir_to_vir(c);
2119
2120 /* Emit the last THRSW before STVPM and TLB writes. */
2121 vir_emit_last_thrsw(c);
2122
2123 switch (c->s->info.stage) {
2124 case MESA_SHADER_FRAGMENT:
2125 emit_frag_end(c);
2126 break;
2127 case MESA_SHADER_VERTEX:
2128 emit_vert_end(c);
2129 break;
2130 default:
2131 unreachable("bad stage");
2132 }
2133
2134 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2135 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2136 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
2137 vir_get_stage_name(c),
2138 c->program_id, c->variant_id);
2139 vir_dump(c);
2140 fprintf(stderr, "\n");
2141 }
2142
2143 vir_optimize(c);
2144 vir_lower_uniforms(c);
2145
2146 vir_check_payload_w(c);
2147
2148 /* XXX perf: On VC4, we do a VIR-level instruction scheduling here.
2149 * We used that on that platform to pipeline TMU writes and reduce the
2150 * number of thread switches, as well as try (mostly successfully) to
2151 * reduce maximum register pressure to allow more threads. We should
2152 * do something of that sort for V3D -- either instruction scheduling
2153 * here, or delay the the THRSW and LDTMUs from our texture
2154 * instructions until the results are needed.
2155 */
2156
2157 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2158 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2159 fprintf(stderr, "%s prog %d/%d VIR:\n",
2160 vir_get_stage_name(c),
2161 c->program_id, c->variant_id);
2162 vir_dump(c);
2163 fprintf(stderr, "\n");
2164 }
2165
2166 /* Attempt to allocate registers for the temporaries. If we fail,
2167 * reduce thread count and try again.
2168 */
2169 int min_threads = (c->devinfo->ver >= 41) ? 2 : 1;
2170 struct qpu_reg *temp_registers;
2171 while (true) {
2172 bool spilled;
2173 temp_registers = v3d_register_allocate(c, &spilled);
2174 if (spilled)
2175 continue;
2176
2177 if (temp_registers)
2178 break;
2179
2180 if (c->threads == min_threads) {
2181 fprintf(stderr, "Failed to register allocate at %d threads:\n",
2182 c->threads);
2183 vir_dump(c);
2184 c->failed = true;
2185 return;
2186 }
2187
2188 c->threads /= 2;
2189
2190 if (c->threads == 1)
2191 vir_remove_thrsw(c);
2192 }
2193
2194 v3d_vir_to_qpu(c, temp_registers);
2195 }