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v3d: Kill off vir_PF(), which is hard to use right.
[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
34
35 #define GENERAL_TMU_LOOKUP_PER_QUAD (0 << 7)
36 #define GENERAL_TMU_LOOKUP_PER_PIXEL (1 << 7)
37 #define GENERAL_TMU_READ_OP_PREFETCH (0 << 3)
38 #define GENERAL_TMU_READ_OP_CACHE_CLEAR (1 << 3)
39 #define GENERAL_TMU_READ_OP_CACHE_FLUSH (3 << 3)
40 #define GENERAL_TMU_READ_OP_CACHE_CLEAN (3 << 3)
41 #define GENERAL_TMU_READ_OP_CACHE_L1T_CLEAR (4 << 3)
42 #define GENERAL_TMU_READ_OP_CACHE_L1T_FLUSH_AGGREGATION (5 << 3)
43 #define GENERAL_TMU_READ_OP_ATOMIC_INC (8 << 3)
44 #define GENERAL_TMU_READ_OP_ATOMIC_DEC (9 << 3)
45 #define GENERAL_TMU_READ_OP_ATOMIC_NOT (10 << 3)
46 #define GENERAL_TMU_READ_OP_READ (15 << 3)
47 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_I (0 << 0)
48 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_I (1 << 0)
49 #define GENERAL_TMU_LOOKUP_TYPE_VEC2 (2 << 0)
50 #define GENERAL_TMU_LOOKUP_TYPE_VEC3 (3 << 0)
51 #define GENERAL_TMU_LOOKUP_TYPE_VEC4 (4 << 0)
52 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_UI (5 << 0)
53 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_UI (6 << 0)
54 #define GENERAL_TMU_LOOKUP_TYPE_32BIT_UI (7 << 0)
55
56 #define GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP (0 << 3)
57 #define GENERAL_TMU_WRITE_OP_ATOMIC_SUB_WRAP (1 << 3)
58 #define GENERAL_TMU_WRITE_OP_ATOMIC_XCHG (2 << 3)
59 #define GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG (3 << 3)
60 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMIN (4 << 3)
61 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMAX (5 << 3)
62 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMIN (6 << 3)
63 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMAX (7 << 3)
64 #define GENERAL_TMU_WRITE_OP_ATOMIC_AND (8 << 3)
65 #define GENERAL_TMU_WRITE_OP_ATOMIC_OR (9 << 3)
66 #define GENERAL_TMU_WRITE_OP_ATOMIC_XOR (10 << 3)
67 #define GENERAL_TMU_WRITE_OP_WRITE (15 << 3)
68
69 #define V3D_TSY_SET_QUORUM 0
70 #define V3D_TSY_INC_WAITERS 1
71 #define V3D_TSY_DEC_WAITERS 2
72 #define V3D_TSY_INC_QUORUM 3
73 #define V3D_TSY_DEC_QUORUM 4
74 #define V3D_TSY_FREE_ALL 5
75 #define V3D_TSY_RELEASE 6
76 #define V3D_TSY_ACQUIRE 7
77 #define V3D_TSY_WAIT 8
78 #define V3D_TSY_WAIT_INC 9
79 #define V3D_TSY_WAIT_CHECK 10
80 #define V3D_TSY_WAIT_INC_CHECK 11
81 #define V3D_TSY_WAIT_CV 12
82 #define V3D_TSY_INC_SEMAPHORE 13
83 #define V3D_TSY_DEC_SEMAPHORE 14
84 #define V3D_TSY_SET_QUORUM_FREE_ALL 15
85
86 static void
87 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
88
89 static void
90 resize_qreg_array(struct v3d_compile *c,
91 struct qreg **regs,
92 uint32_t *size,
93 uint32_t decl_size)
94 {
95 if (*size >= decl_size)
96 return;
97
98 uint32_t old_size = *size;
99 *size = MAX2(*size * 2, decl_size);
100 *regs = reralloc(c, *regs, struct qreg, *size);
101 if (!*regs) {
102 fprintf(stderr, "Malloc failure\n");
103 abort();
104 }
105
106 for (uint32_t i = old_size; i < *size; i++)
107 (*regs)[i] = c->undef;
108 }
109
110 void
111 vir_emit_thrsw(struct v3d_compile *c)
112 {
113 if (c->threads == 1)
114 return;
115
116 /* Always thread switch after each texture operation for now.
117 *
118 * We could do better by batching a bunch of texture fetches up and
119 * then doing one thread switch and collecting all their results
120 * afterward.
121 */
122 c->last_thrsw = vir_NOP(c);
123 c->last_thrsw->qpu.sig.thrsw = true;
124 c->last_thrsw_at_top_level = (c->execute.file == QFILE_NULL);
125 }
126
127 static uint32_t
128 v3d_general_tmu_op(nir_intrinsic_instr *instr)
129 {
130 switch (instr->intrinsic) {
131 case nir_intrinsic_load_ssbo:
132 case nir_intrinsic_load_ubo:
133 case nir_intrinsic_load_uniform:
134 case nir_intrinsic_load_shared:
135 return GENERAL_TMU_READ_OP_READ;
136 case nir_intrinsic_store_ssbo:
137 case nir_intrinsic_store_shared:
138 return GENERAL_TMU_WRITE_OP_WRITE;
139 case nir_intrinsic_ssbo_atomic_add:
140 case nir_intrinsic_shared_atomic_add:
141 return GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP;
142 case nir_intrinsic_ssbo_atomic_imin:
143 case nir_intrinsic_shared_atomic_imin:
144 return GENERAL_TMU_WRITE_OP_ATOMIC_SMIN;
145 case nir_intrinsic_ssbo_atomic_umin:
146 case nir_intrinsic_shared_atomic_umin:
147 return GENERAL_TMU_WRITE_OP_ATOMIC_UMIN;
148 case nir_intrinsic_ssbo_atomic_imax:
149 case nir_intrinsic_shared_atomic_imax:
150 return GENERAL_TMU_WRITE_OP_ATOMIC_SMAX;
151 case nir_intrinsic_ssbo_atomic_umax:
152 case nir_intrinsic_shared_atomic_umax:
153 return GENERAL_TMU_WRITE_OP_ATOMIC_UMAX;
154 case nir_intrinsic_ssbo_atomic_and:
155 case nir_intrinsic_shared_atomic_and:
156 return GENERAL_TMU_WRITE_OP_ATOMIC_AND;
157 case nir_intrinsic_ssbo_atomic_or:
158 case nir_intrinsic_shared_atomic_or:
159 return GENERAL_TMU_WRITE_OP_ATOMIC_OR;
160 case nir_intrinsic_ssbo_atomic_xor:
161 case nir_intrinsic_shared_atomic_xor:
162 return GENERAL_TMU_WRITE_OP_ATOMIC_XOR;
163 case nir_intrinsic_ssbo_atomic_exchange:
164 case nir_intrinsic_shared_atomic_exchange:
165 return GENERAL_TMU_WRITE_OP_ATOMIC_XCHG;
166 case nir_intrinsic_ssbo_atomic_comp_swap:
167 case nir_intrinsic_shared_atomic_comp_swap:
168 return GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG;
169 default:
170 unreachable("unknown intrinsic op");
171 }
172 }
173
174 /**
175 * Implements indirect uniform loads and SSBO accesses through the TMU general
176 * memory access interface.
177 */
178 static void
179 ntq_emit_tmu_general(struct v3d_compile *c, nir_intrinsic_instr *instr,
180 bool is_shared)
181 {
182 /* XXX perf: We should turn add/sub of 1 to inc/dec. Perhaps NIR
183 * wants to have support for inc/dec?
184 */
185
186 uint32_t tmu_op = v3d_general_tmu_op(instr);
187 bool is_store = (instr->intrinsic == nir_intrinsic_store_ssbo ||
188 instr->intrinsic == nir_intrinsic_store_shared);
189 bool has_index = !is_shared;
190
191 int offset_src;
192 int tmu_writes = 1; /* address */
193 if (instr->intrinsic == nir_intrinsic_load_uniform) {
194 offset_src = 0;
195 } else if (instr->intrinsic == nir_intrinsic_load_ssbo ||
196 instr->intrinsic == nir_intrinsic_load_ubo ||
197 instr->intrinsic == nir_intrinsic_load_shared) {
198 offset_src = 0 + has_index;
199 } else if (is_store) {
200 offset_src = 1 + has_index;
201 for (int i = 0; i < instr->num_components; i++) {
202 vir_MOV_dest(c,
203 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
204 ntq_get_src(c, instr->src[0], i));
205 tmu_writes++;
206 }
207 } else {
208 offset_src = 0 + has_index;
209 vir_MOV_dest(c,
210 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
211 ntq_get_src(c, instr->src[1 + has_index], 0));
212 tmu_writes++;
213 if (tmu_op == GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG) {
214 vir_MOV_dest(c,
215 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
216 ntq_get_src(c, instr->src[2 + has_index],
217 0));
218 tmu_writes++;
219 }
220 }
221
222 /* Make sure we won't exceed the 16-entry TMU fifo if each thread is
223 * storing at the same time.
224 */
225 while (tmu_writes > 16 / c->threads)
226 c->threads /= 2;
227
228 struct qreg offset;
229 if (instr->intrinsic == nir_intrinsic_load_uniform) {
230 offset = vir_uniform(c, QUNIFORM_UBO_ADDR, 0);
231
232 /* Find what variable in the default uniform block this
233 * uniform load is coming from.
234 */
235 uint32_t base = nir_intrinsic_base(instr);
236 int i;
237 struct v3d_ubo_range *range = NULL;
238 for (i = 0; i < c->num_ubo_ranges; i++) {
239 range = &c->ubo_ranges[i];
240 if (base >= range->src_offset &&
241 base < range->src_offset + range->size) {
242 break;
243 }
244 }
245 /* The driver-location-based offset always has to be within a
246 * declared uniform range.
247 */
248 assert(i != c->num_ubo_ranges);
249 if (!c->ubo_range_used[i]) {
250 c->ubo_range_used[i] = true;
251 range->dst_offset = c->next_ubo_dst_offset;
252 c->next_ubo_dst_offset += range->size;
253 }
254
255 base = base - range->src_offset + range->dst_offset;
256
257 if (base != 0)
258 offset = vir_ADD(c, offset, vir_uniform_ui(c, base));
259 } else if (instr->intrinsic == nir_intrinsic_load_ubo) {
260 /* Note that QUNIFORM_UBO_ADDR takes a UBO index shifted up by
261 * 1 (0 is gallium's constant buffer 0).
262 */
263 offset = vir_uniform(c, QUNIFORM_UBO_ADDR,
264 nir_src_as_uint(instr->src[0]) + 1);
265 } else if (is_shared) {
266 /* Shared variables have no buffer index, and all start from a
267 * common base that we set up at the start of dispatch
268 */
269 offset = c->cs_shared_offset;
270 } else {
271 offset = vir_uniform(c, QUNIFORM_SSBO_OFFSET,
272 nir_src_as_uint(instr->src[is_store ?
273 1 : 0]));
274 }
275
276 uint32_t config = (0xffffff00 |
277 tmu_op |
278 GENERAL_TMU_LOOKUP_PER_PIXEL);
279 if (instr->num_components == 1) {
280 config |= GENERAL_TMU_LOOKUP_TYPE_32BIT_UI;
281 } else {
282 config |= (GENERAL_TMU_LOOKUP_TYPE_VEC2 +
283 instr->num_components - 2);
284 }
285
286 if (c->execute.file != QFILE_NULL) {
287 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
288 V3D_QPU_PF_PUSHZ);
289 }
290
291 struct qreg dest;
292 if (config == ~0)
293 dest = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA);
294 else
295 dest = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUAU);
296
297 struct qinst *tmu;
298 if (nir_src_is_const(instr->src[offset_src]) &&
299 nir_src_as_uint(instr->src[offset_src]) == 0) {
300 tmu = vir_MOV_dest(c, dest, offset);
301 } else {
302 tmu = vir_ADD_dest(c, dest,
303 offset,
304 ntq_get_src(c, instr->src[offset_src], 0));
305 }
306
307 if (config != ~0) {
308 tmu->src[vir_get_implicit_uniform_src(tmu)] =
309 vir_uniform_ui(c, config);
310 }
311
312 if (c->execute.file != QFILE_NULL)
313 vir_set_cond(tmu, V3D_QPU_COND_IFA);
314
315 vir_emit_thrsw(c);
316
317 /* Read the result, or wait for the TMU op to complete. */
318 for (int i = 0; i < nir_intrinsic_dest_components(instr); i++)
319 ntq_store_dest(c, &instr->dest, i, vir_MOV(c, vir_LDTMU(c)));
320
321 if (nir_intrinsic_dest_components(instr) == 0)
322 vir_TMUWT(c);
323 }
324
325 static struct qreg *
326 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
327 {
328 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
329 def->num_components);
330 _mesa_hash_table_insert(c->def_ht, def, qregs);
331 return qregs;
332 }
333
334 /**
335 * This function is responsible for getting VIR results into the associated
336 * storage for a NIR instruction.
337 *
338 * If it's a NIR SSA def, then we just set the associated hash table entry to
339 * the new result.
340 *
341 * If it's a NIR reg, then we need to update the existing qreg assigned to the
342 * NIR destination with the incoming value. To do that without introducing
343 * new MOVs, we require that the incoming qreg either be a uniform, or be
344 * SSA-defined by the previous VIR instruction in the block and rewritable by
345 * this function. That lets us sneak ahead and insert the SF flag beforehand
346 * (knowing that the previous instruction doesn't depend on flags) and rewrite
347 * its destination to be the NIR reg's destination
348 */
349 void
350 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
351 struct qreg result)
352 {
353 struct qinst *last_inst = NULL;
354 if (!list_empty(&c->cur_block->instructions))
355 last_inst = (struct qinst *)c->cur_block->instructions.prev;
356
357 assert(result.file == QFILE_UNIF ||
358 (result.file == QFILE_TEMP &&
359 last_inst && last_inst == c->defs[result.index]));
360
361 if (dest->is_ssa) {
362 assert(chan < dest->ssa.num_components);
363
364 struct qreg *qregs;
365 struct hash_entry *entry =
366 _mesa_hash_table_search(c->def_ht, &dest->ssa);
367
368 if (entry)
369 qregs = entry->data;
370 else
371 qregs = ntq_init_ssa_def(c, &dest->ssa);
372
373 qregs[chan] = result;
374 } else {
375 nir_register *reg = dest->reg.reg;
376 assert(dest->reg.base_offset == 0);
377 assert(reg->num_array_elems == 0);
378 struct hash_entry *entry =
379 _mesa_hash_table_search(c->def_ht, reg);
380 struct qreg *qregs = entry->data;
381
382 /* Insert a MOV if the source wasn't an SSA def in the
383 * previous instruction.
384 */
385 if (result.file == QFILE_UNIF) {
386 result = vir_MOV(c, result);
387 last_inst = c->defs[result.index];
388 }
389
390 /* We know they're both temps, so just rewrite index. */
391 c->defs[last_inst->dst.index] = NULL;
392 last_inst->dst.index = qregs[chan].index;
393
394 /* If we're in control flow, then make this update of the reg
395 * conditional on the execution mask.
396 */
397 if (c->execute.file != QFILE_NULL) {
398 last_inst->dst.index = qregs[chan].index;
399
400 /* Set the flags to the current exec mask.
401 */
402 c->cursor = vir_before_inst(last_inst);
403 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
404 V3D_QPU_PF_PUSHZ);
405 c->cursor = vir_after_inst(last_inst);
406
407 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
408 last_inst->cond_is_exec_mask = true;
409 }
410 }
411 }
412
413 struct qreg
414 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
415 {
416 struct hash_entry *entry;
417 if (src.is_ssa) {
418 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
419 assert(i < src.ssa->num_components);
420 } else {
421 nir_register *reg = src.reg.reg;
422 entry = _mesa_hash_table_search(c->def_ht, reg);
423 assert(reg->num_array_elems == 0);
424 assert(src.reg.base_offset == 0);
425 assert(i < reg->num_components);
426 }
427
428 struct qreg *qregs = entry->data;
429 return qregs[i];
430 }
431
432 static struct qreg
433 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
434 unsigned src)
435 {
436 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
437 unsigned chan = ffs(instr->dest.write_mask) - 1;
438 struct qreg r = ntq_get_src(c, instr->src[src].src,
439 instr->src[src].swizzle[chan]);
440
441 assert(!instr->src[src].abs);
442 assert(!instr->src[src].negate);
443
444 return r;
445 };
446
447 static struct qreg
448 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
449 {
450 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
451 }
452
453 static void
454 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
455 {
456 unsigned unit = instr->texture_index;
457 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
458 int dest_size = nir_tex_instr_dest_size(instr);
459
460 struct qreg lod = c->undef;
461 if (lod_index != -1)
462 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
463
464 for (int i = 0; i < dest_size; i++) {
465 assert(i < 3);
466 enum quniform_contents contents;
467
468 if (instr->is_array && i == dest_size - 1)
469 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
470 else
471 contents = QUNIFORM_TEXTURE_WIDTH + i;
472
473 struct qreg size = vir_uniform(c, contents, unit);
474
475 switch (instr->sampler_dim) {
476 case GLSL_SAMPLER_DIM_1D:
477 case GLSL_SAMPLER_DIM_2D:
478 case GLSL_SAMPLER_DIM_MS:
479 case GLSL_SAMPLER_DIM_3D:
480 case GLSL_SAMPLER_DIM_CUBE:
481 /* Don't minify the array size. */
482 if (!(instr->is_array && i == dest_size - 1)) {
483 size = ntq_minify(c, size, lod);
484 }
485 break;
486
487 case GLSL_SAMPLER_DIM_RECT:
488 /* There's no LOD field for rects */
489 break;
490
491 default:
492 unreachable("Bad sampler type");
493 }
494
495 ntq_store_dest(c, &instr->dest, i, size);
496 }
497 }
498
499 static void
500 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
501 {
502 unsigned unit = instr->texture_index;
503
504 /* Since each texture sampling op requires uploading uniforms to
505 * reference the texture, there's no HW support for texture size and
506 * you just upload uniforms containing the size.
507 */
508 switch (instr->op) {
509 case nir_texop_query_levels:
510 ntq_store_dest(c, &instr->dest, 0,
511 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
512 return;
513 case nir_texop_txs:
514 ntq_emit_txs(c, instr);
515 return;
516 default:
517 break;
518 }
519
520 if (c->devinfo->ver >= 40)
521 v3d40_vir_emit_tex(c, instr);
522 else
523 v3d33_vir_emit_tex(c, instr);
524 }
525
526 static struct qreg
527 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
528 {
529 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
530 if (is_cos)
531 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
532
533 struct qreg periods = vir_FROUND(c, input);
534 struct qreg sin_output = vir_SIN(c, vir_FSUB(c, input, periods));
535 return vir_XOR(c, sin_output, vir_SHL(c,
536 vir_FTOIN(c, periods),
537 vir_uniform_ui(c, -1)));
538 }
539
540 static struct qreg
541 ntq_fsign(struct v3d_compile *c, struct qreg src)
542 {
543 struct qreg t = vir_get_temp(c);
544
545 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
546 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHZ);
547 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
548 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHN);
549 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
550 return vir_MOV(c, t);
551 }
552
553 static void
554 emit_fragcoord_input(struct v3d_compile *c, int attr)
555 {
556 c->inputs[attr * 4 + 0] = vir_FXCD(c);
557 c->inputs[attr * 4 + 1] = vir_FYCD(c);
558 c->inputs[attr * 4 + 2] = c->payload_z;
559 c->inputs[attr * 4 + 3] = vir_RECIP(c, c->payload_w);
560 }
561
562 static struct qreg
563 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
564 uint8_t swizzle, int array_index)
565 {
566 struct qreg r3 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R3);
567 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
568
569 struct qreg vary;
570 if (c->devinfo->ver >= 41) {
571 struct qinst *ldvary = vir_add_inst(V3D_QPU_A_NOP, c->undef,
572 c->undef, c->undef);
573 ldvary->qpu.sig.ldvary = true;
574 vary = vir_emit_def(c, ldvary);
575 } else {
576 vir_NOP(c)->qpu.sig.ldvary = true;
577 vary = r3;
578 }
579
580 /* For gl_PointCoord input or distance along a line, we'll be called
581 * with no nir_variable, and we don't count toward VPM size so we
582 * don't track an input slot.
583 */
584 if (!var) {
585 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
586 }
587
588 int i = c->num_inputs++;
589 c->input_slots[i] =
590 v3d_slot_from_slot_and_component(var->data.location +
591 array_index, swizzle);
592
593 switch (var->data.interpolation) {
594 case INTERP_MODE_NONE:
595 /* If a gl_FrontColor or gl_BackColor input has no interp
596 * qualifier, then if we're using glShadeModel(GL_FLAT) it
597 * needs to be flat shaded.
598 */
599 switch (var->data.location + array_index) {
600 case VARYING_SLOT_COL0:
601 case VARYING_SLOT_COL1:
602 case VARYING_SLOT_BFC0:
603 case VARYING_SLOT_BFC1:
604 if (c->fs_key->shade_model_flat) {
605 BITSET_SET(c->flat_shade_flags, i);
606 vir_MOV_dest(c, c->undef, vary);
607 return vir_MOV(c, r5);
608 } else {
609 return vir_FADD(c, vir_FMUL(c, vary,
610 c->payload_w), r5);
611 }
612 default:
613 break;
614 }
615 /* FALLTHROUGH */
616 case INTERP_MODE_SMOOTH:
617 if (var->data.centroid) {
618 BITSET_SET(c->centroid_flags, i);
619 return vir_FADD(c, vir_FMUL(c, vary,
620 c->payload_w_centroid), r5);
621 } else {
622 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
623 }
624 case INTERP_MODE_NOPERSPECTIVE:
625 BITSET_SET(c->noperspective_flags, i);
626 return vir_FADD(c, vir_MOV(c, vary), r5);
627 case INTERP_MODE_FLAT:
628 BITSET_SET(c->flat_shade_flags, i);
629 vir_MOV_dest(c, c->undef, vary);
630 return vir_MOV(c, r5);
631 default:
632 unreachable("Bad interp mode");
633 }
634 }
635
636 static void
637 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var,
638 int array_index)
639 {
640 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
641 int chan = var->data.location_frac + i;
642 c->inputs[attr * 4 + chan] =
643 emit_fragment_varying(c, var, chan, array_index);
644 }
645 }
646
647 static void
648 add_output(struct v3d_compile *c,
649 uint32_t decl_offset,
650 uint8_t slot,
651 uint8_t swizzle)
652 {
653 uint32_t old_array_size = c->outputs_array_size;
654 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
655 decl_offset + 1);
656
657 if (old_array_size != c->outputs_array_size) {
658 c->output_slots = reralloc(c,
659 c->output_slots,
660 struct v3d_varying_slot,
661 c->outputs_array_size);
662 }
663
664 c->output_slots[decl_offset] =
665 v3d_slot_from_slot_and_component(slot, swizzle);
666 }
667
668 static void
669 declare_uniform_range(struct v3d_compile *c, uint32_t start, uint32_t size)
670 {
671 unsigned array_id = c->num_ubo_ranges++;
672 if (array_id >= c->ubo_ranges_array_size) {
673 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
674 array_id + 1);
675 c->ubo_ranges = reralloc(c, c->ubo_ranges,
676 struct v3d_ubo_range,
677 c->ubo_ranges_array_size);
678 c->ubo_range_used = reralloc(c, c->ubo_range_used,
679 bool,
680 c->ubo_ranges_array_size);
681 }
682
683 c->ubo_ranges[array_id].dst_offset = 0;
684 c->ubo_ranges[array_id].src_offset = start;
685 c->ubo_ranges[array_id].size = size;
686 c->ubo_range_used[array_id] = false;
687 }
688
689 /**
690 * If compare_instr is a valid comparison instruction, emits the
691 * compare_instr's comparison and returns the sel_instr's return value based
692 * on the compare_instr's result.
693 */
694 static bool
695 ntq_emit_comparison(struct v3d_compile *c,
696 nir_alu_instr *compare_instr,
697 enum v3d_qpu_cond *out_cond)
698 {
699 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
700 struct qreg src1;
701 if (nir_op_infos[compare_instr->op].num_inputs > 1)
702 src1 = ntq_get_alu_src(c, compare_instr, 1);
703 bool cond_invert = false;
704 struct qreg nop = vir_nop_reg();
705
706 switch (compare_instr->op) {
707 case nir_op_feq32:
708 case nir_op_seq:
709 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
710 break;
711 case nir_op_ieq32:
712 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
713 break;
714
715 case nir_op_fne32:
716 case nir_op_sne:
717 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
718 cond_invert = true;
719 break;
720 case nir_op_ine32:
721 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
722 cond_invert = true;
723 break;
724
725 case nir_op_fge32:
726 case nir_op_sge:
727 vir_set_pf(vir_FCMP_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
728 break;
729 case nir_op_ige32:
730 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
731 cond_invert = true;
732 break;
733 case nir_op_uge32:
734 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
735 cond_invert = true;
736 break;
737
738 case nir_op_slt:
739 case nir_op_flt32:
740 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHN);
741 break;
742 case nir_op_ilt32:
743 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
744 break;
745 case nir_op_ult32:
746 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
747 break;
748
749 default:
750 return false;
751 }
752
753 *out_cond = cond_invert ? V3D_QPU_COND_IFNA : V3D_QPU_COND_IFA;
754
755 return true;
756 }
757
758 /* Finds an ALU instruction that generates our src value that could
759 * (potentially) be greedily emitted in the consuming instruction.
760 */
761 static struct nir_alu_instr *
762 ntq_get_alu_parent(nir_src src)
763 {
764 if (!src.is_ssa || src.ssa->parent_instr->type != nir_instr_type_alu)
765 return NULL;
766 nir_alu_instr *instr = nir_instr_as_alu(src.ssa->parent_instr);
767 if (!instr)
768 return NULL;
769
770 /* If the ALU instr's srcs are non-SSA, then we would have to avoid
771 * moving emission of the ALU instr down past another write of the
772 * src.
773 */
774 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
775 if (!instr->src[i].src.is_ssa)
776 return NULL;
777 }
778
779 return instr;
780 }
781
782 /* Turns a NIR bool into a condition code to predicate on. */
783 static enum v3d_qpu_cond
784 ntq_emit_bool_to_cond(struct v3d_compile *c, nir_src src)
785 {
786 nir_alu_instr *compare = ntq_get_alu_parent(src);
787 if (!compare)
788 goto out;
789
790 enum v3d_qpu_cond cond;
791 if (ntq_emit_comparison(c, compare, &cond))
792 return cond;
793
794 out:
795 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), ntq_get_src(c, src, 0)),
796 V3D_QPU_PF_PUSHZ);
797 return V3D_QPU_COND_IFNA;
798 }
799
800 static void
801 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
802 {
803 /* This should always be lowered to ALU operations for V3D. */
804 assert(!instr->dest.saturate);
805
806 /* Vectors are special in that they have non-scalarized writemasks,
807 * and just take the first swizzle channel for each argument in order
808 * into each writemask channel.
809 */
810 if (instr->op == nir_op_vec2 ||
811 instr->op == nir_op_vec3 ||
812 instr->op == nir_op_vec4) {
813 struct qreg srcs[4];
814 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
815 srcs[i] = ntq_get_src(c, instr->src[i].src,
816 instr->src[i].swizzle[0]);
817 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
818 ntq_store_dest(c, &instr->dest.dest, i,
819 vir_MOV(c, srcs[i]));
820 return;
821 }
822
823 /* General case: We can just grab the one used channel per src. */
824 struct qreg src[nir_op_infos[instr->op].num_inputs];
825 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
826 src[i] = ntq_get_alu_src(c, instr, i);
827 }
828
829 struct qreg result;
830
831 switch (instr->op) {
832 case nir_op_fmov:
833 case nir_op_imov:
834 result = vir_MOV(c, src[0]);
835 break;
836
837 case nir_op_fneg:
838 result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
839 break;
840 case nir_op_ineg:
841 result = vir_NEG(c, src[0]);
842 break;
843
844 case nir_op_fmul:
845 result = vir_FMUL(c, src[0], src[1]);
846 break;
847 case nir_op_fadd:
848 result = vir_FADD(c, src[0], src[1]);
849 break;
850 case nir_op_fsub:
851 result = vir_FSUB(c, src[0], src[1]);
852 break;
853 case nir_op_fmin:
854 result = vir_FMIN(c, src[0], src[1]);
855 break;
856 case nir_op_fmax:
857 result = vir_FMAX(c, src[0], src[1]);
858 break;
859
860 case nir_op_f2i32:
861 result = vir_FTOIZ(c, src[0]);
862 break;
863 case nir_op_f2u32:
864 result = vir_FTOUZ(c, src[0]);
865 break;
866 case nir_op_i2f32:
867 result = vir_ITOF(c, src[0]);
868 break;
869 case nir_op_u2f32:
870 result = vir_UTOF(c, src[0]);
871 break;
872 case nir_op_b2f32:
873 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
874 break;
875 case nir_op_b2i32:
876 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
877 break;
878 case nir_op_i2b32:
879 case nir_op_f2b32:
880 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), src[0]),
881 V3D_QPU_PF_PUSHZ);
882 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
883 vir_uniform_ui(c, ~0),
884 vir_uniform_ui(c, 0)));
885 break;
886
887 case nir_op_iadd:
888 result = vir_ADD(c, src[0], src[1]);
889 break;
890 case nir_op_ushr:
891 result = vir_SHR(c, src[0], src[1]);
892 break;
893 case nir_op_isub:
894 result = vir_SUB(c, src[0], src[1]);
895 break;
896 case nir_op_ishr:
897 result = vir_ASR(c, src[0], src[1]);
898 break;
899 case nir_op_ishl:
900 result = vir_SHL(c, src[0], src[1]);
901 break;
902 case nir_op_imin:
903 result = vir_MIN(c, src[0], src[1]);
904 break;
905 case nir_op_umin:
906 result = vir_UMIN(c, src[0], src[1]);
907 break;
908 case nir_op_imax:
909 result = vir_MAX(c, src[0], src[1]);
910 break;
911 case nir_op_umax:
912 result = vir_UMAX(c, src[0], src[1]);
913 break;
914 case nir_op_iand:
915 result = vir_AND(c, src[0], src[1]);
916 break;
917 case nir_op_ior:
918 result = vir_OR(c, src[0], src[1]);
919 break;
920 case nir_op_ixor:
921 result = vir_XOR(c, src[0], src[1]);
922 break;
923 case nir_op_inot:
924 result = vir_NOT(c, src[0]);
925 break;
926
927 case nir_op_ufind_msb:
928 result = vir_SUB(c, vir_uniform_ui(c, 31), vir_CLZ(c, src[0]));
929 break;
930
931 case nir_op_imul:
932 result = vir_UMUL(c, src[0], src[1]);
933 break;
934
935 case nir_op_seq:
936 case nir_op_sne:
937 case nir_op_sge:
938 case nir_op_slt: {
939 enum v3d_qpu_cond cond;
940 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
941 assert(ok);
942 result = vir_MOV(c, vir_SEL(c, cond,
943 vir_uniform_f(c, 1.0),
944 vir_uniform_f(c, 0.0)));
945 break;
946 }
947
948 case nir_op_feq32:
949 case nir_op_fne32:
950 case nir_op_fge32:
951 case nir_op_flt32:
952 case nir_op_ieq32:
953 case nir_op_ine32:
954 case nir_op_ige32:
955 case nir_op_uge32:
956 case nir_op_ilt32:
957 case nir_op_ult32: {
958 enum v3d_qpu_cond cond;
959 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
960 assert(ok);
961 result = vir_MOV(c, vir_SEL(c, cond,
962 vir_uniform_ui(c, ~0),
963 vir_uniform_ui(c, 0)));
964 break;
965 }
966
967 case nir_op_b32csel:
968 result = vir_MOV(c,
969 vir_SEL(c,
970 ntq_emit_bool_to_cond(c, instr->src[0].src),
971 src[1], src[2]));
972 break;
973
974 case nir_op_fcsel:
975 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), src[0]),
976 V3D_QPU_PF_PUSHZ);
977 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
978 src[1], src[2]));
979 break;
980
981 case nir_op_frcp:
982 result = vir_RECIP(c, src[0]);
983 break;
984 case nir_op_frsq:
985 result = vir_RSQRT(c, src[0]);
986 break;
987 case nir_op_fexp2:
988 result = vir_EXP(c, src[0]);
989 break;
990 case nir_op_flog2:
991 result = vir_LOG(c, src[0]);
992 break;
993
994 case nir_op_fceil:
995 result = vir_FCEIL(c, src[0]);
996 break;
997 case nir_op_ffloor:
998 result = vir_FFLOOR(c, src[0]);
999 break;
1000 case nir_op_fround_even:
1001 result = vir_FROUND(c, src[0]);
1002 break;
1003 case nir_op_ftrunc:
1004 result = vir_FTRUNC(c, src[0]);
1005 break;
1006
1007 case nir_op_fsin:
1008 result = ntq_fsincos(c, src[0], false);
1009 break;
1010 case nir_op_fcos:
1011 result = ntq_fsincos(c, src[0], true);
1012 break;
1013
1014 case nir_op_fsign:
1015 result = ntq_fsign(c, src[0]);
1016 break;
1017
1018 case nir_op_fabs: {
1019 result = vir_FMOV(c, src[0]);
1020 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
1021 break;
1022 }
1023
1024 case nir_op_iabs:
1025 result = vir_MAX(c, src[0],
1026 vir_SUB(c, vir_uniform_ui(c, 0), src[0]));
1027 break;
1028
1029 case nir_op_fddx:
1030 case nir_op_fddx_coarse:
1031 case nir_op_fddx_fine:
1032 result = vir_FDX(c, src[0]);
1033 break;
1034
1035 case nir_op_fddy:
1036 case nir_op_fddy_coarse:
1037 case nir_op_fddy_fine:
1038 result = vir_FDY(c, src[0]);
1039 break;
1040
1041 case nir_op_uadd_carry:
1042 vir_set_pf(vir_ADD_dest(c, vir_nop_reg(), src[0], src[1]),
1043 V3D_QPU_PF_PUSHC);
1044 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1045 vir_uniform_ui(c, ~0),
1046 vir_uniform_ui(c, 0)));
1047 break;
1048
1049 case nir_op_pack_half_2x16_split:
1050 result = vir_VFPACK(c, src[0], src[1]);
1051 break;
1052
1053 case nir_op_unpack_half_2x16_split_x:
1054 result = vir_FMOV(c, src[0]);
1055 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_L);
1056 break;
1057
1058 case nir_op_unpack_half_2x16_split_y:
1059 result = vir_FMOV(c, src[0]);
1060 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_H);
1061 break;
1062
1063 default:
1064 fprintf(stderr, "unknown NIR ALU inst: ");
1065 nir_print_instr(&instr->instr, stderr);
1066 fprintf(stderr, "\n");
1067 abort();
1068 }
1069
1070 /* We have a scalar result, so the instruction should only have a
1071 * single channel written to.
1072 */
1073 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
1074 ntq_store_dest(c, &instr->dest.dest,
1075 ffs(instr->dest.write_mask) - 1, result);
1076 }
1077
1078 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
1079 * specifier. They come from a register that's preloaded with 0xffffffff
1080 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
1081 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
1082 */
1083 #define TLB_TYPE_F16_COLOR (3 << 6)
1084 #define TLB_TYPE_I32_COLOR (1 << 6)
1085 #define TLB_TYPE_F32_COLOR (0 << 6)
1086 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
1087 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
1088 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
1089 #define TLB_F16_SWAP_HI_LO (1 << 1)
1090 #define TLB_VEC_SIZE_4_F16 (1 << 0)
1091 #define TLB_VEC_SIZE_2_F16 (0 << 0)
1092 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
1093
1094 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
1095 * flag is set.
1096 */
1097 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
1098 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
1099 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
1100 #define TLB_V42_DEPTH_TYPE_INVARIANT (0 << 3) /* Unmodified sideband input used */
1101 #define TLB_V42_DEPTH_TYPE_PER_PIXEL (1 << 3) /* QPU result used */
1102
1103 /* Stencil is a single 32-bit write. */
1104 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1105
1106 static void
1107 emit_frag_end(struct v3d_compile *c)
1108 {
1109 /* XXX
1110 if (c->output_sample_mask_index != -1) {
1111 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1112 }
1113 */
1114
1115 bool has_any_tlb_color_write = false;
1116 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1117 if (c->fs_key->cbufs & (1 << rt) && c->output_color_var[rt])
1118 has_any_tlb_color_write = true;
1119 }
1120
1121 if (c->fs_key->sample_alpha_to_coverage && c->output_color_var[0]) {
1122 struct nir_variable *var = c->output_color_var[0];
1123 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1124
1125 vir_SETMSF_dest(c, vir_nop_reg(),
1126 vir_AND(c,
1127 vir_MSF(c),
1128 vir_FTOC(c, color[3])));
1129 }
1130
1131 if (c->output_position_index != -1) {
1132 struct qinst *inst = vir_MOV_dest(c,
1133 vir_reg(QFILE_TLBU, 0),
1134 c->outputs[c->output_position_index]);
1135 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1136
1137 if (c->devinfo->ver >= 42) {
1138 tlb_specifier |= (TLB_V42_DEPTH_TYPE_PER_PIXEL |
1139 TLB_SAMPLE_MODE_PER_PIXEL);
1140 } else
1141 tlb_specifier |= TLB_DEPTH_TYPE_PER_PIXEL;
1142
1143 inst->src[vir_get_implicit_uniform_src(inst)] =
1144 vir_uniform_ui(c, tlb_specifier | 0xffffff00);
1145 c->writes_z = true;
1146 } else if (c->s->info.fs.uses_discard ||
1147 !c->s->info.fs.early_fragment_tests ||
1148 c->fs_key->sample_alpha_to_coverage ||
1149 !has_any_tlb_color_write) {
1150 /* Emit passthrough Z if it needed to be delayed until shader
1151 * end due to potential discards.
1152 *
1153 * Since (single-threaded) fragment shaders always need a TLB
1154 * write, emit passthrouh Z if we didn't have any color
1155 * buffers and flag us as potentially discarding, so that we
1156 * can use Z as the TLB write.
1157 */
1158 c->s->info.fs.uses_discard = true;
1159
1160 struct qinst *inst = vir_MOV_dest(c,
1161 vir_reg(QFILE_TLBU, 0),
1162 vir_nop_reg());
1163 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1164
1165 if (c->devinfo->ver >= 42) {
1166 /* The spec says the PER_PIXEL flag is ignored for
1167 * invariant writes, but the simulator demands it.
1168 */
1169 tlb_specifier |= (TLB_V42_DEPTH_TYPE_INVARIANT |
1170 TLB_SAMPLE_MODE_PER_PIXEL);
1171 } else {
1172 tlb_specifier |= TLB_DEPTH_TYPE_INVARIANT;
1173 }
1174
1175 inst->src[vir_get_implicit_uniform_src(inst)] =
1176 vir_uniform_ui(c, tlb_specifier | 0xffffff00);
1177 c->writes_z = true;
1178 }
1179
1180 /* XXX: Performance improvement: Merge Z write and color writes TLB
1181 * uniform setup
1182 */
1183
1184 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1185 if (!(c->fs_key->cbufs & (1 << rt)) || !c->output_color_var[rt])
1186 continue;
1187
1188 nir_variable *var = c->output_color_var[rt];
1189 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1190 int num_components = glsl_get_vector_elements(var->type);
1191 uint32_t conf = 0xffffff00;
1192 struct qinst *inst;
1193
1194 conf |= TLB_SAMPLE_MODE_PER_PIXEL;
1195 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1196
1197 if (c->fs_key->swap_color_rb & (1 << rt))
1198 num_components = MAX2(num_components, 3);
1199
1200 assert(num_components != 0);
1201 switch (glsl_get_base_type(var->type)) {
1202 case GLSL_TYPE_UINT:
1203 case GLSL_TYPE_INT:
1204 /* The F32 vs I32 distinction was dropped in 4.2. */
1205 if (c->devinfo->ver < 42)
1206 conf |= TLB_TYPE_I32_COLOR;
1207 else
1208 conf |= TLB_TYPE_F32_COLOR;
1209 conf |= ((num_components - 1) <<
1210 TLB_VEC_SIZE_MINUS_1_SHIFT);
1211
1212 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
1213 inst->src[vir_get_implicit_uniform_src(inst)] =
1214 vir_uniform_ui(c, conf);
1215
1216 for (int i = 1; i < num_components; i++) {
1217 inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
1218 color[i]);
1219 }
1220 break;
1221
1222 default: {
1223 struct qreg r = color[0];
1224 struct qreg g = color[1];
1225 struct qreg b = color[2];
1226 struct qreg a = color[3];
1227
1228 if (c->fs_key->f32_color_rb & (1 << rt)) {
1229 conf |= TLB_TYPE_F32_COLOR;
1230 conf |= ((num_components - 1) <<
1231 TLB_VEC_SIZE_MINUS_1_SHIFT);
1232 } else {
1233 conf |= TLB_TYPE_F16_COLOR;
1234 conf |= TLB_F16_SWAP_HI_LO;
1235 if (num_components >= 3)
1236 conf |= TLB_VEC_SIZE_4_F16;
1237 else
1238 conf |= TLB_VEC_SIZE_2_F16;
1239 }
1240
1241 if (c->fs_key->swap_color_rb & (1 << rt)) {
1242 r = color[2];
1243 b = color[0];
1244 }
1245
1246 if (c->fs_key->sample_alpha_to_one)
1247 a = vir_uniform_f(c, 1.0);
1248
1249 if (c->fs_key->f32_color_rb & (1 << rt)) {
1250 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), r);
1251 inst->src[vir_get_implicit_uniform_src(inst)] =
1252 vir_uniform_ui(c, conf);
1253
1254 if (num_components >= 2)
1255 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), g);
1256 if (num_components >= 3)
1257 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), b);
1258 if (num_components >= 4)
1259 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), a);
1260 } else {
1261 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), r, g);
1262 if (conf != ~0) {
1263 inst->dst.file = QFILE_TLBU;
1264 inst->src[vir_get_implicit_uniform_src(inst)] =
1265 vir_uniform_ui(c, conf);
1266 }
1267
1268 if (num_components >= 3)
1269 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), b, a);
1270 }
1271 break;
1272 }
1273 }
1274 }
1275 }
1276
1277 static void
1278 vir_VPM_WRITE(struct v3d_compile *c, struct qreg val, uint32_t *vpm_index)
1279 {
1280 if (c->devinfo->ver >= 40) {
1281 vir_STVPMV(c, vir_uniform_ui(c, *vpm_index), val);
1282 *vpm_index = *vpm_index + 1;
1283 } else {
1284 vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM), val);
1285 }
1286
1287 c->num_vpm_writes++;
1288 }
1289
1290 static void
1291 emit_scaled_viewport_write(struct v3d_compile *c, struct qreg rcp_w,
1292 uint32_t *vpm_index)
1293 {
1294 for (int i = 0; i < 2; i++) {
1295 struct qreg coord = c->outputs[c->output_position_index + i];
1296 coord = vir_FMUL(c, coord,
1297 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i,
1298 0));
1299 coord = vir_FMUL(c, coord, rcp_w);
1300 vir_VPM_WRITE(c, vir_FTOIN(c, coord), vpm_index);
1301 }
1302
1303 }
1304
1305 static void
1306 emit_zs_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index)
1307 {
1308 struct qreg zscale = vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1309 struct qreg zoffset = vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1310
1311 struct qreg z = c->outputs[c->output_position_index + 2];
1312 z = vir_FMUL(c, z, zscale);
1313 z = vir_FMUL(c, z, rcp_w);
1314 z = vir_FADD(c, z, zoffset);
1315 vir_VPM_WRITE(c, z, vpm_index);
1316 }
1317
1318 static void
1319 emit_rcp_wc_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index)
1320 {
1321 vir_VPM_WRITE(c, rcp_w, vpm_index);
1322 }
1323
1324 static void
1325 emit_point_size_write(struct v3d_compile *c, uint32_t *vpm_index)
1326 {
1327 struct qreg point_size;
1328
1329 if (c->output_point_size_index != -1)
1330 point_size = c->outputs[c->output_point_size_index];
1331 else
1332 point_size = vir_uniform_f(c, 1.0);
1333
1334 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1335 * BCM21553).
1336 */
1337 point_size = vir_FMAX(c, point_size, vir_uniform_f(c, .125));
1338
1339 vir_VPM_WRITE(c, point_size, vpm_index);
1340 }
1341
1342 static void
1343 emit_vpm_write_setup(struct v3d_compile *c)
1344 {
1345 if (c->devinfo->ver >= 40)
1346 return;
1347
1348 v3d33_vir_vpm_write_setup(c);
1349 }
1350
1351 /**
1352 * Sets up c->outputs[c->output_position_index] for the vertex shader
1353 * epilogue, if an output vertex position wasn't specified in the user's
1354 * shader. This may be the case for transform feedback with rasterizer
1355 * discard enabled.
1356 */
1357 static void
1358 setup_default_position(struct v3d_compile *c)
1359 {
1360 if (c->output_position_index != -1)
1361 return;
1362
1363 c->output_position_index = c->outputs_array_size;
1364 for (int i = 0; i < 4; i++) {
1365 add_output(c,
1366 c->output_position_index + i,
1367 VARYING_SLOT_POS, i);
1368 }
1369 }
1370
1371 static void
1372 emit_vert_end(struct v3d_compile *c)
1373 {
1374 setup_default_position(c);
1375
1376 uint32_t vpm_index = 0;
1377 struct qreg rcp_w = vir_RECIP(c,
1378 c->outputs[c->output_position_index + 3]);
1379
1380 emit_vpm_write_setup(c);
1381
1382 if (c->vs_key->is_coord) {
1383 for (int i = 0; i < 4; i++)
1384 vir_VPM_WRITE(c, c->outputs[c->output_position_index + i],
1385 &vpm_index);
1386 emit_scaled_viewport_write(c, rcp_w, &vpm_index);
1387 if (c->vs_key->per_vertex_point_size) {
1388 emit_point_size_write(c, &vpm_index);
1389 /* emit_rcp_wc_write(c, rcp_w); */
1390 }
1391 /* XXX: Z-only rendering */
1392 if (0)
1393 emit_zs_write(c, rcp_w, &vpm_index);
1394 } else {
1395 emit_scaled_viewport_write(c, rcp_w, &vpm_index);
1396 emit_zs_write(c, rcp_w, &vpm_index);
1397 emit_rcp_wc_write(c, rcp_w, &vpm_index);
1398 if (c->vs_key->per_vertex_point_size)
1399 emit_point_size_write(c, &vpm_index);
1400 }
1401
1402 for (int i = 0; i < c->vs_key->num_fs_inputs; i++) {
1403 struct v3d_varying_slot input = c->vs_key->fs_inputs[i];
1404 int j;
1405
1406 for (j = 0; j < c->num_outputs; j++) {
1407 struct v3d_varying_slot output = c->output_slots[j];
1408
1409 if (!memcmp(&input, &output, sizeof(input))) {
1410 vir_VPM_WRITE(c, c->outputs[j],
1411 &vpm_index);
1412 break;
1413 }
1414 }
1415 /* Emit padding if we didn't find a declared VS output for
1416 * this FS input.
1417 */
1418 if (j == c->num_outputs)
1419 vir_VPM_WRITE(c, vir_uniform_f(c, 0.0),
1420 &vpm_index);
1421 }
1422
1423 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1424 */
1425 if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
1426 vir_VPMWT(c);
1427 }
1428
1429 void
1430 v3d_optimize_nir(struct nir_shader *s)
1431 {
1432 bool progress;
1433
1434 do {
1435 progress = false;
1436
1437 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1438 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1439 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1440 NIR_PASS(progress, s, nir_copy_prop);
1441 NIR_PASS(progress, s, nir_opt_remove_phis);
1442 NIR_PASS(progress, s, nir_opt_dce);
1443 NIR_PASS(progress, s, nir_opt_dead_cf);
1444 NIR_PASS(progress, s, nir_opt_cse);
1445 NIR_PASS(progress, s, nir_opt_peephole_select, 8, true, true);
1446 NIR_PASS(progress, s, nir_opt_algebraic);
1447 NIR_PASS(progress, s, nir_opt_constant_folding);
1448 NIR_PASS(progress, s, nir_opt_undef);
1449 } while (progress);
1450
1451 NIR_PASS(progress, s, nir_opt_move_load_ubo);
1452 }
1453
1454 static int
1455 driver_location_compare(const void *in_a, const void *in_b)
1456 {
1457 const nir_variable *const *a = in_a;
1458 const nir_variable *const *b = in_b;
1459
1460 return (*a)->data.driver_location - (*b)->data.driver_location;
1461 }
1462
1463 static struct qreg
1464 ntq_emit_vpm_read(struct v3d_compile *c,
1465 uint32_t *num_components_queued,
1466 uint32_t *remaining,
1467 uint32_t vpm_index)
1468 {
1469 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1470
1471 if (c->devinfo->ver >= 40 ) {
1472 return vir_LDVPMV_IN(c,
1473 vir_uniform_ui(c,
1474 (*num_components_queued)++));
1475 }
1476
1477 if (*num_components_queued != 0) {
1478 (*num_components_queued)--;
1479 c->num_inputs++;
1480 return vir_MOV(c, vpm);
1481 }
1482
1483 uint32_t num_components = MIN2(*remaining, 32);
1484
1485 v3d33_vir_vpm_read_setup(c, num_components);
1486
1487 *num_components_queued = num_components - 1;
1488 *remaining -= num_components;
1489 c->num_inputs++;
1490
1491 return vir_MOV(c, vpm);
1492 }
1493
1494 static void
1495 ntq_setup_vpm_inputs(struct v3d_compile *c)
1496 {
1497 /* Figure out how many components of each vertex attribute the shader
1498 * uses. Each variable should have been split to individual
1499 * components and unused ones DCEed. The vertex fetcher will load
1500 * from the start of the attribute to the number of components we
1501 * declare we need in c->vattr_sizes[].
1502 */
1503 nir_foreach_variable(var, &c->s->inputs) {
1504 /* No VS attribute array support. */
1505 assert(MAX2(glsl_get_length(var->type), 1) == 1);
1506
1507 unsigned loc = var->data.driver_location;
1508 int start_component = var->data.location_frac;
1509 int num_components = glsl_get_components(var->type);
1510
1511 c->vattr_sizes[loc] = MAX2(c->vattr_sizes[loc],
1512 start_component + num_components);
1513 }
1514
1515 unsigned num_components = 0;
1516 uint32_t vpm_components_queued = 0;
1517 bool uses_iid = c->s->info.system_values_read &
1518 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1519 bool uses_vid = c->s->info.system_values_read &
1520 (1ull << SYSTEM_VALUE_VERTEX_ID);
1521 num_components += uses_iid;
1522 num_components += uses_vid;
1523
1524 for (int i = 0; i < ARRAY_SIZE(c->vattr_sizes); i++)
1525 num_components += c->vattr_sizes[i];
1526
1527 if (uses_iid) {
1528 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1529 &num_components, ~0);
1530 }
1531
1532 if (uses_vid) {
1533 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1534 &num_components, ~0);
1535 }
1536
1537 for (int loc = 0; loc < ARRAY_SIZE(c->vattr_sizes); loc++) {
1538 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1539 (loc + 1) * 4);
1540
1541 for (int i = 0; i < c->vattr_sizes[loc]; i++) {
1542 c->inputs[loc * 4 + i] =
1543 ntq_emit_vpm_read(c,
1544 &vpm_components_queued,
1545 &num_components,
1546 loc * 4 + i);
1547
1548 }
1549 }
1550
1551 if (c->devinfo->ver >= 40) {
1552 assert(vpm_components_queued == num_components);
1553 } else {
1554 assert(vpm_components_queued == 0);
1555 assert(num_components == 0);
1556 }
1557 }
1558
1559 static void
1560 ntq_setup_fs_inputs(struct v3d_compile *c)
1561 {
1562 unsigned num_entries = 0;
1563 unsigned num_components = 0;
1564 nir_foreach_variable(var, &c->s->inputs) {
1565 num_entries++;
1566 num_components += glsl_get_components(var->type);
1567 }
1568
1569 nir_variable *vars[num_entries];
1570
1571 unsigned i = 0;
1572 nir_foreach_variable(var, &c->s->inputs)
1573 vars[i++] = var;
1574
1575 /* Sort the variables so that we emit the input setup in
1576 * driver_location order. This is required for VPM reads, whose data
1577 * is fetched into the VPM in driver_location (TGSI register index)
1578 * order.
1579 */
1580 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1581
1582 for (unsigned i = 0; i < num_entries; i++) {
1583 nir_variable *var = vars[i];
1584 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1585 unsigned loc = var->data.driver_location;
1586
1587 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1588 (loc + array_len) * 4);
1589
1590 if (var->data.location == VARYING_SLOT_POS) {
1591 emit_fragcoord_input(c, loc);
1592 } else if (var->data.location == VARYING_SLOT_PNTC ||
1593 (var->data.location >= VARYING_SLOT_VAR0 &&
1594 (c->fs_key->point_sprite_mask &
1595 (1 << (var->data.location -
1596 VARYING_SLOT_VAR0))))) {
1597 c->inputs[loc * 4 + 0] = c->point_x;
1598 c->inputs[loc * 4 + 1] = c->point_y;
1599 } else {
1600 for (int j = 0; j < array_len; j++)
1601 emit_fragment_input(c, loc + j, var, j);
1602 }
1603 }
1604 }
1605
1606 static void
1607 ntq_setup_outputs(struct v3d_compile *c)
1608 {
1609 nir_foreach_variable(var, &c->s->outputs) {
1610 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1611 unsigned loc = var->data.driver_location * 4;
1612
1613 assert(array_len == 1);
1614 (void)array_len;
1615
1616 for (int i = 0; i < 4 - var->data.location_frac; i++) {
1617 add_output(c, loc + var->data.location_frac + i,
1618 var->data.location,
1619 var->data.location_frac + i);
1620 }
1621
1622 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1623 switch (var->data.location) {
1624 case FRAG_RESULT_COLOR:
1625 c->output_color_var[0] = var;
1626 c->output_color_var[1] = var;
1627 c->output_color_var[2] = var;
1628 c->output_color_var[3] = var;
1629 break;
1630 case FRAG_RESULT_DATA0:
1631 case FRAG_RESULT_DATA1:
1632 case FRAG_RESULT_DATA2:
1633 case FRAG_RESULT_DATA3:
1634 c->output_color_var[var->data.location -
1635 FRAG_RESULT_DATA0] = var;
1636 break;
1637 case FRAG_RESULT_DEPTH:
1638 c->output_position_index = loc;
1639 break;
1640 case FRAG_RESULT_SAMPLE_MASK:
1641 c->output_sample_mask_index = loc;
1642 break;
1643 }
1644 } else {
1645 switch (var->data.location) {
1646 case VARYING_SLOT_POS:
1647 c->output_position_index = loc;
1648 break;
1649 case VARYING_SLOT_PSIZ:
1650 c->output_point_size_index = loc;
1651 break;
1652 }
1653 }
1654 }
1655 }
1656
1657 static void
1658 ntq_setup_uniforms(struct v3d_compile *c)
1659 {
1660 nir_foreach_variable(var, &c->s->uniforms) {
1661 uint32_t vec4_count = glsl_count_attribute_slots(var->type,
1662 false);
1663 unsigned vec4_size = 4 * sizeof(float);
1664
1665 if (var->data.mode != nir_var_uniform)
1666 continue;
1667
1668 declare_uniform_range(c, var->data.driver_location * vec4_size,
1669 vec4_count * vec4_size);
1670
1671 }
1672 }
1673
1674 /**
1675 * Sets up the mapping from nir_register to struct qreg *.
1676 *
1677 * Each nir_register gets a struct qreg per 32-bit component being stored.
1678 */
1679 static void
1680 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1681 {
1682 foreach_list_typed(nir_register, nir_reg, node, list) {
1683 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1684 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1685 array_len *
1686 nir_reg->num_components);
1687
1688 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1689
1690 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1691 qregs[i] = vir_get_temp(c);
1692 }
1693 }
1694
1695 static void
1696 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1697 {
1698 /* XXX perf: Experiment with using immediate loads to avoid having
1699 * these end up in the uniform stream. Watch out for breaking the
1700 * small immediates optimization in the process!
1701 */
1702 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1703 for (int i = 0; i < instr->def.num_components; i++)
1704 qregs[i] = vir_uniform_ui(c, instr->value.u32[i]);
1705
1706 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1707 }
1708
1709 static void
1710 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1711 {
1712 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1713
1714 /* VIR needs there to be *some* value, so pick 0 (same as for
1715 * ntq_setup_registers().
1716 */
1717 for (int i = 0; i < instr->def.num_components; i++)
1718 qregs[i] = vir_uniform_ui(c, 0);
1719 }
1720
1721 static void
1722 ntq_emit_image_size(struct v3d_compile *c, nir_intrinsic_instr *instr)
1723 {
1724 assert(instr->intrinsic == nir_intrinsic_image_deref_size);
1725 nir_variable *var = nir_intrinsic_get_var(instr, 0);
1726 unsigned image_index = var->data.driver_location;
1727 const struct glsl_type *sampler_type = glsl_without_array(var->type);
1728 bool is_array = glsl_sampler_type_is_array(sampler_type);
1729
1730 ntq_store_dest(c, &instr->dest, 0,
1731 vir_uniform(c, QUNIFORM_IMAGE_WIDTH, image_index));
1732 if (instr->num_components > 1) {
1733 ntq_store_dest(c, &instr->dest, 1,
1734 vir_uniform(c, QUNIFORM_IMAGE_HEIGHT,
1735 image_index));
1736 }
1737 if (instr->num_components > 2) {
1738 ntq_store_dest(c, &instr->dest, 2,
1739 vir_uniform(c,
1740 is_array ?
1741 QUNIFORM_IMAGE_ARRAY_SIZE :
1742 QUNIFORM_IMAGE_DEPTH,
1743 image_index));
1744 }
1745 }
1746
1747 static void
1748 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
1749 {
1750 unsigned offset;
1751
1752 switch (instr->intrinsic) {
1753 case nir_intrinsic_load_uniform:
1754 if (nir_src_is_const(instr->src[0])) {
1755 int offset = (nir_intrinsic_base(instr) +
1756 nir_src_as_uint(instr->src[0]));
1757 assert(offset % 4 == 0);
1758 /* We need dwords */
1759 offset = offset / 4;
1760 for (int i = 0; i < instr->num_components; i++) {
1761 ntq_store_dest(c, &instr->dest, i,
1762 vir_uniform(c, QUNIFORM_UNIFORM,
1763 offset + i));
1764 }
1765 } else {
1766 ntq_emit_tmu_general(c, instr, false);
1767 }
1768 break;
1769
1770 case nir_intrinsic_load_ubo:
1771 ntq_emit_tmu_general(c, instr, false);
1772 break;
1773
1774 case nir_intrinsic_ssbo_atomic_add:
1775 case nir_intrinsic_ssbo_atomic_imin:
1776 case nir_intrinsic_ssbo_atomic_umin:
1777 case nir_intrinsic_ssbo_atomic_imax:
1778 case nir_intrinsic_ssbo_atomic_umax:
1779 case nir_intrinsic_ssbo_atomic_and:
1780 case nir_intrinsic_ssbo_atomic_or:
1781 case nir_intrinsic_ssbo_atomic_xor:
1782 case nir_intrinsic_ssbo_atomic_exchange:
1783 case nir_intrinsic_ssbo_atomic_comp_swap:
1784 case nir_intrinsic_load_ssbo:
1785 case nir_intrinsic_store_ssbo:
1786 ntq_emit_tmu_general(c, instr, false);
1787 break;
1788
1789 case nir_intrinsic_shared_atomic_add:
1790 case nir_intrinsic_shared_atomic_imin:
1791 case nir_intrinsic_shared_atomic_umin:
1792 case nir_intrinsic_shared_atomic_imax:
1793 case nir_intrinsic_shared_atomic_umax:
1794 case nir_intrinsic_shared_atomic_and:
1795 case nir_intrinsic_shared_atomic_or:
1796 case nir_intrinsic_shared_atomic_xor:
1797 case nir_intrinsic_shared_atomic_exchange:
1798 case nir_intrinsic_shared_atomic_comp_swap:
1799 case nir_intrinsic_load_shared:
1800 case nir_intrinsic_store_shared:
1801 ntq_emit_tmu_general(c, instr, true);
1802 break;
1803
1804 case nir_intrinsic_image_deref_load:
1805 case nir_intrinsic_image_deref_store:
1806 case nir_intrinsic_image_deref_atomic_add:
1807 case nir_intrinsic_image_deref_atomic_min:
1808 case nir_intrinsic_image_deref_atomic_max:
1809 case nir_intrinsic_image_deref_atomic_and:
1810 case nir_intrinsic_image_deref_atomic_or:
1811 case nir_intrinsic_image_deref_atomic_xor:
1812 case nir_intrinsic_image_deref_atomic_exchange:
1813 case nir_intrinsic_image_deref_atomic_comp_swap:
1814 v3d40_vir_emit_image_load_store(c, instr);
1815 break;
1816
1817 case nir_intrinsic_get_buffer_size:
1818 ntq_store_dest(c, &instr->dest, 0,
1819 vir_uniform(c, QUNIFORM_GET_BUFFER_SIZE,
1820 nir_src_as_uint(instr->src[0])));
1821 break;
1822
1823 case nir_intrinsic_load_user_clip_plane:
1824 for (int i = 0; i < instr->num_components; i++) {
1825 ntq_store_dest(c, &instr->dest, i,
1826 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1827 nir_intrinsic_ucp_id(instr) *
1828 4 + i));
1829 }
1830 break;
1831
1832 case nir_intrinsic_load_alpha_ref_float:
1833 ntq_store_dest(c, &instr->dest, 0,
1834 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1835 break;
1836
1837 case nir_intrinsic_load_sample_mask_in:
1838 ntq_store_dest(c, &instr->dest, 0, vir_MSF(c));
1839 break;
1840
1841 case nir_intrinsic_load_helper_invocation:
1842 vir_set_pf(vir_MSF_dest(c, vir_nop_reg()), V3D_QPU_PF_PUSHZ);
1843 ntq_store_dest(c, &instr->dest, 0,
1844 vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1845 vir_uniform_ui(c, ~0),
1846 vir_uniform_ui(c, 0))));
1847 break;
1848
1849 case nir_intrinsic_load_front_face:
1850 /* The register contains 0 (front) or 1 (back), and we need to
1851 * turn it into a NIR bool where true means front.
1852 */
1853 ntq_store_dest(c, &instr->dest, 0,
1854 vir_ADD(c,
1855 vir_uniform_ui(c, -1),
1856 vir_REVF(c)));
1857 break;
1858
1859 case nir_intrinsic_load_instance_id:
1860 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
1861 break;
1862
1863 case nir_intrinsic_load_vertex_id:
1864 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
1865 break;
1866
1867 case nir_intrinsic_load_input:
1868 for (int i = 0; i < instr->num_components; i++) {
1869 offset = (nir_intrinsic_base(instr) +
1870 nir_src_as_uint(instr->src[0]));
1871 int comp = nir_intrinsic_component(instr) + i;
1872 ntq_store_dest(c, &instr->dest, i,
1873 vir_MOV(c, c->inputs[offset * 4 + comp]));
1874 }
1875 break;
1876
1877 case nir_intrinsic_store_output:
1878 offset = ((nir_intrinsic_base(instr) +
1879 nir_src_as_uint(instr->src[1])) * 4 +
1880 nir_intrinsic_component(instr));
1881
1882 for (int i = 0; i < instr->num_components; i++) {
1883 c->outputs[offset + i] =
1884 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
1885 }
1886 c->num_outputs = MAX2(c->num_outputs,
1887 offset + instr->num_components);
1888 break;
1889
1890 case nir_intrinsic_image_deref_size:
1891 ntq_emit_image_size(c, instr);
1892 break;
1893
1894 case nir_intrinsic_discard:
1895 if (c->execute.file != QFILE_NULL) {
1896 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
1897 V3D_QPU_PF_PUSHZ);
1898 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
1899 vir_uniform_ui(c, 0)),
1900 V3D_QPU_COND_IFA);
1901 } else {
1902 vir_SETMSF_dest(c, vir_nop_reg(),
1903 vir_uniform_ui(c, 0));
1904 }
1905 break;
1906
1907 case nir_intrinsic_discard_if: {
1908 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, instr->src[0]);
1909
1910 if (c->execute.file != QFILE_NULL) {
1911 struct qinst *exec_flag = vir_MOV_dest(c, vir_nop_reg(),
1912 c->execute);
1913 if (cond == V3D_QPU_COND_IFA) {
1914 vir_set_uf(exec_flag, V3D_QPU_UF_ANDZ);
1915 } else {
1916 vir_set_uf(exec_flag, V3D_QPU_UF_NORNZ);
1917 cond = V3D_QPU_COND_IFA;
1918 }
1919 }
1920
1921 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
1922 vir_uniform_ui(c, 0)), cond);
1923
1924 break;
1925 }
1926
1927 case nir_intrinsic_memory_barrier:
1928 case nir_intrinsic_memory_barrier_atomic_counter:
1929 case nir_intrinsic_memory_barrier_buffer:
1930 case nir_intrinsic_memory_barrier_image:
1931 case nir_intrinsic_memory_barrier_shared:
1932 /* We don't do any instruction scheduling of these NIR
1933 * instructions between each other, so we just need to make
1934 * sure that the TMU operations before the barrier are flushed
1935 * before the ones after the barrier. That is currently
1936 * handled by having a THRSW in each of them and a LDTMU
1937 * series or a TMUWT after.
1938 */
1939 break;
1940
1941 case nir_intrinsic_barrier:
1942 /* Emit a TSY op to get all invocations in the workgroup
1943 * (actually supergroup) to block until the last invocation
1944 * reaches the TSY op.
1945 */
1946 if (c->devinfo->ver >= 42) {
1947 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
1948 V3D_QPU_WADDR_SYNCB));
1949 } else {
1950 struct qinst *sync =
1951 vir_BARRIERID_dest(c,
1952 vir_reg(QFILE_MAGIC,
1953 V3D_QPU_WADDR_SYNCU));
1954 sync->src[vir_get_implicit_uniform_src(sync)] =
1955 vir_uniform_ui(c,
1956 0xffffff00 |
1957 V3D_TSY_WAIT_INC_CHECK);
1958
1959 }
1960
1961 /* The blocking of a TSY op only happens at the next thread
1962 * switch. No texturing may be outstanding at the time of a
1963 * TSY blocking operation.
1964 */
1965 vir_emit_thrsw(c);
1966 break;
1967
1968 case nir_intrinsic_load_num_work_groups:
1969 for (int i = 0; i < 3; i++) {
1970 ntq_store_dest(c, &instr->dest, i,
1971 vir_uniform(c, QUNIFORM_NUM_WORK_GROUPS,
1972 i));
1973 }
1974 break;
1975
1976 case nir_intrinsic_load_local_invocation_index:
1977 ntq_store_dest(c, &instr->dest, 0,
1978 vir_SHR(c, c->cs_payload[1],
1979 vir_uniform_ui(c, 32 - c->local_invocation_index_bits)));
1980 break;
1981
1982 case nir_intrinsic_load_work_group_id:
1983 ntq_store_dest(c, &instr->dest, 0,
1984 vir_AND(c, c->cs_payload[0],
1985 vir_uniform_ui(c, 0xffff)));
1986 ntq_store_dest(c, &instr->dest, 1,
1987 vir_SHR(c, c->cs_payload[0],
1988 vir_uniform_ui(c, 16)));
1989 ntq_store_dest(c, &instr->dest, 2,
1990 vir_AND(c, c->cs_payload[1],
1991 vir_uniform_ui(c, 0xffff)));
1992 break;
1993
1994 default:
1995 fprintf(stderr, "Unknown intrinsic: ");
1996 nir_print_instr(&instr->instr, stderr);
1997 fprintf(stderr, "\n");
1998 break;
1999 }
2000 }
2001
2002 /* Clears (activates) the execute flags for any channels whose jump target
2003 * matches this block.
2004 *
2005 * XXX perf: Could we be using flpush/flpop somehow for our execution channel
2006 * enabling?
2007 *
2008 * XXX perf: For uniform control flow, we should be able to skip c->execute
2009 * handling entirely.
2010 */
2011 static void
2012 ntq_activate_execute_for_block(struct v3d_compile *c)
2013 {
2014 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
2015 c->execute, vir_uniform_ui(c, c->cur_block->index)),
2016 V3D_QPU_PF_PUSHZ);
2017
2018 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2019 }
2020
2021 static void
2022 ntq_emit_uniform_if(struct v3d_compile *c, nir_if *if_stmt)
2023 {
2024 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2025 bool empty_else_block =
2026 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2027 exec_list_is_empty(&nir_else_block->instr_list));
2028
2029 struct qblock *then_block = vir_new_block(c);
2030 struct qblock *after_block = vir_new_block(c);
2031 struct qblock *else_block;
2032 if (empty_else_block)
2033 else_block = after_block;
2034 else
2035 else_block = vir_new_block(c);
2036
2037 /* Set up the flags for the IF condition (taking the THEN branch). */
2038 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
2039
2040 /* Jump to ELSE. */
2041 vir_BRANCH(c, cond == V3D_QPU_COND_IFA ?
2042 V3D_QPU_BRANCH_COND_ALLNA :
2043 V3D_QPU_BRANCH_COND_ALLA);
2044 vir_link_blocks(c->cur_block, else_block);
2045 vir_link_blocks(c->cur_block, then_block);
2046
2047 /* Process the THEN block. */
2048 vir_set_emit_block(c, then_block);
2049 ntq_emit_cf_list(c, &if_stmt->then_list);
2050
2051 if (!empty_else_block) {
2052 /* At the end of the THEN block, jump to ENDIF */
2053 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALWAYS);
2054 vir_link_blocks(c->cur_block, after_block);
2055
2056 /* Emit the else block. */
2057 vir_set_emit_block(c, else_block);
2058 ntq_activate_execute_for_block(c);
2059 ntq_emit_cf_list(c, &if_stmt->else_list);
2060 }
2061
2062 vir_link_blocks(c->cur_block, after_block);
2063
2064 vir_set_emit_block(c, after_block);
2065 }
2066
2067 static void
2068 ntq_emit_nonuniform_if(struct v3d_compile *c, nir_if *if_stmt)
2069 {
2070 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2071 bool empty_else_block =
2072 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2073 exec_list_is_empty(&nir_else_block->instr_list));
2074
2075 struct qblock *then_block = vir_new_block(c);
2076 struct qblock *after_block = vir_new_block(c);
2077 struct qblock *else_block;
2078 if (empty_else_block)
2079 else_block = after_block;
2080 else
2081 else_block = vir_new_block(c);
2082
2083 bool was_top_level = false;
2084 if (c->execute.file == QFILE_NULL) {
2085 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2086 was_top_level = true;
2087 }
2088
2089 /* Set up the flags for the IF condition (taking the THEN branch). */
2090 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
2091
2092 /* Update the flags+cond to mean "Taking the ELSE branch (!cond) and
2093 * was previously active (execute Z) for updating the exec flags.
2094 */
2095 if (was_top_level) {
2096 cond = v3d_qpu_cond_invert(cond);
2097 } else {
2098 struct qinst *inst = vir_MOV_dest(c, vir_nop_reg(), c->execute);
2099 if (cond == V3D_QPU_COND_IFA) {
2100 vir_set_uf(inst, V3D_QPU_UF_NORNZ);
2101 } else {
2102 vir_set_uf(inst, V3D_QPU_UF_ANDZ);
2103 cond = V3D_QPU_COND_IFA;
2104 }
2105 }
2106
2107 vir_MOV_cond(c, cond,
2108 c->execute,
2109 vir_uniform_ui(c, else_block->index));
2110
2111 /* Jump to ELSE if nothing is active for THEN, otherwise fall
2112 * through.
2113 */
2114 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ);
2115 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
2116 vir_link_blocks(c->cur_block, else_block);
2117 vir_link_blocks(c->cur_block, then_block);
2118
2119 /* Process the THEN block. */
2120 vir_set_emit_block(c, then_block);
2121 ntq_emit_cf_list(c, &if_stmt->then_list);
2122
2123 if (!empty_else_block) {
2124 /* Handle the end of the THEN block. First, all currently
2125 * active channels update their execute flags to point to
2126 * ENDIF
2127 */
2128 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2129 V3D_QPU_PF_PUSHZ);
2130 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2131 vir_uniform_ui(c, after_block->index));
2132
2133 /* If everything points at ENDIF, then jump there immediately. */
2134 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
2135 c->execute,
2136 vir_uniform_ui(c, after_block->index)),
2137 V3D_QPU_PF_PUSHZ);
2138 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
2139 vir_link_blocks(c->cur_block, after_block);
2140 vir_link_blocks(c->cur_block, else_block);
2141
2142 vir_set_emit_block(c, else_block);
2143 ntq_activate_execute_for_block(c);
2144 ntq_emit_cf_list(c, &if_stmt->else_list);
2145 }
2146
2147 vir_link_blocks(c->cur_block, after_block);
2148
2149 vir_set_emit_block(c, after_block);
2150 if (was_top_level)
2151 c->execute = c->undef;
2152 else
2153 ntq_activate_execute_for_block(c);
2154 }
2155
2156 static void
2157 ntq_emit_if(struct v3d_compile *c, nir_if *nif)
2158 {
2159 if (c->execute.file == QFILE_NULL &&
2160 nir_src_is_dynamically_uniform(nif->condition)) {
2161 ntq_emit_uniform_if(c, nif);
2162 } else {
2163 ntq_emit_nonuniform_if(c, nif);
2164 }
2165 }
2166
2167 static void
2168 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
2169 {
2170 switch (jump->type) {
2171 case nir_jump_break:
2172 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2173 V3D_QPU_PF_PUSHZ);
2174 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2175 vir_uniform_ui(c, c->loop_break_block->index));
2176 break;
2177
2178 case nir_jump_continue:
2179 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2180 V3D_QPU_PF_PUSHZ);
2181 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2182 vir_uniform_ui(c, c->loop_cont_block->index));
2183 break;
2184
2185 case nir_jump_return:
2186 unreachable("All returns shouold be lowered\n");
2187 }
2188 }
2189
2190 static void
2191 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
2192 {
2193 switch (instr->type) {
2194 case nir_instr_type_deref:
2195 /* ignored, will be walked by the intrinsic using it. */
2196 break;
2197
2198 case nir_instr_type_alu:
2199 ntq_emit_alu(c, nir_instr_as_alu(instr));
2200 break;
2201
2202 case nir_instr_type_intrinsic:
2203 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
2204 break;
2205
2206 case nir_instr_type_load_const:
2207 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
2208 break;
2209
2210 case nir_instr_type_ssa_undef:
2211 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
2212 break;
2213
2214 case nir_instr_type_tex:
2215 ntq_emit_tex(c, nir_instr_as_tex(instr));
2216 break;
2217
2218 case nir_instr_type_jump:
2219 ntq_emit_jump(c, nir_instr_as_jump(instr));
2220 break;
2221
2222 default:
2223 fprintf(stderr, "Unknown NIR instr type: ");
2224 nir_print_instr(instr, stderr);
2225 fprintf(stderr, "\n");
2226 abort();
2227 }
2228 }
2229
2230 static void
2231 ntq_emit_block(struct v3d_compile *c, nir_block *block)
2232 {
2233 nir_foreach_instr(instr, block) {
2234 ntq_emit_instr(c, instr);
2235 }
2236 }
2237
2238 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
2239
2240 static void
2241 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
2242 {
2243 bool was_top_level = false;
2244 if (c->execute.file == QFILE_NULL) {
2245 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2246 was_top_level = true;
2247 }
2248
2249 struct qblock *save_loop_cont_block = c->loop_cont_block;
2250 struct qblock *save_loop_break_block = c->loop_break_block;
2251
2252 c->loop_cont_block = vir_new_block(c);
2253 c->loop_break_block = vir_new_block(c);
2254
2255 vir_link_blocks(c->cur_block, c->loop_cont_block);
2256 vir_set_emit_block(c, c->loop_cont_block);
2257 ntq_activate_execute_for_block(c);
2258
2259 ntq_emit_cf_list(c, &loop->body);
2260
2261 /* Re-enable any previous continues now, so our ANYA check below
2262 * works.
2263 *
2264 * XXX: Use the .ORZ flags update, instead.
2265 */
2266 vir_set_pf(vir_XOR_dest(c,
2267 vir_nop_reg(),
2268 c->execute,
2269 vir_uniform_ui(c, c->loop_cont_block->index)),
2270 V3D_QPU_PF_PUSHZ);
2271 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2272
2273 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ);
2274
2275 struct qinst *branch = vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
2276 /* Pixels that were not dispatched or have been discarded should not
2277 * contribute to looping again.
2278 */
2279 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P;
2280 vir_link_blocks(c->cur_block, c->loop_cont_block);
2281 vir_link_blocks(c->cur_block, c->loop_break_block);
2282
2283 vir_set_emit_block(c, c->loop_break_block);
2284 if (was_top_level)
2285 c->execute = c->undef;
2286 else
2287 ntq_activate_execute_for_block(c);
2288
2289 c->loop_break_block = save_loop_break_block;
2290 c->loop_cont_block = save_loop_cont_block;
2291
2292 c->loops++;
2293 }
2294
2295 static void
2296 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
2297 {
2298 fprintf(stderr, "FUNCTIONS not handled.\n");
2299 abort();
2300 }
2301
2302 static void
2303 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
2304 {
2305 foreach_list_typed(nir_cf_node, node, node, list) {
2306 switch (node->type) {
2307 case nir_cf_node_block:
2308 ntq_emit_block(c, nir_cf_node_as_block(node));
2309 break;
2310
2311 case nir_cf_node_if:
2312 ntq_emit_if(c, nir_cf_node_as_if(node));
2313 break;
2314
2315 case nir_cf_node_loop:
2316 ntq_emit_loop(c, nir_cf_node_as_loop(node));
2317 break;
2318
2319 case nir_cf_node_function:
2320 ntq_emit_function(c, nir_cf_node_as_function(node));
2321 break;
2322
2323 default:
2324 fprintf(stderr, "Unknown NIR node type\n");
2325 abort();
2326 }
2327 }
2328 }
2329
2330 static void
2331 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
2332 {
2333 ntq_setup_registers(c, &impl->registers);
2334 ntq_emit_cf_list(c, &impl->body);
2335 }
2336
2337 static void
2338 nir_to_vir(struct v3d_compile *c)
2339 {
2340 switch (c->s->info.stage) {
2341 case MESA_SHADER_FRAGMENT:
2342 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
2343 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
2344 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
2345
2346 /* XXX perf: We could set the "disable implicit point/line
2347 * varyings" field in the shader record and not emit these, if
2348 * they're not going to be used.
2349 */
2350 if (c->fs_key->is_points) {
2351 c->point_x = emit_fragment_varying(c, NULL, 0, 0);
2352 c->point_y = emit_fragment_varying(c, NULL, 0, 0);
2353 } else if (c->fs_key->is_lines) {
2354 c->line_x = emit_fragment_varying(c, NULL, 0, 0);
2355 }
2356 break;
2357 case MESA_SHADER_COMPUTE:
2358 /* Set up the TSO for barriers, assuming we do some. */
2359 if (c->devinfo->ver < 42) {
2360 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
2361 V3D_QPU_WADDR_SYNC));
2362 }
2363
2364 if (c->s->info.system_values_read &
2365 ((1ull << SYSTEM_VALUE_LOCAL_INVOCATION_INDEX) |
2366 (1ull << SYSTEM_VALUE_WORK_GROUP_ID))) {
2367 c->cs_payload[0] = vir_MOV(c, vir_reg(QFILE_REG, 0));
2368 }
2369 if ((c->s->info.system_values_read &
2370 ((1ull << SYSTEM_VALUE_WORK_GROUP_ID))) ||
2371 c->s->info.cs.shared_size) {
2372 c->cs_payload[1] = vir_MOV(c, vir_reg(QFILE_REG, 2));
2373 }
2374
2375 /* Set up the division between gl_LocalInvocationIndex and
2376 * wg_in_mem in the payload reg.
2377 */
2378 int wg_size = (c->s->info.cs.local_size[0] *
2379 c->s->info.cs.local_size[1] *
2380 c->s->info.cs.local_size[2]);
2381 c->local_invocation_index_bits =
2382 ffs(util_next_power_of_two(MAX2(wg_size, 64))) - 1;
2383 assert(c->local_invocation_index_bits <= 8);
2384
2385 if (c->s->info.cs.shared_size) {
2386 struct qreg wg_in_mem = vir_SHR(c, c->cs_payload[1],
2387 vir_uniform_ui(c, 16));
2388 if (c->s->info.cs.local_size[0] != 1 ||
2389 c->s->info.cs.local_size[1] != 1 ||
2390 c->s->info.cs.local_size[2] != 1) {
2391 int wg_bits = (16 -
2392 c->local_invocation_index_bits);
2393 int wg_mask = (1 << wg_bits) - 1;
2394 wg_in_mem = vir_AND(c, wg_in_mem,
2395 vir_uniform_ui(c, wg_mask));
2396 }
2397 struct qreg shared_per_wg =
2398 vir_uniform_ui(c, c->s->info.cs.shared_size);
2399
2400 c->cs_shared_offset =
2401 vir_ADD(c,
2402 vir_uniform(c, QUNIFORM_SHARED_OFFSET,0),
2403 vir_UMUL(c, wg_in_mem, shared_per_wg));
2404 }
2405 break;
2406 default:
2407 break;
2408 }
2409
2410 if (c->s->info.stage == MESA_SHADER_FRAGMENT)
2411 ntq_setup_fs_inputs(c);
2412 else
2413 ntq_setup_vpm_inputs(c);
2414
2415 ntq_setup_outputs(c);
2416 ntq_setup_uniforms(c);
2417 ntq_setup_registers(c, &c->s->registers);
2418
2419 /* Find the main function and emit the body. */
2420 nir_foreach_function(function, c->s) {
2421 assert(strcmp(function->name, "main") == 0);
2422 assert(function->impl);
2423 ntq_emit_impl(c, function->impl);
2424 }
2425 }
2426
2427 const nir_shader_compiler_options v3d_nir_options = {
2428 .lower_all_io_to_temps = true,
2429 .lower_extract_byte = true,
2430 .lower_extract_word = true,
2431 .lower_bfm = true,
2432 .lower_bitfield_insert_to_shifts = true,
2433 .lower_bitfield_extract_to_shifts = true,
2434 .lower_bitfield_reverse = true,
2435 .lower_bit_count = true,
2436 .lower_cs_local_id_from_index = true,
2437 .lower_ffract = true,
2438 .lower_pack_unorm_2x16 = true,
2439 .lower_pack_snorm_2x16 = true,
2440 .lower_pack_unorm_4x8 = true,
2441 .lower_pack_snorm_4x8 = true,
2442 .lower_unpack_unorm_4x8 = true,
2443 .lower_unpack_snorm_4x8 = true,
2444 .lower_pack_half_2x16 = true,
2445 .lower_unpack_half_2x16 = true,
2446 .lower_fdiv = true,
2447 .lower_find_lsb = true,
2448 .lower_ffma = true,
2449 .lower_flrp32 = true,
2450 .lower_fpow = true,
2451 .lower_fsat = true,
2452 .lower_fsqrt = true,
2453 .lower_ifind_msb = true,
2454 .lower_isign = true,
2455 .lower_ldexp = true,
2456 .lower_mul_high = true,
2457 .lower_wpos_pntc = true,
2458 .native_integers = true,
2459 };
2460
2461 /**
2462 * When demoting a shader down to single-threaded, removes the THRSW
2463 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
2464 * program end).
2465 */
2466 static void
2467 vir_remove_thrsw(struct v3d_compile *c)
2468 {
2469 vir_for_each_block(block, c) {
2470 vir_for_each_inst_safe(inst, block) {
2471 if (inst->qpu.sig.thrsw)
2472 vir_remove_instruction(c, inst);
2473 }
2474 }
2475
2476 c->last_thrsw = NULL;
2477 }
2478
2479 void
2480 vir_emit_last_thrsw(struct v3d_compile *c)
2481 {
2482 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
2483 * switching, so disable threads if we didn't do any TMU ops (each of
2484 * which would have emitted a THRSW).
2485 */
2486 if (!c->last_thrsw_at_top_level && c->devinfo->ver < 41) {
2487 c->threads = 1;
2488 if (c->last_thrsw)
2489 vir_remove_thrsw(c);
2490 return;
2491 }
2492
2493 /* If we're threaded and the last THRSW was in conditional code, then
2494 * we need to emit another one so that we can flag it as the last
2495 * thrsw.
2496 */
2497 if (c->last_thrsw && !c->last_thrsw_at_top_level) {
2498 assert(c->devinfo->ver >= 41);
2499 vir_emit_thrsw(c);
2500 }
2501
2502 /* If we're threaded, then we need to mark the last THRSW instruction
2503 * so we can emit a pair of them at QPU emit time.
2504 *
2505 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2506 * post-last-THRSW state, so we can skip this.
2507 */
2508 if (!c->last_thrsw && c->s->info.stage == MESA_SHADER_FRAGMENT) {
2509 assert(c->devinfo->ver >= 41);
2510 vir_emit_thrsw(c);
2511 }
2512
2513 if (c->last_thrsw)
2514 c->last_thrsw->is_last_thrsw = true;
2515 }
2516
2517 /* There's a flag in the shader for "center W is needed for reasons other than
2518 * non-centroid varyings", so we just walk the program after VIR optimization
2519 * to see if it's used. It should be harmless to set even if we only use
2520 * center W for varyings.
2521 */
2522 static void
2523 vir_check_payload_w(struct v3d_compile *c)
2524 {
2525 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
2526 return;
2527
2528 vir_for_each_inst_inorder(inst, c) {
2529 for (int i = 0; i < vir_get_nsrc(inst); i++) {
2530 if (inst->src[i].file == QFILE_REG &&
2531 inst->src[i].index == 0) {
2532 c->uses_center_w = true;
2533 return;
2534 }
2535 }
2536 }
2537
2538 }
2539
2540 void
2541 v3d_nir_to_vir(struct v3d_compile *c)
2542 {
2543 if (V3D_DEBUG & (V3D_DEBUG_NIR |
2544 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2545 fprintf(stderr, "%s prog %d/%d NIR:\n",
2546 vir_get_stage_name(c),
2547 c->program_id, c->variant_id);
2548 nir_print_shader(c->s, stderr);
2549 }
2550
2551 nir_to_vir(c);
2552
2553 /* Emit the last THRSW before STVPM and TLB writes. */
2554 vir_emit_last_thrsw(c);
2555
2556 switch (c->s->info.stage) {
2557 case MESA_SHADER_FRAGMENT:
2558 emit_frag_end(c);
2559 break;
2560 case MESA_SHADER_VERTEX:
2561 emit_vert_end(c);
2562 break;
2563 default:
2564 unreachable("bad stage");
2565 }
2566
2567 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2568 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2569 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
2570 vir_get_stage_name(c),
2571 c->program_id, c->variant_id);
2572 vir_dump(c);
2573 fprintf(stderr, "\n");
2574 }
2575
2576 vir_optimize(c);
2577 vir_lower_uniforms(c);
2578
2579 vir_check_payload_w(c);
2580
2581 /* XXX perf: On VC4, we do a VIR-level instruction scheduling here.
2582 * We used that on that platform to pipeline TMU writes and reduce the
2583 * number of thread switches, as well as try (mostly successfully) to
2584 * reduce maximum register pressure to allow more threads. We should
2585 * do something of that sort for V3D -- either instruction scheduling
2586 * here, or delay the the THRSW and LDTMUs from our texture
2587 * instructions until the results are needed.
2588 */
2589
2590 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2591 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2592 fprintf(stderr, "%s prog %d/%d VIR:\n",
2593 vir_get_stage_name(c),
2594 c->program_id, c->variant_id);
2595 vir_dump(c);
2596 fprintf(stderr, "\n");
2597 }
2598
2599 /* Attempt to allocate registers for the temporaries. If we fail,
2600 * reduce thread count and try again.
2601 */
2602 int min_threads = (c->devinfo->ver >= 41) ? 2 : 1;
2603 struct qpu_reg *temp_registers;
2604 while (true) {
2605 bool spilled;
2606 temp_registers = v3d_register_allocate(c, &spilled);
2607 if (spilled)
2608 continue;
2609
2610 if (temp_registers)
2611 break;
2612
2613 if (c->threads == min_threads) {
2614 fprintf(stderr, "Failed to register allocate at %d threads:\n",
2615 c->threads);
2616 vir_dump(c);
2617 c->failed = true;
2618 return;
2619 }
2620
2621 c->threads /= 2;
2622
2623 if (c->threads == 1)
2624 vir_remove_thrsw(c);
2625 }
2626
2627 v3d_vir_to_qpu(c, temp_registers);
2628 }