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v3d: Use the NIR lowering for isign instead of rolling our own.
[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
34
35 #define GENERAL_TMU_LOOKUP_PER_QUAD (0 << 7)
36 #define GENERAL_TMU_LOOKUP_PER_PIXEL (1 << 7)
37 #define GENERAL_TMU_READ_OP_PREFETCH (0 << 3)
38 #define GENERAL_TMU_READ_OP_CACHE_CLEAR (1 << 3)
39 #define GENERAL_TMU_READ_OP_CACHE_FLUSH (3 << 3)
40 #define GENERAL_TMU_READ_OP_CACHE_CLEAN (3 << 3)
41 #define GENERAL_TMU_READ_OP_CACHE_L1T_CLEAR (4 << 3)
42 #define GENERAL_TMU_READ_OP_CACHE_L1T_FLUSH_AGGREGATION (5 << 3)
43 #define GENERAL_TMU_READ_OP_ATOMIC_INC (8 << 3)
44 #define GENERAL_TMU_READ_OP_ATOMIC_DEC (9 << 3)
45 #define GENERAL_TMU_READ_OP_ATOMIC_NOT (10 << 3)
46 #define GENERAL_TMU_READ_OP_READ (15 << 3)
47 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_I (0 << 0)
48 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_I (1 << 0)
49 #define GENERAL_TMU_LOOKUP_TYPE_VEC2 (2 << 0)
50 #define GENERAL_TMU_LOOKUP_TYPE_VEC3 (3 << 0)
51 #define GENERAL_TMU_LOOKUP_TYPE_VEC4 (4 << 0)
52 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_UI (5 << 0)
53 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_UI (6 << 0)
54 #define GENERAL_TMU_LOOKUP_TYPE_32BIT_UI (7 << 0)
55
56 #define GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP (0 << 3)
57 #define GENERAL_TMU_WRITE_OP_ATOMIC_SUB_WRAP (1 << 3)
58 #define GENERAL_TMU_WRITE_OP_ATOMIC_XCHG (2 << 3)
59 #define GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG (3 << 3)
60 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMIN (4 << 3)
61 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMAX (5 << 3)
62 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMIN (6 << 3)
63 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMAX (7 << 3)
64 #define GENERAL_TMU_WRITE_OP_ATOMIC_AND (8 << 3)
65 #define GENERAL_TMU_WRITE_OP_ATOMIC_OR (9 << 3)
66 #define GENERAL_TMU_WRITE_OP_ATOMIC_XOR (10 << 3)
67 #define GENERAL_TMU_WRITE_OP_WRITE (15 << 3)
68
69 #define V3D_TSY_SET_QUORUM 0
70 #define V3D_TSY_INC_WAITERS 1
71 #define V3D_TSY_DEC_WAITERS 2
72 #define V3D_TSY_INC_QUORUM 3
73 #define V3D_TSY_DEC_QUORUM 4
74 #define V3D_TSY_FREE_ALL 5
75 #define V3D_TSY_RELEASE 6
76 #define V3D_TSY_ACQUIRE 7
77 #define V3D_TSY_WAIT 8
78 #define V3D_TSY_WAIT_INC 9
79 #define V3D_TSY_WAIT_CHECK 10
80 #define V3D_TSY_WAIT_INC_CHECK 11
81 #define V3D_TSY_WAIT_CV 12
82 #define V3D_TSY_INC_SEMAPHORE 13
83 #define V3D_TSY_DEC_SEMAPHORE 14
84 #define V3D_TSY_SET_QUORUM_FREE_ALL 15
85
86 static void
87 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
88
89 static void
90 resize_qreg_array(struct v3d_compile *c,
91 struct qreg **regs,
92 uint32_t *size,
93 uint32_t decl_size)
94 {
95 if (*size >= decl_size)
96 return;
97
98 uint32_t old_size = *size;
99 *size = MAX2(*size * 2, decl_size);
100 *regs = reralloc(c, *regs, struct qreg, *size);
101 if (!*regs) {
102 fprintf(stderr, "Malloc failure\n");
103 abort();
104 }
105
106 for (uint32_t i = old_size; i < *size; i++)
107 (*regs)[i] = c->undef;
108 }
109
110 void
111 vir_emit_thrsw(struct v3d_compile *c)
112 {
113 if (c->threads == 1)
114 return;
115
116 /* Always thread switch after each texture operation for now.
117 *
118 * We could do better by batching a bunch of texture fetches up and
119 * then doing one thread switch and collecting all their results
120 * afterward.
121 */
122 c->last_thrsw = vir_NOP(c);
123 c->last_thrsw->qpu.sig.thrsw = true;
124 c->last_thrsw_at_top_level = (c->execute.file == QFILE_NULL);
125 }
126
127 static uint32_t
128 v3d_general_tmu_op(nir_intrinsic_instr *instr)
129 {
130 switch (instr->intrinsic) {
131 case nir_intrinsic_load_ssbo:
132 case nir_intrinsic_load_ubo:
133 case nir_intrinsic_load_uniform:
134 case nir_intrinsic_load_shared:
135 return GENERAL_TMU_READ_OP_READ;
136 case nir_intrinsic_store_ssbo:
137 case nir_intrinsic_store_shared:
138 return GENERAL_TMU_WRITE_OP_WRITE;
139 case nir_intrinsic_ssbo_atomic_add:
140 case nir_intrinsic_shared_atomic_add:
141 return GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP;
142 case nir_intrinsic_ssbo_atomic_imin:
143 case nir_intrinsic_shared_atomic_imin:
144 return GENERAL_TMU_WRITE_OP_ATOMIC_SMIN;
145 case nir_intrinsic_ssbo_atomic_umin:
146 case nir_intrinsic_shared_atomic_umin:
147 return GENERAL_TMU_WRITE_OP_ATOMIC_UMIN;
148 case nir_intrinsic_ssbo_atomic_imax:
149 case nir_intrinsic_shared_atomic_imax:
150 return GENERAL_TMU_WRITE_OP_ATOMIC_SMAX;
151 case nir_intrinsic_ssbo_atomic_umax:
152 case nir_intrinsic_shared_atomic_umax:
153 return GENERAL_TMU_WRITE_OP_ATOMIC_UMAX;
154 case nir_intrinsic_ssbo_atomic_and:
155 case nir_intrinsic_shared_atomic_and:
156 return GENERAL_TMU_WRITE_OP_ATOMIC_AND;
157 case nir_intrinsic_ssbo_atomic_or:
158 case nir_intrinsic_shared_atomic_or:
159 return GENERAL_TMU_WRITE_OP_ATOMIC_OR;
160 case nir_intrinsic_ssbo_atomic_xor:
161 case nir_intrinsic_shared_atomic_xor:
162 return GENERAL_TMU_WRITE_OP_ATOMIC_XOR;
163 case nir_intrinsic_ssbo_atomic_exchange:
164 case nir_intrinsic_shared_atomic_exchange:
165 return GENERAL_TMU_WRITE_OP_ATOMIC_XCHG;
166 case nir_intrinsic_ssbo_atomic_comp_swap:
167 case nir_intrinsic_shared_atomic_comp_swap:
168 return GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG;
169 default:
170 unreachable("unknown intrinsic op");
171 }
172 }
173
174 /**
175 * Implements indirect uniform loads and SSBO accesses through the TMU general
176 * memory access interface.
177 */
178 static void
179 ntq_emit_tmu_general(struct v3d_compile *c, nir_intrinsic_instr *instr,
180 bool is_shared)
181 {
182 /* XXX perf: We should turn add/sub of 1 to inc/dec. Perhaps NIR
183 * wants to have support for inc/dec?
184 */
185
186 uint32_t tmu_op = v3d_general_tmu_op(instr);
187 bool is_store = (instr->intrinsic == nir_intrinsic_store_ssbo ||
188 instr->intrinsic == nir_intrinsic_store_shared);
189 bool has_index = !is_shared;
190
191 int offset_src;
192 int tmu_writes = 1; /* address */
193 if (instr->intrinsic == nir_intrinsic_load_uniform) {
194 offset_src = 0;
195 } else if (instr->intrinsic == nir_intrinsic_load_ssbo ||
196 instr->intrinsic == nir_intrinsic_load_ubo ||
197 instr->intrinsic == nir_intrinsic_load_shared) {
198 offset_src = 0 + has_index;
199 } else if (is_store) {
200 offset_src = 1 + has_index;
201 for (int i = 0; i < instr->num_components; i++) {
202 vir_MOV_dest(c,
203 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
204 ntq_get_src(c, instr->src[0], i));
205 tmu_writes++;
206 }
207 } else {
208 offset_src = 0 + has_index;
209 vir_MOV_dest(c,
210 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
211 ntq_get_src(c, instr->src[1 + has_index], 0));
212 tmu_writes++;
213 if (tmu_op == GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG) {
214 vir_MOV_dest(c,
215 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
216 ntq_get_src(c, instr->src[2 + has_index],
217 0));
218 tmu_writes++;
219 }
220 }
221
222 /* Make sure we won't exceed the 16-entry TMU fifo if each thread is
223 * storing at the same time.
224 */
225 while (tmu_writes > 16 / c->threads)
226 c->threads /= 2;
227
228 struct qreg offset;
229 if (instr->intrinsic == nir_intrinsic_load_uniform) {
230 offset = vir_uniform(c, QUNIFORM_UBO_ADDR, 0);
231
232 /* Find what variable in the default uniform block this
233 * uniform load is coming from.
234 */
235 uint32_t base = nir_intrinsic_base(instr);
236 int i;
237 struct v3d_ubo_range *range = NULL;
238 for (i = 0; i < c->num_ubo_ranges; i++) {
239 range = &c->ubo_ranges[i];
240 if (base >= range->src_offset &&
241 base < range->src_offset + range->size) {
242 break;
243 }
244 }
245 /* The driver-location-based offset always has to be within a
246 * declared uniform range.
247 */
248 assert(i != c->num_ubo_ranges);
249 if (!c->ubo_range_used[i]) {
250 c->ubo_range_used[i] = true;
251 range->dst_offset = c->next_ubo_dst_offset;
252 c->next_ubo_dst_offset += range->size;
253 }
254
255 base = base - range->src_offset + range->dst_offset;
256
257 if (base != 0)
258 offset = vir_ADD(c, offset, vir_uniform_ui(c, base));
259 } else if (instr->intrinsic == nir_intrinsic_load_ubo) {
260 /* Note that QUNIFORM_UBO_ADDR takes a UBO index shifted up by
261 * 1 (0 is gallium's constant buffer 0).
262 */
263 offset = vir_uniform(c, QUNIFORM_UBO_ADDR,
264 nir_src_as_uint(instr->src[0]) + 1);
265 } else if (is_shared) {
266 /* Shared variables have no buffer index, and all start from a
267 * common base that we set up at the start of dispatch
268 */
269 offset = c->cs_shared_offset;
270 } else {
271 offset = vir_uniform(c, QUNIFORM_SSBO_OFFSET,
272 nir_src_as_uint(instr->src[is_store ?
273 1 : 0]));
274 }
275
276 uint32_t config = (0xffffff00 |
277 tmu_op |
278 GENERAL_TMU_LOOKUP_PER_PIXEL);
279 if (instr->num_components == 1) {
280 config |= GENERAL_TMU_LOOKUP_TYPE_32BIT_UI;
281 } else {
282 config |= (GENERAL_TMU_LOOKUP_TYPE_VEC2 +
283 instr->num_components - 2);
284 }
285
286 if (c->execute.file != QFILE_NULL)
287 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
288
289 struct qreg dest;
290 if (config == ~0)
291 dest = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA);
292 else
293 dest = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUAU);
294
295 struct qinst *tmu;
296 if (nir_src_is_const(instr->src[offset_src]) &&
297 nir_src_as_uint(instr->src[offset_src]) == 0) {
298 tmu = vir_MOV_dest(c, dest, offset);
299 } else {
300 tmu = vir_ADD_dest(c, dest,
301 offset,
302 ntq_get_src(c, instr->src[offset_src], 0));
303 }
304
305 if (config != ~0) {
306 tmu->src[vir_get_implicit_uniform_src(tmu)] =
307 vir_uniform_ui(c, config);
308 }
309
310 if (c->execute.file != QFILE_NULL)
311 vir_set_cond(tmu, V3D_QPU_COND_IFA);
312
313 vir_emit_thrsw(c);
314
315 /* Read the result, or wait for the TMU op to complete. */
316 for (int i = 0; i < nir_intrinsic_dest_components(instr); i++)
317 ntq_store_dest(c, &instr->dest, i, vir_MOV(c, vir_LDTMU(c)));
318
319 if (nir_intrinsic_dest_components(instr) == 0)
320 vir_TMUWT(c);
321 }
322
323 static struct qreg *
324 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
325 {
326 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
327 def->num_components);
328 _mesa_hash_table_insert(c->def_ht, def, qregs);
329 return qregs;
330 }
331
332 /**
333 * This function is responsible for getting VIR results into the associated
334 * storage for a NIR instruction.
335 *
336 * If it's a NIR SSA def, then we just set the associated hash table entry to
337 * the new result.
338 *
339 * If it's a NIR reg, then we need to update the existing qreg assigned to the
340 * NIR destination with the incoming value. To do that without introducing
341 * new MOVs, we require that the incoming qreg either be a uniform, or be
342 * SSA-defined by the previous VIR instruction in the block and rewritable by
343 * this function. That lets us sneak ahead and insert the SF flag beforehand
344 * (knowing that the previous instruction doesn't depend on flags) and rewrite
345 * its destination to be the NIR reg's destination
346 */
347 void
348 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
349 struct qreg result)
350 {
351 struct qinst *last_inst = NULL;
352 if (!list_empty(&c->cur_block->instructions))
353 last_inst = (struct qinst *)c->cur_block->instructions.prev;
354
355 assert(result.file == QFILE_UNIF ||
356 (result.file == QFILE_TEMP &&
357 last_inst && last_inst == c->defs[result.index]));
358
359 if (dest->is_ssa) {
360 assert(chan < dest->ssa.num_components);
361
362 struct qreg *qregs;
363 struct hash_entry *entry =
364 _mesa_hash_table_search(c->def_ht, &dest->ssa);
365
366 if (entry)
367 qregs = entry->data;
368 else
369 qregs = ntq_init_ssa_def(c, &dest->ssa);
370
371 qregs[chan] = result;
372 } else {
373 nir_register *reg = dest->reg.reg;
374 assert(dest->reg.base_offset == 0);
375 assert(reg->num_array_elems == 0);
376 struct hash_entry *entry =
377 _mesa_hash_table_search(c->def_ht, reg);
378 struct qreg *qregs = entry->data;
379
380 /* Insert a MOV if the source wasn't an SSA def in the
381 * previous instruction.
382 */
383 if (result.file == QFILE_UNIF) {
384 result = vir_MOV(c, result);
385 last_inst = c->defs[result.index];
386 }
387
388 /* We know they're both temps, so just rewrite index. */
389 c->defs[last_inst->dst.index] = NULL;
390 last_inst->dst.index = qregs[chan].index;
391
392 /* If we're in control flow, then make this update of the reg
393 * conditional on the execution mask.
394 */
395 if (c->execute.file != QFILE_NULL) {
396 last_inst->dst.index = qregs[chan].index;
397
398 /* Set the flags to the current exec mask.
399 */
400 c->cursor = vir_before_inst(last_inst);
401 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
402 c->cursor = vir_after_inst(last_inst);
403
404 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
405 last_inst->cond_is_exec_mask = true;
406 }
407 }
408 }
409
410 struct qreg
411 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
412 {
413 struct hash_entry *entry;
414 if (src.is_ssa) {
415 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
416 assert(i < src.ssa->num_components);
417 } else {
418 nir_register *reg = src.reg.reg;
419 entry = _mesa_hash_table_search(c->def_ht, reg);
420 assert(reg->num_array_elems == 0);
421 assert(src.reg.base_offset == 0);
422 assert(i < reg->num_components);
423 }
424
425 struct qreg *qregs = entry->data;
426 return qregs[i];
427 }
428
429 static struct qreg
430 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
431 unsigned src)
432 {
433 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
434 unsigned chan = ffs(instr->dest.write_mask) - 1;
435 struct qreg r = ntq_get_src(c, instr->src[src].src,
436 instr->src[src].swizzle[chan]);
437
438 assert(!instr->src[src].abs);
439 assert(!instr->src[src].negate);
440
441 return r;
442 };
443
444 static struct qreg
445 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
446 {
447 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
448 }
449
450 static void
451 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
452 {
453 unsigned unit = instr->texture_index;
454 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
455 int dest_size = nir_tex_instr_dest_size(instr);
456
457 struct qreg lod = c->undef;
458 if (lod_index != -1)
459 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
460
461 for (int i = 0; i < dest_size; i++) {
462 assert(i < 3);
463 enum quniform_contents contents;
464
465 if (instr->is_array && i == dest_size - 1)
466 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
467 else
468 contents = QUNIFORM_TEXTURE_WIDTH + i;
469
470 struct qreg size = vir_uniform(c, contents, unit);
471
472 switch (instr->sampler_dim) {
473 case GLSL_SAMPLER_DIM_1D:
474 case GLSL_SAMPLER_DIM_2D:
475 case GLSL_SAMPLER_DIM_MS:
476 case GLSL_SAMPLER_DIM_3D:
477 case GLSL_SAMPLER_DIM_CUBE:
478 /* Don't minify the array size. */
479 if (!(instr->is_array && i == dest_size - 1)) {
480 size = ntq_minify(c, size, lod);
481 }
482 break;
483
484 case GLSL_SAMPLER_DIM_RECT:
485 /* There's no LOD field for rects */
486 break;
487
488 default:
489 unreachable("Bad sampler type");
490 }
491
492 ntq_store_dest(c, &instr->dest, i, size);
493 }
494 }
495
496 static void
497 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
498 {
499 unsigned unit = instr->texture_index;
500
501 /* Since each texture sampling op requires uploading uniforms to
502 * reference the texture, there's no HW support for texture size and
503 * you just upload uniforms containing the size.
504 */
505 switch (instr->op) {
506 case nir_texop_query_levels:
507 ntq_store_dest(c, &instr->dest, 0,
508 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
509 return;
510 case nir_texop_txs:
511 ntq_emit_txs(c, instr);
512 return;
513 default:
514 break;
515 }
516
517 if (c->devinfo->ver >= 40)
518 v3d40_vir_emit_tex(c, instr);
519 else
520 v3d33_vir_emit_tex(c, instr);
521 }
522
523 static struct qreg
524 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
525 {
526 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
527 if (is_cos)
528 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
529
530 struct qreg periods = vir_FROUND(c, input);
531 struct qreg sin_output = vir_SIN(c, vir_FSUB(c, input, periods));
532 return vir_XOR(c, sin_output, vir_SHL(c,
533 vir_FTOIN(c, periods),
534 vir_uniform_ui(c, -1)));
535 }
536
537 static struct qreg
538 ntq_fsign(struct v3d_compile *c, struct qreg src)
539 {
540 struct qreg t = vir_get_temp(c);
541
542 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
543 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHZ);
544 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
545 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHN);
546 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
547 return vir_MOV(c, t);
548 }
549
550 static void
551 emit_fragcoord_input(struct v3d_compile *c, int attr)
552 {
553 c->inputs[attr * 4 + 0] = vir_FXCD(c);
554 c->inputs[attr * 4 + 1] = vir_FYCD(c);
555 c->inputs[attr * 4 + 2] = c->payload_z;
556 c->inputs[attr * 4 + 3] = vir_RECIP(c, c->payload_w);
557 }
558
559 static struct qreg
560 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
561 uint8_t swizzle, int array_index)
562 {
563 struct qreg r3 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R3);
564 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
565
566 struct qreg vary;
567 if (c->devinfo->ver >= 41) {
568 struct qinst *ldvary = vir_add_inst(V3D_QPU_A_NOP, c->undef,
569 c->undef, c->undef);
570 ldvary->qpu.sig.ldvary = true;
571 vary = vir_emit_def(c, ldvary);
572 } else {
573 vir_NOP(c)->qpu.sig.ldvary = true;
574 vary = r3;
575 }
576
577 /* For gl_PointCoord input or distance along a line, we'll be called
578 * with no nir_variable, and we don't count toward VPM size so we
579 * don't track an input slot.
580 */
581 if (!var) {
582 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
583 }
584
585 int i = c->num_inputs++;
586 c->input_slots[i] =
587 v3d_slot_from_slot_and_component(var->data.location +
588 array_index, swizzle);
589
590 switch (var->data.interpolation) {
591 case INTERP_MODE_NONE:
592 /* If a gl_FrontColor or gl_BackColor input has no interp
593 * qualifier, then if we're using glShadeModel(GL_FLAT) it
594 * needs to be flat shaded.
595 */
596 switch (var->data.location + array_index) {
597 case VARYING_SLOT_COL0:
598 case VARYING_SLOT_COL1:
599 case VARYING_SLOT_BFC0:
600 case VARYING_SLOT_BFC1:
601 if (c->fs_key->shade_model_flat) {
602 BITSET_SET(c->flat_shade_flags, i);
603 vir_MOV_dest(c, c->undef, vary);
604 return vir_MOV(c, r5);
605 } else {
606 return vir_FADD(c, vir_FMUL(c, vary,
607 c->payload_w), r5);
608 }
609 default:
610 break;
611 }
612 /* FALLTHROUGH */
613 case INTERP_MODE_SMOOTH:
614 if (var->data.centroid) {
615 BITSET_SET(c->centroid_flags, i);
616 return vir_FADD(c, vir_FMUL(c, vary,
617 c->payload_w_centroid), r5);
618 } else {
619 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
620 }
621 case INTERP_MODE_NOPERSPECTIVE:
622 BITSET_SET(c->noperspective_flags, i);
623 return vir_FADD(c, vir_MOV(c, vary), r5);
624 case INTERP_MODE_FLAT:
625 BITSET_SET(c->flat_shade_flags, i);
626 vir_MOV_dest(c, c->undef, vary);
627 return vir_MOV(c, r5);
628 default:
629 unreachable("Bad interp mode");
630 }
631 }
632
633 static void
634 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var,
635 int array_index)
636 {
637 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
638 int chan = var->data.location_frac + i;
639 c->inputs[attr * 4 + chan] =
640 emit_fragment_varying(c, var, chan, array_index);
641 }
642 }
643
644 static void
645 add_output(struct v3d_compile *c,
646 uint32_t decl_offset,
647 uint8_t slot,
648 uint8_t swizzle)
649 {
650 uint32_t old_array_size = c->outputs_array_size;
651 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
652 decl_offset + 1);
653
654 if (old_array_size != c->outputs_array_size) {
655 c->output_slots = reralloc(c,
656 c->output_slots,
657 struct v3d_varying_slot,
658 c->outputs_array_size);
659 }
660
661 c->output_slots[decl_offset] =
662 v3d_slot_from_slot_and_component(slot, swizzle);
663 }
664
665 static void
666 declare_uniform_range(struct v3d_compile *c, uint32_t start, uint32_t size)
667 {
668 unsigned array_id = c->num_ubo_ranges++;
669 if (array_id >= c->ubo_ranges_array_size) {
670 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
671 array_id + 1);
672 c->ubo_ranges = reralloc(c, c->ubo_ranges,
673 struct v3d_ubo_range,
674 c->ubo_ranges_array_size);
675 c->ubo_range_used = reralloc(c, c->ubo_range_used,
676 bool,
677 c->ubo_ranges_array_size);
678 }
679
680 c->ubo_ranges[array_id].dst_offset = 0;
681 c->ubo_ranges[array_id].src_offset = start;
682 c->ubo_ranges[array_id].size = size;
683 c->ubo_range_used[array_id] = false;
684 }
685
686 /**
687 * If compare_instr is a valid comparison instruction, emits the
688 * compare_instr's comparison and returns the sel_instr's return value based
689 * on the compare_instr's result.
690 */
691 static bool
692 ntq_emit_comparison(struct v3d_compile *c,
693 nir_alu_instr *compare_instr,
694 enum v3d_qpu_cond *out_cond)
695 {
696 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
697 struct qreg src1;
698 if (nir_op_infos[compare_instr->op].num_inputs > 1)
699 src1 = ntq_get_alu_src(c, compare_instr, 1);
700 bool cond_invert = false;
701 struct qreg nop = vir_reg(QFILE_NULL, 0);
702
703 switch (compare_instr->op) {
704 case nir_op_feq32:
705 case nir_op_seq:
706 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
707 break;
708 case nir_op_ieq32:
709 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
710 break;
711
712 case nir_op_fne32:
713 case nir_op_sne:
714 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
715 cond_invert = true;
716 break;
717 case nir_op_ine32:
718 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
719 cond_invert = true;
720 break;
721
722 case nir_op_fge32:
723 case nir_op_sge:
724 vir_set_pf(vir_FCMP_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
725 break;
726 case nir_op_ige32:
727 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
728 cond_invert = true;
729 break;
730 case nir_op_uge32:
731 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
732 cond_invert = true;
733 break;
734
735 case nir_op_slt:
736 case nir_op_flt32:
737 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHN);
738 break;
739 case nir_op_ilt32:
740 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
741 break;
742 case nir_op_ult32:
743 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
744 break;
745
746 default:
747 return false;
748 }
749
750 *out_cond = cond_invert ? V3D_QPU_COND_IFNA : V3D_QPU_COND_IFA;
751
752 return true;
753 }
754
755 /* Finds an ALU instruction that generates our src value that could
756 * (potentially) be greedily emitted in the consuming instruction.
757 */
758 static struct nir_alu_instr *
759 ntq_get_alu_parent(nir_src src)
760 {
761 if (!src.is_ssa || src.ssa->parent_instr->type != nir_instr_type_alu)
762 return NULL;
763 nir_alu_instr *instr = nir_instr_as_alu(src.ssa->parent_instr);
764 if (!instr)
765 return NULL;
766
767 /* If the ALU instr's srcs are non-SSA, then we would have to avoid
768 * moving emission of the ALU instr down past another write of the
769 * src.
770 */
771 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
772 if (!instr->src[i].src.is_ssa)
773 return NULL;
774 }
775
776 return instr;
777 }
778
779 /**
780 * Attempts to fold a comparison generating a boolean result into the
781 * condition code for selecting between two values, instead of comparing the
782 * boolean result against 0 to generate the condition code.
783 */
784 static struct qreg ntq_emit_bcsel(struct v3d_compile *c, nir_alu_instr *instr,
785 struct qreg *src)
786 {
787 nir_alu_instr *compare = ntq_get_alu_parent(instr->src[0].src);
788 if (!compare)
789 goto out;
790
791 enum v3d_qpu_cond cond;
792 if (ntq_emit_comparison(c, compare, &cond))
793 return vir_MOV(c, vir_SEL(c, cond, src[1], src[2]));
794
795 out:
796 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
797 return vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA, src[1], src[2]));
798 }
799
800
801 static void
802 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
803 {
804 /* This should always be lowered to ALU operations for V3D. */
805 assert(!instr->dest.saturate);
806
807 /* Vectors are special in that they have non-scalarized writemasks,
808 * and just take the first swizzle channel for each argument in order
809 * into each writemask channel.
810 */
811 if (instr->op == nir_op_vec2 ||
812 instr->op == nir_op_vec3 ||
813 instr->op == nir_op_vec4) {
814 struct qreg srcs[4];
815 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
816 srcs[i] = ntq_get_src(c, instr->src[i].src,
817 instr->src[i].swizzle[0]);
818 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
819 ntq_store_dest(c, &instr->dest.dest, i,
820 vir_MOV(c, srcs[i]));
821 return;
822 }
823
824 /* General case: We can just grab the one used channel per src. */
825 struct qreg src[nir_op_infos[instr->op].num_inputs];
826 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
827 src[i] = ntq_get_alu_src(c, instr, i);
828 }
829
830 struct qreg result;
831
832 switch (instr->op) {
833 case nir_op_fmov:
834 case nir_op_imov:
835 result = vir_MOV(c, src[0]);
836 break;
837
838 case nir_op_fneg:
839 result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
840 break;
841 case nir_op_ineg:
842 result = vir_NEG(c, src[0]);
843 break;
844
845 case nir_op_fmul:
846 result = vir_FMUL(c, src[0], src[1]);
847 break;
848 case nir_op_fadd:
849 result = vir_FADD(c, src[0], src[1]);
850 break;
851 case nir_op_fsub:
852 result = vir_FSUB(c, src[0], src[1]);
853 break;
854 case nir_op_fmin:
855 result = vir_FMIN(c, src[0], src[1]);
856 break;
857 case nir_op_fmax:
858 result = vir_FMAX(c, src[0], src[1]);
859 break;
860
861 case nir_op_f2i32:
862 result = vir_FTOIZ(c, src[0]);
863 break;
864 case nir_op_f2u32:
865 result = vir_FTOUZ(c, src[0]);
866 break;
867 case nir_op_i2f32:
868 result = vir_ITOF(c, src[0]);
869 break;
870 case nir_op_u2f32:
871 result = vir_UTOF(c, src[0]);
872 break;
873 case nir_op_b2f32:
874 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
875 break;
876 case nir_op_b2i32:
877 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
878 break;
879 case nir_op_i2b32:
880 case nir_op_f2b32:
881 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
882 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
883 vir_uniform_ui(c, ~0),
884 vir_uniform_ui(c, 0)));
885 break;
886
887 case nir_op_iadd:
888 result = vir_ADD(c, src[0], src[1]);
889 break;
890 case nir_op_ushr:
891 result = vir_SHR(c, src[0], src[1]);
892 break;
893 case nir_op_isub:
894 result = vir_SUB(c, src[0], src[1]);
895 break;
896 case nir_op_ishr:
897 result = vir_ASR(c, src[0], src[1]);
898 break;
899 case nir_op_ishl:
900 result = vir_SHL(c, src[0], src[1]);
901 break;
902 case nir_op_imin:
903 result = vir_MIN(c, src[0], src[1]);
904 break;
905 case nir_op_umin:
906 result = vir_UMIN(c, src[0], src[1]);
907 break;
908 case nir_op_imax:
909 result = vir_MAX(c, src[0], src[1]);
910 break;
911 case nir_op_umax:
912 result = vir_UMAX(c, src[0], src[1]);
913 break;
914 case nir_op_iand:
915 result = vir_AND(c, src[0], src[1]);
916 break;
917 case nir_op_ior:
918 result = vir_OR(c, src[0], src[1]);
919 break;
920 case nir_op_ixor:
921 result = vir_XOR(c, src[0], src[1]);
922 break;
923 case nir_op_inot:
924 result = vir_NOT(c, src[0]);
925 break;
926
927 case nir_op_ufind_msb:
928 result = vir_SUB(c, vir_uniform_ui(c, 31), vir_CLZ(c, src[0]));
929 break;
930
931 case nir_op_imul:
932 result = vir_UMUL(c, src[0], src[1]);
933 break;
934
935 case nir_op_seq:
936 case nir_op_sne:
937 case nir_op_sge:
938 case nir_op_slt: {
939 enum v3d_qpu_cond cond;
940 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
941 assert(ok);
942 result = vir_MOV(c, vir_SEL(c, cond,
943 vir_uniform_f(c, 1.0),
944 vir_uniform_f(c, 0.0)));
945 break;
946 }
947
948 case nir_op_feq32:
949 case nir_op_fne32:
950 case nir_op_fge32:
951 case nir_op_flt32:
952 case nir_op_ieq32:
953 case nir_op_ine32:
954 case nir_op_ige32:
955 case nir_op_uge32:
956 case nir_op_ilt32:
957 case nir_op_ult32: {
958 enum v3d_qpu_cond cond;
959 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
960 assert(ok);
961 result = vir_MOV(c, vir_SEL(c, cond,
962 vir_uniform_ui(c, ~0),
963 vir_uniform_ui(c, 0)));
964 break;
965 }
966
967 case nir_op_b32csel:
968 result = ntq_emit_bcsel(c, instr, src);
969 break;
970 case nir_op_fcsel:
971 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
972 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
973 src[1], src[2]));
974 break;
975
976 case nir_op_frcp:
977 result = vir_RECIP(c, src[0]);
978 break;
979 case nir_op_frsq:
980 result = vir_RSQRT(c, src[0]);
981 break;
982 case nir_op_fexp2:
983 result = vir_EXP(c, src[0]);
984 break;
985 case nir_op_flog2:
986 result = vir_LOG(c, src[0]);
987 break;
988
989 case nir_op_fceil:
990 result = vir_FCEIL(c, src[0]);
991 break;
992 case nir_op_ffloor:
993 result = vir_FFLOOR(c, src[0]);
994 break;
995 case nir_op_fround_even:
996 result = vir_FROUND(c, src[0]);
997 break;
998 case nir_op_ftrunc:
999 result = vir_FTRUNC(c, src[0]);
1000 break;
1001 case nir_op_ffract:
1002 result = vir_FSUB(c, src[0], vir_FFLOOR(c, src[0]));
1003 break;
1004
1005 case nir_op_fsin:
1006 result = ntq_fsincos(c, src[0], false);
1007 break;
1008 case nir_op_fcos:
1009 result = ntq_fsincos(c, src[0], true);
1010 break;
1011
1012 case nir_op_fsign:
1013 result = ntq_fsign(c, src[0]);
1014 break;
1015
1016 case nir_op_fabs: {
1017 result = vir_FMOV(c, src[0]);
1018 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
1019 break;
1020 }
1021
1022 case nir_op_iabs:
1023 result = vir_MAX(c, src[0],
1024 vir_SUB(c, vir_uniform_ui(c, 0), src[0]));
1025 break;
1026
1027 case nir_op_fddx:
1028 case nir_op_fddx_coarse:
1029 case nir_op_fddx_fine:
1030 result = vir_FDX(c, src[0]);
1031 break;
1032
1033 case nir_op_fddy:
1034 case nir_op_fddy_coarse:
1035 case nir_op_fddy_fine:
1036 result = vir_FDY(c, src[0]);
1037 break;
1038
1039 case nir_op_uadd_carry:
1040 vir_PF(c, vir_ADD(c, src[0], src[1]), V3D_QPU_PF_PUSHC);
1041 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1042 vir_uniform_ui(c, ~0),
1043 vir_uniform_ui(c, 0)));
1044 break;
1045
1046 case nir_op_pack_half_2x16_split:
1047 result = vir_VFPACK(c, src[0], src[1]);
1048 break;
1049
1050 case nir_op_unpack_half_2x16_split_x:
1051 /* XXX perf: It would be good to be able to merge this unpack
1052 * with whatever uses our result.
1053 */
1054 result = vir_FMOV(c, src[0]);
1055 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_L);
1056 break;
1057
1058 case nir_op_unpack_half_2x16_split_y:
1059 result = vir_FMOV(c, src[0]);
1060 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_H);
1061 break;
1062
1063 default:
1064 fprintf(stderr, "unknown NIR ALU inst: ");
1065 nir_print_instr(&instr->instr, stderr);
1066 fprintf(stderr, "\n");
1067 abort();
1068 }
1069
1070 /* We have a scalar result, so the instruction should only have a
1071 * single channel written to.
1072 */
1073 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
1074 ntq_store_dest(c, &instr->dest.dest,
1075 ffs(instr->dest.write_mask) - 1, result);
1076 }
1077
1078 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
1079 * specifier. They come from a register that's preloaded with 0xffffffff
1080 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
1081 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
1082 */
1083 #define TLB_TYPE_F16_COLOR (3 << 6)
1084 #define TLB_TYPE_I32_COLOR (1 << 6)
1085 #define TLB_TYPE_F32_COLOR (0 << 6)
1086 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
1087 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
1088 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
1089 #define TLB_F16_SWAP_HI_LO (1 << 1)
1090 #define TLB_VEC_SIZE_4_F16 (1 << 0)
1091 #define TLB_VEC_SIZE_2_F16 (0 << 0)
1092 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
1093
1094 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
1095 * flag is set.
1096 */
1097 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
1098 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
1099 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
1100 #define TLB_V42_DEPTH_TYPE_INVARIANT (0 << 3) /* Unmodified sideband input used */
1101 #define TLB_V42_DEPTH_TYPE_PER_PIXEL (1 << 3) /* QPU result used */
1102
1103 /* Stencil is a single 32-bit write. */
1104 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1105
1106 static void
1107 emit_frag_end(struct v3d_compile *c)
1108 {
1109 /* XXX
1110 if (c->output_sample_mask_index != -1) {
1111 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1112 }
1113 */
1114
1115 bool has_any_tlb_color_write = false;
1116 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1117 if (c->fs_key->cbufs & (1 << rt) && c->output_color_var[rt])
1118 has_any_tlb_color_write = true;
1119 }
1120
1121 if (c->fs_key->sample_alpha_to_coverage && c->output_color_var[0]) {
1122 struct nir_variable *var = c->output_color_var[0];
1123 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1124
1125 vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1126 vir_AND(c,
1127 vir_MSF(c),
1128 vir_FTOC(c, color[3])));
1129 }
1130
1131 if (c->output_position_index != -1) {
1132 struct qinst *inst = vir_MOV_dest(c,
1133 vir_reg(QFILE_TLBU, 0),
1134 c->outputs[c->output_position_index]);
1135 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1136
1137 if (c->devinfo->ver >= 42) {
1138 tlb_specifier |= (TLB_V42_DEPTH_TYPE_PER_PIXEL |
1139 TLB_SAMPLE_MODE_PER_PIXEL);
1140 } else
1141 tlb_specifier |= TLB_DEPTH_TYPE_PER_PIXEL;
1142
1143 inst->src[vir_get_implicit_uniform_src(inst)] =
1144 vir_uniform_ui(c, tlb_specifier | 0xffffff00);
1145 } else if (c->s->info.fs.uses_discard ||
1146 c->fs_key->sample_alpha_to_coverage ||
1147 !has_any_tlb_color_write) {
1148 /* Emit passthrough Z if it needed to be delayed until shader
1149 * end due to potential discards.
1150 *
1151 * Since (single-threaded) fragment shaders always need a TLB
1152 * write, emit passthrouh Z if we didn't have any color
1153 * buffers and flag us as potentially discarding, so that we
1154 * can use Z as the TLB write.
1155 */
1156 c->s->info.fs.uses_discard = true;
1157
1158 struct qinst *inst = vir_MOV_dest(c,
1159 vir_reg(QFILE_TLBU, 0),
1160 vir_reg(QFILE_NULL, 0));
1161 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1162
1163 if (c->devinfo->ver >= 42) {
1164 /* The spec says the PER_PIXEL flag is ignored for
1165 * invariant writes, but the simulator demands it.
1166 */
1167 tlb_specifier |= (TLB_V42_DEPTH_TYPE_INVARIANT |
1168 TLB_SAMPLE_MODE_PER_PIXEL);
1169 } else {
1170 tlb_specifier |= TLB_DEPTH_TYPE_INVARIANT;
1171 }
1172
1173 inst->src[vir_get_implicit_uniform_src(inst)] =
1174 vir_uniform_ui(c, tlb_specifier | 0xffffff00);
1175 }
1176
1177 /* XXX: Performance improvement: Merge Z write and color writes TLB
1178 * uniform setup
1179 */
1180
1181 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1182 if (!(c->fs_key->cbufs & (1 << rt)) || !c->output_color_var[rt])
1183 continue;
1184
1185 nir_variable *var = c->output_color_var[rt];
1186 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1187 int num_components = glsl_get_vector_elements(var->type);
1188 uint32_t conf = 0xffffff00;
1189 struct qinst *inst;
1190
1191 conf |= TLB_SAMPLE_MODE_PER_PIXEL;
1192 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1193
1194 if (c->fs_key->swap_color_rb & (1 << rt))
1195 num_components = MAX2(num_components, 3);
1196
1197 assert(num_components != 0);
1198 switch (glsl_get_base_type(var->type)) {
1199 case GLSL_TYPE_UINT:
1200 case GLSL_TYPE_INT:
1201 /* The F32 vs I32 distinction was dropped in 4.2. */
1202 if (c->devinfo->ver < 42)
1203 conf |= TLB_TYPE_I32_COLOR;
1204 else
1205 conf |= TLB_TYPE_F32_COLOR;
1206 conf |= ((num_components - 1) <<
1207 TLB_VEC_SIZE_MINUS_1_SHIFT);
1208
1209 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
1210 inst->src[vir_get_implicit_uniform_src(inst)] =
1211 vir_uniform_ui(c, conf);
1212
1213 for (int i = 1; i < num_components; i++) {
1214 inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
1215 color[i]);
1216 }
1217 break;
1218
1219 default: {
1220 struct qreg r = color[0];
1221 struct qreg g = color[1];
1222 struct qreg b = color[2];
1223 struct qreg a = color[3];
1224
1225 if (c->fs_key->f32_color_rb & (1 << rt)) {
1226 conf |= TLB_TYPE_F32_COLOR;
1227 conf |= ((num_components - 1) <<
1228 TLB_VEC_SIZE_MINUS_1_SHIFT);
1229 } else {
1230 conf |= TLB_TYPE_F16_COLOR;
1231 conf |= TLB_F16_SWAP_HI_LO;
1232 if (num_components >= 3)
1233 conf |= TLB_VEC_SIZE_4_F16;
1234 else
1235 conf |= TLB_VEC_SIZE_2_F16;
1236 }
1237
1238 if (c->fs_key->swap_color_rb & (1 << rt)) {
1239 r = color[2];
1240 b = color[0];
1241 }
1242
1243 if (c->fs_key->sample_alpha_to_one)
1244 a = vir_uniform_f(c, 1.0);
1245
1246 if (c->fs_key->f32_color_rb & (1 << rt)) {
1247 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), r);
1248 inst->src[vir_get_implicit_uniform_src(inst)] =
1249 vir_uniform_ui(c, conf);
1250
1251 if (num_components >= 2)
1252 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), g);
1253 if (num_components >= 3)
1254 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), b);
1255 if (num_components >= 4)
1256 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), a);
1257 } else {
1258 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), r, g);
1259 if (conf != ~0) {
1260 inst->dst.file = QFILE_TLBU;
1261 inst->src[vir_get_implicit_uniform_src(inst)] =
1262 vir_uniform_ui(c, conf);
1263 }
1264
1265 if (num_components >= 3)
1266 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), b, a);
1267 }
1268 break;
1269 }
1270 }
1271 }
1272 }
1273
1274 static void
1275 vir_VPM_WRITE(struct v3d_compile *c, struct qreg val, uint32_t *vpm_index)
1276 {
1277 if (c->devinfo->ver >= 40) {
1278 vir_STVPMV(c, vir_uniform_ui(c, *vpm_index), val);
1279 *vpm_index = *vpm_index + 1;
1280 } else {
1281 vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM), val);
1282 }
1283
1284 c->num_vpm_writes++;
1285 }
1286
1287 static void
1288 emit_scaled_viewport_write(struct v3d_compile *c, struct qreg rcp_w,
1289 uint32_t *vpm_index)
1290 {
1291 for (int i = 0; i < 2; i++) {
1292 struct qreg coord = c->outputs[c->output_position_index + i];
1293 coord = vir_FMUL(c, coord,
1294 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i,
1295 0));
1296 coord = vir_FMUL(c, coord, rcp_w);
1297 vir_VPM_WRITE(c, vir_FTOIN(c, coord), vpm_index);
1298 }
1299
1300 }
1301
1302 static void
1303 emit_zs_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index)
1304 {
1305 struct qreg zscale = vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1306 struct qreg zoffset = vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1307
1308 struct qreg z = c->outputs[c->output_position_index + 2];
1309 z = vir_FMUL(c, z, zscale);
1310 z = vir_FMUL(c, z, rcp_w);
1311 z = vir_FADD(c, z, zoffset);
1312 vir_VPM_WRITE(c, z, vpm_index);
1313 }
1314
1315 static void
1316 emit_rcp_wc_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index)
1317 {
1318 vir_VPM_WRITE(c, rcp_w, vpm_index);
1319 }
1320
1321 static void
1322 emit_point_size_write(struct v3d_compile *c, uint32_t *vpm_index)
1323 {
1324 struct qreg point_size;
1325
1326 if (c->output_point_size_index != -1)
1327 point_size = c->outputs[c->output_point_size_index];
1328 else
1329 point_size = vir_uniform_f(c, 1.0);
1330
1331 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1332 * BCM21553).
1333 */
1334 point_size = vir_FMAX(c, point_size, vir_uniform_f(c, .125));
1335
1336 vir_VPM_WRITE(c, point_size, vpm_index);
1337 }
1338
1339 static void
1340 emit_vpm_write_setup(struct v3d_compile *c)
1341 {
1342 if (c->devinfo->ver >= 40)
1343 return;
1344
1345 v3d33_vir_vpm_write_setup(c);
1346 }
1347
1348 /**
1349 * Sets up c->outputs[c->output_position_index] for the vertex shader
1350 * epilogue, if an output vertex position wasn't specified in the user's
1351 * shader. This may be the case for transform feedback with rasterizer
1352 * discard enabled.
1353 */
1354 static void
1355 setup_default_position(struct v3d_compile *c)
1356 {
1357 if (c->output_position_index != -1)
1358 return;
1359
1360 c->output_position_index = c->outputs_array_size;
1361 for (int i = 0; i < 4; i++) {
1362 add_output(c,
1363 c->output_position_index + i,
1364 VARYING_SLOT_POS, i);
1365 }
1366 }
1367
1368 static void
1369 emit_vert_end(struct v3d_compile *c)
1370 {
1371 setup_default_position(c);
1372
1373 uint32_t vpm_index = 0;
1374 struct qreg rcp_w = vir_RECIP(c,
1375 c->outputs[c->output_position_index + 3]);
1376
1377 emit_vpm_write_setup(c);
1378
1379 if (c->vs_key->is_coord) {
1380 for (int i = 0; i < 4; i++)
1381 vir_VPM_WRITE(c, c->outputs[c->output_position_index + i],
1382 &vpm_index);
1383 emit_scaled_viewport_write(c, rcp_w, &vpm_index);
1384 if (c->vs_key->per_vertex_point_size) {
1385 emit_point_size_write(c, &vpm_index);
1386 /* emit_rcp_wc_write(c, rcp_w); */
1387 }
1388 /* XXX: Z-only rendering */
1389 if (0)
1390 emit_zs_write(c, rcp_w, &vpm_index);
1391 } else {
1392 emit_scaled_viewport_write(c, rcp_w, &vpm_index);
1393 emit_zs_write(c, rcp_w, &vpm_index);
1394 emit_rcp_wc_write(c, rcp_w, &vpm_index);
1395 if (c->vs_key->per_vertex_point_size)
1396 emit_point_size_write(c, &vpm_index);
1397 }
1398
1399 for (int i = 0; i < c->vs_key->num_fs_inputs; i++) {
1400 struct v3d_varying_slot input = c->vs_key->fs_inputs[i];
1401 int j;
1402
1403 for (j = 0; j < c->num_outputs; j++) {
1404 struct v3d_varying_slot output = c->output_slots[j];
1405
1406 if (!memcmp(&input, &output, sizeof(input))) {
1407 vir_VPM_WRITE(c, c->outputs[j],
1408 &vpm_index);
1409 break;
1410 }
1411 }
1412 /* Emit padding if we didn't find a declared VS output for
1413 * this FS input.
1414 */
1415 if (j == c->num_outputs)
1416 vir_VPM_WRITE(c, vir_uniform_f(c, 0.0),
1417 &vpm_index);
1418 }
1419
1420 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1421 */
1422 if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
1423 vir_VPMWT(c);
1424 }
1425
1426 void
1427 v3d_optimize_nir(struct nir_shader *s)
1428 {
1429 bool progress;
1430
1431 do {
1432 progress = false;
1433
1434 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1435 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1436 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1437 NIR_PASS(progress, s, nir_copy_prop);
1438 NIR_PASS(progress, s, nir_opt_remove_phis);
1439 NIR_PASS(progress, s, nir_opt_dce);
1440 NIR_PASS(progress, s, nir_opt_dead_cf);
1441 NIR_PASS(progress, s, nir_opt_cse);
1442 NIR_PASS(progress, s, nir_opt_peephole_select, 8, true, true);
1443 NIR_PASS(progress, s, nir_opt_algebraic);
1444 NIR_PASS(progress, s, nir_opt_constant_folding);
1445 NIR_PASS(progress, s, nir_opt_undef);
1446 } while (progress);
1447
1448 NIR_PASS(progress, s, nir_opt_move_load_ubo);
1449 }
1450
1451 static int
1452 driver_location_compare(const void *in_a, const void *in_b)
1453 {
1454 const nir_variable *const *a = in_a;
1455 const nir_variable *const *b = in_b;
1456
1457 return (*a)->data.driver_location - (*b)->data.driver_location;
1458 }
1459
1460 static struct qreg
1461 ntq_emit_vpm_read(struct v3d_compile *c,
1462 uint32_t *num_components_queued,
1463 uint32_t *remaining,
1464 uint32_t vpm_index)
1465 {
1466 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1467
1468 if (c->devinfo->ver >= 40 ) {
1469 return vir_LDVPMV_IN(c,
1470 vir_uniform_ui(c,
1471 (*num_components_queued)++));
1472 }
1473
1474 if (*num_components_queued != 0) {
1475 (*num_components_queued)--;
1476 c->num_inputs++;
1477 return vir_MOV(c, vpm);
1478 }
1479
1480 uint32_t num_components = MIN2(*remaining, 32);
1481
1482 v3d33_vir_vpm_read_setup(c, num_components);
1483
1484 *num_components_queued = num_components - 1;
1485 *remaining -= num_components;
1486 c->num_inputs++;
1487
1488 return vir_MOV(c, vpm);
1489 }
1490
1491 static void
1492 ntq_setup_vpm_inputs(struct v3d_compile *c)
1493 {
1494 /* Figure out how many components of each vertex attribute the shader
1495 * uses. Each variable should have been split to individual
1496 * components and unused ones DCEed. The vertex fetcher will load
1497 * from the start of the attribute to the number of components we
1498 * declare we need in c->vattr_sizes[].
1499 */
1500 nir_foreach_variable(var, &c->s->inputs) {
1501 /* No VS attribute array support. */
1502 assert(MAX2(glsl_get_length(var->type), 1) == 1);
1503
1504 unsigned loc = var->data.driver_location;
1505 int start_component = var->data.location_frac;
1506 int num_components = glsl_get_components(var->type);
1507
1508 c->vattr_sizes[loc] = MAX2(c->vattr_sizes[loc],
1509 start_component + num_components);
1510 }
1511
1512 unsigned num_components = 0;
1513 uint32_t vpm_components_queued = 0;
1514 bool uses_iid = c->s->info.system_values_read &
1515 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1516 bool uses_vid = c->s->info.system_values_read &
1517 (1ull << SYSTEM_VALUE_VERTEX_ID);
1518 num_components += uses_iid;
1519 num_components += uses_vid;
1520
1521 for (int i = 0; i < ARRAY_SIZE(c->vattr_sizes); i++)
1522 num_components += c->vattr_sizes[i];
1523
1524 if (uses_iid) {
1525 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1526 &num_components, ~0);
1527 }
1528
1529 if (uses_vid) {
1530 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1531 &num_components, ~0);
1532 }
1533
1534 for (int loc = 0; loc < ARRAY_SIZE(c->vattr_sizes); loc++) {
1535 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1536 (loc + 1) * 4);
1537
1538 for (int i = 0; i < c->vattr_sizes[loc]; i++) {
1539 c->inputs[loc * 4 + i] =
1540 ntq_emit_vpm_read(c,
1541 &vpm_components_queued,
1542 &num_components,
1543 loc * 4 + i);
1544
1545 }
1546 }
1547
1548 if (c->devinfo->ver >= 40) {
1549 assert(vpm_components_queued == num_components);
1550 } else {
1551 assert(vpm_components_queued == 0);
1552 assert(num_components == 0);
1553 }
1554 }
1555
1556 static void
1557 ntq_setup_fs_inputs(struct v3d_compile *c)
1558 {
1559 unsigned num_entries = 0;
1560 unsigned num_components = 0;
1561 nir_foreach_variable(var, &c->s->inputs) {
1562 num_entries++;
1563 num_components += glsl_get_components(var->type);
1564 }
1565
1566 nir_variable *vars[num_entries];
1567
1568 unsigned i = 0;
1569 nir_foreach_variable(var, &c->s->inputs)
1570 vars[i++] = var;
1571
1572 /* Sort the variables so that we emit the input setup in
1573 * driver_location order. This is required for VPM reads, whose data
1574 * is fetched into the VPM in driver_location (TGSI register index)
1575 * order.
1576 */
1577 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1578
1579 for (unsigned i = 0; i < num_entries; i++) {
1580 nir_variable *var = vars[i];
1581 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1582 unsigned loc = var->data.driver_location;
1583
1584 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1585 (loc + array_len) * 4);
1586
1587 if (var->data.location == VARYING_SLOT_POS) {
1588 emit_fragcoord_input(c, loc);
1589 } else if (var->data.location == VARYING_SLOT_PNTC ||
1590 (var->data.location >= VARYING_SLOT_VAR0 &&
1591 (c->fs_key->point_sprite_mask &
1592 (1 << (var->data.location -
1593 VARYING_SLOT_VAR0))))) {
1594 c->inputs[loc * 4 + 0] = c->point_x;
1595 c->inputs[loc * 4 + 1] = c->point_y;
1596 } else {
1597 for (int j = 0; j < array_len; j++)
1598 emit_fragment_input(c, loc + j, var, j);
1599 }
1600 }
1601 }
1602
1603 static void
1604 ntq_setup_outputs(struct v3d_compile *c)
1605 {
1606 nir_foreach_variable(var, &c->s->outputs) {
1607 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1608 unsigned loc = var->data.driver_location * 4;
1609
1610 assert(array_len == 1);
1611 (void)array_len;
1612
1613 for (int i = 0; i < 4 - var->data.location_frac; i++) {
1614 add_output(c, loc + var->data.location_frac + i,
1615 var->data.location,
1616 var->data.location_frac + i);
1617 }
1618
1619 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1620 switch (var->data.location) {
1621 case FRAG_RESULT_COLOR:
1622 c->output_color_var[0] = var;
1623 c->output_color_var[1] = var;
1624 c->output_color_var[2] = var;
1625 c->output_color_var[3] = var;
1626 break;
1627 case FRAG_RESULT_DATA0:
1628 case FRAG_RESULT_DATA1:
1629 case FRAG_RESULT_DATA2:
1630 case FRAG_RESULT_DATA3:
1631 c->output_color_var[var->data.location -
1632 FRAG_RESULT_DATA0] = var;
1633 break;
1634 case FRAG_RESULT_DEPTH:
1635 c->output_position_index = loc;
1636 break;
1637 case FRAG_RESULT_SAMPLE_MASK:
1638 c->output_sample_mask_index = loc;
1639 break;
1640 }
1641 } else {
1642 switch (var->data.location) {
1643 case VARYING_SLOT_POS:
1644 c->output_position_index = loc;
1645 break;
1646 case VARYING_SLOT_PSIZ:
1647 c->output_point_size_index = loc;
1648 break;
1649 }
1650 }
1651 }
1652 }
1653
1654 static void
1655 ntq_setup_uniforms(struct v3d_compile *c)
1656 {
1657 nir_foreach_variable(var, &c->s->uniforms) {
1658 uint32_t vec4_count = glsl_count_attribute_slots(var->type,
1659 false);
1660 unsigned vec4_size = 4 * sizeof(float);
1661
1662 if (var->data.mode != nir_var_uniform)
1663 continue;
1664
1665 declare_uniform_range(c, var->data.driver_location * vec4_size,
1666 vec4_count * vec4_size);
1667
1668 }
1669 }
1670
1671 /**
1672 * Sets up the mapping from nir_register to struct qreg *.
1673 *
1674 * Each nir_register gets a struct qreg per 32-bit component being stored.
1675 */
1676 static void
1677 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1678 {
1679 foreach_list_typed(nir_register, nir_reg, node, list) {
1680 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1681 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1682 array_len *
1683 nir_reg->num_components);
1684
1685 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1686
1687 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1688 qregs[i] = vir_get_temp(c);
1689 }
1690 }
1691
1692 static void
1693 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1694 {
1695 /* XXX perf: Experiment with using immediate loads to avoid having
1696 * these end up in the uniform stream. Watch out for breaking the
1697 * small immediates optimization in the process!
1698 */
1699 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1700 for (int i = 0; i < instr->def.num_components; i++)
1701 qregs[i] = vir_uniform_ui(c, instr->value.u32[i]);
1702
1703 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1704 }
1705
1706 static void
1707 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1708 {
1709 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1710
1711 /* VIR needs there to be *some* value, so pick 0 (same as for
1712 * ntq_setup_registers().
1713 */
1714 for (int i = 0; i < instr->def.num_components; i++)
1715 qregs[i] = vir_uniform_ui(c, 0);
1716 }
1717
1718 static void
1719 ntq_emit_image_size(struct v3d_compile *c, nir_intrinsic_instr *instr)
1720 {
1721 assert(instr->intrinsic == nir_intrinsic_image_deref_size);
1722 nir_variable *var = nir_intrinsic_get_var(instr, 0);
1723 unsigned image_index = var->data.driver_location;
1724 const struct glsl_type *sampler_type = glsl_without_array(var->type);
1725 bool is_array = glsl_sampler_type_is_array(sampler_type);
1726
1727 ntq_store_dest(c, &instr->dest, 0,
1728 vir_uniform(c, QUNIFORM_IMAGE_WIDTH, image_index));
1729 if (instr->num_components > 1) {
1730 ntq_store_dest(c, &instr->dest, 1,
1731 vir_uniform(c, QUNIFORM_IMAGE_HEIGHT,
1732 image_index));
1733 }
1734 if (instr->num_components > 2) {
1735 ntq_store_dest(c, &instr->dest, 2,
1736 vir_uniform(c,
1737 is_array ?
1738 QUNIFORM_IMAGE_ARRAY_SIZE :
1739 QUNIFORM_IMAGE_DEPTH,
1740 image_index));
1741 }
1742 }
1743
1744 static void
1745 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
1746 {
1747 unsigned offset;
1748
1749 switch (instr->intrinsic) {
1750 case nir_intrinsic_load_uniform:
1751 if (nir_src_is_const(instr->src[0])) {
1752 int offset = (nir_intrinsic_base(instr) +
1753 nir_src_as_uint(instr->src[0]));
1754 assert(offset % 4 == 0);
1755 /* We need dwords */
1756 offset = offset / 4;
1757 for (int i = 0; i < instr->num_components; i++) {
1758 ntq_store_dest(c, &instr->dest, i,
1759 vir_uniform(c, QUNIFORM_UNIFORM,
1760 offset + i));
1761 }
1762 } else {
1763 ntq_emit_tmu_general(c, instr, false);
1764 }
1765 break;
1766
1767 case nir_intrinsic_load_ubo:
1768 ntq_emit_tmu_general(c, instr, false);
1769 break;
1770
1771 case nir_intrinsic_ssbo_atomic_add:
1772 case nir_intrinsic_ssbo_atomic_imin:
1773 case nir_intrinsic_ssbo_atomic_umin:
1774 case nir_intrinsic_ssbo_atomic_imax:
1775 case nir_intrinsic_ssbo_atomic_umax:
1776 case nir_intrinsic_ssbo_atomic_and:
1777 case nir_intrinsic_ssbo_atomic_or:
1778 case nir_intrinsic_ssbo_atomic_xor:
1779 case nir_intrinsic_ssbo_atomic_exchange:
1780 case nir_intrinsic_ssbo_atomic_comp_swap:
1781 case nir_intrinsic_load_ssbo:
1782 case nir_intrinsic_store_ssbo:
1783 ntq_emit_tmu_general(c, instr, false);
1784 break;
1785
1786 case nir_intrinsic_shared_atomic_add:
1787 case nir_intrinsic_shared_atomic_imin:
1788 case nir_intrinsic_shared_atomic_umin:
1789 case nir_intrinsic_shared_atomic_imax:
1790 case nir_intrinsic_shared_atomic_umax:
1791 case nir_intrinsic_shared_atomic_and:
1792 case nir_intrinsic_shared_atomic_or:
1793 case nir_intrinsic_shared_atomic_xor:
1794 case nir_intrinsic_shared_atomic_exchange:
1795 case nir_intrinsic_shared_atomic_comp_swap:
1796 case nir_intrinsic_load_shared:
1797 case nir_intrinsic_store_shared:
1798 ntq_emit_tmu_general(c, instr, true);
1799 break;
1800
1801 case nir_intrinsic_image_deref_load:
1802 case nir_intrinsic_image_deref_store:
1803 case nir_intrinsic_image_deref_atomic_add:
1804 case nir_intrinsic_image_deref_atomic_min:
1805 case nir_intrinsic_image_deref_atomic_max:
1806 case nir_intrinsic_image_deref_atomic_and:
1807 case nir_intrinsic_image_deref_atomic_or:
1808 case nir_intrinsic_image_deref_atomic_xor:
1809 case nir_intrinsic_image_deref_atomic_exchange:
1810 case nir_intrinsic_image_deref_atomic_comp_swap:
1811 v3d40_vir_emit_image_load_store(c, instr);
1812 break;
1813
1814 case nir_intrinsic_get_buffer_size:
1815 ntq_store_dest(c, &instr->dest, 0,
1816 vir_uniform(c, QUNIFORM_GET_BUFFER_SIZE,
1817 nir_src_as_uint(instr->src[0])));
1818 break;
1819
1820 case nir_intrinsic_load_user_clip_plane:
1821 for (int i = 0; i < instr->num_components; i++) {
1822 ntq_store_dest(c, &instr->dest, i,
1823 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1824 nir_intrinsic_ucp_id(instr) *
1825 4 + i));
1826 }
1827 break;
1828
1829 case nir_intrinsic_load_alpha_ref_float:
1830 ntq_store_dest(c, &instr->dest, 0,
1831 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1832 break;
1833
1834 case nir_intrinsic_load_sample_mask_in:
1835 ntq_store_dest(c, &instr->dest, 0, vir_MSF(c));
1836 break;
1837
1838 case nir_intrinsic_load_helper_invocation:
1839 vir_PF(c, vir_MSF(c), V3D_QPU_PF_PUSHZ);
1840 ntq_store_dest(c, &instr->dest, 0,
1841 vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1842 vir_uniform_ui(c, ~0),
1843 vir_uniform_ui(c, 0))));
1844 break;
1845
1846 case nir_intrinsic_load_front_face:
1847 /* The register contains 0 (front) or 1 (back), and we need to
1848 * turn it into a NIR bool where true means front.
1849 */
1850 ntq_store_dest(c, &instr->dest, 0,
1851 vir_ADD(c,
1852 vir_uniform_ui(c, -1),
1853 vir_REVF(c)));
1854 break;
1855
1856 case nir_intrinsic_load_instance_id:
1857 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
1858 break;
1859
1860 case nir_intrinsic_load_vertex_id:
1861 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
1862 break;
1863
1864 case nir_intrinsic_load_input:
1865 for (int i = 0; i < instr->num_components; i++) {
1866 offset = (nir_intrinsic_base(instr) +
1867 nir_src_as_uint(instr->src[0]));
1868 int comp = nir_intrinsic_component(instr) + i;
1869 ntq_store_dest(c, &instr->dest, i,
1870 vir_MOV(c, c->inputs[offset * 4 + comp]));
1871 }
1872 break;
1873
1874 case nir_intrinsic_store_output:
1875 offset = ((nir_intrinsic_base(instr) +
1876 nir_src_as_uint(instr->src[1])) * 4 +
1877 nir_intrinsic_component(instr));
1878
1879 for (int i = 0; i < instr->num_components; i++) {
1880 c->outputs[offset + i] =
1881 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
1882 }
1883 c->num_outputs = MAX2(c->num_outputs,
1884 offset + instr->num_components);
1885 break;
1886
1887 case nir_intrinsic_image_deref_size:
1888 ntq_emit_image_size(c, instr);
1889 break;
1890
1891 case nir_intrinsic_discard:
1892 if (c->execute.file != QFILE_NULL) {
1893 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1894 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1895 vir_uniform_ui(c, 0)),
1896 V3D_QPU_COND_IFA);
1897 } else {
1898 vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1899 vir_uniform_ui(c, 0));
1900 }
1901 break;
1902
1903 case nir_intrinsic_discard_if: {
1904 /* true (~0) if we're discarding */
1905 struct qreg cond = ntq_get_src(c, instr->src[0], 0);
1906
1907 if (c->execute.file != QFILE_NULL) {
1908 /* execute == 0 means the channel is active. Invert
1909 * the condition so that we can use zero as "executing
1910 * and discarding."
1911 */
1912 vir_PF(c, vir_OR(c, c->execute, vir_NOT(c, cond)),
1913 V3D_QPU_PF_PUSHZ);
1914 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1915 vir_uniform_ui(c, 0)),
1916 V3D_QPU_COND_IFA);
1917 } else {
1918 vir_PF(c, cond, V3D_QPU_PF_PUSHZ);
1919 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1920 vir_uniform_ui(c, 0)),
1921 V3D_QPU_COND_IFNA);
1922 }
1923
1924 break;
1925 }
1926
1927 case nir_intrinsic_memory_barrier:
1928 case nir_intrinsic_memory_barrier_atomic_counter:
1929 case nir_intrinsic_memory_barrier_buffer:
1930 case nir_intrinsic_memory_barrier_image:
1931 case nir_intrinsic_memory_barrier_shared:
1932 /* We don't do any instruction scheduling of these NIR
1933 * instructions between each other, so we just need to make
1934 * sure that the TMU operations before the barrier are flushed
1935 * before the ones after the barrier. That is currently
1936 * handled by having a THRSW in each of them and a LDTMU
1937 * series or a TMUWT after.
1938 */
1939 break;
1940
1941 case nir_intrinsic_barrier:
1942 /* Emit a TSY op to get all invocations in the workgroup
1943 * (actually supergroup) to block until the last invocation
1944 * reaches the TSY op.
1945 */
1946 if (c->devinfo->ver >= 42) {
1947 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
1948 V3D_QPU_WADDR_SYNCB));
1949 } else {
1950 struct qinst *sync =
1951 vir_BARRIERID_dest(c,
1952 vir_reg(QFILE_MAGIC,
1953 V3D_QPU_WADDR_SYNCU));
1954 sync->src[vir_get_implicit_uniform_src(sync)] =
1955 vir_uniform_ui(c,
1956 0xffffff00 |
1957 V3D_TSY_WAIT_INC_CHECK);
1958
1959 }
1960
1961 /* The blocking of a TSY op only happens at the next thread
1962 * switch. No texturing may be outstanding at the time of a
1963 * TSY blocking operation.
1964 */
1965 vir_emit_thrsw(c);
1966 break;
1967
1968 case nir_intrinsic_load_num_work_groups:
1969 for (int i = 0; i < 3; i++) {
1970 ntq_store_dest(c, &instr->dest, i,
1971 vir_uniform(c, QUNIFORM_NUM_WORK_GROUPS,
1972 i));
1973 }
1974 break;
1975
1976 case nir_intrinsic_load_local_invocation_index:
1977 ntq_store_dest(c, &instr->dest, 0,
1978 vir_SHR(c, c->cs_payload[1],
1979 vir_uniform_ui(c, 32 - c->local_invocation_index_bits)));
1980 break;
1981
1982 case nir_intrinsic_load_work_group_id:
1983 ntq_store_dest(c, &instr->dest, 0,
1984 vir_AND(c, c->cs_payload[0],
1985 vir_uniform_ui(c, 0xffff)));
1986 ntq_store_dest(c, &instr->dest, 1,
1987 vir_SHR(c, c->cs_payload[0],
1988 vir_uniform_ui(c, 16)));
1989 ntq_store_dest(c, &instr->dest, 2,
1990 vir_AND(c, c->cs_payload[1],
1991 vir_uniform_ui(c, 0xffff)));
1992 break;
1993
1994 default:
1995 fprintf(stderr, "Unknown intrinsic: ");
1996 nir_print_instr(&instr->instr, stderr);
1997 fprintf(stderr, "\n");
1998 break;
1999 }
2000 }
2001
2002 /* Clears (activates) the execute flags for any channels whose jump target
2003 * matches this block.
2004 *
2005 * XXX perf: Could we be using flpush/flpop somehow for our execution channel
2006 * enabling?
2007 *
2008 * XXX perf: For uniform control flow, we should be able to skip c->execute
2009 * handling entirely.
2010 */
2011 static void
2012 ntq_activate_execute_for_block(struct v3d_compile *c)
2013 {
2014 vir_set_pf(vir_XOR_dest(c, vir_reg(QFILE_NULL, 0),
2015 c->execute, vir_uniform_ui(c, c->cur_block->index)),
2016 V3D_QPU_PF_PUSHZ);
2017
2018 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2019 }
2020
2021 static void
2022 ntq_emit_uniform_if(struct v3d_compile *c, nir_if *if_stmt)
2023 {
2024 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2025 bool empty_else_block =
2026 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2027 exec_list_is_empty(&nir_else_block->instr_list));
2028
2029 struct qblock *then_block = vir_new_block(c);
2030 struct qblock *after_block = vir_new_block(c);
2031 struct qblock *else_block;
2032 if (empty_else_block)
2033 else_block = after_block;
2034 else
2035 else_block = vir_new_block(c);
2036
2037 /* Set up the flags for the IF condition (taking the THEN branch). */
2038 nir_alu_instr *if_condition_alu = ntq_get_alu_parent(if_stmt->condition);
2039 enum v3d_qpu_cond cond;
2040 if (!if_condition_alu ||
2041 !ntq_emit_comparison(c, if_condition_alu, &cond)) {
2042 vir_PF(c, ntq_get_src(c, if_stmt->condition, 0),
2043 V3D_QPU_PF_PUSHZ);
2044 cond = V3D_QPU_COND_IFNA;
2045 }
2046
2047 /* Jump to ELSE. */
2048 vir_BRANCH(c, cond == V3D_QPU_COND_IFA ?
2049 V3D_QPU_BRANCH_COND_ALLNA :
2050 V3D_QPU_BRANCH_COND_ALLA);
2051 vir_link_blocks(c->cur_block, else_block);
2052 vir_link_blocks(c->cur_block, then_block);
2053
2054 /* Process the THEN block. */
2055 vir_set_emit_block(c, then_block);
2056 ntq_emit_cf_list(c, &if_stmt->then_list);
2057
2058 if (!empty_else_block) {
2059 /* At the end of the THEN block, jump to ENDIF */
2060 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALWAYS);
2061 vir_link_blocks(c->cur_block, after_block);
2062
2063 /* Emit the else block. */
2064 vir_set_emit_block(c, else_block);
2065 ntq_activate_execute_for_block(c);
2066 ntq_emit_cf_list(c, &if_stmt->else_list);
2067 }
2068
2069 vir_link_blocks(c->cur_block, after_block);
2070
2071 vir_set_emit_block(c, after_block);
2072 }
2073
2074 static void
2075 ntq_emit_nonuniform_if(struct v3d_compile *c, nir_if *if_stmt)
2076 {
2077 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2078 bool empty_else_block =
2079 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2080 exec_list_is_empty(&nir_else_block->instr_list));
2081
2082 struct qblock *then_block = vir_new_block(c);
2083 struct qblock *after_block = vir_new_block(c);
2084 struct qblock *else_block;
2085 if (empty_else_block)
2086 else_block = after_block;
2087 else
2088 else_block = vir_new_block(c);
2089
2090 bool was_top_level = false;
2091 if (c->execute.file == QFILE_NULL) {
2092 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2093 was_top_level = true;
2094 }
2095
2096 /* Set up the flags for the IF condition (taking the THEN branch). */
2097 nir_alu_instr *if_condition_alu = ntq_get_alu_parent(if_stmt->condition);
2098 enum v3d_qpu_cond cond;
2099 if (!if_condition_alu ||
2100 !ntq_emit_comparison(c, if_condition_alu, &cond)) {
2101 vir_PF(c, ntq_get_src(c, if_stmt->condition, 0),
2102 V3D_QPU_PF_PUSHZ);
2103 cond = V3D_QPU_COND_IFNA;
2104 }
2105
2106 /* Update the flags+cond to mean "Taking the ELSE branch (!cond) and
2107 * was previously active (execute Z) for updating the exec flags.
2108 */
2109 if (was_top_level) {
2110 cond = v3d_qpu_cond_invert(cond);
2111 } else {
2112 struct qinst *inst = vir_MOV_dest(c, vir_reg(QFILE_NULL, 0),
2113 c->execute);
2114 if (cond == V3D_QPU_COND_IFA) {
2115 vir_set_uf(inst, V3D_QPU_UF_NORNZ);
2116 } else {
2117 vir_set_uf(inst, V3D_QPU_UF_ANDZ);
2118 cond = V3D_QPU_COND_IFA;
2119 }
2120 }
2121
2122 vir_MOV_cond(c, cond,
2123 c->execute,
2124 vir_uniform_ui(c, else_block->index));
2125
2126 /* Jump to ELSE if nothing is active for THEN, otherwise fall
2127 * through.
2128 */
2129 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
2130 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
2131 vir_link_blocks(c->cur_block, else_block);
2132 vir_link_blocks(c->cur_block, then_block);
2133
2134 /* Process the THEN block. */
2135 vir_set_emit_block(c, then_block);
2136 ntq_emit_cf_list(c, &if_stmt->then_list);
2137
2138 if (!empty_else_block) {
2139 /* Handle the end of the THEN block. First, all currently
2140 * active channels update their execute flags to point to
2141 * ENDIF
2142 */
2143 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
2144 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2145 vir_uniform_ui(c, after_block->index));
2146
2147 /* If everything points at ENDIF, then jump there immediately. */
2148 vir_PF(c, vir_XOR(c, c->execute,
2149 vir_uniform_ui(c, after_block->index)),
2150 V3D_QPU_PF_PUSHZ);
2151 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
2152 vir_link_blocks(c->cur_block, after_block);
2153 vir_link_blocks(c->cur_block, else_block);
2154
2155 vir_set_emit_block(c, else_block);
2156 ntq_activate_execute_for_block(c);
2157 ntq_emit_cf_list(c, &if_stmt->else_list);
2158 }
2159
2160 vir_link_blocks(c->cur_block, after_block);
2161
2162 vir_set_emit_block(c, after_block);
2163 if (was_top_level)
2164 c->execute = c->undef;
2165 else
2166 ntq_activate_execute_for_block(c);
2167 }
2168
2169 static void
2170 ntq_emit_if(struct v3d_compile *c, nir_if *nif)
2171 {
2172 if (c->execute.file == QFILE_NULL &&
2173 nir_src_is_dynamically_uniform(nif->condition)) {
2174 ntq_emit_uniform_if(c, nif);
2175 } else {
2176 ntq_emit_nonuniform_if(c, nif);
2177 }
2178 }
2179
2180 static void
2181 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
2182 {
2183 switch (jump->type) {
2184 case nir_jump_break:
2185 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
2186 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2187 vir_uniform_ui(c, c->loop_break_block->index));
2188 break;
2189
2190 case nir_jump_continue:
2191 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
2192 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2193 vir_uniform_ui(c, c->loop_cont_block->index));
2194 break;
2195
2196 case nir_jump_return:
2197 unreachable("All returns shouold be lowered\n");
2198 }
2199 }
2200
2201 static void
2202 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
2203 {
2204 switch (instr->type) {
2205 case nir_instr_type_deref:
2206 /* ignored, will be walked by the intrinsic using it. */
2207 break;
2208
2209 case nir_instr_type_alu:
2210 ntq_emit_alu(c, nir_instr_as_alu(instr));
2211 break;
2212
2213 case nir_instr_type_intrinsic:
2214 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
2215 break;
2216
2217 case nir_instr_type_load_const:
2218 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
2219 break;
2220
2221 case nir_instr_type_ssa_undef:
2222 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
2223 break;
2224
2225 case nir_instr_type_tex:
2226 ntq_emit_tex(c, nir_instr_as_tex(instr));
2227 break;
2228
2229 case nir_instr_type_jump:
2230 ntq_emit_jump(c, nir_instr_as_jump(instr));
2231 break;
2232
2233 default:
2234 fprintf(stderr, "Unknown NIR instr type: ");
2235 nir_print_instr(instr, stderr);
2236 fprintf(stderr, "\n");
2237 abort();
2238 }
2239 }
2240
2241 static void
2242 ntq_emit_block(struct v3d_compile *c, nir_block *block)
2243 {
2244 nir_foreach_instr(instr, block) {
2245 ntq_emit_instr(c, instr);
2246 }
2247 }
2248
2249 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
2250
2251 static void
2252 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
2253 {
2254 bool was_top_level = false;
2255 if (c->execute.file == QFILE_NULL) {
2256 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2257 was_top_level = true;
2258 }
2259
2260 struct qblock *save_loop_cont_block = c->loop_cont_block;
2261 struct qblock *save_loop_break_block = c->loop_break_block;
2262
2263 c->loop_cont_block = vir_new_block(c);
2264 c->loop_break_block = vir_new_block(c);
2265
2266 vir_link_blocks(c->cur_block, c->loop_cont_block);
2267 vir_set_emit_block(c, c->loop_cont_block);
2268 ntq_activate_execute_for_block(c);
2269
2270 ntq_emit_cf_list(c, &loop->body);
2271
2272 /* Re-enable any previous continues now, so our ANYA check below
2273 * works.
2274 *
2275 * XXX: Use the .ORZ flags update, instead.
2276 */
2277 vir_PF(c, vir_XOR(c,
2278 c->execute,
2279 vir_uniform_ui(c, c->loop_cont_block->index)),
2280 V3D_QPU_PF_PUSHZ);
2281 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2282
2283 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
2284
2285 struct qinst *branch = vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
2286 /* Pixels that were not dispatched or have been discarded should not
2287 * contribute to looping again.
2288 */
2289 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P;
2290 vir_link_blocks(c->cur_block, c->loop_cont_block);
2291 vir_link_blocks(c->cur_block, c->loop_break_block);
2292
2293 vir_set_emit_block(c, c->loop_break_block);
2294 if (was_top_level)
2295 c->execute = c->undef;
2296 else
2297 ntq_activate_execute_for_block(c);
2298
2299 c->loop_break_block = save_loop_break_block;
2300 c->loop_cont_block = save_loop_cont_block;
2301
2302 c->loops++;
2303 }
2304
2305 static void
2306 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
2307 {
2308 fprintf(stderr, "FUNCTIONS not handled.\n");
2309 abort();
2310 }
2311
2312 static void
2313 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
2314 {
2315 foreach_list_typed(nir_cf_node, node, node, list) {
2316 switch (node->type) {
2317 case nir_cf_node_block:
2318 ntq_emit_block(c, nir_cf_node_as_block(node));
2319 break;
2320
2321 case nir_cf_node_if:
2322 ntq_emit_if(c, nir_cf_node_as_if(node));
2323 break;
2324
2325 case nir_cf_node_loop:
2326 ntq_emit_loop(c, nir_cf_node_as_loop(node));
2327 break;
2328
2329 case nir_cf_node_function:
2330 ntq_emit_function(c, nir_cf_node_as_function(node));
2331 break;
2332
2333 default:
2334 fprintf(stderr, "Unknown NIR node type\n");
2335 abort();
2336 }
2337 }
2338 }
2339
2340 static void
2341 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
2342 {
2343 ntq_setup_registers(c, &impl->registers);
2344 ntq_emit_cf_list(c, &impl->body);
2345 }
2346
2347 static void
2348 nir_to_vir(struct v3d_compile *c)
2349 {
2350 switch (c->s->info.stage) {
2351 case MESA_SHADER_FRAGMENT:
2352 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
2353 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
2354 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
2355
2356 /* XXX perf: We could set the "disable implicit point/line
2357 * varyings" field in the shader record and not emit these, if
2358 * they're not going to be used.
2359 */
2360 if (c->fs_key->is_points) {
2361 c->point_x = emit_fragment_varying(c, NULL, 0, 0);
2362 c->point_y = emit_fragment_varying(c, NULL, 0, 0);
2363 } else if (c->fs_key->is_lines) {
2364 c->line_x = emit_fragment_varying(c, NULL, 0, 0);
2365 }
2366 break;
2367 case MESA_SHADER_COMPUTE:
2368 /* Set up the TSO for barriers, assuming we do some. */
2369 if (c->devinfo->ver < 42) {
2370 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
2371 V3D_QPU_WADDR_SYNC));
2372 }
2373
2374 if (c->s->info.system_values_read &
2375 ((1ull << SYSTEM_VALUE_LOCAL_INVOCATION_INDEX) |
2376 (1ull << SYSTEM_VALUE_WORK_GROUP_ID))) {
2377 c->cs_payload[0] = vir_MOV(c, vir_reg(QFILE_REG, 0));
2378 }
2379 if ((c->s->info.system_values_read &
2380 ((1ull << SYSTEM_VALUE_WORK_GROUP_ID))) ||
2381 c->s->info.cs.shared_size) {
2382 c->cs_payload[1] = vir_MOV(c, vir_reg(QFILE_REG, 2));
2383 }
2384
2385 /* Set up the division between gl_LocalInvocationIndex and
2386 * wg_in_mem in the payload reg.
2387 */
2388 int wg_size = (c->s->info.cs.local_size[0] *
2389 c->s->info.cs.local_size[1] *
2390 c->s->info.cs.local_size[2]);
2391 c->local_invocation_index_bits =
2392 ffs(util_next_power_of_two(MAX2(wg_size, 64))) - 1;
2393 assert(c->local_invocation_index_bits <= 8);
2394
2395 if (c->s->info.cs.shared_size) {
2396 struct qreg wg_in_mem = vir_SHR(c, c->cs_payload[1],
2397 vir_uniform_ui(c, 16));
2398 if (c->s->info.cs.local_size[0] != 1 ||
2399 c->s->info.cs.local_size[1] != 1 ||
2400 c->s->info.cs.local_size[2] != 1) {
2401 int wg_bits = (16 -
2402 c->local_invocation_index_bits);
2403 int wg_mask = (1 << wg_bits) - 1;
2404 wg_in_mem = vir_AND(c, wg_in_mem,
2405 vir_uniform_ui(c, wg_mask));
2406 }
2407 struct qreg shared_per_wg =
2408 vir_uniform_ui(c, c->s->info.cs.shared_size);
2409
2410 c->cs_shared_offset =
2411 vir_ADD(c,
2412 vir_uniform(c, QUNIFORM_SHARED_OFFSET,0),
2413 vir_UMUL(c, wg_in_mem, shared_per_wg));
2414 }
2415 break;
2416 default:
2417 break;
2418 }
2419
2420 if (c->s->info.stage == MESA_SHADER_FRAGMENT)
2421 ntq_setup_fs_inputs(c);
2422 else
2423 ntq_setup_vpm_inputs(c);
2424
2425 ntq_setup_outputs(c);
2426 ntq_setup_uniforms(c);
2427 ntq_setup_registers(c, &c->s->registers);
2428
2429 /* Find the main function and emit the body. */
2430 nir_foreach_function(function, c->s) {
2431 assert(strcmp(function->name, "main") == 0);
2432 assert(function->impl);
2433 ntq_emit_impl(c, function->impl);
2434 }
2435 }
2436
2437 const nir_shader_compiler_options v3d_nir_options = {
2438 .lower_all_io_to_temps = true,
2439 .lower_extract_byte = true,
2440 .lower_extract_word = true,
2441 .lower_bfm = true,
2442 .lower_bitfield_insert_to_shifts = true,
2443 .lower_bitfield_extract_to_shifts = true,
2444 .lower_bitfield_reverse = true,
2445 .lower_bit_count = true,
2446 .lower_cs_local_id_from_index = true,
2447 .lower_pack_unorm_2x16 = true,
2448 .lower_pack_snorm_2x16 = true,
2449 .lower_pack_unorm_4x8 = true,
2450 .lower_pack_snorm_4x8 = true,
2451 .lower_unpack_unorm_4x8 = true,
2452 .lower_unpack_snorm_4x8 = true,
2453 .lower_pack_half_2x16 = true,
2454 .lower_unpack_half_2x16 = true,
2455 .lower_fdiv = true,
2456 .lower_find_lsb = true,
2457 .lower_ffma = true,
2458 .lower_flrp32 = true,
2459 .lower_fpow = true,
2460 .lower_fsat = true,
2461 .lower_fsqrt = true,
2462 .lower_ifind_msb = true,
2463 .lower_isign = true,
2464 .lower_ldexp = true,
2465 .lower_mul_high = true,
2466 .lower_wpos_pntc = true,
2467 .native_integers = true,
2468 };
2469
2470 /**
2471 * When demoting a shader down to single-threaded, removes the THRSW
2472 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
2473 * program end).
2474 */
2475 static void
2476 vir_remove_thrsw(struct v3d_compile *c)
2477 {
2478 vir_for_each_block(block, c) {
2479 vir_for_each_inst_safe(inst, block) {
2480 if (inst->qpu.sig.thrsw)
2481 vir_remove_instruction(c, inst);
2482 }
2483 }
2484
2485 c->last_thrsw = NULL;
2486 }
2487
2488 void
2489 vir_emit_last_thrsw(struct v3d_compile *c)
2490 {
2491 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
2492 * switching, so disable threads if we didn't do any TMU ops (each of
2493 * which would have emitted a THRSW).
2494 */
2495 if (!c->last_thrsw_at_top_level && c->devinfo->ver < 41) {
2496 c->threads = 1;
2497 if (c->last_thrsw)
2498 vir_remove_thrsw(c);
2499 return;
2500 }
2501
2502 /* If we're threaded and the last THRSW was in conditional code, then
2503 * we need to emit another one so that we can flag it as the last
2504 * thrsw.
2505 */
2506 if (c->last_thrsw && !c->last_thrsw_at_top_level) {
2507 assert(c->devinfo->ver >= 41);
2508 vir_emit_thrsw(c);
2509 }
2510
2511 /* If we're threaded, then we need to mark the last THRSW instruction
2512 * so we can emit a pair of them at QPU emit time.
2513 *
2514 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2515 * post-last-THRSW state, so we can skip this.
2516 */
2517 if (!c->last_thrsw && c->s->info.stage == MESA_SHADER_FRAGMENT) {
2518 assert(c->devinfo->ver >= 41);
2519 vir_emit_thrsw(c);
2520 }
2521
2522 if (c->last_thrsw)
2523 c->last_thrsw->is_last_thrsw = true;
2524 }
2525
2526 /* There's a flag in the shader for "center W is needed for reasons other than
2527 * non-centroid varyings", so we just walk the program after VIR optimization
2528 * to see if it's used. It should be harmless to set even if we only use
2529 * center W for varyings.
2530 */
2531 static void
2532 vir_check_payload_w(struct v3d_compile *c)
2533 {
2534 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
2535 return;
2536
2537 vir_for_each_inst_inorder(inst, c) {
2538 for (int i = 0; i < vir_get_nsrc(inst); i++) {
2539 if (inst->src[i].file == QFILE_REG &&
2540 inst->src[i].index == 0) {
2541 c->uses_center_w = true;
2542 return;
2543 }
2544 }
2545 }
2546
2547 }
2548
2549 void
2550 v3d_nir_to_vir(struct v3d_compile *c)
2551 {
2552 if (V3D_DEBUG & (V3D_DEBUG_NIR |
2553 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2554 fprintf(stderr, "%s prog %d/%d NIR:\n",
2555 vir_get_stage_name(c),
2556 c->program_id, c->variant_id);
2557 nir_print_shader(c->s, stderr);
2558 }
2559
2560 nir_to_vir(c);
2561
2562 /* Emit the last THRSW before STVPM and TLB writes. */
2563 vir_emit_last_thrsw(c);
2564
2565 switch (c->s->info.stage) {
2566 case MESA_SHADER_FRAGMENT:
2567 emit_frag_end(c);
2568 break;
2569 case MESA_SHADER_VERTEX:
2570 emit_vert_end(c);
2571 break;
2572 default:
2573 unreachable("bad stage");
2574 }
2575
2576 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2577 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2578 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
2579 vir_get_stage_name(c),
2580 c->program_id, c->variant_id);
2581 vir_dump(c);
2582 fprintf(stderr, "\n");
2583 }
2584
2585 vir_optimize(c);
2586 vir_lower_uniforms(c);
2587
2588 vir_check_payload_w(c);
2589
2590 /* XXX perf: On VC4, we do a VIR-level instruction scheduling here.
2591 * We used that on that platform to pipeline TMU writes and reduce the
2592 * number of thread switches, as well as try (mostly successfully) to
2593 * reduce maximum register pressure to allow more threads. We should
2594 * do something of that sort for V3D -- either instruction scheduling
2595 * here, or delay the the THRSW and LDTMUs from our texture
2596 * instructions until the results are needed.
2597 */
2598
2599 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2600 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2601 fprintf(stderr, "%s prog %d/%d VIR:\n",
2602 vir_get_stage_name(c),
2603 c->program_id, c->variant_id);
2604 vir_dump(c);
2605 fprintf(stderr, "\n");
2606 }
2607
2608 /* Attempt to allocate registers for the temporaries. If we fail,
2609 * reduce thread count and try again.
2610 */
2611 int min_threads = (c->devinfo->ver >= 41) ? 2 : 1;
2612 struct qpu_reg *temp_registers;
2613 while (true) {
2614 bool spilled;
2615 temp_registers = v3d_register_allocate(c, &spilled);
2616 if (spilled)
2617 continue;
2618
2619 if (temp_registers)
2620 break;
2621
2622 if (c->threads == min_threads) {
2623 fprintf(stderr, "Failed to register allocate at %d threads:\n",
2624 c->threads);
2625 vir_dump(c);
2626 c->failed = true;
2627 return;
2628 }
2629
2630 c->threads /= 2;
2631
2632 if (c->threads == 1)
2633 vir_remove_thrsw(c);
2634 }
2635
2636 v3d_vir_to_qpu(c, temp_registers);
2637 }