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nir: Get rid of global registers
[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
34
35 #define GENERAL_TMU_LOOKUP_PER_QUAD (0 << 7)
36 #define GENERAL_TMU_LOOKUP_PER_PIXEL (1 << 7)
37 #define GENERAL_TMU_READ_OP_PREFETCH (0 << 3)
38 #define GENERAL_TMU_READ_OP_CACHE_CLEAR (1 << 3)
39 #define GENERAL_TMU_READ_OP_CACHE_FLUSH (3 << 3)
40 #define GENERAL_TMU_READ_OP_CACHE_CLEAN (3 << 3)
41 #define GENERAL_TMU_READ_OP_CACHE_L1T_CLEAR (4 << 3)
42 #define GENERAL_TMU_READ_OP_CACHE_L1T_FLUSH_AGGREGATION (5 << 3)
43 #define GENERAL_TMU_READ_OP_ATOMIC_INC (8 << 3)
44 #define GENERAL_TMU_READ_OP_ATOMIC_DEC (9 << 3)
45 #define GENERAL_TMU_READ_OP_ATOMIC_NOT (10 << 3)
46 #define GENERAL_TMU_READ_OP_READ (15 << 3)
47 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_I (0 << 0)
48 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_I (1 << 0)
49 #define GENERAL_TMU_LOOKUP_TYPE_VEC2 (2 << 0)
50 #define GENERAL_TMU_LOOKUP_TYPE_VEC3 (3 << 0)
51 #define GENERAL_TMU_LOOKUP_TYPE_VEC4 (4 << 0)
52 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_UI (5 << 0)
53 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_UI (6 << 0)
54 #define GENERAL_TMU_LOOKUP_TYPE_32BIT_UI (7 << 0)
55
56 #define GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP (0 << 3)
57 #define GENERAL_TMU_WRITE_OP_ATOMIC_SUB_WRAP (1 << 3)
58 #define GENERAL_TMU_WRITE_OP_ATOMIC_XCHG (2 << 3)
59 #define GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG (3 << 3)
60 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMIN (4 << 3)
61 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMAX (5 << 3)
62 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMIN (6 << 3)
63 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMAX (7 << 3)
64 #define GENERAL_TMU_WRITE_OP_ATOMIC_AND (8 << 3)
65 #define GENERAL_TMU_WRITE_OP_ATOMIC_OR (9 << 3)
66 #define GENERAL_TMU_WRITE_OP_ATOMIC_XOR (10 << 3)
67 #define GENERAL_TMU_WRITE_OP_WRITE (15 << 3)
68
69 #define V3D_TSY_SET_QUORUM 0
70 #define V3D_TSY_INC_WAITERS 1
71 #define V3D_TSY_DEC_WAITERS 2
72 #define V3D_TSY_INC_QUORUM 3
73 #define V3D_TSY_DEC_QUORUM 4
74 #define V3D_TSY_FREE_ALL 5
75 #define V3D_TSY_RELEASE 6
76 #define V3D_TSY_ACQUIRE 7
77 #define V3D_TSY_WAIT 8
78 #define V3D_TSY_WAIT_INC 9
79 #define V3D_TSY_WAIT_CHECK 10
80 #define V3D_TSY_WAIT_INC_CHECK 11
81 #define V3D_TSY_WAIT_CV 12
82 #define V3D_TSY_INC_SEMAPHORE 13
83 #define V3D_TSY_DEC_SEMAPHORE 14
84 #define V3D_TSY_SET_QUORUM_FREE_ALL 15
85
86 static void
87 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
88
89 static void
90 resize_qreg_array(struct v3d_compile *c,
91 struct qreg **regs,
92 uint32_t *size,
93 uint32_t decl_size)
94 {
95 if (*size >= decl_size)
96 return;
97
98 uint32_t old_size = *size;
99 *size = MAX2(*size * 2, decl_size);
100 *regs = reralloc(c, *regs, struct qreg, *size);
101 if (!*regs) {
102 fprintf(stderr, "Malloc failure\n");
103 abort();
104 }
105
106 for (uint32_t i = old_size; i < *size; i++)
107 (*regs)[i] = c->undef;
108 }
109
110 void
111 vir_emit_thrsw(struct v3d_compile *c)
112 {
113 if (c->threads == 1)
114 return;
115
116 /* Always thread switch after each texture operation for now.
117 *
118 * We could do better by batching a bunch of texture fetches up and
119 * then doing one thread switch and collecting all their results
120 * afterward.
121 */
122 c->last_thrsw = vir_NOP(c);
123 c->last_thrsw->qpu.sig.thrsw = true;
124 c->last_thrsw_at_top_level = !c->in_control_flow;
125 }
126
127 static uint32_t
128 v3d_general_tmu_op(nir_intrinsic_instr *instr)
129 {
130 switch (instr->intrinsic) {
131 case nir_intrinsic_load_ssbo:
132 case nir_intrinsic_load_ubo:
133 case nir_intrinsic_load_uniform:
134 case nir_intrinsic_load_shared:
135 return GENERAL_TMU_READ_OP_READ;
136 case nir_intrinsic_store_ssbo:
137 case nir_intrinsic_store_shared:
138 return GENERAL_TMU_WRITE_OP_WRITE;
139 case nir_intrinsic_ssbo_atomic_add:
140 case nir_intrinsic_shared_atomic_add:
141 return GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP;
142 case nir_intrinsic_ssbo_atomic_imin:
143 case nir_intrinsic_shared_atomic_imin:
144 return GENERAL_TMU_WRITE_OP_ATOMIC_SMIN;
145 case nir_intrinsic_ssbo_atomic_umin:
146 case nir_intrinsic_shared_atomic_umin:
147 return GENERAL_TMU_WRITE_OP_ATOMIC_UMIN;
148 case nir_intrinsic_ssbo_atomic_imax:
149 case nir_intrinsic_shared_atomic_imax:
150 return GENERAL_TMU_WRITE_OP_ATOMIC_SMAX;
151 case nir_intrinsic_ssbo_atomic_umax:
152 case nir_intrinsic_shared_atomic_umax:
153 return GENERAL_TMU_WRITE_OP_ATOMIC_UMAX;
154 case nir_intrinsic_ssbo_atomic_and:
155 case nir_intrinsic_shared_atomic_and:
156 return GENERAL_TMU_WRITE_OP_ATOMIC_AND;
157 case nir_intrinsic_ssbo_atomic_or:
158 case nir_intrinsic_shared_atomic_or:
159 return GENERAL_TMU_WRITE_OP_ATOMIC_OR;
160 case nir_intrinsic_ssbo_atomic_xor:
161 case nir_intrinsic_shared_atomic_xor:
162 return GENERAL_TMU_WRITE_OP_ATOMIC_XOR;
163 case nir_intrinsic_ssbo_atomic_exchange:
164 case nir_intrinsic_shared_atomic_exchange:
165 return GENERAL_TMU_WRITE_OP_ATOMIC_XCHG;
166 case nir_intrinsic_ssbo_atomic_comp_swap:
167 case nir_intrinsic_shared_atomic_comp_swap:
168 return GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG;
169 default:
170 unreachable("unknown intrinsic op");
171 }
172 }
173
174 /**
175 * Implements indirect uniform loads and SSBO accesses through the TMU general
176 * memory access interface.
177 */
178 static void
179 ntq_emit_tmu_general(struct v3d_compile *c, nir_intrinsic_instr *instr,
180 bool is_shared)
181 {
182 /* XXX perf: We should turn add/sub of 1 to inc/dec. Perhaps NIR
183 * wants to have support for inc/dec?
184 */
185
186 uint32_t tmu_op = v3d_general_tmu_op(instr);
187 bool is_store = (instr->intrinsic == nir_intrinsic_store_ssbo ||
188 instr->intrinsic == nir_intrinsic_store_shared);
189 bool has_index = !is_shared;
190
191 int offset_src;
192 int tmu_writes = 1; /* address */
193 if (instr->intrinsic == nir_intrinsic_load_uniform) {
194 offset_src = 0;
195 } else if (instr->intrinsic == nir_intrinsic_load_ssbo ||
196 instr->intrinsic == nir_intrinsic_load_ubo ||
197 instr->intrinsic == nir_intrinsic_load_shared) {
198 offset_src = 0 + has_index;
199 } else if (is_store) {
200 offset_src = 1 + has_index;
201 for (int i = 0; i < instr->num_components; i++) {
202 vir_MOV_dest(c,
203 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
204 ntq_get_src(c, instr->src[0], i));
205 tmu_writes++;
206 }
207 } else {
208 offset_src = 0 + has_index;
209 vir_MOV_dest(c,
210 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
211 ntq_get_src(c, instr->src[1 + has_index], 0));
212 tmu_writes++;
213 if (tmu_op == GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG) {
214 vir_MOV_dest(c,
215 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
216 ntq_get_src(c, instr->src[2 + has_index],
217 0));
218 tmu_writes++;
219 }
220 }
221
222 uint32_t const_offset = 0;
223 if (nir_src_is_const(instr->src[offset_src]))
224 const_offset = nir_src_as_uint(instr->src[offset_src]);
225
226 /* Make sure we won't exceed the 16-entry TMU fifo if each thread is
227 * storing at the same time.
228 */
229 while (tmu_writes > 16 / c->threads)
230 c->threads /= 2;
231
232 struct qreg offset;
233 if (instr->intrinsic == nir_intrinsic_load_uniform) {
234 const_offset += nir_intrinsic_base(instr);
235 offset = vir_uniform(c, QUNIFORM_UBO_ADDR,
236 v3d_unit_data_create(0, const_offset));
237 const_offset = 0;
238 } else if (instr->intrinsic == nir_intrinsic_load_ubo) {
239 uint32_t index = nir_src_as_uint(instr->src[0]) + 1;
240 /* Note that QUNIFORM_UBO_ADDR takes a UBO index shifted up by
241 * 1 (0 is gallium's constant buffer 0).
242 */
243 offset = vir_uniform(c, QUNIFORM_UBO_ADDR,
244 v3d_unit_data_create(index, const_offset));
245 const_offset = 0;
246 } else if (is_shared) {
247 /* Shared variables have no buffer index, and all start from a
248 * common base that we set up at the start of dispatch
249 */
250 offset = c->cs_shared_offset;
251 } else {
252 offset = vir_uniform(c, QUNIFORM_SSBO_OFFSET,
253 nir_src_as_uint(instr->src[is_store ?
254 1 : 0]));
255 }
256
257 uint32_t config = (0xffffff00 |
258 tmu_op |
259 GENERAL_TMU_LOOKUP_PER_PIXEL);
260 if (instr->num_components == 1) {
261 config |= GENERAL_TMU_LOOKUP_TYPE_32BIT_UI;
262 } else {
263 config |= (GENERAL_TMU_LOOKUP_TYPE_VEC2 +
264 instr->num_components - 2);
265 }
266
267 if (vir_in_nonuniform_control_flow(c)) {
268 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
269 V3D_QPU_PF_PUSHZ);
270 }
271
272 struct qreg dest;
273 if (config == ~0)
274 dest = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA);
275 else
276 dest = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUAU);
277
278 struct qinst *tmu;
279 if (nir_src_is_const(instr->src[offset_src]) && const_offset == 0) {
280 tmu = vir_MOV_dest(c, dest, offset);
281 } else {
282 tmu = vir_ADD_dest(c, dest,
283 offset,
284 ntq_get_src(c, instr->src[offset_src], 0));
285 }
286
287 if (config != ~0) {
288 tmu->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT,
289 config);
290 }
291
292 if (vir_in_nonuniform_control_flow(c))
293 vir_set_cond(tmu, V3D_QPU_COND_IFA);
294
295 vir_emit_thrsw(c);
296
297 /* Read the result, or wait for the TMU op to complete. */
298 for (int i = 0; i < nir_intrinsic_dest_components(instr); i++)
299 ntq_store_dest(c, &instr->dest, i, vir_MOV(c, vir_LDTMU(c)));
300
301 if (nir_intrinsic_dest_components(instr) == 0)
302 vir_TMUWT(c);
303 }
304
305 static struct qreg *
306 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
307 {
308 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
309 def->num_components);
310 _mesa_hash_table_insert(c->def_ht, def, qregs);
311 return qregs;
312 }
313
314 /**
315 * This function is responsible for getting VIR results into the associated
316 * storage for a NIR instruction.
317 *
318 * If it's a NIR SSA def, then we just set the associated hash table entry to
319 * the new result.
320 *
321 * If it's a NIR reg, then we need to update the existing qreg assigned to the
322 * NIR destination with the incoming value. To do that without introducing
323 * new MOVs, we require that the incoming qreg either be a uniform, or be
324 * SSA-defined by the previous VIR instruction in the block and rewritable by
325 * this function. That lets us sneak ahead and insert the SF flag beforehand
326 * (knowing that the previous instruction doesn't depend on flags) and rewrite
327 * its destination to be the NIR reg's destination
328 */
329 void
330 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
331 struct qreg result)
332 {
333 struct qinst *last_inst = NULL;
334 if (!list_empty(&c->cur_block->instructions))
335 last_inst = (struct qinst *)c->cur_block->instructions.prev;
336
337 assert((result.file == QFILE_TEMP &&
338 last_inst && last_inst == c->defs[result.index]));
339
340 if (dest->is_ssa) {
341 assert(chan < dest->ssa.num_components);
342
343 struct qreg *qregs;
344 struct hash_entry *entry =
345 _mesa_hash_table_search(c->def_ht, &dest->ssa);
346
347 if (entry)
348 qregs = entry->data;
349 else
350 qregs = ntq_init_ssa_def(c, &dest->ssa);
351
352 qregs[chan] = result;
353 } else {
354 nir_register *reg = dest->reg.reg;
355 assert(dest->reg.base_offset == 0);
356 assert(reg->num_array_elems == 0);
357 struct hash_entry *entry =
358 _mesa_hash_table_search(c->def_ht, reg);
359 struct qreg *qregs = entry->data;
360
361 /* Insert a MOV if the source wasn't an SSA def in the
362 * previous instruction.
363 */
364 if ((vir_in_nonuniform_control_flow(c) &&
365 c->defs[last_inst->dst.index]->qpu.sig.ldunif)) {
366 result = vir_MOV(c, result);
367 last_inst = c->defs[result.index];
368 }
369
370 /* We know they're both temps, so just rewrite index. */
371 c->defs[last_inst->dst.index] = NULL;
372 last_inst->dst.index = qregs[chan].index;
373
374 /* If we're in control flow, then make this update of the reg
375 * conditional on the execution mask.
376 */
377 if (vir_in_nonuniform_control_flow(c)) {
378 last_inst->dst.index = qregs[chan].index;
379
380 /* Set the flags to the current exec mask.
381 */
382 c->cursor = vir_before_inst(last_inst);
383 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
384 V3D_QPU_PF_PUSHZ);
385 c->cursor = vir_after_inst(last_inst);
386
387 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
388 }
389 }
390 }
391
392 struct qreg
393 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
394 {
395 struct hash_entry *entry;
396 if (src.is_ssa) {
397 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
398 assert(i < src.ssa->num_components);
399 } else {
400 nir_register *reg = src.reg.reg;
401 entry = _mesa_hash_table_search(c->def_ht, reg);
402 assert(reg->num_array_elems == 0);
403 assert(src.reg.base_offset == 0);
404 assert(i < reg->num_components);
405 }
406
407 struct qreg *qregs = entry->data;
408 return qregs[i];
409 }
410
411 static struct qreg
412 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
413 unsigned src)
414 {
415 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
416 unsigned chan = ffs(instr->dest.write_mask) - 1;
417 struct qreg r = ntq_get_src(c, instr->src[src].src,
418 instr->src[src].swizzle[chan]);
419
420 assert(!instr->src[src].abs);
421 assert(!instr->src[src].negate);
422
423 return r;
424 };
425
426 static struct qreg
427 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
428 {
429 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
430 }
431
432 static void
433 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
434 {
435 unsigned unit = instr->texture_index;
436 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
437 int dest_size = nir_tex_instr_dest_size(instr);
438
439 struct qreg lod = c->undef;
440 if (lod_index != -1)
441 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
442
443 for (int i = 0; i < dest_size; i++) {
444 assert(i < 3);
445 enum quniform_contents contents;
446
447 if (instr->is_array && i == dest_size - 1)
448 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
449 else
450 contents = QUNIFORM_TEXTURE_WIDTH + i;
451
452 struct qreg size = vir_uniform(c, contents, unit);
453
454 switch (instr->sampler_dim) {
455 case GLSL_SAMPLER_DIM_1D:
456 case GLSL_SAMPLER_DIM_2D:
457 case GLSL_SAMPLER_DIM_MS:
458 case GLSL_SAMPLER_DIM_3D:
459 case GLSL_SAMPLER_DIM_CUBE:
460 /* Don't minify the array size. */
461 if (!(instr->is_array && i == dest_size - 1)) {
462 size = ntq_minify(c, size, lod);
463 }
464 break;
465
466 case GLSL_SAMPLER_DIM_RECT:
467 /* There's no LOD field for rects */
468 break;
469
470 default:
471 unreachable("Bad sampler type");
472 }
473
474 ntq_store_dest(c, &instr->dest, i, size);
475 }
476 }
477
478 static void
479 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
480 {
481 unsigned unit = instr->texture_index;
482
483 /* Since each texture sampling op requires uploading uniforms to
484 * reference the texture, there's no HW support for texture size and
485 * you just upload uniforms containing the size.
486 */
487 switch (instr->op) {
488 case nir_texop_query_levels:
489 ntq_store_dest(c, &instr->dest, 0,
490 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
491 return;
492 case nir_texop_txs:
493 ntq_emit_txs(c, instr);
494 return;
495 default:
496 break;
497 }
498
499 if (c->devinfo->ver >= 40)
500 v3d40_vir_emit_tex(c, instr);
501 else
502 v3d33_vir_emit_tex(c, instr);
503 }
504
505 static struct qreg
506 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
507 {
508 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
509 if (is_cos)
510 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
511
512 struct qreg periods = vir_FROUND(c, input);
513 struct qreg sin_output = vir_SIN(c, vir_FSUB(c, input, periods));
514 return vir_XOR(c, sin_output, vir_SHL(c,
515 vir_FTOIN(c, periods),
516 vir_uniform_ui(c, -1)));
517 }
518
519 static struct qreg
520 ntq_fsign(struct v3d_compile *c, struct qreg src)
521 {
522 struct qreg t = vir_get_temp(c);
523
524 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
525 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHZ);
526 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
527 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHN);
528 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
529 return vir_MOV(c, t);
530 }
531
532 static void
533 emit_fragcoord_input(struct v3d_compile *c, int attr)
534 {
535 c->inputs[attr * 4 + 0] = vir_FXCD(c);
536 c->inputs[attr * 4 + 1] = vir_FYCD(c);
537 c->inputs[attr * 4 + 2] = c->payload_z;
538 c->inputs[attr * 4 + 3] = vir_RECIP(c, c->payload_w);
539 }
540
541 static struct qreg
542 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
543 uint8_t swizzle, int array_index)
544 {
545 struct qreg r3 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R3);
546 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
547
548 struct qreg vary;
549 if (c->devinfo->ver >= 41) {
550 struct qinst *ldvary = vir_add_inst(V3D_QPU_A_NOP, c->undef,
551 c->undef, c->undef);
552 ldvary->qpu.sig.ldvary = true;
553 vary = vir_emit_def(c, ldvary);
554 } else {
555 vir_NOP(c)->qpu.sig.ldvary = true;
556 vary = r3;
557 }
558
559 /* For gl_PointCoord input or distance along a line, we'll be called
560 * with no nir_variable, and we don't count toward VPM size so we
561 * don't track an input slot.
562 */
563 if (!var) {
564 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
565 }
566
567 int i = c->num_inputs++;
568 c->input_slots[i] =
569 v3d_slot_from_slot_and_component(var->data.location +
570 array_index, swizzle);
571
572 switch (var->data.interpolation) {
573 case INTERP_MODE_NONE:
574 /* If a gl_FrontColor or gl_BackColor input has no interp
575 * qualifier, then if we're using glShadeModel(GL_FLAT) it
576 * needs to be flat shaded.
577 */
578 switch (var->data.location + array_index) {
579 case VARYING_SLOT_COL0:
580 case VARYING_SLOT_COL1:
581 case VARYING_SLOT_BFC0:
582 case VARYING_SLOT_BFC1:
583 if (c->fs_key->shade_model_flat) {
584 BITSET_SET(c->flat_shade_flags, i);
585 vir_MOV_dest(c, c->undef, vary);
586 return vir_MOV(c, r5);
587 } else {
588 return vir_FADD(c, vir_FMUL(c, vary,
589 c->payload_w), r5);
590 }
591 default:
592 break;
593 }
594 /* FALLTHROUGH */
595 case INTERP_MODE_SMOOTH:
596 if (var->data.centroid) {
597 BITSET_SET(c->centroid_flags, i);
598 return vir_FADD(c, vir_FMUL(c, vary,
599 c->payload_w_centroid), r5);
600 } else {
601 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
602 }
603 case INTERP_MODE_NOPERSPECTIVE:
604 BITSET_SET(c->noperspective_flags, i);
605 return vir_FADD(c, vir_MOV(c, vary), r5);
606 case INTERP_MODE_FLAT:
607 BITSET_SET(c->flat_shade_flags, i);
608 vir_MOV_dest(c, c->undef, vary);
609 return vir_MOV(c, r5);
610 default:
611 unreachable("Bad interp mode");
612 }
613 }
614
615 static void
616 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var,
617 int array_index)
618 {
619 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
620 int chan = var->data.location_frac + i;
621 c->inputs[attr * 4 + chan] =
622 emit_fragment_varying(c, var, chan, array_index);
623 }
624 }
625
626 static void
627 add_output(struct v3d_compile *c,
628 uint32_t decl_offset,
629 uint8_t slot,
630 uint8_t swizzle)
631 {
632 uint32_t old_array_size = c->outputs_array_size;
633 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
634 decl_offset + 1);
635
636 if (old_array_size != c->outputs_array_size) {
637 c->output_slots = reralloc(c,
638 c->output_slots,
639 struct v3d_varying_slot,
640 c->outputs_array_size);
641 }
642
643 c->output_slots[decl_offset] =
644 v3d_slot_from_slot_and_component(slot, swizzle);
645 }
646
647 /**
648 * If compare_instr is a valid comparison instruction, emits the
649 * compare_instr's comparison and returns the sel_instr's return value based
650 * on the compare_instr's result.
651 */
652 static bool
653 ntq_emit_comparison(struct v3d_compile *c,
654 nir_alu_instr *compare_instr,
655 enum v3d_qpu_cond *out_cond)
656 {
657 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
658 struct qreg src1;
659 if (nir_op_infos[compare_instr->op].num_inputs > 1)
660 src1 = ntq_get_alu_src(c, compare_instr, 1);
661 bool cond_invert = false;
662 struct qreg nop = vir_nop_reg();
663
664 switch (compare_instr->op) {
665 case nir_op_feq32:
666 case nir_op_seq:
667 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
668 break;
669 case nir_op_ieq32:
670 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
671 break;
672
673 case nir_op_fne32:
674 case nir_op_sne:
675 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
676 cond_invert = true;
677 break;
678 case nir_op_ine32:
679 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
680 cond_invert = true;
681 break;
682
683 case nir_op_fge32:
684 case nir_op_sge:
685 vir_set_pf(vir_FCMP_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
686 break;
687 case nir_op_ige32:
688 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
689 cond_invert = true;
690 break;
691 case nir_op_uge32:
692 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
693 cond_invert = true;
694 break;
695
696 case nir_op_slt:
697 case nir_op_flt32:
698 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHN);
699 break;
700 case nir_op_ilt32:
701 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
702 break;
703 case nir_op_ult32:
704 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
705 break;
706
707 case nir_op_i2b32:
708 vir_set_pf(vir_MOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ);
709 cond_invert = true;
710 break;
711
712 case nir_op_f2b32:
713 vir_set_pf(vir_FMOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ);
714 cond_invert = true;
715 break;
716
717 default:
718 return false;
719 }
720
721 *out_cond = cond_invert ? V3D_QPU_COND_IFNA : V3D_QPU_COND_IFA;
722
723 return true;
724 }
725
726 /* Finds an ALU instruction that generates our src value that could
727 * (potentially) be greedily emitted in the consuming instruction.
728 */
729 static struct nir_alu_instr *
730 ntq_get_alu_parent(nir_src src)
731 {
732 if (!src.is_ssa || src.ssa->parent_instr->type != nir_instr_type_alu)
733 return NULL;
734 nir_alu_instr *instr = nir_instr_as_alu(src.ssa->parent_instr);
735 if (!instr)
736 return NULL;
737
738 /* If the ALU instr's srcs are non-SSA, then we would have to avoid
739 * moving emission of the ALU instr down past another write of the
740 * src.
741 */
742 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
743 if (!instr->src[i].src.is_ssa)
744 return NULL;
745 }
746
747 return instr;
748 }
749
750 /* Turns a NIR bool into a condition code to predicate on. */
751 static enum v3d_qpu_cond
752 ntq_emit_bool_to_cond(struct v3d_compile *c, nir_src src)
753 {
754 nir_alu_instr *compare = ntq_get_alu_parent(src);
755 if (!compare)
756 goto out;
757
758 enum v3d_qpu_cond cond;
759 if (ntq_emit_comparison(c, compare, &cond))
760 return cond;
761
762 out:
763 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), ntq_get_src(c, src, 0)),
764 V3D_QPU_PF_PUSHZ);
765 return V3D_QPU_COND_IFNA;
766 }
767
768 static void
769 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
770 {
771 /* This should always be lowered to ALU operations for V3D. */
772 assert(!instr->dest.saturate);
773
774 /* Vectors are special in that they have non-scalarized writemasks,
775 * and just take the first swizzle channel for each argument in order
776 * into each writemask channel.
777 */
778 if (instr->op == nir_op_vec2 ||
779 instr->op == nir_op_vec3 ||
780 instr->op == nir_op_vec4) {
781 struct qreg srcs[4];
782 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
783 srcs[i] = ntq_get_src(c, instr->src[i].src,
784 instr->src[i].swizzle[0]);
785 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
786 ntq_store_dest(c, &instr->dest.dest, i,
787 vir_MOV(c, srcs[i]));
788 return;
789 }
790
791 /* General case: We can just grab the one used channel per src. */
792 struct qreg src[nir_op_infos[instr->op].num_inputs];
793 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
794 src[i] = ntq_get_alu_src(c, instr, i);
795 }
796
797 struct qreg result;
798
799 switch (instr->op) {
800 case nir_op_fmov:
801 case nir_op_imov:
802 result = vir_MOV(c, src[0]);
803 break;
804
805 case nir_op_fneg:
806 result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
807 break;
808 case nir_op_ineg:
809 result = vir_NEG(c, src[0]);
810 break;
811
812 case nir_op_fmul:
813 result = vir_FMUL(c, src[0], src[1]);
814 break;
815 case nir_op_fadd:
816 result = vir_FADD(c, src[0], src[1]);
817 break;
818 case nir_op_fsub:
819 result = vir_FSUB(c, src[0], src[1]);
820 break;
821 case nir_op_fmin:
822 result = vir_FMIN(c, src[0], src[1]);
823 break;
824 case nir_op_fmax:
825 result = vir_FMAX(c, src[0], src[1]);
826 break;
827
828 case nir_op_f2i32: {
829 nir_alu_instr *src0_alu = ntq_get_alu_parent(instr->src[0].src);
830 if (src0_alu && src0_alu->op == nir_op_fround_even) {
831 result = vir_FTOIN(c, ntq_get_alu_src(c, src0_alu, 0));
832 } else {
833 result = vir_FTOIZ(c, src[0]);
834 }
835 break;
836 }
837
838 case nir_op_f2u32:
839 result = vir_FTOUZ(c, src[0]);
840 break;
841 case nir_op_i2f32:
842 result = vir_ITOF(c, src[0]);
843 break;
844 case nir_op_u2f32:
845 result = vir_UTOF(c, src[0]);
846 break;
847 case nir_op_b2f32:
848 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
849 break;
850 case nir_op_b2i32:
851 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
852 break;
853
854 case nir_op_iadd:
855 result = vir_ADD(c, src[0], src[1]);
856 break;
857 case nir_op_ushr:
858 result = vir_SHR(c, src[0], src[1]);
859 break;
860 case nir_op_isub:
861 result = vir_SUB(c, src[0], src[1]);
862 break;
863 case nir_op_ishr:
864 result = vir_ASR(c, src[0], src[1]);
865 break;
866 case nir_op_ishl:
867 result = vir_SHL(c, src[0], src[1]);
868 break;
869 case nir_op_imin:
870 result = vir_MIN(c, src[0], src[1]);
871 break;
872 case nir_op_umin:
873 result = vir_UMIN(c, src[0], src[1]);
874 break;
875 case nir_op_imax:
876 result = vir_MAX(c, src[0], src[1]);
877 break;
878 case nir_op_umax:
879 result = vir_UMAX(c, src[0], src[1]);
880 break;
881 case nir_op_iand:
882 result = vir_AND(c, src[0], src[1]);
883 break;
884 case nir_op_ior:
885 result = vir_OR(c, src[0], src[1]);
886 break;
887 case nir_op_ixor:
888 result = vir_XOR(c, src[0], src[1]);
889 break;
890 case nir_op_inot:
891 result = vir_NOT(c, src[0]);
892 break;
893
894 case nir_op_ufind_msb:
895 result = vir_SUB(c, vir_uniform_ui(c, 31), vir_CLZ(c, src[0]));
896 break;
897
898 case nir_op_imul:
899 result = vir_UMUL(c, src[0], src[1]);
900 break;
901
902 case nir_op_seq:
903 case nir_op_sne:
904 case nir_op_sge:
905 case nir_op_slt: {
906 enum v3d_qpu_cond cond;
907 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
908 assert(ok);
909 result = vir_MOV(c, vir_SEL(c, cond,
910 vir_uniform_f(c, 1.0),
911 vir_uniform_f(c, 0.0)));
912 break;
913 }
914
915 case nir_op_i2b32:
916 case nir_op_f2b32:
917 case nir_op_feq32:
918 case nir_op_fne32:
919 case nir_op_fge32:
920 case nir_op_flt32:
921 case nir_op_ieq32:
922 case nir_op_ine32:
923 case nir_op_ige32:
924 case nir_op_uge32:
925 case nir_op_ilt32:
926 case nir_op_ult32: {
927 enum v3d_qpu_cond cond;
928 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
929 assert(ok);
930 result = vir_MOV(c, vir_SEL(c, cond,
931 vir_uniform_ui(c, ~0),
932 vir_uniform_ui(c, 0)));
933 break;
934 }
935
936 case nir_op_b32csel:
937 result = vir_MOV(c,
938 vir_SEL(c,
939 ntq_emit_bool_to_cond(c, instr->src[0].src),
940 src[1], src[2]));
941 break;
942
943 case nir_op_fcsel:
944 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), src[0]),
945 V3D_QPU_PF_PUSHZ);
946 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
947 src[1], src[2]));
948 break;
949
950 case nir_op_frcp:
951 result = vir_RECIP(c, src[0]);
952 break;
953 case nir_op_frsq:
954 result = vir_RSQRT(c, src[0]);
955 break;
956 case nir_op_fexp2:
957 result = vir_EXP(c, src[0]);
958 break;
959 case nir_op_flog2:
960 result = vir_LOG(c, src[0]);
961 break;
962
963 case nir_op_fceil:
964 result = vir_FCEIL(c, src[0]);
965 break;
966 case nir_op_ffloor:
967 result = vir_FFLOOR(c, src[0]);
968 break;
969 case nir_op_fround_even:
970 result = vir_FROUND(c, src[0]);
971 break;
972 case nir_op_ftrunc:
973 result = vir_FTRUNC(c, src[0]);
974 break;
975
976 case nir_op_fsin:
977 result = ntq_fsincos(c, src[0], false);
978 break;
979 case nir_op_fcos:
980 result = ntq_fsincos(c, src[0], true);
981 break;
982
983 case nir_op_fsign:
984 result = ntq_fsign(c, src[0]);
985 break;
986
987 case nir_op_fabs: {
988 result = vir_FMOV(c, src[0]);
989 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
990 break;
991 }
992
993 case nir_op_iabs:
994 result = vir_MAX(c, src[0], vir_NEG(c, src[0]));
995 break;
996
997 case nir_op_fddx:
998 case nir_op_fddx_coarse:
999 case nir_op_fddx_fine:
1000 result = vir_FDX(c, src[0]);
1001 break;
1002
1003 case nir_op_fddy:
1004 case nir_op_fddy_coarse:
1005 case nir_op_fddy_fine:
1006 result = vir_FDY(c, src[0]);
1007 break;
1008
1009 case nir_op_uadd_carry:
1010 vir_set_pf(vir_ADD_dest(c, vir_nop_reg(), src[0], src[1]),
1011 V3D_QPU_PF_PUSHC);
1012 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1013 vir_uniform_ui(c, ~0),
1014 vir_uniform_ui(c, 0)));
1015 break;
1016
1017 case nir_op_pack_half_2x16_split:
1018 result = vir_VFPACK(c, src[0], src[1]);
1019 break;
1020
1021 case nir_op_unpack_half_2x16_split_x:
1022 result = vir_FMOV(c, src[0]);
1023 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_L);
1024 break;
1025
1026 case nir_op_unpack_half_2x16_split_y:
1027 result = vir_FMOV(c, src[0]);
1028 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_H);
1029 break;
1030
1031 default:
1032 fprintf(stderr, "unknown NIR ALU inst: ");
1033 nir_print_instr(&instr->instr, stderr);
1034 fprintf(stderr, "\n");
1035 abort();
1036 }
1037
1038 /* We have a scalar result, so the instruction should only have a
1039 * single channel written to.
1040 */
1041 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
1042 ntq_store_dest(c, &instr->dest.dest,
1043 ffs(instr->dest.write_mask) - 1, result);
1044 }
1045
1046 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
1047 * specifier. They come from a register that's preloaded with 0xffffffff
1048 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
1049 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
1050 */
1051 #define TLB_TYPE_F16_COLOR (3 << 6)
1052 #define TLB_TYPE_I32_COLOR (1 << 6)
1053 #define TLB_TYPE_F32_COLOR (0 << 6)
1054 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
1055 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
1056 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
1057 #define TLB_F16_SWAP_HI_LO (1 << 1)
1058 #define TLB_VEC_SIZE_4_F16 (1 << 0)
1059 #define TLB_VEC_SIZE_2_F16 (0 << 0)
1060 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
1061
1062 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
1063 * flag is set.
1064 */
1065 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
1066 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
1067 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
1068 #define TLB_V42_DEPTH_TYPE_INVARIANT (0 << 3) /* Unmodified sideband input used */
1069 #define TLB_V42_DEPTH_TYPE_PER_PIXEL (1 << 3) /* QPU result used */
1070
1071 /* Stencil is a single 32-bit write. */
1072 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1073
1074 static void
1075 emit_frag_end(struct v3d_compile *c)
1076 {
1077 /* XXX
1078 if (c->output_sample_mask_index != -1) {
1079 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1080 }
1081 */
1082
1083 bool has_any_tlb_color_write = false;
1084 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1085 if (c->fs_key->cbufs & (1 << rt) && c->output_color_var[rt])
1086 has_any_tlb_color_write = true;
1087 }
1088
1089 if (c->fs_key->sample_alpha_to_coverage && c->output_color_var[0]) {
1090 struct nir_variable *var = c->output_color_var[0];
1091 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1092
1093 vir_SETMSF_dest(c, vir_nop_reg(),
1094 vir_AND(c,
1095 vir_MSF(c),
1096 vir_FTOC(c, color[3])));
1097 }
1098
1099 struct qreg tlb_reg = vir_magic_reg(V3D_QPU_WADDR_TLB);
1100 struct qreg tlbu_reg = vir_magic_reg(V3D_QPU_WADDR_TLBU);
1101 if (c->output_position_index != -1) {
1102 struct qinst *inst = vir_MOV_dest(c, tlbu_reg,
1103 c->outputs[c->output_position_index]);
1104 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1105
1106 if (c->devinfo->ver >= 42) {
1107 tlb_specifier |= (TLB_V42_DEPTH_TYPE_PER_PIXEL |
1108 TLB_SAMPLE_MODE_PER_PIXEL);
1109 } else
1110 tlb_specifier |= TLB_DEPTH_TYPE_PER_PIXEL;
1111
1112 inst->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT,
1113 tlb_specifier |
1114 0xffffff00);
1115 c->writes_z = true;
1116 } else if (c->s->info.fs.uses_discard ||
1117 !c->s->info.fs.early_fragment_tests ||
1118 c->fs_key->sample_alpha_to_coverage ||
1119 !has_any_tlb_color_write) {
1120 /* Emit passthrough Z if it needed to be delayed until shader
1121 * end due to potential discards.
1122 *
1123 * Since (single-threaded) fragment shaders always need a TLB
1124 * write, emit passthrouh Z if we didn't have any color
1125 * buffers and flag us as potentially discarding, so that we
1126 * can use Z as the TLB write.
1127 */
1128 c->s->info.fs.uses_discard = true;
1129
1130 struct qinst *inst = vir_MOV_dest(c, tlbu_reg,
1131 vir_nop_reg());
1132 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1133
1134 if (c->devinfo->ver >= 42) {
1135 /* The spec says the PER_PIXEL flag is ignored for
1136 * invariant writes, but the simulator demands it.
1137 */
1138 tlb_specifier |= (TLB_V42_DEPTH_TYPE_INVARIANT |
1139 TLB_SAMPLE_MODE_PER_PIXEL);
1140 } else {
1141 tlb_specifier |= TLB_DEPTH_TYPE_INVARIANT;
1142 }
1143
1144 inst->uniform = vir_get_uniform_index(c,
1145 QUNIFORM_CONSTANT,
1146 tlb_specifier |
1147 0xffffff00);
1148 c->writes_z = true;
1149 }
1150
1151 /* XXX: Performance improvement: Merge Z write and color writes TLB
1152 * uniform setup
1153 */
1154
1155 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1156 if (!(c->fs_key->cbufs & (1 << rt)) || !c->output_color_var[rt])
1157 continue;
1158
1159 nir_variable *var = c->output_color_var[rt];
1160 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1161 int num_components = glsl_get_vector_elements(var->type);
1162 uint32_t conf = 0xffffff00;
1163 struct qinst *inst;
1164
1165 conf |= TLB_SAMPLE_MODE_PER_PIXEL;
1166 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1167
1168 if (c->fs_key->swap_color_rb & (1 << rt))
1169 num_components = MAX2(num_components, 3);
1170
1171 assert(num_components != 0);
1172 switch (glsl_get_base_type(var->type)) {
1173 case GLSL_TYPE_UINT:
1174 case GLSL_TYPE_INT:
1175 /* The F32 vs I32 distinction was dropped in 4.2. */
1176 if (c->devinfo->ver < 42)
1177 conf |= TLB_TYPE_I32_COLOR;
1178 else
1179 conf |= TLB_TYPE_F32_COLOR;
1180 conf |= ((num_components - 1) <<
1181 TLB_VEC_SIZE_MINUS_1_SHIFT);
1182
1183 inst = vir_MOV_dest(c, tlbu_reg, color[0]);
1184 inst->uniform = vir_get_uniform_index(c,
1185 QUNIFORM_CONSTANT,
1186 conf);
1187
1188 for (int i = 1; i < num_components; i++) {
1189 inst = vir_MOV_dest(c, tlb_reg, color[i]);
1190 }
1191 break;
1192
1193 default: {
1194 struct qreg r = color[0];
1195 struct qreg g = color[1];
1196 struct qreg b = color[2];
1197 struct qreg a = color[3];
1198
1199 if (c->fs_key->f32_color_rb & (1 << rt)) {
1200 conf |= TLB_TYPE_F32_COLOR;
1201 conf |= ((num_components - 1) <<
1202 TLB_VEC_SIZE_MINUS_1_SHIFT);
1203 } else {
1204 conf |= TLB_TYPE_F16_COLOR;
1205 conf |= TLB_F16_SWAP_HI_LO;
1206 if (num_components >= 3)
1207 conf |= TLB_VEC_SIZE_4_F16;
1208 else
1209 conf |= TLB_VEC_SIZE_2_F16;
1210 }
1211
1212 if (c->fs_key->swap_color_rb & (1 << rt)) {
1213 r = color[2];
1214 b = color[0];
1215 }
1216
1217 if (c->fs_key->sample_alpha_to_one)
1218 a = vir_uniform_f(c, 1.0);
1219
1220 if (c->fs_key->f32_color_rb & (1 << rt)) {
1221 inst = vir_MOV_dest(c, tlbu_reg, r);
1222 inst->uniform = vir_get_uniform_index(c,
1223 QUNIFORM_CONSTANT,
1224 conf);
1225
1226 if (num_components >= 2)
1227 vir_MOV_dest(c, tlb_reg, g);
1228 if (num_components >= 3)
1229 vir_MOV_dest(c, tlb_reg, b);
1230 if (num_components >= 4)
1231 vir_MOV_dest(c, tlb_reg, a);
1232 } else {
1233 inst = vir_VFPACK_dest(c, tlb_reg, r, g);
1234 if (conf != ~0) {
1235 inst->dst = tlbu_reg;
1236 inst->uniform = vir_get_uniform_index(c,
1237 QUNIFORM_CONSTANT,
1238 conf);
1239 }
1240
1241 if (num_components >= 3)
1242 inst = vir_VFPACK_dest(c, tlb_reg, b, a);
1243 }
1244 break;
1245 }
1246 }
1247 }
1248 }
1249
1250 static void
1251 vir_VPM_WRITE(struct v3d_compile *c, struct qreg val, uint32_t vpm_index)
1252 {
1253 if (c->devinfo->ver >= 40) {
1254 vir_STVPMV(c, vir_uniform_ui(c, vpm_index), val);
1255 } else {
1256 /* XXX: v3d33_vir_vpm_write_setup(c); */
1257 vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM), val);
1258 }
1259 }
1260
1261 static void
1262 emit_vert_end(struct v3d_compile *c)
1263 {
1264 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1265 */
1266 if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
1267 vir_VPMWT(c);
1268 }
1269
1270 void
1271 v3d_optimize_nir(struct nir_shader *s)
1272 {
1273 bool progress;
1274
1275 do {
1276 progress = false;
1277
1278 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1279 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1280 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1281 NIR_PASS(progress, s, nir_copy_prop);
1282 NIR_PASS(progress, s, nir_opt_remove_phis);
1283 NIR_PASS(progress, s, nir_opt_dce);
1284 NIR_PASS(progress, s, nir_opt_dead_cf);
1285 NIR_PASS(progress, s, nir_opt_cse);
1286 NIR_PASS(progress, s, nir_opt_peephole_select, 8, true, true);
1287 NIR_PASS(progress, s, nir_opt_algebraic);
1288 NIR_PASS(progress, s, nir_opt_constant_folding);
1289 NIR_PASS(progress, s, nir_opt_undef);
1290 } while (progress);
1291
1292 NIR_PASS(progress, s, nir_opt_move_load_ubo);
1293 }
1294
1295 static int
1296 driver_location_compare(const void *in_a, const void *in_b)
1297 {
1298 const nir_variable *const *a = in_a;
1299 const nir_variable *const *b = in_b;
1300
1301 return (*a)->data.driver_location - (*b)->data.driver_location;
1302 }
1303
1304 static struct qreg
1305 ntq_emit_vpm_read(struct v3d_compile *c,
1306 uint32_t *num_components_queued,
1307 uint32_t *remaining,
1308 uint32_t vpm_index)
1309 {
1310 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1311
1312 if (c->devinfo->ver >= 40 ) {
1313 return vir_LDVPMV_IN(c,
1314 vir_uniform_ui(c,
1315 (*num_components_queued)++));
1316 }
1317
1318 if (*num_components_queued != 0) {
1319 (*num_components_queued)--;
1320 return vir_MOV(c, vpm);
1321 }
1322
1323 uint32_t num_components = MIN2(*remaining, 32);
1324
1325 v3d33_vir_vpm_read_setup(c, num_components);
1326
1327 *num_components_queued = num_components - 1;
1328 *remaining -= num_components;
1329
1330 return vir_MOV(c, vpm);
1331 }
1332
1333 static void
1334 ntq_setup_vpm_inputs(struct v3d_compile *c)
1335 {
1336 /* Figure out how many components of each vertex attribute the shader
1337 * uses. Each variable should have been split to individual
1338 * components and unused ones DCEed. The vertex fetcher will load
1339 * from the start of the attribute to the number of components we
1340 * declare we need in c->vattr_sizes[].
1341 */
1342 nir_foreach_variable(var, &c->s->inputs) {
1343 /* No VS attribute array support. */
1344 assert(MAX2(glsl_get_length(var->type), 1) == 1);
1345
1346 unsigned loc = var->data.driver_location;
1347 int start_component = var->data.location_frac;
1348 int num_components = glsl_get_components(var->type);
1349
1350 c->vattr_sizes[loc] = MAX2(c->vattr_sizes[loc],
1351 start_component + num_components);
1352 }
1353
1354 unsigned num_components = 0;
1355 uint32_t vpm_components_queued = 0;
1356 bool uses_iid = c->s->info.system_values_read &
1357 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1358 bool uses_vid = c->s->info.system_values_read &
1359 (1ull << SYSTEM_VALUE_VERTEX_ID);
1360 num_components += uses_iid;
1361 num_components += uses_vid;
1362
1363 for (int i = 0; i < ARRAY_SIZE(c->vattr_sizes); i++)
1364 num_components += c->vattr_sizes[i];
1365
1366 if (uses_iid) {
1367 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1368 &num_components, ~0);
1369 }
1370
1371 if (uses_vid) {
1372 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1373 &num_components, ~0);
1374 }
1375
1376 /* The actual loads will happen directly in nir_intrinsic_load_input
1377 * on newer versions.
1378 */
1379 if (c->devinfo->ver >= 40)
1380 return;
1381
1382 for (int loc = 0; loc < ARRAY_SIZE(c->vattr_sizes); loc++) {
1383 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1384 (loc + 1) * 4);
1385
1386 for (int i = 0; i < c->vattr_sizes[loc]; i++) {
1387 c->inputs[loc * 4 + i] =
1388 ntq_emit_vpm_read(c,
1389 &vpm_components_queued,
1390 &num_components,
1391 loc * 4 + i);
1392
1393 }
1394 }
1395
1396 if (c->devinfo->ver >= 40) {
1397 assert(vpm_components_queued == num_components);
1398 } else {
1399 assert(vpm_components_queued == 0);
1400 assert(num_components == 0);
1401 }
1402 }
1403
1404 static void
1405 ntq_setup_fs_inputs(struct v3d_compile *c)
1406 {
1407 unsigned num_entries = 0;
1408 unsigned num_components = 0;
1409 nir_foreach_variable(var, &c->s->inputs) {
1410 num_entries++;
1411 num_components += glsl_get_components(var->type);
1412 }
1413
1414 nir_variable *vars[num_entries];
1415
1416 unsigned i = 0;
1417 nir_foreach_variable(var, &c->s->inputs)
1418 vars[i++] = var;
1419
1420 /* Sort the variables so that we emit the input setup in
1421 * driver_location order. This is required for VPM reads, whose data
1422 * is fetched into the VPM in driver_location (TGSI register index)
1423 * order.
1424 */
1425 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1426
1427 for (unsigned i = 0; i < num_entries; i++) {
1428 nir_variable *var = vars[i];
1429 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1430 unsigned loc = var->data.driver_location;
1431
1432 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1433 (loc + array_len) * 4);
1434
1435 if (var->data.location == VARYING_SLOT_POS) {
1436 emit_fragcoord_input(c, loc);
1437 } else if (var->data.location == VARYING_SLOT_PNTC ||
1438 (var->data.location >= VARYING_SLOT_VAR0 &&
1439 (c->fs_key->point_sprite_mask &
1440 (1 << (var->data.location -
1441 VARYING_SLOT_VAR0))))) {
1442 c->inputs[loc * 4 + 0] = c->point_x;
1443 c->inputs[loc * 4 + 1] = c->point_y;
1444 } else {
1445 for (int j = 0; j < array_len; j++)
1446 emit_fragment_input(c, loc + j, var, j);
1447 }
1448 }
1449 }
1450
1451 static void
1452 ntq_setup_outputs(struct v3d_compile *c)
1453 {
1454 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
1455 return;
1456
1457 nir_foreach_variable(var, &c->s->outputs) {
1458 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1459 unsigned loc = var->data.driver_location * 4;
1460
1461 assert(array_len == 1);
1462 (void)array_len;
1463
1464 for (int i = 0; i < 4 - var->data.location_frac; i++) {
1465 add_output(c, loc + var->data.location_frac + i,
1466 var->data.location,
1467 var->data.location_frac + i);
1468 }
1469
1470 switch (var->data.location) {
1471 case FRAG_RESULT_COLOR:
1472 c->output_color_var[0] = var;
1473 c->output_color_var[1] = var;
1474 c->output_color_var[2] = var;
1475 c->output_color_var[3] = var;
1476 break;
1477 case FRAG_RESULT_DATA0:
1478 case FRAG_RESULT_DATA1:
1479 case FRAG_RESULT_DATA2:
1480 case FRAG_RESULT_DATA3:
1481 c->output_color_var[var->data.location -
1482 FRAG_RESULT_DATA0] = var;
1483 break;
1484 case FRAG_RESULT_DEPTH:
1485 c->output_position_index = loc;
1486 break;
1487 case FRAG_RESULT_SAMPLE_MASK:
1488 c->output_sample_mask_index = loc;
1489 break;
1490 }
1491 }
1492 }
1493
1494 /**
1495 * Sets up the mapping from nir_register to struct qreg *.
1496 *
1497 * Each nir_register gets a struct qreg per 32-bit component being stored.
1498 */
1499 static void
1500 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1501 {
1502 foreach_list_typed(nir_register, nir_reg, node, list) {
1503 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1504 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1505 array_len *
1506 nir_reg->num_components);
1507
1508 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1509
1510 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1511 qregs[i] = vir_get_temp(c);
1512 }
1513 }
1514
1515 static void
1516 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1517 {
1518 /* XXX perf: Experiment with using immediate loads to avoid having
1519 * these end up in the uniform stream. Watch out for breaking the
1520 * small immediates optimization in the process!
1521 */
1522 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1523 for (int i = 0; i < instr->def.num_components; i++)
1524 qregs[i] = vir_uniform_ui(c, instr->value.u32[i]);
1525
1526 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1527 }
1528
1529 static void
1530 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1531 {
1532 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1533
1534 /* VIR needs there to be *some* value, so pick 0 (same as for
1535 * ntq_setup_registers().
1536 */
1537 for (int i = 0; i < instr->def.num_components; i++)
1538 qregs[i] = vir_uniform_ui(c, 0);
1539 }
1540
1541 static void
1542 ntq_emit_image_size(struct v3d_compile *c, nir_intrinsic_instr *instr)
1543 {
1544 assert(instr->intrinsic == nir_intrinsic_image_deref_size);
1545 nir_variable *var = nir_intrinsic_get_var(instr, 0);
1546 unsigned image_index = var->data.driver_location;
1547 const struct glsl_type *sampler_type = glsl_without_array(var->type);
1548 bool is_array = glsl_sampler_type_is_array(sampler_type);
1549
1550 ntq_store_dest(c, &instr->dest, 0,
1551 vir_uniform(c, QUNIFORM_IMAGE_WIDTH, image_index));
1552 if (instr->num_components > 1) {
1553 ntq_store_dest(c, &instr->dest, 1,
1554 vir_uniform(c, QUNIFORM_IMAGE_HEIGHT,
1555 image_index));
1556 }
1557 if (instr->num_components > 2) {
1558 ntq_store_dest(c, &instr->dest, 2,
1559 vir_uniform(c,
1560 is_array ?
1561 QUNIFORM_IMAGE_ARRAY_SIZE :
1562 QUNIFORM_IMAGE_DEPTH,
1563 image_index));
1564 }
1565 }
1566
1567 static void
1568 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
1569 {
1570 unsigned offset;
1571
1572 switch (instr->intrinsic) {
1573 case nir_intrinsic_load_uniform:
1574 if (nir_src_is_const(instr->src[0])) {
1575 int offset = (nir_intrinsic_base(instr) +
1576 nir_src_as_uint(instr->src[0]));
1577 assert(offset % 4 == 0);
1578 /* We need dwords */
1579 offset = offset / 4;
1580 for (int i = 0; i < instr->num_components; i++) {
1581 ntq_store_dest(c, &instr->dest, i,
1582 vir_uniform(c, QUNIFORM_UNIFORM,
1583 offset + i));
1584 }
1585 } else {
1586 ntq_emit_tmu_general(c, instr, false);
1587 }
1588 break;
1589
1590 case nir_intrinsic_load_ubo:
1591 ntq_emit_tmu_general(c, instr, false);
1592 break;
1593
1594 case nir_intrinsic_ssbo_atomic_add:
1595 case nir_intrinsic_ssbo_atomic_imin:
1596 case nir_intrinsic_ssbo_atomic_umin:
1597 case nir_intrinsic_ssbo_atomic_imax:
1598 case nir_intrinsic_ssbo_atomic_umax:
1599 case nir_intrinsic_ssbo_atomic_and:
1600 case nir_intrinsic_ssbo_atomic_or:
1601 case nir_intrinsic_ssbo_atomic_xor:
1602 case nir_intrinsic_ssbo_atomic_exchange:
1603 case nir_intrinsic_ssbo_atomic_comp_swap:
1604 case nir_intrinsic_load_ssbo:
1605 case nir_intrinsic_store_ssbo:
1606 ntq_emit_tmu_general(c, instr, false);
1607 break;
1608
1609 case nir_intrinsic_shared_atomic_add:
1610 case nir_intrinsic_shared_atomic_imin:
1611 case nir_intrinsic_shared_atomic_umin:
1612 case nir_intrinsic_shared_atomic_imax:
1613 case nir_intrinsic_shared_atomic_umax:
1614 case nir_intrinsic_shared_atomic_and:
1615 case nir_intrinsic_shared_atomic_or:
1616 case nir_intrinsic_shared_atomic_xor:
1617 case nir_intrinsic_shared_atomic_exchange:
1618 case nir_intrinsic_shared_atomic_comp_swap:
1619 case nir_intrinsic_load_shared:
1620 case nir_intrinsic_store_shared:
1621 ntq_emit_tmu_general(c, instr, true);
1622 break;
1623
1624 case nir_intrinsic_image_deref_load:
1625 case nir_intrinsic_image_deref_store:
1626 case nir_intrinsic_image_deref_atomic_add:
1627 case nir_intrinsic_image_deref_atomic_min:
1628 case nir_intrinsic_image_deref_atomic_max:
1629 case nir_intrinsic_image_deref_atomic_and:
1630 case nir_intrinsic_image_deref_atomic_or:
1631 case nir_intrinsic_image_deref_atomic_xor:
1632 case nir_intrinsic_image_deref_atomic_exchange:
1633 case nir_intrinsic_image_deref_atomic_comp_swap:
1634 v3d40_vir_emit_image_load_store(c, instr);
1635 break;
1636
1637 case nir_intrinsic_get_buffer_size:
1638 ntq_store_dest(c, &instr->dest, 0,
1639 vir_uniform(c, QUNIFORM_GET_BUFFER_SIZE,
1640 nir_src_as_uint(instr->src[0])));
1641 break;
1642
1643 case nir_intrinsic_load_user_clip_plane:
1644 for (int i = 0; i < instr->num_components; i++) {
1645 ntq_store_dest(c, &instr->dest, i,
1646 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1647 nir_intrinsic_ucp_id(instr) *
1648 4 + i));
1649 }
1650 break;
1651
1652 case nir_intrinsic_load_viewport_x_scale:
1653 ntq_store_dest(c, &instr->dest, 0,
1654 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE, 0));
1655 break;
1656
1657 case nir_intrinsic_load_viewport_y_scale:
1658 ntq_store_dest(c, &instr->dest, 0,
1659 vir_uniform(c, QUNIFORM_VIEWPORT_Y_SCALE, 0));
1660 break;
1661
1662 case nir_intrinsic_load_viewport_z_scale:
1663 ntq_store_dest(c, &instr->dest, 0,
1664 vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0));
1665 break;
1666
1667 case nir_intrinsic_load_viewport_z_offset:
1668 ntq_store_dest(c, &instr->dest, 0,
1669 vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0));
1670 break;
1671
1672 case nir_intrinsic_load_alpha_ref_float:
1673 ntq_store_dest(c, &instr->dest, 0,
1674 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1675 break;
1676
1677 case nir_intrinsic_load_sample_mask_in:
1678 ntq_store_dest(c, &instr->dest, 0, vir_MSF(c));
1679 break;
1680
1681 case nir_intrinsic_load_helper_invocation:
1682 vir_set_pf(vir_MSF_dest(c, vir_nop_reg()), V3D_QPU_PF_PUSHZ);
1683 ntq_store_dest(c, &instr->dest, 0,
1684 vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1685 vir_uniform_ui(c, ~0),
1686 vir_uniform_ui(c, 0))));
1687 break;
1688
1689 case nir_intrinsic_load_front_face:
1690 /* The register contains 0 (front) or 1 (back), and we need to
1691 * turn it into a NIR bool where true means front.
1692 */
1693 ntq_store_dest(c, &instr->dest, 0,
1694 vir_ADD(c,
1695 vir_uniform_ui(c, -1),
1696 vir_REVF(c)));
1697 break;
1698
1699 case nir_intrinsic_load_instance_id:
1700 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
1701 break;
1702
1703 case nir_intrinsic_load_vertex_id:
1704 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
1705 break;
1706
1707 case nir_intrinsic_load_input:
1708 offset = (nir_intrinsic_base(instr) +
1709 nir_src_as_uint(instr->src[0]));
1710 if (c->s->info.stage != MESA_SHADER_FRAGMENT &&
1711 c->devinfo->ver >= 40) {
1712 /* Emit the LDVPM directly now, rather than at the top
1713 * of the shader like we did for V3D 3.x (which needs
1714 * vpmsetup when not just taking the next offset).
1715 *
1716 * Note that delaying like this may introduce stalls,
1717 * as LDVPMV takes a minimum of 1 instruction but may
1718 * be slower if the VPM unit is busy with another QPU.
1719 */
1720 int index = 0;
1721 if (c->s->info.system_values_read &
1722 (1ull << SYSTEM_VALUE_INSTANCE_ID)) {
1723 index++;
1724 }
1725 if (c->s->info.system_values_read &
1726 (1ull << SYSTEM_VALUE_VERTEX_ID)) {
1727 index++;
1728 }
1729 for (int i = 0; i < offset; i++)
1730 index += c->vattr_sizes[i];
1731 index += nir_intrinsic_component(instr);
1732 for (int i = 0; i < instr->num_components; i++) {
1733 struct qreg vpm_offset =
1734 vir_uniform_ui(c, index++);
1735 ntq_store_dest(c, &instr->dest, i,
1736 vir_LDVPMV_IN(c, vpm_offset));
1737 }
1738 } else {
1739 for (int i = 0; i < instr->num_components; i++) {
1740 int comp = nir_intrinsic_component(instr) + i;
1741 ntq_store_dest(c, &instr->dest, i,
1742 vir_MOV(c, c->inputs[offset * 4 +
1743 comp]));
1744 }
1745 }
1746 break;
1747
1748 case nir_intrinsic_store_output:
1749 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1750 offset = ((nir_intrinsic_base(instr) +
1751 nir_src_as_uint(instr->src[1])) * 4 +
1752 nir_intrinsic_component(instr));
1753 for (int i = 0; i < instr->num_components; i++) {
1754 c->outputs[offset + i] =
1755 vir_MOV(c,
1756 ntq_get_src(c,
1757 instr->src[0], i));
1758 }
1759 } else {
1760 assert(instr->num_components == 1);
1761
1762 vir_VPM_WRITE(c,
1763 ntq_get_src(c, instr->src[0], 0),
1764 nir_intrinsic_base(instr));
1765 }
1766 break;
1767
1768 case nir_intrinsic_image_deref_size:
1769 ntq_emit_image_size(c, instr);
1770 break;
1771
1772 case nir_intrinsic_discard:
1773 if (vir_in_nonuniform_control_flow(c)) {
1774 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
1775 V3D_QPU_PF_PUSHZ);
1776 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
1777 vir_uniform_ui(c, 0)),
1778 V3D_QPU_COND_IFA);
1779 } else {
1780 vir_SETMSF_dest(c, vir_nop_reg(),
1781 vir_uniform_ui(c, 0));
1782 }
1783 break;
1784
1785 case nir_intrinsic_discard_if: {
1786 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, instr->src[0]);
1787
1788 if (vir_in_nonuniform_control_flow(c)) {
1789 struct qinst *exec_flag = vir_MOV_dest(c, vir_nop_reg(),
1790 c->execute);
1791 if (cond == V3D_QPU_COND_IFA) {
1792 vir_set_uf(exec_flag, V3D_QPU_UF_ANDZ);
1793 } else {
1794 vir_set_uf(exec_flag, V3D_QPU_UF_NORNZ);
1795 cond = V3D_QPU_COND_IFA;
1796 }
1797 }
1798
1799 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
1800 vir_uniform_ui(c, 0)), cond);
1801
1802 break;
1803 }
1804
1805 case nir_intrinsic_memory_barrier:
1806 case nir_intrinsic_memory_barrier_atomic_counter:
1807 case nir_intrinsic_memory_barrier_buffer:
1808 case nir_intrinsic_memory_barrier_image:
1809 case nir_intrinsic_memory_barrier_shared:
1810 /* We don't do any instruction scheduling of these NIR
1811 * instructions between each other, so we just need to make
1812 * sure that the TMU operations before the barrier are flushed
1813 * before the ones after the barrier. That is currently
1814 * handled by having a THRSW in each of them and a LDTMU
1815 * series or a TMUWT after.
1816 */
1817 break;
1818
1819 case nir_intrinsic_barrier:
1820 /* Emit a TSY op to get all invocations in the workgroup
1821 * (actually supergroup) to block until the last invocation
1822 * reaches the TSY op.
1823 */
1824 if (c->devinfo->ver >= 42) {
1825 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
1826 V3D_QPU_WADDR_SYNCB));
1827 } else {
1828 struct qinst *sync =
1829 vir_BARRIERID_dest(c,
1830 vir_reg(QFILE_MAGIC,
1831 V3D_QPU_WADDR_SYNCU));
1832 sync->uniform =
1833 vir_get_uniform_index(c, QUNIFORM_CONSTANT,
1834 0xffffff00 |
1835 V3D_TSY_WAIT_INC_CHECK);
1836
1837 }
1838
1839 /* The blocking of a TSY op only happens at the next thread
1840 * switch. No texturing may be outstanding at the time of a
1841 * TSY blocking operation.
1842 */
1843 vir_emit_thrsw(c);
1844 break;
1845
1846 case nir_intrinsic_load_num_work_groups:
1847 for (int i = 0; i < 3; i++) {
1848 ntq_store_dest(c, &instr->dest, i,
1849 vir_uniform(c, QUNIFORM_NUM_WORK_GROUPS,
1850 i));
1851 }
1852 break;
1853
1854 case nir_intrinsic_load_local_invocation_index:
1855 ntq_store_dest(c, &instr->dest, 0,
1856 vir_SHR(c, c->cs_payload[1],
1857 vir_uniform_ui(c, 32 - c->local_invocation_index_bits)));
1858 break;
1859
1860 case nir_intrinsic_load_work_group_id:
1861 ntq_store_dest(c, &instr->dest, 0,
1862 vir_AND(c, c->cs_payload[0],
1863 vir_uniform_ui(c, 0xffff)));
1864 ntq_store_dest(c, &instr->dest, 1,
1865 vir_SHR(c, c->cs_payload[0],
1866 vir_uniform_ui(c, 16)));
1867 ntq_store_dest(c, &instr->dest, 2,
1868 vir_AND(c, c->cs_payload[1],
1869 vir_uniform_ui(c, 0xffff)));
1870 break;
1871
1872 default:
1873 fprintf(stderr, "Unknown intrinsic: ");
1874 nir_print_instr(&instr->instr, stderr);
1875 fprintf(stderr, "\n");
1876 break;
1877 }
1878 }
1879
1880 /* Clears (activates) the execute flags for any channels whose jump target
1881 * matches this block.
1882 *
1883 * XXX perf: Could we be using flpush/flpop somehow for our execution channel
1884 * enabling?
1885 *
1886 * XXX perf: For uniform control flow, we should be able to skip c->execute
1887 * handling entirely.
1888 */
1889 static void
1890 ntq_activate_execute_for_block(struct v3d_compile *c)
1891 {
1892 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
1893 c->execute, vir_uniform_ui(c, c->cur_block->index)),
1894 V3D_QPU_PF_PUSHZ);
1895
1896 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
1897 }
1898
1899 static void
1900 ntq_emit_uniform_if(struct v3d_compile *c, nir_if *if_stmt)
1901 {
1902 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
1903 bool empty_else_block =
1904 (nir_else_block == nir_if_last_else_block(if_stmt) &&
1905 exec_list_is_empty(&nir_else_block->instr_list));
1906
1907 struct qblock *then_block = vir_new_block(c);
1908 struct qblock *after_block = vir_new_block(c);
1909 struct qblock *else_block;
1910 if (empty_else_block)
1911 else_block = after_block;
1912 else
1913 else_block = vir_new_block(c);
1914
1915 /* Set up the flags for the IF condition (taking the THEN branch). */
1916 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
1917
1918 /* Jump to ELSE. */
1919 vir_BRANCH(c, cond == V3D_QPU_COND_IFA ?
1920 V3D_QPU_BRANCH_COND_ALLNA :
1921 V3D_QPU_BRANCH_COND_ALLA);
1922 vir_link_blocks(c->cur_block, else_block);
1923 vir_link_blocks(c->cur_block, then_block);
1924
1925 /* Process the THEN block. */
1926 vir_set_emit_block(c, then_block);
1927 ntq_emit_cf_list(c, &if_stmt->then_list);
1928
1929 if (!empty_else_block) {
1930 /* At the end of the THEN block, jump to ENDIF */
1931 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALWAYS);
1932 vir_link_blocks(c->cur_block, after_block);
1933
1934 /* Emit the else block. */
1935 vir_set_emit_block(c, else_block);
1936 ntq_activate_execute_for_block(c);
1937 ntq_emit_cf_list(c, &if_stmt->else_list);
1938 }
1939
1940 vir_link_blocks(c->cur_block, after_block);
1941
1942 vir_set_emit_block(c, after_block);
1943 }
1944
1945 static void
1946 ntq_emit_nonuniform_if(struct v3d_compile *c, nir_if *if_stmt)
1947 {
1948 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
1949 bool empty_else_block =
1950 (nir_else_block == nir_if_last_else_block(if_stmt) &&
1951 exec_list_is_empty(&nir_else_block->instr_list));
1952
1953 struct qblock *then_block = vir_new_block(c);
1954 struct qblock *after_block = vir_new_block(c);
1955 struct qblock *else_block;
1956 if (empty_else_block)
1957 else_block = after_block;
1958 else
1959 else_block = vir_new_block(c);
1960
1961 bool was_uniform_control_flow = false;
1962 if (!vir_in_nonuniform_control_flow(c)) {
1963 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
1964 was_uniform_control_flow = true;
1965 }
1966
1967 /* Set up the flags for the IF condition (taking the THEN branch). */
1968 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
1969
1970 /* Update the flags+cond to mean "Taking the ELSE branch (!cond) and
1971 * was previously active (execute Z) for updating the exec flags.
1972 */
1973 if (was_uniform_control_flow) {
1974 cond = v3d_qpu_cond_invert(cond);
1975 } else {
1976 struct qinst *inst = vir_MOV_dest(c, vir_nop_reg(), c->execute);
1977 if (cond == V3D_QPU_COND_IFA) {
1978 vir_set_uf(inst, V3D_QPU_UF_NORNZ);
1979 } else {
1980 vir_set_uf(inst, V3D_QPU_UF_ANDZ);
1981 cond = V3D_QPU_COND_IFA;
1982 }
1983 }
1984
1985 vir_MOV_cond(c, cond,
1986 c->execute,
1987 vir_uniform_ui(c, else_block->index));
1988
1989 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1990 * through.
1991 */
1992 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ);
1993 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
1994 vir_link_blocks(c->cur_block, else_block);
1995 vir_link_blocks(c->cur_block, then_block);
1996
1997 /* Process the THEN block. */
1998 vir_set_emit_block(c, then_block);
1999 ntq_emit_cf_list(c, &if_stmt->then_list);
2000
2001 if (!empty_else_block) {
2002 /* Handle the end of the THEN block. First, all currently
2003 * active channels update their execute flags to point to
2004 * ENDIF
2005 */
2006 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2007 V3D_QPU_PF_PUSHZ);
2008 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2009 vir_uniform_ui(c, after_block->index));
2010
2011 /* If everything points at ENDIF, then jump there immediately. */
2012 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
2013 c->execute,
2014 vir_uniform_ui(c, after_block->index)),
2015 V3D_QPU_PF_PUSHZ);
2016 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
2017 vir_link_blocks(c->cur_block, after_block);
2018 vir_link_blocks(c->cur_block, else_block);
2019
2020 vir_set_emit_block(c, else_block);
2021 ntq_activate_execute_for_block(c);
2022 ntq_emit_cf_list(c, &if_stmt->else_list);
2023 }
2024
2025 vir_link_blocks(c->cur_block, after_block);
2026
2027 vir_set_emit_block(c, after_block);
2028 if (was_uniform_control_flow)
2029 c->execute = c->undef;
2030 else
2031 ntq_activate_execute_for_block(c);
2032 }
2033
2034 static void
2035 ntq_emit_if(struct v3d_compile *c, nir_if *nif)
2036 {
2037 bool was_in_control_flow = c->in_control_flow;
2038 c->in_control_flow = true;
2039 if (!vir_in_nonuniform_control_flow(c) &&
2040 nir_src_is_dynamically_uniform(nif->condition)) {
2041 ntq_emit_uniform_if(c, nif);
2042 } else {
2043 ntq_emit_nonuniform_if(c, nif);
2044 }
2045 c->in_control_flow = was_in_control_flow;
2046 }
2047
2048 static void
2049 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
2050 {
2051 switch (jump->type) {
2052 case nir_jump_break:
2053 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2054 V3D_QPU_PF_PUSHZ);
2055 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2056 vir_uniform_ui(c, c->loop_break_block->index));
2057 break;
2058
2059 case nir_jump_continue:
2060 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2061 V3D_QPU_PF_PUSHZ);
2062 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2063 vir_uniform_ui(c, c->loop_cont_block->index));
2064 break;
2065
2066 case nir_jump_return:
2067 unreachable("All returns shouold be lowered\n");
2068 }
2069 }
2070
2071 static void
2072 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
2073 {
2074 switch (instr->type) {
2075 case nir_instr_type_deref:
2076 /* ignored, will be walked by the intrinsic using it. */
2077 break;
2078
2079 case nir_instr_type_alu:
2080 ntq_emit_alu(c, nir_instr_as_alu(instr));
2081 break;
2082
2083 case nir_instr_type_intrinsic:
2084 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
2085 break;
2086
2087 case nir_instr_type_load_const:
2088 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
2089 break;
2090
2091 case nir_instr_type_ssa_undef:
2092 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
2093 break;
2094
2095 case nir_instr_type_tex:
2096 ntq_emit_tex(c, nir_instr_as_tex(instr));
2097 break;
2098
2099 case nir_instr_type_jump:
2100 ntq_emit_jump(c, nir_instr_as_jump(instr));
2101 break;
2102
2103 default:
2104 fprintf(stderr, "Unknown NIR instr type: ");
2105 nir_print_instr(instr, stderr);
2106 fprintf(stderr, "\n");
2107 abort();
2108 }
2109 }
2110
2111 static void
2112 ntq_emit_block(struct v3d_compile *c, nir_block *block)
2113 {
2114 nir_foreach_instr(instr, block) {
2115 ntq_emit_instr(c, instr);
2116 }
2117 }
2118
2119 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
2120
2121 static void
2122 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
2123 {
2124 bool was_in_control_flow = c->in_control_flow;
2125 c->in_control_flow = true;
2126
2127 bool was_uniform_control_flow = false;
2128 if (!vir_in_nonuniform_control_flow(c)) {
2129 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2130 was_uniform_control_flow = true;
2131 }
2132
2133 struct qblock *save_loop_cont_block = c->loop_cont_block;
2134 struct qblock *save_loop_break_block = c->loop_break_block;
2135
2136 c->loop_cont_block = vir_new_block(c);
2137 c->loop_break_block = vir_new_block(c);
2138
2139 vir_link_blocks(c->cur_block, c->loop_cont_block);
2140 vir_set_emit_block(c, c->loop_cont_block);
2141 ntq_activate_execute_for_block(c);
2142
2143 ntq_emit_cf_list(c, &loop->body);
2144
2145 /* Re-enable any previous continues now, so our ANYA check below
2146 * works.
2147 *
2148 * XXX: Use the .ORZ flags update, instead.
2149 */
2150 vir_set_pf(vir_XOR_dest(c,
2151 vir_nop_reg(),
2152 c->execute,
2153 vir_uniform_ui(c, c->loop_cont_block->index)),
2154 V3D_QPU_PF_PUSHZ);
2155 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2156
2157 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ);
2158
2159 struct qinst *branch = vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
2160 /* Pixels that were not dispatched or have been discarded should not
2161 * contribute to looping again.
2162 */
2163 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P;
2164 vir_link_blocks(c->cur_block, c->loop_cont_block);
2165 vir_link_blocks(c->cur_block, c->loop_break_block);
2166
2167 vir_set_emit_block(c, c->loop_break_block);
2168 if (was_uniform_control_flow)
2169 c->execute = c->undef;
2170 else
2171 ntq_activate_execute_for_block(c);
2172
2173 c->loop_break_block = save_loop_break_block;
2174 c->loop_cont_block = save_loop_cont_block;
2175
2176 c->loops++;
2177
2178 c->in_control_flow = was_in_control_flow;
2179 }
2180
2181 static void
2182 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
2183 {
2184 fprintf(stderr, "FUNCTIONS not handled.\n");
2185 abort();
2186 }
2187
2188 static void
2189 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
2190 {
2191 foreach_list_typed(nir_cf_node, node, node, list) {
2192 switch (node->type) {
2193 case nir_cf_node_block:
2194 ntq_emit_block(c, nir_cf_node_as_block(node));
2195 break;
2196
2197 case nir_cf_node_if:
2198 ntq_emit_if(c, nir_cf_node_as_if(node));
2199 break;
2200
2201 case nir_cf_node_loop:
2202 ntq_emit_loop(c, nir_cf_node_as_loop(node));
2203 break;
2204
2205 case nir_cf_node_function:
2206 ntq_emit_function(c, nir_cf_node_as_function(node));
2207 break;
2208
2209 default:
2210 fprintf(stderr, "Unknown NIR node type\n");
2211 abort();
2212 }
2213 }
2214 }
2215
2216 static void
2217 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
2218 {
2219 ntq_setup_registers(c, &impl->registers);
2220 ntq_emit_cf_list(c, &impl->body);
2221 }
2222
2223 static void
2224 nir_to_vir(struct v3d_compile *c)
2225 {
2226 switch (c->s->info.stage) {
2227 case MESA_SHADER_FRAGMENT:
2228 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
2229 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
2230 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
2231
2232 /* XXX perf: We could set the "disable implicit point/line
2233 * varyings" field in the shader record and not emit these, if
2234 * they're not going to be used.
2235 */
2236 if (c->fs_key->is_points) {
2237 c->point_x = emit_fragment_varying(c, NULL, 0, 0);
2238 c->point_y = emit_fragment_varying(c, NULL, 0, 0);
2239 } else if (c->fs_key->is_lines) {
2240 c->line_x = emit_fragment_varying(c, NULL, 0, 0);
2241 }
2242 break;
2243 case MESA_SHADER_COMPUTE:
2244 /* Set up the TSO for barriers, assuming we do some. */
2245 if (c->devinfo->ver < 42) {
2246 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
2247 V3D_QPU_WADDR_SYNC));
2248 }
2249
2250 if (c->s->info.system_values_read &
2251 ((1ull << SYSTEM_VALUE_LOCAL_INVOCATION_INDEX) |
2252 (1ull << SYSTEM_VALUE_WORK_GROUP_ID))) {
2253 c->cs_payload[0] = vir_MOV(c, vir_reg(QFILE_REG, 0));
2254 }
2255 if ((c->s->info.system_values_read &
2256 ((1ull << SYSTEM_VALUE_WORK_GROUP_ID))) ||
2257 c->s->info.cs.shared_size) {
2258 c->cs_payload[1] = vir_MOV(c, vir_reg(QFILE_REG, 2));
2259 }
2260
2261 /* Set up the division between gl_LocalInvocationIndex and
2262 * wg_in_mem in the payload reg.
2263 */
2264 int wg_size = (c->s->info.cs.local_size[0] *
2265 c->s->info.cs.local_size[1] *
2266 c->s->info.cs.local_size[2]);
2267 c->local_invocation_index_bits =
2268 ffs(util_next_power_of_two(MAX2(wg_size, 64))) - 1;
2269 assert(c->local_invocation_index_bits <= 8);
2270
2271 if (c->s->info.cs.shared_size) {
2272 struct qreg wg_in_mem = vir_SHR(c, c->cs_payload[1],
2273 vir_uniform_ui(c, 16));
2274 if (c->s->info.cs.local_size[0] != 1 ||
2275 c->s->info.cs.local_size[1] != 1 ||
2276 c->s->info.cs.local_size[2] != 1) {
2277 int wg_bits = (16 -
2278 c->local_invocation_index_bits);
2279 int wg_mask = (1 << wg_bits) - 1;
2280 wg_in_mem = vir_AND(c, wg_in_mem,
2281 vir_uniform_ui(c, wg_mask));
2282 }
2283 struct qreg shared_per_wg =
2284 vir_uniform_ui(c, c->s->info.cs.shared_size);
2285
2286 c->cs_shared_offset =
2287 vir_ADD(c,
2288 vir_uniform(c, QUNIFORM_SHARED_OFFSET,0),
2289 vir_UMUL(c, wg_in_mem, shared_per_wg));
2290 }
2291 break;
2292 default:
2293 break;
2294 }
2295
2296 if (c->s->info.stage == MESA_SHADER_FRAGMENT)
2297 ntq_setup_fs_inputs(c);
2298 else
2299 ntq_setup_vpm_inputs(c);
2300
2301 ntq_setup_outputs(c);
2302
2303 /* Find the main function and emit the body. */
2304 nir_foreach_function(function, c->s) {
2305 assert(strcmp(function->name, "main") == 0);
2306 assert(function->impl);
2307 ntq_emit_impl(c, function->impl);
2308 }
2309 }
2310
2311 const nir_shader_compiler_options v3d_nir_options = {
2312 .lower_all_io_to_temps = true,
2313 .lower_extract_byte = true,
2314 .lower_extract_word = true,
2315 .lower_bfm = true,
2316 .lower_bitfield_insert_to_shifts = true,
2317 .lower_bitfield_extract_to_shifts = true,
2318 .lower_bitfield_reverse = true,
2319 .lower_bit_count = true,
2320 .lower_cs_local_id_from_index = true,
2321 .lower_ffract = true,
2322 .lower_pack_unorm_2x16 = true,
2323 .lower_pack_snorm_2x16 = true,
2324 .lower_pack_unorm_4x8 = true,
2325 .lower_pack_snorm_4x8 = true,
2326 .lower_unpack_unorm_4x8 = true,
2327 .lower_unpack_snorm_4x8 = true,
2328 .lower_pack_half_2x16 = true,
2329 .lower_unpack_half_2x16 = true,
2330 .lower_fdiv = true,
2331 .lower_find_lsb = true,
2332 .lower_ffma = true,
2333 .lower_flrp32 = true,
2334 .lower_fpow = true,
2335 .lower_fsat = true,
2336 .lower_fsqrt = true,
2337 .lower_ifind_msb = true,
2338 .lower_isign = true,
2339 .lower_ldexp = true,
2340 .lower_mul_high = true,
2341 .lower_wpos_pntc = true,
2342 .native_integers = true,
2343 };
2344
2345 /**
2346 * When demoting a shader down to single-threaded, removes the THRSW
2347 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
2348 * program end).
2349 */
2350 static void
2351 vir_remove_thrsw(struct v3d_compile *c)
2352 {
2353 vir_for_each_block(block, c) {
2354 vir_for_each_inst_safe(inst, block) {
2355 if (inst->qpu.sig.thrsw)
2356 vir_remove_instruction(c, inst);
2357 }
2358 }
2359
2360 c->last_thrsw = NULL;
2361 }
2362
2363 void
2364 vir_emit_last_thrsw(struct v3d_compile *c)
2365 {
2366 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
2367 * switching, so disable threads if we didn't do any TMU ops (each of
2368 * which would have emitted a THRSW).
2369 */
2370 if (!c->last_thrsw_at_top_level && c->devinfo->ver < 41) {
2371 c->threads = 1;
2372 if (c->last_thrsw)
2373 vir_remove_thrsw(c);
2374 return;
2375 }
2376
2377 /* If we're threaded and the last THRSW was in conditional code, then
2378 * we need to emit another one so that we can flag it as the last
2379 * thrsw.
2380 */
2381 if (c->last_thrsw && !c->last_thrsw_at_top_level) {
2382 assert(c->devinfo->ver >= 41);
2383 vir_emit_thrsw(c);
2384 }
2385
2386 /* If we're threaded, then we need to mark the last THRSW instruction
2387 * so we can emit a pair of them at QPU emit time.
2388 *
2389 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2390 * post-last-THRSW state, so we can skip this.
2391 */
2392 if (!c->last_thrsw && c->s->info.stage == MESA_SHADER_FRAGMENT) {
2393 assert(c->devinfo->ver >= 41);
2394 vir_emit_thrsw(c);
2395 }
2396
2397 if (c->last_thrsw)
2398 c->last_thrsw->is_last_thrsw = true;
2399 }
2400
2401 /* There's a flag in the shader for "center W is needed for reasons other than
2402 * non-centroid varyings", so we just walk the program after VIR optimization
2403 * to see if it's used. It should be harmless to set even if we only use
2404 * center W for varyings.
2405 */
2406 static void
2407 vir_check_payload_w(struct v3d_compile *c)
2408 {
2409 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
2410 return;
2411
2412 vir_for_each_inst_inorder(inst, c) {
2413 for (int i = 0; i < vir_get_nsrc(inst); i++) {
2414 if (inst->src[i].file == QFILE_REG &&
2415 inst->src[i].index == 0) {
2416 c->uses_center_w = true;
2417 return;
2418 }
2419 }
2420 }
2421
2422 }
2423
2424 void
2425 v3d_nir_to_vir(struct v3d_compile *c)
2426 {
2427 if (V3D_DEBUG & (V3D_DEBUG_NIR |
2428 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2429 fprintf(stderr, "%s prog %d/%d NIR:\n",
2430 vir_get_stage_name(c),
2431 c->program_id, c->variant_id);
2432 nir_print_shader(c->s, stderr);
2433 }
2434
2435 nir_to_vir(c);
2436
2437 /* Emit the last THRSW before STVPM and TLB writes. */
2438 vir_emit_last_thrsw(c);
2439
2440 switch (c->s->info.stage) {
2441 case MESA_SHADER_FRAGMENT:
2442 emit_frag_end(c);
2443 break;
2444 case MESA_SHADER_VERTEX:
2445 emit_vert_end(c);
2446 break;
2447 default:
2448 unreachable("bad stage");
2449 }
2450
2451 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2452 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2453 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
2454 vir_get_stage_name(c),
2455 c->program_id, c->variant_id);
2456 vir_dump(c);
2457 fprintf(stderr, "\n");
2458 }
2459
2460 vir_optimize(c);
2461
2462 vir_check_payload_w(c);
2463
2464 /* XXX perf: On VC4, we do a VIR-level instruction scheduling here.
2465 * We used that on that platform to pipeline TMU writes and reduce the
2466 * number of thread switches, as well as try (mostly successfully) to
2467 * reduce maximum register pressure to allow more threads. We should
2468 * do something of that sort for V3D -- either instruction scheduling
2469 * here, or delay the the THRSW and LDTMUs from our texture
2470 * instructions until the results are needed.
2471 */
2472
2473 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2474 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2475 fprintf(stderr, "%s prog %d/%d VIR:\n",
2476 vir_get_stage_name(c),
2477 c->program_id, c->variant_id);
2478 vir_dump(c);
2479 fprintf(stderr, "\n");
2480 }
2481
2482 /* Attempt to allocate registers for the temporaries. If we fail,
2483 * reduce thread count and try again.
2484 */
2485 int min_threads = (c->devinfo->ver >= 41) ? 2 : 1;
2486 struct qpu_reg *temp_registers;
2487 while (true) {
2488 bool spilled;
2489 temp_registers = v3d_register_allocate(c, &spilled);
2490 if (spilled)
2491 continue;
2492
2493 if (temp_registers)
2494 break;
2495
2496 if (c->threads == min_threads) {
2497 fprintf(stderr, "Failed to register allocate at %d threads:\n",
2498 c->threads);
2499 vir_dump(c);
2500 c->failed = true;
2501 return;
2502 }
2503
2504 c->threads /= 2;
2505
2506 if (c->threads == 1)
2507 vir_remove_thrsw(c);
2508 }
2509
2510 if (c->spill_size &&
2511 (V3D_DEBUG & (V3D_DEBUG_VIR |
2512 v3d_debug_flag_for_shader_stage(c->s->info.stage)))) {
2513 fprintf(stderr, "%s prog %d/%d spilled VIR:\n",
2514 vir_get_stage_name(c),
2515 c->program_id, c->variant_id);
2516 vir_dump(c);
2517 fprintf(stderr, "\n");
2518 }
2519
2520 v3d_vir_to_qpu(c, temp_registers);
2521 }