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broadcom/vc5: Fix BASE_LEVEL handling with txl.
[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "v3d_compiler.h"
33
34 /* We don't do any address packing. */
35 #define __gen_user_data void
36 #define __gen_address_type uint32_t
37 #define __gen_address_offset(reloc) (*reloc)
38 #define __gen_emit_reloc(cl, reloc)
39 #include "cle/v3d_packet_v33_pack.h"
40
41 static struct qreg
42 ntq_get_src(struct v3d_compile *c, nir_src src, int i);
43 static void
44 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
45
46 static void
47 resize_qreg_array(struct v3d_compile *c,
48 struct qreg **regs,
49 uint32_t *size,
50 uint32_t decl_size)
51 {
52 if (*size >= decl_size)
53 return;
54
55 uint32_t old_size = *size;
56 *size = MAX2(*size * 2, decl_size);
57 *regs = reralloc(c, *regs, struct qreg, *size);
58 if (!*regs) {
59 fprintf(stderr, "Malloc failure\n");
60 abort();
61 }
62
63 for (uint32_t i = old_size; i < *size; i++)
64 (*regs)[i] = c->undef;
65 }
66
67 static struct qreg
68 vir_SFU(struct v3d_compile *c, int waddr, struct qreg src)
69 {
70 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, waddr), src);
71 return vir_FMOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4));
72 }
73
74 static struct qreg
75 vir_LDTMU(struct v3d_compile *c)
76 {
77 vir_NOP(c)->qpu.sig.ldtmu = true;
78 return vir_MOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4));
79 }
80
81 static struct qreg
82 indirect_uniform_load(struct v3d_compile *c, nir_intrinsic_instr *intr)
83 {
84 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
85 uint32_t offset = nir_intrinsic_base(intr);
86 struct v3d_ubo_range *range = NULL;
87 unsigned i;
88
89 for (i = 0; i < c->num_ubo_ranges; i++) {
90 range = &c->ubo_ranges[i];
91 if (offset >= range->src_offset &&
92 offset < range->src_offset + range->size) {
93 break;
94 }
95 }
96 /* The driver-location-based offset always has to be within a declared
97 * uniform range.
98 */
99 assert(i != c->num_ubo_ranges);
100 if (!c->ubo_range_used[i]) {
101 c->ubo_range_used[i] = true;
102 range->dst_offset = c->next_ubo_dst_offset;
103 c->next_ubo_dst_offset += range->size;
104 }
105
106 offset -= range->src_offset;
107
108 if (range->dst_offset + offset != 0) {
109 indirect_offset = vir_ADD(c, indirect_offset,
110 vir_uniform_ui(c, range->dst_offset +
111 offset));
112 }
113
114 /* Adjust for where we stored the TGSI register base. */
115 vir_ADD_dest(c,
116 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA),
117 vir_uniform(c, QUNIFORM_UBO_ADDR, 0),
118 indirect_offset);
119
120 return vir_LDTMU(c);
121 }
122
123 static struct qreg *
124 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
125 {
126 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
127 def->num_components);
128 _mesa_hash_table_insert(c->def_ht, def, qregs);
129 return qregs;
130 }
131
132 /**
133 * This function is responsible for getting VIR results into the associated
134 * storage for a NIR instruction.
135 *
136 * If it's a NIR SSA def, then we just set the associated hash table entry to
137 * the new result.
138 *
139 * If it's a NIR reg, then we need to update the existing qreg assigned to the
140 * NIR destination with the incoming value. To do that without introducing
141 * new MOVs, we require that the incoming qreg either be a uniform, or be
142 * SSA-defined by the previous VIR instruction in the block and rewritable by
143 * this function. That lets us sneak ahead and insert the SF flag beforehand
144 * (knowing that the previous instruction doesn't depend on flags) and rewrite
145 * its destination to be the NIR reg's destination
146 */
147 static void
148 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
149 struct qreg result)
150 {
151 struct qinst *last_inst = NULL;
152 if (!list_empty(&c->cur_block->instructions))
153 last_inst = (struct qinst *)c->cur_block->instructions.prev;
154
155 assert(result.file == QFILE_UNIF ||
156 (result.file == QFILE_TEMP &&
157 last_inst && last_inst == c->defs[result.index]));
158
159 if (dest->is_ssa) {
160 assert(chan < dest->ssa.num_components);
161
162 struct qreg *qregs;
163 struct hash_entry *entry =
164 _mesa_hash_table_search(c->def_ht, &dest->ssa);
165
166 if (entry)
167 qregs = entry->data;
168 else
169 qregs = ntq_init_ssa_def(c, &dest->ssa);
170
171 qregs[chan] = result;
172 } else {
173 nir_register *reg = dest->reg.reg;
174 assert(dest->reg.base_offset == 0);
175 assert(reg->num_array_elems == 0);
176 struct hash_entry *entry =
177 _mesa_hash_table_search(c->def_ht, reg);
178 struct qreg *qregs = entry->data;
179
180 /* Insert a MOV if the source wasn't an SSA def in the
181 * previous instruction.
182 */
183 if (result.file == QFILE_UNIF) {
184 result = vir_MOV(c, result);
185 last_inst = c->defs[result.index];
186 }
187
188 /* We know they're both temps, so just rewrite index. */
189 c->defs[last_inst->dst.index] = NULL;
190 last_inst->dst.index = qregs[chan].index;
191
192 /* If we're in control flow, then make this update of the reg
193 * conditional on the execution mask.
194 */
195 if (c->execute.file != QFILE_NULL) {
196 last_inst->dst.index = qregs[chan].index;
197
198 /* Set the flags to the current exec mask. To insert
199 * the flags push, we temporarily remove our SSA
200 * instruction.
201 */
202 list_del(&last_inst->link);
203 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
204 list_addtail(&last_inst->link,
205 &c->cur_block->instructions);
206
207 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
208 last_inst->cond_is_exec_mask = true;
209 }
210 }
211 }
212
213 static struct qreg
214 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
215 {
216 struct hash_entry *entry;
217 if (src.is_ssa) {
218 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
219 assert(i < src.ssa->num_components);
220 } else {
221 nir_register *reg = src.reg.reg;
222 entry = _mesa_hash_table_search(c->def_ht, reg);
223 assert(reg->num_array_elems == 0);
224 assert(src.reg.base_offset == 0);
225 assert(i < reg->num_components);
226 }
227
228 struct qreg *qregs = entry->data;
229 return qregs[i];
230 }
231
232 static struct qreg
233 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
234 unsigned src)
235 {
236 assert(util_is_power_of_two(instr->dest.write_mask));
237 unsigned chan = ffs(instr->dest.write_mask) - 1;
238 struct qreg r = ntq_get_src(c, instr->src[src].src,
239 instr->src[src].swizzle[chan]);
240
241 assert(!instr->src[src].abs);
242 assert(!instr->src[src].negate);
243
244 return r;
245 };
246
247 static inline struct qreg
248 vir_SAT(struct v3d_compile *c, struct qreg val)
249 {
250 return vir_FMAX(c,
251 vir_FMIN(c, val, vir_uniform_f(c, 1.0)),
252 vir_uniform_f(c, 0.0));
253 }
254
255 static struct qreg
256 ntq_umul(struct v3d_compile *c, struct qreg src0, struct qreg src1)
257 {
258 vir_MULTOP(c, src0, src1);
259 return vir_UMUL24(c, src0, src1);
260 }
261
262 static struct qreg
263 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
264 {
265 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
266 }
267
268 static void
269 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
270 {
271 unsigned unit = instr->texture_index;
272 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
273 int dest_size = nir_tex_instr_dest_size(instr);
274
275 struct qreg lod = c->undef;
276 if (lod_index != -1)
277 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
278
279 for (int i = 0; i < dest_size; i++) {
280 assert(i < 3);
281 enum quniform_contents contents;
282
283 if (instr->is_array && i == dest_size - 1)
284 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
285 else
286 contents = QUNIFORM_TEXTURE_WIDTH + i;
287
288 struct qreg size = vir_uniform(c, contents, unit);
289
290 switch (instr->sampler_dim) {
291 case GLSL_SAMPLER_DIM_1D:
292 case GLSL_SAMPLER_DIM_2D:
293 case GLSL_SAMPLER_DIM_3D:
294 case GLSL_SAMPLER_DIM_CUBE:
295 /* Don't minify the array size. */
296 if (!(instr->is_array && i == dest_size - 1)) {
297 size = ntq_minify(c, size, lod);
298 }
299 break;
300
301 case GLSL_SAMPLER_DIM_RECT:
302 /* There's no LOD field for rects */
303 break;
304
305 default:
306 unreachable("Bad sampler type");
307 }
308
309 ntq_store_dest(c, &instr->dest, i, size);
310 }
311 }
312
313 static void
314 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
315 {
316 unsigned unit = instr->texture_index;
317
318 /* Since each texture sampling op requires uploading uniforms to
319 * reference the texture, there's no HW support for texture size and
320 * you just upload uniforms containing the size.
321 */
322 switch (instr->op) {
323 case nir_texop_query_levels:
324 ntq_store_dest(c, &instr->dest, 0,
325 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
326 return;
327 case nir_texop_txs:
328 ntq_emit_txs(c, instr);
329 return;
330 default:
331 break;
332 }
333
334 struct V3D33_TEXTURE_UNIFORM_PARAMETER_0_CFG_MODE1 p0_unpacked = {
335 V3D33_TEXTURE_UNIFORM_PARAMETER_0_CFG_MODE1_header,
336
337 .fetch_sample_mode = instr->op == nir_texop_txf,
338 };
339
340 switch (instr->sampler_dim) {
341 case GLSL_SAMPLER_DIM_1D:
342 if (instr->is_array)
343 p0_unpacked.lookup_type = TEXTURE_1D_ARRAY;
344 else
345 p0_unpacked.lookup_type = TEXTURE_1D;
346 break;
347 case GLSL_SAMPLER_DIM_2D:
348 case GLSL_SAMPLER_DIM_RECT:
349 if (instr->is_array)
350 p0_unpacked.lookup_type = TEXTURE_2D_ARRAY;
351 else
352 p0_unpacked.lookup_type = TEXTURE_2D;
353 break;
354 case GLSL_SAMPLER_DIM_3D:
355 p0_unpacked.lookup_type = TEXTURE_3D;
356 break;
357 case GLSL_SAMPLER_DIM_CUBE:
358 p0_unpacked.lookup_type = TEXTURE_CUBE_MAP;
359 break;
360 default:
361 unreachable("Bad sampler type");
362 }
363
364 struct qreg coords[5];
365 int next_coord = 0;
366 for (unsigned i = 0; i < instr->num_srcs; i++) {
367 switch (instr->src[i].src_type) {
368 case nir_tex_src_coord:
369 for (int j = 0; j < instr->coord_components; j++) {
370 coords[next_coord++] =
371 ntq_get_src(c, instr->src[i].src, j);
372 }
373 if (instr->coord_components < 2)
374 coords[next_coord++] = vir_uniform_f(c, 0.5);
375 break;
376 case nir_tex_src_bias:
377 coords[next_coord++] =
378 ntq_get_src(c, instr->src[i].src, 0);
379
380 p0_unpacked.bias_supplied = true;
381 break;
382 case nir_tex_src_lod:
383 coords[next_coord++] =
384 vir_FADD(c,
385 ntq_get_src(c, instr->src[i].src, 0),
386 vir_uniform(c, QUNIFORM_TEXTURE_FIRST_LEVEL,
387 unit));
388
389 if (instr->op != nir_texop_txf &&
390 instr->op != nir_texop_tg4) {
391 p0_unpacked.disable_autolod_use_bias_only = true;
392 }
393 break;
394 case nir_tex_src_comparator:
395 coords[next_coord++] =
396 ntq_get_src(c, instr->src[i].src, 0);
397
398 p0_unpacked.shadow = true;
399 break;
400
401 case nir_tex_src_offset: {
402 nir_const_value *offset =
403 nir_src_as_const_value(instr->src[i].src);
404 p0_unpacked.texel_offset_for_s_coordinate =
405 offset->i32[0];
406
407 if (instr->coord_components >= 2)
408 p0_unpacked.texel_offset_for_t_coordinate =
409 offset->i32[1];
410
411 if (instr->coord_components >= 3)
412 p0_unpacked.texel_offset_for_r_coordinate =
413 offset->i32[2];
414 break;
415 }
416
417 default:
418 unreachable("unknown texture source");
419 }
420 }
421
422 uint32_t p0_packed;
423 V3D33_TEXTURE_UNIFORM_PARAMETER_0_CFG_MODE1_pack(NULL,
424 (uint8_t *)&p0_packed,
425 &p0_unpacked);
426
427 /* There is no native support for GL texture rectangle coordinates, so
428 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
429 * 1]).
430 */
431 if (instr->sampler_dim == GLSL_SAMPLER_DIM_RECT) {
432 coords[0] = vir_FMUL(c, coords[0],
433 vir_uniform(c, QUNIFORM_TEXRECT_SCALE_X,
434 unit));
435 coords[1] = vir_FMUL(c, coords[1],
436 vir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y,
437 unit));
438 }
439
440 struct qreg texture_u[] = {
441 vir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0_0 + unit, p0_packed),
442 vir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
443 };
444 uint32_t next_texture_u = 0;
445
446 for (int i = 0; i < next_coord; i++) {
447 struct qreg dst;
448
449 if (i == next_coord - 1)
450 dst = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUL);
451 else
452 dst = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMU);
453
454 struct qinst *tmu = vir_MOV_dest(c, dst, coords[i]);
455
456 if (i < 2) {
457 tmu->has_implicit_uniform = true;
458 tmu->src[vir_get_implicit_uniform_src(tmu)] =
459 texture_u[next_texture_u++];
460 }
461 }
462
463 bool return_16 = (c->key->tex[unit].return_size == 16 ||
464 p0_unpacked.shadow);
465
466 struct qreg return_values[4];
467 for (int i = 0; i < c->key->tex[unit].return_channels; i++)
468 return_values[i] = vir_LDTMU(c);
469 /* Swizzling .zw of an RG texture should give undefined results, not
470 * crash the compiler.
471 */
472 for (int i = c->key->tex[unit].return_channels; i < 4; i++)
473 return_values[i] = c->undef;
474
475 for (int i = 0; i < nir_tex_instr_dest_size(instr); i++) {
476 struct qreg chan;
477
478 if (return_16) {
479 STATIC_ASSERT(PIPE_SWIZZLE_X == 0);
480 chan = return_values[i / 2];
481
482 if (nir_alu_type_get_base_type(instr->dest_type) ==
483 nir_type_float) {
484 enum v3d_qpu_input_unpack unpack;
485 if (i & 1)
486 unpack = V3D_QPU_UNPACK_H;
487 else
488 unpack = V3D_QPU_UNPACK_L;
489
490 chan = vir_FMOV(c, chan);
491 vir_set_unpack(c->defs[chan.index], 0, unpack);
492 } else {
493 /* If we're unpacking the low field, shift it
494 * up to the top first.
495 */
496 if ((i & 1) == 0) {
497 chan = vir_SHL(c, chan,
498 vir_uniform_ui(c, 16));
499 }
500
501 /* Do proper sign extension to a 32-bit int. */
502 if (nir_alu_type_get_base_type(instr->dest_type) ==
503 nir_type_int) {
504 chan = vir_ASR(c, chan,
505 vir_uniform_ui(c, 16));
506 } else {
507 chan = vir_SHR(c, chan,
508 vir_uniform_ui(c, 16));
509 }
510 }
511 } else {
512 chan = vir_MOV(c, return_values[i]);
513 }
514 ntq_store_dest(c, &instr->dest, i, chan);
515 }
516 }
517
518 static struct qreg
519 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
520 {
521 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
522 if (is_cos)
523 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
524
525 struct qreg periods = vir_FROUND(c, input);
526 struct qreg sin_output = vir_SFU(c, V3D_QPU_WADDR_SIN,
527 vir_FSUB(c, input, periods));
528 return vir_XOR(c, sin_output, vir_SHL(c,
529 vir_FTOIN(c, periods),
530 vir_uniform_ui(c, -1)));
531 }
532
533 static struct qreg
534 ntq_fsign(struct v3d_compile *c, struct qreg src)
535 {
536 struct qreg t = vir_get_temp(c);
537
538 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
539 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHZ);
540 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
541 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHN);
542 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
543 return vir_MOV(c, t);
544 }
545
546 static struct qreg
547 ntq_isign(struct v3d_compile *c, struct qreg src)
548 {
549 struct qreg t = vir_get_temp(c);
550
551 vir_MOV_dest(c, t, vir_uniform_ui(c, 0));
552 vir_PF(c, vir_MOV(c, src), V3D_QPU_PF_PUSHZ);
553 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_ui(c, 1));
554 vir_PF(c, vir_MOV(c, src), V3D_QPU_PF_PUSHN);
555 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_ui(c, -1));
556 return vir_MOV(c, t);
557 }
558
559 static void
560 emit_fragcoord_input(struct v3d_compile *c, int attr)
561 {
562 c->inputs[attr * 4 + 0] = vir_FXCD(c);
563 c->inputs[attr * 4 + 1] = vir_FYCD(c);
564 c->inputs[attr * 4 + 2] = c->payload_z;
565 c->inputs[attr * 4 + 3] = vir_SFU(c, V3D_QPU_WADDR_RECIP,
566 c->payload_w);
567 }
568
569 static struct qreg
570 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
571 uint8_t swizzle)
572 {
573 struct qreg vary = vir_reg(QFILE_VARY, ~0);
574 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
575
576 /* For gl_PointCoord input or distance along a line, we'll be called
577 * with no nir_variable, and we don't count toward VPM size so we
578 * don't track an input slot.
579 */
580 if (!var) {
581 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
582 }
583
584 int i = c->num_inputs++;
585 c->input_slots[i] = v3d_slot_from_slot_and_component(var->data.location,
586 swizzle);
587
588 switch (var->data.interpolation) {
589 case INTERP_MODE_NONE:
590 /* If a gl_FrontColor or gl_BackColor input has no interp
591 * qualifier, then flag it for glShadeModel() handling by the
592 * driver.
593 */
594 switch (var->data.location) {
595 case VARYING_SLOT_COL0:
596 case VARYING_SLOT_COL1:
597 case VARYING_SLOT_BFC0:
598 case VARYING_SLOT_BFC1:
599 BITSET_SET(c->shade_model_flags, i);
600 break;
601 default:
602 break;
603 }
604 /* FALLTHROUGH */
605 case INTERP_MODE_SMOOTH:
606 if (var->data.centroid) {
607 return vir_FADD(c, vir_FMUL(c, vary,
608 c->payload_w_centroid), r5);
609 } else {
610 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
611 }
612 case INTERP_MODE_NOPERSPECTIVE:
613 /* C appears after the mov from the varying.
614 XXX: improve ldvary setup.
615 */
616 return vir_FADD(c, vir_MOV(c, vary), r5);
617 case INTERP_MODE_FLAT:
618 BITSET_SET(c->flat_shade_flags, i);
619 vir_MOV_dest(c, c->undef, vary);
620 return vir_MOV(c, r5);
621 default:
622 unreachable("Bad interp mode");
623 }
624 }
625
626 static void
627 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var)
628 {
629 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
630 c->inputs[attr * 4 + i] =
631 emit_fragment_varying(c, var, i);
632 }
633 }
634
635 static void
636 add_output(struct v3d_compile *c,
637 uint32_t decl_offset,
638 uint8_t slot,
639 uint8_t swizzle)
640 {
641 uint32_t old_array_size = c->outputs_array_size;
642 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
643 decl_offset + 1);
644
645 if (old_array_size != c->outputs_array_size) {
646 c->output_slots = reralloc(c,
647 c->output_slots,
648 struct v3d_varying_slot,
649 c->outputs_array_size);
650 }
651
652 c->output_slots[decl_offset] =
653 v3d_slot_from_slot_and_component(slot, swizzle);
654 }
655
656 static void
657 declare_uniform_range(struct v3d_compile *c, uint32_t start, uint32_t size)
658 {
659 unsigned array_id = c->num_ubo_ranges++;
660 if (array_id >= c->ubo_ranges_array_size) {
661 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
662 array_id + 1);
663 c->ubo_ranges = reralloc(c, c->ubo_ranges,
664 struct v3d_ubo_range,
665 c->ubo_ranges_array_size);
666 c->ubo_range_used = reralloc(c, c->ubo_range_used,
667 bool,
668 c->ubo_ranges_array_size);
669 }
670
671 c->ubo_ranges[array_id].dst_offset = 0;
672 c->ubo_ranges[array_id].src_offset = start;
673 c->ubo_ranges[array_id].size = size;
674 c->ubo_range_used[array_id] = false;
675 }
676
677 /**
678 * If compare_instr is a valid comparison instruction, emits the
679 * compare_instr's comparison and returns the sel_instr's return value based
680 * on the compare_instr's result.
681 */
682 static bool
683 ntq_emit_comparison(struct v3d_compile *c, struct qreg *dest,
684 nir_alu_instr *compare_instr,
685 nir_alu_instr *sel_instr)
686 {
687 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
688 struct qreg src1 = ntq_get_alu_src(c, compare_instr, 1);
689 bool cond_invert = false;
690
691 switch (compare_instr->op) {
692 case nir_op_feq:
693 case nir_op_seq:
694 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHZ);
695 break;
696 case nir_op_ieq:
697 vir_PF(c, vir_XOR(c, src0, src1), V3D_QPU_PF_PUSHZ);
698 break;
699
700 case nir_op_fne:
701 case nir_op_sne:
702 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHZ);
703 cond_invert = true;
704 break;
705 case nir_op_ine:
706 vir_PF(c, vir_XOR(c, src0, src1), V3D_QPU_PF_PUSHZ);
707 cond_invert = true;
708 break;
709
710 case nir_op_fge:
711 case nir_op_sge:
712 vir_PF(c, vir_FCMP(c, src1, src0), V3D_QPU_PF_PUSHC);
713 break;
714 case nir_op_ige:
715 vir_PF(c, vir_MIN(c, src1, src0), V3D_QPU_PF_PUSHC);
716 cond_invert = true;
717 break;
718 case nir_op_uge:
719 vir_PF(c, vir_SUB(c, src0, src1), V3D_QPU_PF_PUSHC);
720 cond_invert = true;
721 break;
722
723 case nir_op_slt:
724 case nir_op_flt:
725 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHN);
726 break;
727 case nir_op_ilt:
728 vir_PF(c, vir_MIN(c, src1, src0), V3D_QPU_PF_PUSHC);
729 break;
730 case nir_op_ult:
731 vir_PF(c, vir_SUB(c, src0, src1), V3D_QPU_PF_PUSHC);
732 break;
733
734 default:
735 return false;
736 }
737
738 enum v3d_qpu_cond cond = (cond_invert ?
739 V3D_QPU_COND_IFNA :
740 V3D_QPU_COND_IFA);
741
742 switch (sel_instr->op) {
743 case nir_op_seq:
744 case nir_op_sne:
745 case nir_op_sge:
746 case nir_op_slt:
747 *dest = vir_SEL(c, cond,
748 vir_uniform_f(c, 1.0), vir_uniform_f(c, 0.0));
749 break;
750
751 case nir_op_bcsel:
752 *dest = vir_SEL(c, cond,
753 ntq_get_alu_src(c, sel_instr, 1),
754 ntq_get_alu_src(c, sel_instr, 2));
755 break;
756
757 default:
758 *dest = vir_SEL(c, cond,
759 vir_uniform_ui(c, ~0), vir_uniform_ui(c, 0));
760 break;
761 }
762
763 /* Make the temporary for nir_store_dest(). */
764 *dest = vir_MOV(c, *dest);
765
766 return true;
767 }
768
769 /**
770 * Attempts to fold a comparison generating a boolean result into the
771 * condition code for selecting between two values, instead of comparing the
772 * boolean result against 0 to generate the condition code.
773 */
774 static struct qreg ntq_emit_bcsel(struct v3d_compile *c, nir_alu_instr *instr,
775 struct qreg *src)
776 {
777 if (!instr->src[0].src.is_ssa)
778 goto out;
779 if (instr->src[0].src.ssa->parent_instr->type != nir_instr_type_alu)
780 goto out;
781 nir_alu_instr *compare =
782 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
783 if (!compare)
784 goto out;
785
786 struct qreg dest;
787 if (ntq_emit_comparison(c, &dest, compare, instr))
788 return dest;
789
790 out:
791 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
792 return vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA, src[1], src[2]));
793 }
794
795
796 static void
797 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
798 {
799 /* This should always be lowered to ALU operations for V3D. */
800 assert(!instr->dest.saturate);
801
802 /* Vectors are special in that they have non-scalarized writemasks,
803 * and just take the first swizzle channel for each argument in order
804 * into each writemask channel.
805 */
806 if (instr->op == nir_op_vec2 ||
807 instr->op == nir_op_vec3 ||
808 instr->op == nir_op_vec4) {
809 struct qreg srcs[4];
810 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
811 srcs[i] = ntq_get_src(c, instr->src[i].src,
812 instr->src[i].swizzle[0]);
813 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
814 ntq_store_dest(c, &instr->dest.dest, i,
815 vir_MOV(c, srcs[i]));
816 return;
817 }
818
819 /* General case: We can just grab the one used channel per src. */
820 struct qreg src[nir_op_infos[instr->op].num_inputs];
821 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
822 src[i] = ntq_get_alu_src(c, instr, i);
823 }
824
825 struct qreg result;
826
827 switch (instr->op) {
828 case nir_op_fmov:
829 case nir_op_imov:
830 result = vir_MOV(c, src[0]);
831 break;
832
833 case nir_op_fneg:
834 result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
835 break;
836 case nir_op_ineg:
837 result = vir_NEG(c, src[0]);
838 break;
839
840 case nir_op_fmul:
841 result = vir_FMUL(c, src[0], src[1]);
842 break;
843 case nir_op_fadd:
844 result = vir_FADD(c, src[0], src[1]);
845 break;
846 case nir_op_fsub:
847 result = vir_FSUB(c, src[0], src[1]);
848 break;
849 case nir_op_fmin:
850 result = vir_FMIN(c, src[0], src[1]);
851 break;
852 case nir_op_fmax:
853 result = vir_FMAX(c, src[0], src[1]);
854 break;
855
856 case nir_op_f2i32:
857 result = vir_FTOIZ(c, src[0]);
858 break;
859 case nir_op_f2u32:
860 result = vir_FTOUZ(c, src[0]);
861 break;
862 case nir_op_i2f32:
863 result = vir_ITOF(c, src[0]);
864 break;
865 case nir_op_u2f32:
866 result = vir_UTOF(c, src[0]);
867 break;
868 case nir_op_b2f:
869 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
870 break;
871 case nir_op_b2i:
872 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
873 break;
874 case nir_op_i2b:
875 case nir_op_f2b:
876 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
877 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
878 vir_uniform_ui(c, ~0),
879 vir_uniform_ui(c, 0)));
880 break;
881
882 case nir_op_iadd:
883 result = vir_ADD(c, src[0], src[1]);
884 break;
885 case nir_op_ushr:
886 result = vir_SHR(c, src[0], src[1]);
887 break;
888 case nir_op_isub:
889 result = vir_SUB(c, src[0], src[1]);
890 break;
891 case nir_op_ishr:
892 result = vir_ASR(c, src[0], src[1]);
893 break;
894 case nir_op_ishl:
895 result = vir_SHL(c, src[0], src[1]);
896 break;
897 case nir_op_imin:
898 result = vir_MIN(c, src[0], src[1]);
899 break;
900 case nir_op_umin:
901 result = vir_UMIN(c, src[0], src[1]);
902 break;
903 case nir_op_imax:
904 result = vir_MAX(c, src[0], src[1]);
905 break;
906 case nir_op_umax:
907 result = vir_UMAX(c, src[0], src[1]);
908 break;
909 case nir_op_iand:
910 result = vir_AND(c, src[0], src[1]);
911 break;
912 case nir_op_ior:
913 result = vir_OR(c, src[0], src[1]);
914 break;
915 case nir_op_ixor:
916 result = vir_XOR(c, src[0], src[1]);
917 break;
918 case nir_op_inot:
919 result = vir_NOT(c, src[0]);
920 break;
921
922 case nir_op_imul:
923 result = ntq_umul(c, src[0], src[1]);
924 break;
925
926 case nir_op_seq:
927 case nir_op_sne:
928 case nir_op_sge:
929 case nir_op_slt:
930 case nir_op_feq:
931 case nir_op_fne:
932 case nir_op_fge:
933 case nir_op_flt:
934 case nir_op_ieq:
935 case nir_op_ine:
936 case nir_op_ige:
937 case nir_op_uge:
938 case nir_op_ilt:
939 case nir_op_ult:
940 if (!ntq_emit_comparison(c, &result, instr, instr)) {
941 fprintf(stderr, "Bad comparison instruction\n");
942 }
943 break;
944
945 case nir_op_bcsel:
946 result = ntq_emit_bcsel(c, instr, src);
947 break;
948 case nir_op_fcsel:
949 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
950 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
951 src[1], src[2]));
952 break;
953
954 case nir_op_frcp:
955 result = vir_SFU(c, V3D_QPU_WADDR_RECIP, src[0]);
956 break;
957 case nir_op_frsq:
958 result = vir_SFU(c, V3D_QPU_WADDR_RSQRT, src[0]);
959 break;
960 case nir_op_fexp2:
961 result = vir_SFU(c, V3D_QPU_WADDR_EXP, src[0]);
962 break;
963 case nir_op_flog2:
964 result = vir_SFU(c, V3D_QPU_WADDR_LOG, src[0]);
965 break;
966
967 case nir_op_fceil:
968 result = vir_FCEIL(c, src[0]);
969 break;
970 case nir_op_ffloor:
971 result = vir_FFLOOR(c, src[0]);
972 break;
973 case nir_op_fround_even:
974 result = vir_FROUND(c, src[0]);
975 break;
976 case nir_op_ftrunc:
977 result = vir_FTRUNC(c, src[0]);
978 break;
979 case nir_op_ffract:
980 result = vir_FSUB(c, src[0], vir_FFLOOR(c, src[0]));
981 break;
982
983 case nir_op_fsin:
984 result = ntq_fsincos(c, src[0], false);
985 break;
986 case nir_op_fcos:
987 result = ntq_fsincos(c, src[0], true);
988 break;
989
990 case nir_op_fsign:
991 result = ntq_fsign(c, src[0]);
992 break;
993 case nir_op_isign:
994 result = ntq_isign(c, src[0]);
995 break;
996
997 case nir_op_fabs: {
998 result = vir_FMOV(c, src[0]);
999 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
1000 break;
1001 }
1002
1003 case nir_op_iabs:
1004 result = vir_MAX(c, src[0],
1005 vir_SUB(c, vir_uniform_ui(c, 0), src[0]));
1006 break;
1007
1008 case nir_op_fddx:
1009 case nir_op_fddx_coarse:
1010 case nir_op_fddx_fine:
1011 result = vir_FDX(c, src[0]);
1012 break;
1013
1014 case nir_op_fddy:
1015 case nir_op_fddy_coarse:
1016 case nir_op_fddy_fine:
1017 result = vir_FDY(c, src[0]);
1018 break;
1019
1020 default:
1021 fprintf(stderr, "unknown NIR ALU inst: ");
1022 nir_print_instr(&instr->instr, stderr);
1023 fprintf(stderr, "\n");
1024 abort();
1025 }
1026
1027 /* We have a scalar result, so the instruction should only have a
1028 * single channel written to.
1029 */
1030 assert(util_is_power_of_two(instr->dest.write_mask));
1031 ntq_store_dest(c, &instr->dest.dest,
1032 ffs(instr->dest.write_mask) - 1, result);
1033 }
1034
1035 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
1036 * specifier. They come from a register that's preloaded with 0xffffffff
1037 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
1038 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
1039 */
1040 #define TLB_TYPE_F16_COLOR (3 << 6)
1041 #define TLB_TYPE_I32_COLOR (1 << 6)
1042 #define TLB_TYPE_F32_COLOR (0 << 6)
1043 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
1044 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
1045 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
1046 #define TLB_F16_SWAP_HI_LO (1 << 1)
1047 #define TLB_VEC_SIZE_4_F16 (1 << 0)
1048 #define TLB_VEC_SIZE_2_F16 (0 << 0)
1049 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
1050
1051 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
1052 * flag is set.
1053 */
1054 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
1055 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
1056 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
1057
1058 /* Stencil is a single 32-bit write. */
1059 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1060
1061 static void
1062 emit_frag_end(struct v3d_compile *c)
1063 {
1064 /* XXX
1065 if (c->output_sample_mask_index != -1) {
1066 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1067 }
1068 */
1069
1070 bool has_any_tlb_color_write = false;
1071 for (int rt = 0; rt < c->fs_key->nr_cbufs; rt++) {
1072 if (c->output_color_var[rt])
1073 has_any_tlb_color_write = true;
1074 }
1075
1076 if (c->output_position_index != -1) {
1077 struct qinst *inst = vir_MOV_dest(c,
1078 vir_reg(QFILE_TLBU, 0),
1079 c->outputs[c->output_position_index]);
1080
1081 inst->src[vir_get_implicit_uniform_src(inst)] =
1082 vir_uniform_ui(c,
1083 TLB_TYPE_DEPTH |
1084 TLB_DEPTH_TYPE_PER_PIXEL |
1085 0xffffff00);
1086 } else if (c->s->info.fs.uses_discard || !has_any_tlb_color_write) {
1087 /* Emit passthrough Z if it needed to be delayed until shader
1088 * end due to potential discards.
1089 *
1090 * Since (single-threaded) fragment shaders always need a TLB
1091 * write, emit passthrouh Z if we didn't have any color
1092 * buffers and flag us as potentially discarding, so that we
1093 * can use Z as the TLB write.
1094 */
1095 c->s->info.fs.uses_discard = true;
1096
1097 struct qinst *inst = vir_MOV_dest(c,
1098 vir_reg(QFILE_TLBU, 0),
1099 vir_reg(QFILE_NULL, 0));
1100
1101 inst->src[vir_get_implicit_uniform_src(inst)] =
1102 vir_uniform_ui(c,
1103 TLB_TYPE_DEPTH |
1104 TLB_DEPTH_TYPE_INVARIANT |
1105 0xffffff00);
1106 }
1107
1108 /* XXX: Performance improvement: Merge Z write and color writes TLB
1109 * uniform setup
1110 */
1111
1112 for (int rt = 0; rt < c->fs_key->nr_cbufs; rt++) {
1113 if (!c->output_color_var[rt])
1114 continue;
1115
1116 nir_variable *var = c->output_color_var[rt];
1117 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1118 int num_components = glsl_get_vector_elements(var->type);
1119 uint32_t conf = 0xffffff00;
1120 struct qinst *inst;
1121
1122 conf |= TLB_SAMPLE_MODE_PER_PIXEL;
1123 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1124
1125 assert(num_components != 0);
1126 switch (glsl_get_base_type(var->type)) {
1127 case GLSL_TYPE_UINT:
1128 case GLSL_TYPE_INT:
1129 conf |= TLB_TYPE_I32_COLOR;
1130 conf |= ((num_components - 1) <<
1131 TLB_VEC_SIZE_MINUS_1_SHIFT);
1132
1133 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
1134 inst->src[vir_get_implicit_uniform_src(inst)] =
1135 vir_uniform_ui(c, conf);
1136
1137 for (int i = 1; i < num_components; i++) {
1138 inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
1139 color[i]);
1140 }
1141 break;
1142
1143 default: {
1144 struct qreg r = color[0];
1145 struct qreg g = color[1];
1146 struct qreg b = color[2];
1147 struct qreg a = color[3];
1148
1149 if (c->fs_key->f32_color_rb) {
1150 conf |= TLB_TYPE_F32_COLOR;
1151 conf |= ((num_components - 1) <<
1152 TLB_VEC_SIZE_MINUS_1_SHIFT);
1153 } else {
1154 conf |= TLB_TYPE_F16_COLOR;
1155 conf |= TLB_F16_SWAP_HI_LO;
1156 if (num_components >= 3)
1157 conf |= TLB_VEC_SIZE_4_F16;
1158 else
1159 conf |= TLB_VEC_SIZE_2_F16;
1160 }
1161
1162 if (c->fs_key->swap_color_rb & (1 << rt)) {
1163 r = color[2];
1164 b = color[0];
1165 }
1166
1167 if (c->fs_key->f32_color_rb & (1 << rt)) {
1168 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
1169 inst->src[vir_get_implicit_uniform_src(inst)] =
1170 vir_uniform_ui(c, conf);
1171
1172 for (int i = 1; i < num_components; i++) {
1173 inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
1174 color[i]);
1175 }
1176 } else {
1177 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), r, g);
1178 if (conf != ~0) {
1179 inst->dst.file = QFILE_TLBU;
1180 inst->src[vir_get_implicit_uniform_src(inst)] =
1181 vir_uniform_ui(c, conf);
1182 }
1183
1184 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), b, a);
1185 }
1186 break;
1187 }
1188 }
1189 }
1190 }
1191
1192 static void
1193 emit_scaled_viewport_write(struct v3d_compile *c, struct qreg rcp_w)
1194 {
1195 for (int i = 0; i < 2; i++) {
1196 struct qreg coord = c->outputs[c->output_position_index + i];
1197 coord = vir_FMUL(c, coord,
1198 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i,
1199 0));
1200 coord = vir_FMUL(c, coord, rcp_w);
1201 vir_FTOIN_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM),
1202 coord);
1203 }
1204
1205 }
1206
1207 static void
1208 emit_zs_write(struct v3d_compile *c, struct qreg rcp_w)
1209 {
1210 struct qreg zscale = vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1211 struct qreg zoffset = vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1212
1213 vir_FADD_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM),
1214 vir_FMUL(c, vir_FMUL(c,
1215 c->outputs[c->output_position_index + 2],
1216 zscale),
1217 rcp_w),
1218 zoffset);
1219 }
1220
1221 static void
1222 emit_rcp_wc_write(struct v3d_compile *c, struct qreg rcp_w)
1223 {
1224 vir_VPM_WRITE(c, rcp_w);
1225 }
1226
1227 static void
1228 emit_point_size_write(struct v3d_compile *c)
1229 {
1230 struct qreg point_size;
1231
1232 if (c->output_point_size_index != -1)
1233 point_size = c->outputs[c->output_point_size_index];
1234 else
1235 point_size = vir_uniform_f(c, 1.0);
1236
1237 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1238 * BCM21553).
1239 */
1240 point_size = vir_FMAX(c, point_size, vir_uniform_f(c, .125));
1241
1242 vir_VPM_WRITE(c, point_size);
1243 }
1244
1245 static void
1246 emit_vpm_write_setup(struct v3d_compile *c)
1247 {
1248 uint32_t packed;
1249 struct V3D33_VPM_GENERIC_BLOCK_WRITE_SETUP unpacked = {
1250 V3D33_VPM_GENERIC_BLOCK_WRITE_SETUP_header,
1251
1252 .horiz = true,
1253 .laned = false,
1254 .segs = true,
1255 .stride = 1,
1256 .size = VPM_SETUP_SIZE_32_BIT,
1257 .addr = 0,
1258 };
1259
1260 V3D33_VPM_GENERIC_BLOCK_WRITE_SETUP_pack(NULL,
1261 (uint8_t *)&packed,
1262 &unpacked);
1263 vir_VPMSETUP(c, vir_uniform_ui(c, packed));
1264 }
1265
1266 static void
1267 emit_vert_end(struct v3d_compile *c)
1268 {
1269 struct qreg rcp_w = vir_SFU(c, V3D_QPU_WADDR_RECIP,
1270 c->outputs[c->output_position_index + 3]);
1271
1272 emit_vpm_write_setup(c);
1273
1274 if (c->vs_key->is_coord) {
1275 for (int i = 0; i < 4; i++)
1276 vir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1277 emit_scaled_viewport_write(c, rcp_w);
1278 if (c->vs_key->per_vertex_point_size) {
1279 emit_point_size_write(c);
1280 /* emit_rcp_wc_write(c, rcp_w); */
1281 }
1282 /* XXX: Z-only rendering */
1283 if (0)
1284 emit_zs_write(c, rcp_w);
1285 } else {
1286 emit_scaled_viewport_write(c, rcp_w);
1287 emit_zs_write(c, rcp_w);
1288 emit_rcp_wc_write(c, rcp_w);
1289 if (c->vs_key->per_vertex_point_size)
1290 emit_point_size_write(c);
1291 }
1292
1293 for (int i = 0; i < c->vs_key->num_fs_inputs; i++) {
1294 struct v3d_varying_slot input = c->vs_key->fs_inputs[i];
1295 int j;
1296
1297 for (j = 0; j < c->num_outputs; j++) {
1298 struct v3d_varying_slot output = c->output_slots[j];
1299
1300 if (!memcmp(&input, &output, sizeof(input))) {
1301 vir_VPM_WRITE(c, c->outputs[j]);
1302 break;
1303 }
1304 }
1305 /* Emit padding if we didn't find a declared VS output for
1306 * this FS input.
1307 */
1308 if (j == c->num_outputs)
1309 vir_VPM_WRITE(c, vir_uniform_f(c, 0.0));
1310 }
1311 }
1312
1313 void
1314 v3d_optimize_nir(struct nir_shader *s)
1315 {
1316 bool progress;
1317
1318 do {
1319 progress = false;
1320
1321 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1322 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1323 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1324 NIR_PASS(progress, s, nir_copy_prop);
1325 NIR_PASS(progress, s, nir_opt_remove_phis);
1326 NIR_PASS(progress, s, nir_opt_dce);
1327 NIR_PASS(progress, s, nir_opt_dead_cf);
1328 NIR_PASS(progress, s, nir_opt_cse);
1329 NIR_PASS(progress, s, nir_opt_peephole_select, 8);
1330 NIR_PASS(progress, s, nir_opt_algebraic);
1331 NIR_PASS(progress, s, nir_opt_constant_folding);
1332 NIR_PASS(progress, s, nir_opt_undef);
1333 } while (progress);
1334 }
1335
1336 static int
1337 driver_location_compare(const void *in_a, const void *in_b)
1338 {
1339 const nir_variable *const *a = in_a;
1340 const nir_variable *const *b = in_b;
1341
1342 return (*a)->data.driver_location - (*b)->data.driver_location;
1343 }
1344
1345 static struct qreg
1346 ntq_emit_vpm_read(struct v3d_compile *c,
1347 uint32_t *num_components_queued,
1348 uint32_t *remaining,
1349 uint32_t vpm_index)
1350 {
1351 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1352
1353 if (*num_components_queued != 0) {
1354 (*num_components_queued)--;
1355 c->num_inputs++;
1356 return vir_MOV(c, vpm);
1357 }
1358
1359 uint32_t num_components = MIN2(*remaining, 32);
1360
1361 struct V3D33_VPM_GENERIC_BLOCK_READ_SETUP unpacked = {
1362 V3D33_VPM_GENERIC_BLOCK_READ_SETUP_header,
1363
1364 .horiz = true,
1365 .laned = false,
1366 /* If the field is 0, that means a read count of 32. */
1367 .num = num_components & 31,
1368 .segs = true,
1369 .stride = 1,
1370 .size = VPM_SETUP_SIZE_32_BIT,
1371 .addr = c->num_inputs,
1372 };
1373
1374 uint32_t packed;
1375 V3D33_VPM_GENERIC_BLOCK_READ_SETUP_pack(NULL,
1376 (uint8_t *)&packed,
1377 &unpacked);
1378 vir_VPMSETUP(c, vir_uniform_ui(c, packed));
1379
1380 *num_components_queued = num_components - 1;
1381 *remaining -= num_components;
1382 c->num_inputs++;
1383
1384 return vir_MOV(c, vpm);
1385 }
1386
1387 static void
1388 ntq_setup_inputs(struct v3d_compile *c)
1389 {
1390 unsigned num_entries = 0;
1391 unsigned num_components = 0;
1392 nir_foreach_variable(var, &c->s->inputs) {
1393 num_entries++;
1394 num_components += glsl_get_components(var->type);
1395 }
1396
1397 nir_variable *vars[num_entries];
1398
1399 unsigned i = 0;
1400 nir_foreach_variable(var, &c->s->inputs)
1401 vars[i++] = var;
1402
1403 /* Sort the variables so that we emit the input setup in
1404 * driver_location order. This is required for VPM reads, whose data
1405 * is fetched into the VPM in driver_location (TGSI register index)
1406 * order.
1407 */
1408 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1409
1410 uint32_t vpm_components_queued = 0;
1411 if (c->s->info.stage == MESA_SHADER_VERTEX) {
1412 bool uses_iid = c->s->info.system_values_read &
1413 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1414 bool uses_vid = c->s->info.system_values_read &
1415 (1ull << SYSTEM_VALUE_VERTEX_ID);
1416
1417 num_components += uses_iid;
1418 num_components += uses_vid;
1419
1420 if (uses_iid) {
1421 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1422 &num_components, ~0);
1423 }
1424
1425 if (uses_vid) {
1426 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1427 &num_components, ~0);
1428 }
1429 }
1430
1431 for (unsigned i = 0; i < num_entries; i++) {
1432 nir_variable *var = vars[i];
1433 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1434 unsigned loc = var->data.driver_location;
1435
1436 assert(array_len == 1);
1437 (void)array_len;
1438 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1439 (loc + 1) * 4);
1440
1441 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1442 if (var->data.location == VARYING_SLOT_POS) {
1443 emit_fragcoord_input(c, loc);
1444 } else if (var->data.location == VARYING_SLOT_PNTC ||
1445 (var->data.location >= VARYING_SLOT_VAR0 &&
1446 (c->fs_key->point_sprite_mask &
1447 (1 << (var->data.location -
1448 VARYING_SLOT_VAR0))))) {
1449 c->inputs[loc * 4 + 0] = c->point_x;
1450 c->inputs[loc * 4 + 1] = c->point_y;
1451 } else {
1452 emit_fragment_input(c, loc, var);
1453 }
1454 } else {
1455 int var_components = glsl_get_components(var->type);
1456
1457 for (int i = 0; i < var_components; i++) {
1458 c->inputs[loc * 4 + i] =
1459 ntq_emit_vpm_read(c,
1460 &vpm_components_queued,
1461 &num_components,
1462 loc * 4 + i);
1463
1464 }
1465 c->vattr_sizes[loc] = var_components;
1466 }
1467 }
1468
1469 if (c->s->info.stage == MESA_SHADER_VERTEX) {
1470 assert(vpm_components_queued == 0);
1471 assert(num_components == 0);
1472 }
1473 }
1474
1475 static void
1476 ntq_setup_outputs(struct v3d_compile *c)
1477 {
1478 nir_foreach_variable(var, &c->s->outputs) {
1479 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1480 unsigned loc = var->data.driver_location * 4;
1481
1482 assert(array_len == 1);
1483 (void)array_len;
1484
1485 for (int i = 0; i < 4; i++)
1486 add_output(c, loc + i, var->data.location, i);
1487
1488 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1489 switch (var->data.location) {
1490 case FRAG_RESULT_COLOR:
1491 c->output_color_var[0] = var;
1492 c->output_color_var[1] = var;
1493 c->output_color_var[2] = var;
1494 c->output_color_var[3] = var;
1495 break;
1496 case FRAG_RESULT_DATA0:
1497 case FRAG_RESULT_DATA1:
1498 case FRAG_RESULT_DATA2:
1499 case FRAG_RESULT_DATA3:
1500 c->output_color_var[var->data.location -
1501 FRAG_RESULT_DATA0] = var;
1502 break;
1503 case FRAG_RESULT_DEPTH:
1504 c->output_position_index = loc;
1505 break;
1506 case FRAG_RESULT_SAMPLE_MASK:
1507 c->output_sample_mask_index = loc;
1508 break;
1509 }
1510 } else {
1511 switch (var->data.location) {
1512 case VARYING_SLOT_POS:
1513 c->output_position_index = loc;
1514 break;
1515 case VARYING_SLOT_PSIZ:
1516 c->output_point_size_index = loc;
1517 break;
1518 }
1519 }
1520 }
1521 }
1522
1523 static void
1524 ntq_setup_uniforms(struct v3d_compile *c)
1525 {
1526 nir_foreach_variable(var, &c->s->uniforms) {
1527 uint32_t vec4_count = glsl_count_attribute_slots(var->type,
1528 false);
1529 unsigned vec4_size = 4 * sizeof(float);
1530
1531 declare_uniform_range(c, var->data.driver_location * vec4_size,
1532 vec4_count * vec4_size);
1533
1534 }
1535 }
1536
1537 /**
1538 * Sets up the mapping from nir_register to struct qreg *.
1539 *
1540 * Each nir_register gets a struct qreg per 32-bit component being stored.
1541 */
1542 static void
1543 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1544 {
1545 foreach_list_typed(nir_register, nir_reg, node, list) {
1546 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1547 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1548 array_len *
1549 nir_reg->num_components);
1550
1551 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1552
1553 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1554 qregs[i] = vir_get_temp(c);
1555 }
1556 }
1557
1558 static void
1559 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1560 {
1561 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1562 for (int i = 0; i < instr->def.num_components; i++)
1563 qregs[i] = vir_uniform_ui(c, instr->value.u32[i]);
1564
1565 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1566 }
1567
1568 static void
1569 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1570 {
1571 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1572
1573 /* VIR needs there to be *some* value, so pick 0 (same as for
1574 * ntq_setup_registers().
1575 */
1576 for (int i = 0; i < instr->def.num_components; i++)
1577 qregs[i] = vir_uniform_ui(c, 0);
1578 }
1579
1580 static void
1581 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
1582 {
1583 nir_const_value *const_offset;
1584 unsigned offset;
1585
1586 switch (instr->intrinsic) {
1587 case nir_intrinsic_load_uniform:
1588 assert(instr->num_components == 1);
1589 const_offset = nir_src_as_const_value(instr->src[0]);
1590 if (const_offset) {
1591 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1592 assert(offset % 4 == 0);
1593 /* We need dwords */
1594 offset = offset / 4;
1595 ntq_store_dest(c, &instr->dest, 0,
1596 vir_uniform(c, QUNIFORM_UNIFORM,
1597 offset));
1598 } else {
1599 ntq_store_dest(c, &instr->dest, 0,
1600 indirect_uniform_load(c, instr));
1601 }
1602 break;
1603
1604 case nir_intrinsic_load_ubo:
1605 for (int i = 0; i < instr->num_components; i++) {
1606 int ubo = nir_src_as_const_value(instr->src[0])->u32[0];
1607
1608 /* Adjust for where we stored the TGSI register base. */
1609 vir_ADD_dest(c,
1610 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA),
1611 vir_uniform(c, QUNIFORM_UBO_ADDR, 1 + ubo),
1612 vir_ADD(c,
1613 ntq_get_src(c, instr->src[1], 0),
1614 vir_uniform_ui(c, i * 4)));
1615
1616 ntq_store_dest(c, &instr->dest, i, vir_LDTMU(c));
1617 }
1618 break;
1619
1620 const_offset = nir_src_as_const_value(instr->src[0]);
1621 if (const_offset) {
1622 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1623 assert(offset % 4 == 0);
1624 /* We need dwords */
1625 offset = offset / 4;
1626 ntq_store_dest(c, &instr->dest, 0,
1627 vir_uniform(c, QUNIFORM_UNIFORM,
1628 offset));
1629 } else {
1630 ntq_store_dest(c, &instr->dest, 0,
1631 indirect_uniform_load(c, instr));
1632 }
1633 break;
1634
1635 case nir_intrinsic_load_user_clip_plane:
1636 for (int i = 0; i < instr->num_components; i++) {
1637 ntq_store_dest(c, &instr->dest, i,
1638 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1639 nir_intrinsic_ucp_id(instr) *
1640 4 + i));
1641 }
1642 break;
1643
1644 case nir_intrinsic_load_alpha_ref_float:
1645 ntq_store_dest(c, &instr->dest, 0,
1646 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1647 break;
1648
1649 case nir_intrinsic_load_sample_mask_in:
1650 ntq_store_dest(c, &instr->dest, 0,
1651 vir_uniform(c, QUNIFORM_SAMPLE_MASK, 0));
1652 break;
1653
1654 case nir_intrinsic_load_front_face:
1655 /* The register contains 0 (front) or 1 (back), and we need to
1656 * turn it into a NIR bool where true means front.
1657 */
1658 ntq_store_dest(c, &instr->dest, 0,
1659 vir_ADD(c,
1660 vir_uniform_ui(c, -1),
1661 vir_REVF(c)));
1662 break;
1663
1664 case nir_intrinsic_load_instance_id:
1665 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
1666 break;
1667
1668 case nir_intrinsic_load_vertex_id:
1669 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
1670 break;
1671
1672 case nir_intrinsic_load_input:
1673 const_offset = nir_src_as_const_value(instr->src[0]);
1674 assert(const_offset && "v3d doesn't support indirect inputs");
1675 for (int i = 0; i < instr->num_components; i++) {
1676 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1677 int comp = nir_intrinsic_component(instr) + i;
1678 ntq_store_dest(c, &instr->dest, i,
1679 vir_MOV(c, c->inputs[offset * 4 + comp]));
1680 }
1681 break;
1682
1683 case nir_intrinsic_store_output:
1684 const_offset = nir_src_as_const_value(instr->src[1]);
1685 assert(const_offset && "v3d doesn't support indirect outputs");
1686 offset = ((nir_intrinsic_base(instr) +
1687 const_offset->u32[0]) * 4 +
1688 nir_intrinsic_component(instr));
1689
1690 for (int i = 0; i < instr->num_components; i++) {
1691 c->outputs[offset + i] =
1692 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
1693 }
1694 c->num_outputs = MAX2(c->num_outputs,
1695 offset + instr->num_components);
1696 break;
1697
1698 case nir_intrinsic_discard:
1699 if (c->execute.file != QFILE_NULL) {
1700 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1701 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1702 vir_uniform_ui(c, 0)),
1703 V3D_QPU_COND_IFA);
1704 } else {
1705 vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1706 vir_uniform_ui(c, 0));
1707 }
1708 break;
1709
1710 case nir_intrinsic_discard_if: {
1711 /* true (~0) if we're discarding */
1712 struct qreg cond = ntq_get_src(c, instr->src[0], 0);
1713
1714 if (c->execute.file != QFILE_NULL) {
1715 /* execute == 0 means the channel is active. Invert
1716 * the condition so that we can use zero as "executing
1717 * and discarding."
1718 */
1719 vir_PF(c, vir_AND(c, c->execute, vir_NOT(c, cond)),
1720 V3D_QPU_PF_PUSHZ);
1721 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1722 vir_uniform_ui(c, 0)),
1723 V3D_QPU_COND_IFA);
1724 } else {
1725 vir_PF(c, cond, V3D_QPU_PF_PUSHZ);
1726 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1727 vir_uniform_ui(c, 0)),
1728 V3D_QPU_COND_IFNA);
1729 }
1730
1731 break;
1732 }
1733
1734 default:
1735 fprintf(stderr, "Unknown intrinsic: ");
1736 nir_print_instr(&instr->instr, stderr);
1737 fprintf(stderr, "\n");
1738 break;
1739 }
1740 }
1741
1742 /* Clears (activates) the execute flags for any channels whose jump target
1743 * matches this block.
1744 */
1745 static void
1746 ntq_activate_execute_for_block(struct v3d_compile *c)
1747 {
1748 vir_PF(c, vir_SUB(c, c->execute, vir_uniform_ui(c, c->cur_block->index)),
1749 V3D_QPU_PF_PUSHZ);
1750
1751 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
1752 }
1753
1754 static void
1755 ntq_emit_if(struct v3d_compile *c, nir_if *if_stmt)
1756 {
1757 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
1758 bool empty_else_block =
1759 (nir_else_block == nir_if_last_else_block(if_stmt) &&
1760 exec_list_is_empty(&nir_else_block->instr_list));
1761
1762 struct qblock *then_block = vir_new_block(c);
1763 struct qblock *after_block = vir_new_block(c);
1764 struct qblock *else_block;
1765 if (empty_else_block)
1766 else_block = after_block;
1767 else
1768 else_block = vir_new_block(c);
1769
1770 bool was_top_level = false;
1771 if (c->execute.file == QFILE_NULL) {
1772 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
1773 was_top_level = true;
1774 }
1775
1776 /* Set A for executing (execute == 0) and jumping (if->condition ==
1777 * 0) channels, and then update execute flags for those to point to
1778 * the ELSE block.
1779 */
1780 vir_PF(c, vir_OR(c,
1781 c->execute,
1782 ntq_get_src(c, if_stmt->condition, 0)),
1783 V3D_QPU_PF_PUSHZ);
1784 vir_MOV_cond(c, V3D_QPU_COND_IFA,
1785 c->execute,
1786 vir_uniform_ui(c, else_block->index));
1787
1788 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1789 * through.
1790 */
1791 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1792 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
1793 vir_link_blocks(c->cur_block, else_block);
1794 vir_link_blocks(c->cur_block, then_block);
1795
1796 /* Process the THEN block. */
1797 vir_set_emit_block(c, then_block);
1798 ntq_emit_cf_list(c, &if_stmt->then_list);
1799
1800 if (!empty_else_block) {
1801 /* Handle the end of the THEN block. First, all currently
1802 * active channels update their execute flags to point to
1803 * ENDIF
1804 */
1805 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1806 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1807 vir_uniform_ui(c, after_block->index));
1808
1809 /* If everything points at ENDIF, then jump there immediately. */
1810 vir_PF(c, vir_SUB(c, c->execute,
1811 vir_uniform_ui(c, after_block->index)),
1812 V3D_QPU_PF_PUSHZ);
1813 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
1814 vir_link_blocks(c->cur_block, after_block);
1815 vir_link_blocks(c->cur_block, else_block);
1816
1817 vir_set_emit_block(c, else_block);
1818 ntq_activate_execute_for_block(c);
1819 ntq_emit_cf_list(c, &if_stmt->else_list);
1820 }
1821
1822 vir_link_blocks(c->cur_block, after_block);
1823
1824 vir_set_emit_block(c, after_block);
1825 if (was_top_level)
1826 c->execute = c->undef;
1827 else
1828 ntq_activate_execute_for_block(c);
1829 }
1830
1831 static void
1832 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
1833 {
1834 switch (jump->type) {
1835 case nir_jump_break:
1836 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1837 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1838 vir_uniform_ui(c, c->loop_break_block->index));
1839 break;
1840
1841 case nir_jump_continue:
1842 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1843 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1844 vir_uniform_ui(c, c->loop_cont_block->index));
1845 break;
1846
1847 case nir_jump_return:
1848 unreachable("All returns shouold be lowered\n");
1849 }
1850 }
1851
1852 static void
1853 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
1854 {
1855 switch (instr->type) {
1856 case nir_instr_type_alu:
1857 ntq_emit_alu(c, nir_instr_as_alu(instr));
1858 break;
1859
1860 case nir_instr_type_intrinsic:
1861 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
1862 break;
1863
1864 case nir_instr_type_load_const:
1865 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
1866 break;
1867
1868 case nir_instr_type_ssa_undef:
1869 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
1870 break;
1871
1872 case nir_instr_type_tex:
1873 ntq_emit_tex(c, nir_instr_as_tex(instr));
1874 break;
1875
1876 case nir_instr_type_jump:
1877 ntq_emit_jump(c, nir_instr_as_jump(instr));
1878 break;
1879
1880 default:
1881 fprintf(stderr, "Unknown NIR instr type: ");
1882 nir_print_instr(instr, stderr);
1883 fprintf(stderr, "\n");
1884 abort();
1885 }
1886 }
1887
1888 static void
1889 ntq_emit_block(struct v3d_compile *c, nir_block *block)
1890 {
1891 nir_foreach_instr(instr, block) {
1892 ntq_emit_instr(c, instr);
1893 }
1894 }
1895
1896 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
1897
1898 static void
1899 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
1900 {
1901 bool was_top_level = false;
1902 if (c->execute.file == QFILE_NULL) {
1903 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
1904 was_top_level = true;
1905 }
1906
1907 struct qblock *save_loop_cont_block = c->loop_cont_block;
1908 struct qblock *save_loop_break_block = c->loop_break_block;
1909
1910 c->loop_cont_block = vir_new_block(c);
1911 c->loop_break_block = vir_new_block(c);
1912
1913 vir_link_blocks(c->cur_block, c->loop_cont_block);
1914 vir_set_emit_block(c, c->loop_cont_block);
1915 ntq_activate_execute_for_block(c);
1916
1917 ntq_emit_cf_list(c, &loop->body);
1918
1919 /* Re-enable any previous continues now, so our ANYA check below
1920 * works.
1921 *
1922 * XXX: Use the .ORZ flags update, instead.
1923 */
1924 vir_PF(c, vir_SUB(c,
1925 c->execute,
1926 vir_uniform_ui(c, c->loop_cont_block->index)),
1927 V3D_QPU_PF_PUSHZ);
1928 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
1929
1930 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1931
1932 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
1933 vir_link_blocks(c->cur_block, c->loop_cont_block);
1934 vir_link_blocks(c->cur_block, c->loop_break_block);
1935
1936 vir_set_emit_block(c, c->loop_break_block);
1937 if (was_top_level)
1938 c->execute = c->undef;
1939 else
1940 ntq_activate_execute_for_block(c);
1941
1942 c->loop_break_block = save_loop_break_block;
1943 c->loop_cont_block = save_loop_cont_block;
1944 }
1945
1946 static void
1947 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
1948 {
1949 fprintf(stderr, "FUNCTIONS not handled.\n");
1950 abort();
1951 }
1952
1953 static void
1954 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
1955 {
1956 foreach_list_typed(nir_cf_node, node, node, list) {
1957 switch (node->type) {
1958 case nir_cf_node_block:
1959 ntq_emit_block(c, nir_cf_node_as_block(node));
1960 break;
1961
1962 case nir_cf_node_if:
1963 ntq_emit_if(c, nir_cf_node_as_if(node));
1964 break;
1965
1966 case nir_cf_node_loop:
1967 ntq_emit_loop(c, nir_cf_node_as_loop(node));
1968 break;
1969
1970 case nir_cf_node_function:
1971 ntq_emit_function(c, nir_cf_node_as_function(node));
1972 break;
1973
1974 default:
1975 fprintf(stderr, "Unknown NIR node type\n");
1976 abort();
1977 }
1978 }
1979 }
1980
1981 static void
1982 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
1983 {
1984 ntq_setup_registers(c, &impl->registers);
1985 ntq_emit_cf_list(c, &impl->body);
1986 }
1987
1988 static void
1989 nir_to_vir(struct v3d_compile *c)
1990 {
1991 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1992 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
1993 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
1994 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
1995
1996 if (c->fs_key->is_points) {
1997 c->point_x = emit_fragment_varying(c, NULL, 0);
1998 c->point_y = emit_fragment_varying(c, NULL, 0);
1999 } else if (c->fs_key->is_lines) {
2000 c->line_x = emit_fragment_varying(c, NULL, 0);
2001 }
2002 }
2003
2004 ntq_setup_inputs(c);
2005 ntq_setup_outputs(c);
2006 ntq_setup_uniforms(c);
2007 ntq_setup_registers(c, &c->s->registers);
2008
2009 /* Find the main function and emit the body. */
2010 nir_foreach_function(function, c->s) {
2011 assert(strcmp(function->name, "main") == 0);
2012 assert(function->impl);
2013 ntq_emit_impl(c, function->impl);
2014 }
2015 }
2016
2017 const nir_shader_compiler_options v3d_nir_options = {
2018 .lower_extract_byte = true,
2019 .lower_extract_word = true,
2020 .lower_bitfield_insert = true,
2021 .lower_bitfield_extract = true,
2022 .lower_pack_unorm_2x16 = true,
2023 .lower_pack_snorm_2x16 = true,
2024 .lower_pack_unorm_4x8 = true,
2025 .lower_pack_snorm_4x8 = true,
2026 .lower_unpack_unorm_4x8 = true,
2027 .lower_unpack_snorm_4x8 = true,
2028 .lower_fdiv = true,
2029 .lower_ffma = true,
2030 .lower_flrp32 = true,
2031 .lower_fpow = true,
2032 .lower_fsat = true,
2033 .lower_fsqrt = true,
2034 .native_integers = true,
2035 };
2036
2037
2038 #if 0
2039 static int
2040 count_nir_instrs(nir_shader *nir)
2041 {
2042 int count = 0;
2043 nir_foreach_function(function, nir) {
2044 if (!function->impl)
2045 continue;
2046 nir_foreach_block(block, function->impl) {
2047 nir_foreach_instr(instr, block)
2048 count++;
2049 }
2050 }
2051 return count;
2052 }
2053 #endif
2054
2055 void
2056 v3d_nir_to_vir(struct v3d_compile *c)
2057 {
2058 if (V3D_DEBUG & (V3D_DEBUG_NIR |
2059 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2060 fprintf(stderr, "%s prog %d/%d NIR:\n",
2061 vir_get_stage_name(c),
2062 c->program_id, c->variant_id);
2063 nir_print_shader(c->s, stderr);
2064 }
2065
2066 nir_to_vir(c);
2067
2068 switch (c->s->info.stage) {
2069 case MESA_SHADER_FRAGMENT:
2070 emit_frag_end(c);
2071 break;
2072 case MESA_SHADER_VERTEX:
2073 emit_vert_end(c);
2074 break;
2075 default:
2076 unreachable("bad stage");
2077 }
2078
2079 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2080 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2081 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
2082 vir_get_stage_name(c),
2083 c->program_id, c->variant_id);
2084 vir_dump(c);
2085 fprintf(stderr, "\n");
2086 }
2087
2088 vir_optimize(c);
2089 vir_lower_uniforms(c);
2090
2091 /* XXX: vir_schedule_instructions(c); */
2092
2093 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2094 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2095 fprintf(stderr, "%s prog %d/%d VIR:\n",
2096 vir_get_stage_name(c),
2097 c->program_id, c->variant_id);
2098 vir_dump(c);
2099 fprintf(stderr, "\n");
2100 }
2101
2102 v3d_vir_to_qpu(c);
2103 }