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v3d: Refactor bcsel and if condition handling.
[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
34
35 #define GENERAL_TMU_LOOKUP_PER_QUAD (0 << 7)
36 #define GENERAL_TMU_LOOKUP_PER_PIXEL (1 << 7)
37 #define GENERAL_TMU_READ_OP_PREFETCH (0 << 3)
38 #define GENERAL_TMU_READ_OP_CACHE_CLEAR (1 << 3)
39 #define GENERAL_TMU_READ_OP_CACHE_FLUSH (3 << 3)
40 #define GENERAL_TMU_READ_OP_CACHE_CLEAN (3 << 3)
41 #define GENERAL_TMU_READ_OP_CACHE_L1T_CLEAR (4 << 3)
42 #define GENERAL_TMU_READ_OP_CACHE_L1T_FLUSH_AGGREGATION (5 << 3)
43 #define GENERAL_TMU_READ_OP_ATOMIC_INC (8 << 3)
44 #define GENERAL_TMU_READ_OP_ATOMIC_DEC (9 << 3)
45 #define GENERAL_TMU_READ_OP_ATOMIC_NOT (10 << 3)
46 #define GENERAL_TMU_READ_OP_READ (15 << 3)
47 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_I (0 << 0)
48 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_I (1 << 0)
49 #define GENERAL_TMU_LOOKUP_TYPE_VEC2 (2 << 0)
50 #define GENERAL_TMU_LOOKUP_TYPE_VEC3 (3 << 0)
51 #define GENERAL_TMU_LOOKUP_TYPE_VEC4 (4 << 0)
52 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_UI (5 << 0)
53 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_UI (6 << 0)
54 #define GENERAL_TMU_LOOKUP_TYPE_32BIT_UI (7 << 0)
55
56 #define GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP (0 << 3)
57 #define GENERAL_TMU_WRITE_OP_ATOMIC_SUB_WRAP (1 << 3)
58 #define GENERAL_TMU_WRITE_OP_ATOMIC_XCHG (2 << 3)
59 #define GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG (3 << 3)
60 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMIN (4 << 3)
61 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMAX (5 << 3)
62 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMIN (6 << 3)
63 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMAX (7 << 3)
64 #define GENERAL_TMU_WRITE_OP_ATOMIC_AND (8 << 3)
65 #define GENERAL_TMU_WRITE_OP_ATOMIC_OR (9 << 3)
66 #define GENERAL_TMU_WRITE_OP_ATOMIC_XOR (10 << 3)
67 #define GENERAL_TMU_WRITE_OP_WRITE (15 << 3)
68
69 #define V3D_TSY_SET_QUORUM 0
70 #define V3D_TSY_INC_WAITERS 1
71 #define V3D_TSY_DEC_WAITERS 2
72 #define V3D_TSY_INC_QUORUM 3
73 #define V3D_TSY_DEC_QUORUM 4
74 #define V3D_TSY_FREE_ALL 5
75 #define V3D_TSY_RELEASE 6
76 #define V3D_TSY_ACQUIRE 7
77 #define V3D_TSY_WAIT 8
78 #define V3D_TSY_WAIT_INC 9
79 #define V3D_TSY_WAIT_CHECK 10
80 #define V3D_TSY_WAIT_INC_CHECK 11
81 #define V3D_TSY_WAIT_CV 12
82 #define V3D_TSY_INC_SEMAPHORE 13
83 #define V3D_TSY_DEC_SEMAPHORE 14
84 #define V3D_TSY_SET_QUORUM_FREE_ALL 15
85
86 static void
87 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
88
89 static void
90 resize_qreg_array(struct v3d_compile *c,
91 struct qreg **regs,
92 uint32_t *size,
93 uint32_t decl_size)
94 {
95 if (*size >= decl_size)
96 return;
97
98 uint32_t old_size = *size;
99 *size = MAX2(*size * 2, decl_size);
100 *regs = reralloc(c, *regs, struct qreg, *size);
101 if (!*regs) {
102 fprintf(stderr, "Malloc failure\n");
103 abort();
104 }
105
106 for (uint32_t i = old_size; i < *size; i++)
107 (*regs)[i] = c->undef;
108 }
109
110 void
111 vir_emit_thrsw(struct v3d_compile *c)
112 {
113 if (c->threads == 1)
114 return;
115
116 /* Always thread switch after each texture operation for now.
117 *
118 * We could do better by batching a bunch of texture fetches up and
119 * then doing one thread switch and collecting all their results
120 * afterward.
121 */
122 c->last_thrsw = vir_NOP(c);
123 c->last_thrsw->qpu.sig.thrsw = true;
124 c->last_thrsw_at_top_level = (c->execute.file == QFILE_NULL);
125 }
126
127 static uint32_t
128 v3d_general_tmu_op(nir_intrinsic_instr *instr)
129 {
130 switch (instr->intrinsic) {
131 case nir_intrinsic_load_ssbo:
132 case nir_intrinsic_load_ubo:
133 case nir_intrinsic_load_uniform:
134 case nir_intrinsic_load_shared:
135 return GENERAL_TMU_READ_OP_READ;
136 case nir_intrinsic_store_ssbo:
137 case nir_intrinsic_store_shared:
138 return GENERAL_TMU_WRITE_OP_WRITE;
139 case nir_intrinsic_ssbo_atomic_add:
140 case nir_intrinsic_shared_atomic_add:
141 return GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP;
142 case nir_intrinsic_ssbo_atomic_imin:
143 case nir_intrinsic_shared_atomic_imin:
144 return GENERAL_TMU_WRITE_OP_ATOMIC_SMIN;
145 case nir_intrinsic_ssbo_atomic_umin:
146 case nir_intrinsic_shared_atomic_umin:
147 return GENERAL_TMU_WRITE_OP_ATOMIC_UMIN;
148 case nir_intrinsic_ssbo_atomic_imax:
149 case nir_intrinsic_shared_atomic_imax:
150 return GENERAL_TMU_WRITE_OP_ATOMIC_SMAX;
151 case nir_intrinsic_ssbo_atomic_umax:
152 case nir_intrinsic_shared_atomic_umax:
153 return GENERAL_TMU_WRITE_OP_ATOMIC_UMAX;
154 case nir_intrinsic_ssbo_atomic_and:
155 case nir_intrinsic_shared_atomic_and:
156 return GENERAL_TMU_WRITE_OP_ATOMIC_AND;
157 case nir_intrinsic_ssbo_atomic_or:
158 case nir_intrinsic_shared_atomic_or:
159 return GENERAL_TMU_WRITE_OP_ATOMIC_OR;
160 case nir_intrinsic_ssbo_atomic_xor:
161 case nir_intrinsic_shared_atomic_xor:
162 return GENERAL_TMU_WRITE_OP_ATOMIC_XOR;
163 case nir_intrinsic_ssbo_atomic_exchange:
164 case nir_intrinsic_shared_atomic_exchange:
165 return GENERAL_TMU_WRITE_OP_ATOMIC_XCHG;
166 case nir_intrinsic_ssbo_atomic_comp_swap:
167 case nir_intrinsic_shared_atomic_comp_swap:
168 return GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG;
169 default:
170 unreachable("unknown intrinsic op");
171 }
172 }
173
174 /**
175 * Implements indirect uniform loads and SSBO accesses through the TMU general
176 * memory access interface.
177 */
178 static void
179 ntq_emit_tmu_general(struct v3d_compile *c, nir_intrinsic_instr *instr,
180 bool is_shared)
181 {
182 /* XXX perf: We should turn add/sub of 1 to inc/dec. Perhaps NIR
183 * wants to have support for inc/dec?
184 */
185
186 uint32_t tmu_op = v3d_general_tmu_op(instr);
187 bool is_store = (instr->intrinsic == nir_intrinsic_store_ssbo ||
188 instr->intrinsic == nir_intrinsic_store_shared);
189 bool has_index = !is_shared;
190
191 int offset_src;
192 int tmu_writes = 1; /* address */
193 if (instr->intrinsic == nir_intrinsic_load_uniform) {
194 offset_src = 0;
195 } else if (instr->intrinsic == nir_intrinsic_load_ssbo ||
196 instr->intrinsic == nir_intrinsic_load_ubo ||
197 instr->intrinsic == nir_intrinsic_load_shared) {
198 offset_src = 0 + has_index;
199 } else if (is_store) {
200 offset_src = 1 + has_index;
201 for (int i = 0; i < instr->num_components; i++) {
202 vir_MOV_dest(c,
203 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
204 ntq_get_src(c, instr->src[0], i));
205 tmu_writes++;
206 }
207 } else {
208 offset_src = 0 + has_index;
209 vir_MOV_dest(c,
210 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
211 ntq_get_src(c, instr->src[1 + has_index], 0));
212 tmu_writes++;
213 if (tmu_op == GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG) {
214 vir_MOV_dest(c,
215 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
216 ntq_get_src(c, instr->src[2 + has_index],
217 0));
218 tmu_writes++;
219 }
220 }
221
222 /* Make sure we won't exceed the 16-entry TMU fifo if each thread is
223 * storing at the same time.
224 */
225 while (tmu_writes > 16 / c->threads)
226 c->threads /= 2;
227
228 struct qreg offset;
229 if (instr->intrinsic == nir_intrinsic_load_uniform) {
230 offset = vir_uniform(c, QUNIFORM_UBO_ADDR, 0);
231
232 /* Find what variable in the default uniform block this
233 * uniform load is coming from.
234 */
235 uint32_t base = nir_intrinsic_base(instr);
236 int i;
237 struct v3d_ubo_range *range = NULL;
238 for (i = 0; i < c->num_ubo_ranges; i++) {
239 range = &c->ubo_ranges[i];
240 if (base >= range->src_offset &&
241 base < range->src_offset + range->size) {
242 break;
243 }
244 }
245 /* The driver-location-based offset always has to be within a
246 * declared uniform range.
247 */
248 assert(i != c->num_ubo_ranges);
249 if (!c->ubo_range_used[i]) {
250 c->ubo_range_used[i] = true;
251 range->dst_offset = c->next_ubo_dst_offset;
252 c->next_ubo_dst_offset += range->size;
253 }
254
255 base = base - range->src_offset + range->dst_offset;
256
257 if (base != 0)
258 offset = vir_ADD(c, offset, vir_uniform_ui(c, base));
259 } else if (instr->intrinsic == nir_intrinsic_load_ubo) {
260 /* Note that QUNIFORM_UBO_ADDR takes a UBO index shifted up by
261 * 1 (0 is gallium's constant buffer 0).
262 */
263 offset = vir_uniform(c, QUNIFORM_UBO_ADDR,
264 nir_src_as_uint(instr->src[0]) + 1);
265 } else if (is_shared) {
266 /* Shared variables have no buffer index, and all start from a
267 * common base that we set up at the start of dispatch
268 */
269 offset = c->cs_shared_offset;
270 } else {
271 offset = vir_uniform(c, QUNIFORM_SSBO_OFFSET,
272 nir_src_as_uint(instr->src[is_store ?
273 1 : 0]));
274 }
275
276 uint32_t config = (0xffffff00 |
277 tmu_op |
278 GENERAL_TMU_LOOKUP_PER_PIXEL);
279 if (instr->num_components == 1) {
280 config |= GENERAL_TMU_LOOKUP_TYPE_32BIT_UI;
281 } else {
282 config |= (GENERAL_TMU_LOOKUP_TYPE_VEC2 +
283 instr->num_components - 2);
284 }
285
286 if (c->execute.file != QFILE_NULL)
287 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
288
289 struct qreg dest;
290 if (config == ~0)
291 dest = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA);
292 else
293 dest = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUAU);
294
295 struct qinst *tmu;
296 if (nir_src_is_const(instr->src[offset_src]) &&
297 nir_src_as_uint(instr->src[offset_src]) == 0) {
298 tmu = vir_MOV_dest(c, dest, offset);
299 } else {
300 tmu = vir_ADD_dest(c, dest,
301 offset,
302 ntq_get_src(c, instr->src[offset_src], 0));
303 }
304
305 if (config != ~0) {
306 tmu->src[vir_get_implicit_uniform_src(tmu)] =
307 vir_uniform_ui(c, config);
308 }
309
310 if (c->execute.file != QFILE_NULL)
311 vir_set_cond(tmu, V3D_QPU_COND_IFA);
312
313 vir_emit_thrsw(c);
314
315 /* Read the result, or wait for the TMU op to complete. */
316 for (int i = 0; i < nir_intrinsic_dest_components(instr); i++)
317 ntq_store_dest(c, &instr->dest, i, vir_MOV(c, vir_LDTMU(c)));
318
319 if (nir_intrinsic_dest_components(instr) == 0)
320 vir_TMUWT(c);
321 }
322
323 static struct qreg *
324 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
325 {
326 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
327 def->num_components);
328 _mesa_hash_table_insert(c->def_ht, def, qregs);
329 return qregs;
330 }
331
332 /**
333 * This function is responsible for getting VIR results into the associated
334 * storage for a NIR instruction.
335 *
336 * If it's a NIR SSA def, then we just set the associated hash table entry to
337 * the new result.
338 *
339 * If it's a NIR reg, then we need to update the existing qreg assigned to the
340 * NIR destination with the incoming value. To do that without introducing
341 * new MOVs, we require that the incoming qreg either be a uniform, or be
342 * SSA-defined by the previous VIR instruction in the block and rewritable by
343 * this function. That lets us sneak ahead and insert the SF flag beforehand
344 * (knowing that the previous instruction doesn't depend on flags) and rewrite
345 * its destination to be the NIR reg's destination
346 */
347 void
348 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
349 struct qreg result)
350 {
351 struct qinst *last_inst = NULL;
352 if (!list_empty(&c->cur_block->instructions))
353 last_inst = (struct qinst *)c->cur_block->instructions.prev;
354
355 assert(result.file == QFILE_UNIF ||
356 (result.file == QFILE_TEMP &&
357 last_inst && last_inst == c->defs[result.index]));
358
359 if (dest->is_ssa) {
360 assert(chan < dest->ssa.num_components);
361
362 struct qreg *qregs;
363 struct hash_entry *entry =
364 _mesa_hash_table_search(c->def_ht, &dest->ssa);
365
366 if (entry)
367 qregs = entry->data;
368 else
369 qregs = ntq_init_ssa_def(c, &dest->ssa);
370
371 qregs[chan] = result;
372 } else {
373 nir_register *reg = dest->reg.reg;
374 assert(dest->reg.base_offset == 0);
375 assert(reg->num_array_elems == 0);
376 struct hash_entry *entry =
377 _mesa_hash_table_search(c->def_ht, reg);
378 struct qreg *qregs = entry->data;
379
380 /* Insert a MOV if the source wasn't an SSA def in the
381 * previous instruction.
382 */
383 if (result.file == QFILE_UNIF) {
384 result = vir_MOV(c, result);
385 last_inst = c->defs[result.index];
386 }
387
388 /* We know they're both temps, so just rewrite index. */
389 c->defs[last_inst->dst.index] = NULL;
390 last_inst->dst.index = qregs[chan].index;
391
392 /* If we're in control flow, then make this update of the reg
393 * conditional on the execution mask.
394 */
395 if (c->execute.file != QFILE_NULL) {
396 last_inst->dst.index = qregs[chan].index;
397
398 /* Set the flags to the current exec mask.
399 */
400 c->cursor = vir_before_inst(last_inst);
401 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
402 c->cursor = vir_after_inst(last_inst);
403
404 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
405 last_inst->cond_is_exec_mask = true;
406 }
407 }
408 }
409
410 struct qreg
411 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
412 {
413 struct hash_entry *entry;
414 if (src.is_ssa) {
415 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
416 assert(i < src.ssa->num_components);
417 } else {
418 nir_register *reg = src.reg.reg;
419 entry = _mesa_hash_table_search(c->def_ht, reg);
420 assert(reg->num_array_elems == 0);
421 assert(src.reg.base_offset == 0);
422 assert(i < reg->num_components);
423 }
424
425 struct qreg *qregs = entry->data;
426 return qregs[i];
427 }
428
429 static struct qreg
430 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
431 unsigned src)
432 {
433 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
434 unsigned chan = ffs(instr->dest.write_mask) - 1;
435 struct qreg r = ntq_get_src(c, instr->src[src].src,
436 instr->src[src].swizzle[chan]);
437
438 assert(!instr->src[src].abs);
439 assert(!instr->src[src].negate);
440
441 return r;
442 };
443
444 static struct qreg
445 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
446 {
447 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
448 }
449
450 static void
451 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
452 {
453 unsigned unit = instr->texture_index;
454 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
455 int dest_size = nir_tex_instr_dest_size(instr);
456
457 struct qreg lod = c->undef;
458 if (lod_index != -1)
459 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
460
461 for (int i = 0; i < dest_size; i++) {
462 assert(i < 3);
463 enum quniform_contents contents;
464
465 if (instr->is_array && i == dest_size - 1)
466 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
467 else
468 contents = QUNIFORM_TEXTURE_WIDTH + i;
469
470 struct qreg size = vir_uniform(c, contents, unit);
471
472 switch (instr->sampler_dim) {
473 case GLSL_SAMPLER_DIM_1D:
474 case GLSL_SAMPLER_DIM_2D:
475 case GLSL_SAMPLER_DIM_MS:
476 case GLSL_SAMPLER_DIM_3D:
477 case GLSL_SAMPLER_DIM_CUBE:
478 /* Don't minify the array size. */
479 if (!(instr->is_array && i == dest_size - 1)) {
480 size = ntq_minify(c, size, lod);
481 }
482 break;
483
484 case GLSL_SAMPLER_DIM_RECT:
485 /* There's no LOD field for rects */
486 break;
487
488 default:
489 unreachable("Bad sampler type");
490 }
491
492 ntq_store_dest(c, &instr->dest, i, size);
493 }
494 }
495
496 static void
497 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
498 {
499 unsigned unit = instr->texture_index;
500
501 /* Since each texture sampling op requires uploading uniforms to
502 * reference the texture, there's no HW support for texture size and
503 * you just upload uniforms containing the size.
504 */
505 switch (instr->op) {
506 case nir_texop_query_levels:
507 ntq_store_dest(c, &instr->dest, 0,
508 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
509 return;
510 case nir_texop_txs:
511 ntq_emit_txs(c, instr);
512 return;
513 default:
514 break;
515 }
516
517 if (c->devinfo->ver >= 40)
518 v3d40_vir_emit_tex(c, instr);
519 else
520 v3d33_vir_emit_tex(c, instr);
521 }
522
523 static struct qreg
524 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
525 {
526 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
527 if (is_cos)
528 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
529
530 struct qreg periods = vir_FROUND(c, input);
531 struct qreg sin_output = vir_SIN(c, vir_FSUB(c, input, periods));
532 return vir_XOR(c, sin_output, vir_SHL(c,
533 vir_FTOIN(c, periods),
534 vir_uniform_ui(c, -1)));
535 }
536
537 static struct qreg
538 ntq_fsign(struct v3d_compile *c, struct qreg src)
539 {
540 struct qreg t = vir_get_temp(c);
541
542 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
543 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHZ);
544 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
545 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHN);
546 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
547 return vir_MOV(c, t);
548 }
549
550 static void
551 emit_fragcoord_input(struct v3d_compile *c, int attr)
552 {
553 c->inputs[attr * 4 + 0] = vir_FXCD(c);
554 c->inputs[attr * 4 + 1] = vir_FYCD(c);
555 c->inputs[attr * 4 + 2] = c->payload_z;
556 c->inputs[attr * 4 + 3] = vir_RECIP(c, c->payload_w);
557 }
558
559 static struct qreg
560 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
561 uint8_t swizzle, int array_index)
562 {
563 struct qreg r3 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R3);
564 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
565
566 struct qreg vary;
567 if (c->devinfo->ver >= 41) {
568 struct qinst *ldvary = vir_add_inst(V3D_QPU_A_NOP, c->undef,
569 c->undef, c->undef);
570 ldvary->qpu.sig.ldvary = true;
571 vary = vir_emit_def(c, ldvary);
572 } else {
573 vir_NOP(c)->qpu.sig.ldvary = true;
574 vary = r3;
575 }
576
577 /* For gl_PointCoord input or distance along a line, we'll be called
578 * with no nir_variable, and we don't count toward VPM size so we
579 * don't track an input slot.
580 */
581 if (!var) {
582 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
583 }
584
585 int i = c->num_inputs++;
586 c->input_slots[i] =
587 v3d_slot_from_slot_and_component(var->data.location +
588 array_index, swizzle);
589
590 switch (var->data.interpolation) {
591 case INTERP_MODE_NONE:
592 /* If a gl_FrontColor or gl_BackColor input has no interp
593 * qualifier, then if we're using glShadeModel(GL_FLAT) it
594 * needs to be flat shaded.
595 */
596 switch (var->data.location + array_index) {
597 case VARYING_SLOT_COL0:
598 case VARYING_SLOT_COL1:
599 case VARYING_SLOT_BFC0:
600 case VARYING_SLOT_BFC1:
601 if (c->fs_key->shade_model_flat) {
602 BITSET_SET(c->flat_shade_flags, i);
603 vir_MOV_dest(c, c->undef, vary);
604 return vir_MOV(c, r5);
605 } else {
606 return vir_FADD(c, vir_FMUL(c, vary,
607 c->payload_w), r5);
608 }
609 default:
610 break;
611 }
612 /* FALLTHROUGH */
613 case INTERP_MODE_SMOOTH:
614 if (var->data.centroid) {
615 BITSET_SET(c->centroid_flags, i);
616 return vir_FADD(c, vir_FMUL(c, vary,
617 c->payload_w_centroid), r5);
618 } else {
619 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
620 }
621 case INTERP_MODE_NOPERSPECTIVE:
622 BITSET_SET(c->noperspective_flags, i);
623 return vir_FADD(c, vir_MOV(c, vary), r5);
624 case INTERP_MODE_FLAT:
625 BITSET_SET(c->flat_shade_flags, i);
626 vir_MOV_dest(c, c->undef, vary);
627 return vir_MOV(c, r5);
628 default:
629 unreachable("Bad interp mode");
630 }
631 }
632
633 static void
634 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var,
635 int array_index)
636 {
637 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
638 int chan = var->data.location_frac + i;
639 c->inputs[attr * 4 + chan] =
640 emit_fragment_varying(c, var, chan, array_index);
641 }
642 }
643
644 static void
645 add_output(struct v3d_compile *c,
646 uint32_t decl_offset,
647 uint8_t slot,
648 uint8_t swizzle)
649 {
650 uint32_t old_array_size = c->outputs_array_size;
651 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
652 decl_offset + 1);
653
654 if (old_array_size != c->outputs_array_size) {
655 c->output_slots = reralloc(c,
656 c->output_slots,
657 struct v3d_varying_slot,
658 c->outputs_array_size);
659 }
660
661 c->output_slots[decl_offset] =
662 v3d_slot_from_slot_and_component(slot, swizzle);
663 }
664
665 static void
666 declare_uniform_range(struct v3d_compile *c, uint32_t start, uint32_t size)
667 {
668 unsigned array_id = c->num_ubo_ranges++;
669 if (array_id >= c->ubo_ranges_array_size) {
670 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
671 array_id + 1);
672 c->ubo_ranges = reralloc(c, c->ubo_ranges,
673 struct v3d_ubo_range,
674 c->ubo_ranges_array_size);
675 c->ubo_range_used = reralloc(c, c->ubo_range_used,
676 bool,
677 c->ubo_ranges_array_size);
678 }
679
680 c->ubo_ranges[array_id].dst_offset = 0;
681 c->ubo_ranges[array_id].src_offset = start;
682 c->ubo_ranges[array_id].size = size;
683 c->ubo_range_used[array_id] = false;
684 }
685
686 /**
687 * If compare_instr is a valid comparison instruction, emits the
688 * compare_instr's comparison and returns the sel_instr's return value based
689 * on the compare_instr's result.
690 */
691 static bool
692 ntq_emit_comparison(struct v3d_compile *c,
693 nir_alu_instr *compare_instr,
694 enum v3d_qpu_cond *out_cond)
695 {
696 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
697 struct qreg src1;
698 if (nir_op_infos[compare_instr->op].num_inputs > 1)
699 src1 = ntq_get_alu_src(c, compare_instr, 1);
700 bool cond_invert = false;
701 struct qreg nop = vir_nop_reg();
702
703 switch (compare_instr->op) {
704 case nir_op_feq32:
705 case nir_op_seq:
706 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
707 break;
708 case nir_op_ieq32:
709 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
710 break;
711
712 case nir_op_fne32:
713 case nir_op_sne:
714 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
715 cond_invert = true;
716 break;
717 case nir_op_ine32:
718 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
719 cond_invert = true;
720 break;
721
722 case nir_op_fge32:
723 case nir_op_sge:
724 vir_set_pf(vir_FCMP_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
725 break;
726 case nir_op_ige32:
727 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
728 cond_invert = true;
729 break;
730 case nir_op_uge32:
731 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
732 cond_invert = true;
733 break;
734
735 case nir_op_slt:
736 case nir_op_flt32:
737 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHN);
738 break;
739 case nir_op_ilt32:
740 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
741 break;
742 case nir_op_ult32:
743 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
744 break;
745
746 default:
747 return false;
748 }
749
750 *out_cond = cond_invert ? V3D_QPU_COND_IFNA : V3D_QPU_COND_IFA;
751
752 return true;
753 }
754
755 /* Finds an ALU instruction that generates our src value that could
756 * (potentially) be greedily emitted in the consuming instruction.
757 */
758 static struct nir_alu_instr *
759 ntq_get_alu_parent(nir_src src)
760 {
761 if (!src.is_ssa || src.ssa->parent_instr->type != nir_instr_type_alu)
762 return NULL;
763 nir_alu_instr *instr = nir_instr_as_alu(src.ssa->parent_instr);
764 if (!instr)
765 return NULL;
766
767 /* If the ALU instr's srcs are non-SSA, then we would have to avoid
768 * moving emission of the ALU instr down past another write of the
769 * src.
770 */
771 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
772 if (!instr->src[i].src.is_ssa)
773 return NULL;
774 }
775
776 return instr;
777 }
778
779 /* Turns a NIR bool into a condition code to predicate on. */
780 static enum v3d_qpu_cond
781 ntq_emit_bool_to_cond(struct v3d_compile *c, nir_src src)
782 {
783 nir_alu_instr *compare = ntq_get_alu_parent(src);
784 if (!compare)
785 goto out;
786
787 enum v3d_qpu_cond cond;
788 if (ntq_emit_comparison(c, compare, &cond))
789 return cond;
790
791 out:
792 vir_PF(c, ntq_get_src(c, src, 0), V3D_QPU_PF_PUSHZ);
793 return V3D_QPU_COND_IFNA;
794 }
795
796 static void
797 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
798 {
799 /* This should always be lowered to ALU operations for V3D. */
800 assert(!instr->dest.saturate);
801
802 /* Vectors are special in that they have non-scalarized writemasks,
803 * and just take the first swizzle channel for each argument in order
804 * into each writemask channel.
805 */
806 if (instr->op == nir_op_vec2 ||
807 instr->op == nir_op_vec3 ||
808 instr->op == nir_op_vec4) {
809 struct qreg srcs[4];
810 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
811 srcs[i] = ntq_get_src(c, instr->src[i].src,
812 instr->src[i].swizzle[0]);
813 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
814 ntq_store_dest(c, &instr->dest.dest, i,
815 vir_MOV(c, srcs[i]));
816 return;
817 }
818
819 /* General case: We can just grab the one used channel per src. */
820 struct qreg src[nir_op_infos[instr->op].num_inputs];
821 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
822 src[i] = ntq_get_alu_src(c, instr, i);
823 }
824
825 struct qreg result;
826
827 switch (instr->op) {
828 case nir_op_fmov:
829 case nir_op_imov:
830 result = vir_MOV(c, src[0]);
831 break;
832
833 case nir_op_fneg:
834 result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
835 break;
836 case nir_op_ineg:
837 result = vir_NEG(c, src[0]);
838 break;
839
840 case nir_op_fmul:
841 result = vir_FMUL(c, src[0], src[1]);
842 break;
843 case nir_op_fadd:
844 result = vir_FADD(c, src[0], src[1]);
845 break;
846 case nir_op_fsub:
847 result = vir_FSUB(c, src[0], src[1]);
848 break;
849 case nir_op_fmin:
850 result = vir_FMIN(c, src[0], src[1]);
851 break;
852 case nir_op_fmax:
853 result = vir_FMAX(c, src[0], src[1]);
854 break;
855
856 case nir_op_f2i32:
857 result = vir_FTOIZ(c, src[0]);
858 break;
859 case nir_op_f2u32:
860 result = vir_FTOUZ(c, src[0]);
861 break;
862 case nir_op_i2f32:
863 result = vir_ITOF(c, src[0]);
864 break;
865 case nir_op_u2f32:
866 result = vir_UTOF(c, src[0]);
867 break;
868 case nir_op_b2f32:
869 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
870 break;
871 case nir_op_b2i32:
872 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
873 break;
874 case nir_op_i2b32:
875 case nir_op_f2b32:
876 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
877 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
878 vir_uniform_ui(c, ~0),
879 vir_uniform_ui(c, 0)));
880 break;
881
882 case nir_op_iadd:
883 result = vir_ADD(c, src[0], src[1]);
884 break;
885 case nir_op_ushr:
886 result = vir_SHR(c, src[0], src[1]);
887 break;
888 case nir_op_isub:
889 result = vir_SUB(c, src[0], src[1]);
890 break;
891 case nir_op_ishr:
892 result = vir_ASR(c, src[0], src[1]);
893 break;
894 case nir_op_ishl:
895 result = vir_SHL(c, src[0], src[1]);
896 break;
897 case nir_op_imin:
898 result = vir_MIN(c, src[0], src[1]);
899 break;
900 case nir_op_umin:
901 result = vir_UMIN(c, src[0], src[1]);
902 break;
903 case nir_op_imax:
904 result = vir_MAX(c, src[0], src[1]);
905 break;
906 case nir_op_umax:
907 result = vir_UMAX(c, src[0], src[1]);
908 break;
909 case nir_op_iand:
910 result = vir_AND(c, src[0], src[1]);
911 break;
912 case nir_op_ior:
913 result = vir_OR(c, src[0], src[1]);
914 break;
915 case nir_op_ixor:
916 result = vir_XOR(c, src[0], src[1]);
917 break;
918 case nir_op_inot:
919 result = vir_NOT(c, src[0]);
920 break;
921
922 case nir_op_ufind_msb:
923 result = vir_SUB(c, vir_uniform_ui(c, 31), vir_CLZ(c, src[0]));
924 break;
925
926 case nir_op_imul:
927 result = vir_UMUL(c, src[0], src[1]);
928 break;
929
930 case nir_op_seq:
931 case nir_op_sne:
932 case nir_op_sge:
933 case nir_op_slt: {
934 enum v3d_qpu_cond cond;
935 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
936 assert(ok);
937 result = vir_MOV(c, vir_SEL(c, cond,
938 vir_uniform_f(c, 1.0),
939 vir_uniform_f(c, 0.0)));
940 break;
941 }
942
943 case nir_op_feq32:
944 case nir_op_fne32:
945 case nir_op_fge32:
946 case nir_op_flt32:
947 case nir_op_ieq32:
948 case nir_op_ine32:
949 case nir_op_ige32:
950 case nir_op_uge32:
951 case nir_op_ilt32:
952 case nir_op_ult32: {
953 enum v3d_qpu_cond cond;
954 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
955 assert(ok);
956 result = vir_MOV(c, vir_SEL(c, cond,
957 vir_uniform_ui(c, ~0),
958 vir_uniform_ui(c, 0)));
959 break;
960 }
961
962 case nir_op_b32csel:
963 result = vir_MOV(c,
964 vir_SEL(c,
965 ntq_emit_bool_to_cond(c, instr->src[0].src),
966 src[1], src[2]));
967 break;
968
969 case nir_op_fcsel:
970 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
971 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
972 src[1], src[2]));
973 break;
974
975 case nir_op_frcp:
976 result = vir_RECIP(c, src[0]);
977 break;
978 case nir_op_frsq:
979 result = vir_RSQRT(c, src[0]);
980 break;
981 case nir_op_fexp2:
982 result = vir_EXP(c, src[0]);
983 break;
984 case nir_op_flog2:
985 result = vir_LOG(c, src[0]);
986 break;
987
988 case nir_op_fceil:
989 result = vir_FCEIL(c, src[0]);
990 break;
991 case nir_op_ffloor:
992 result = vir_FFLOOR(c, src[0]);
993 break;
994 case nir_op_fround_even:
995 result = vir_FROUND(c, src[0]);
996 break;
997 case nir_op_ftrunc:
998 result = vir_FTRUNC(c, src[0]);
999 break;
1000
1001 case nir_op_fsin:
1002 result = ntq_fsincos(c, src[0], false);
1003 break;
1004 case nir_op_fcos:
1005 result = ntq_fsincos(c, src[0], true);
1006 break;
1007
1008 case nir_op_fsign:
1009 result = ntq_fsign(c, src[0]);
1010 break;
1011
1012 case nir_op_fabs: {
1013 result = vir_FMOV(c, src[0]);
1014 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
1015 break;
1016 }
1017
1018 case nir_op_iabs:
1019 result = vir_MAX(c, src[0],
1020 vir_SUB(c, vir_uniform_ui(c, 0), src[0]));
1021 break;
1022
1023 case nir_op_fddx:
1024 case nir_op_fddx_coarse:
1025 case nir_op_fddx_fine:
1026 result = vir_FDX(c, src[0]);
1027 break;
1028
1029 case nir_op_fddy:
1030 case nir_op_fddy_coarse:
1031 case nir_op_fddy_fine:
1032 result = vir_FDY(c, src[0]);
1033 break;
1034
1035 case nir_op_uadd_carry:
1036 vir_PF(c, vir_ADD(c, src[0], src[1]), V3D_QPU_PF_PUSHC);
1037 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1038 vir_uniform_ui(c, ~0),
1039 vir_uniform_ui(c, 0)));
1040 break;
1041
1042 case nir_op_pack_half_2x16_split:
1043 result = vir_VFPACK(c, src[0], src[1]);
1044 break;
1045
1046 case nir_op_unpack_half_2x16_split_x:
1047 result = vir_FMOV(c, src[0]);
1048 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_L);
1049 break;
1050
1051 case nir_op_unpack_half_2x16_split_y:
1052 result = vir_FMOV(c, src[0]);
1053 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_H);
1054 break;
1055
1056 default:
1057 fprintf(stderr, "unknown NIR ALU inst: ");
1058 nir_print_instr(&instr->instr, stderr);
1059 fprintf(stderr, "\n");
1060 abort();
1061 }
1062
1063 /* We have a scalar result, so the instruction should only have a
1064 * single channel written to.
1065 */
1066 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
1067 ntq_store_dest(c, &instr->dest.dest,
1068 ffs(instr->dest.write_mask) - 1, result);
1069 }
1070
1071 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
1072 * specifier. They come from a register that's preloaded with 0xffffffff
1073 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
1074 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
1075 */
1076 #define TLB_TYPE_F16_COLOR (3 << 6)
1077 #define TLB_TYPE_I32_COLOR (1 << 6)
1078 #define TLB_TYPE_F32_COLOR (0 << 6)
1079 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
1080 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
1081 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
1082 #define TLB_F16_SWAP_HI_LO (1 << 1)
1083 #define TLB_VEC_SIZE_4_F16 (1 << 0)
1084 #define TLB_VEC_SIZE_2_F16 (0 << 0)
1085 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
1086
1087 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
1088 * flag is set.
1089 */
1090 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
1091 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
1092 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
1093 #define TLB_V42_DEPTH_TYPE_INVARIANT (0 << 3) /* Unmodified sideband input used */
1094 #define TLB_V42_DEPTH_TYPE_PER_PIXEL (1 << 3) /* QPU result used */
1095
1096 /* Stencil is a single 32-bit write. */
1097 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1098
1099 static void
1100 emit_frag_end(struct v3d_compile *c)
1101 {
1102 /* XXX
1103 if (c->output_sample_mask_index != -1) {
1104 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1105 }
1106 */
1107
1108 bool has_any_tlb_color_write = false;
1109 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1110 if (c->fs_key->cbufs & (1 << rt) && c->output_color_var[rt])
1111 has_any_tlb_color_write = true;
1112 }
1113
1114 if (c->fs_key->sample_alpha_to_coverage && c->output_color_var[0]) {
1115 struct nir_variable *var = c->output_color_var[0];
1116 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1117
1118 vir_SETMSF_dest(c, vir_nop_reg(),
1119 vir_AND(c,
1120 vir_MSF(c),
1121 vir_FTOC(c, color[3])));
1122 }
1123
1124 if (c->output_position_index != -1) {
1125 struct qinst *inst = vir_MOV_dest(c,
1126 vir_reg(QFILE_TLBU, 0),
1127 c->outputs[c->output_position_index]);
1128 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1129
1130 if (c->devinfo->ver >= 42) {
1131 tlb_specifier |= (TLB_V42_DEPTH_TYPE_PER_PIXEL |
1132 TLB_SAMPLE_MODE_PER_PIXEL);
1133 } else
1134 tlb_specifier |= TLB_DEPTH_TYPE_PER_PIXEL;
1135
1136 inst->src[vir_get_implicit_uniform_src(inst)] =
1137 vir_uniform_ui(c, tlb_specifier | 0xffffff00);
1138 c->writes_z = true;
1139 } else if (c->s->info.fs.uses_discard ||
1140 !c->s->info.fs.early_fragment_tests ||
1141 c->fs_key->sample_alpha_to_coverage ||
1142 !has_any_tlb_color_write) {
1143 /* Emit passthrough Z if it needed to be delayed until shader
1144 * end due to potential discards.
1145 *
1146 * Since (single-threaded) fragment shaders always need a TLB
1147 * write, emit passthrouh Z if we didn't have any color
1148 * buffers and flag us as potentially discarding, so that we
1149 * can use Z as the TLB write.
1150 */
1151 c->s->info.fs.uses_discard = true;
1152
1153 struct qinst *inst = vir_MOV_dest(c,
1154 vir_reg(QFILE_TLBU, 0),
1155 vir_nop_reg());
1156 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1157
1158 if (c->devinfo->ver >= 42) {
1159 /* The spec says the PER_PIXEL flag is ignored for
1160 * invariant writes, but the simulator demands it.
1161 */
1162 tlb_specifier |= (TLB_V42_DEPTH_TYPE_INVARIANT |
1163 TLB_SAMPLE_MODE_PER_PIXEL);
1164 } else {
1165 tlb_specifier |= TLB_DEPTH_TYPE_INVARIANT;
1166 }
1167
1168 inst->src[vir_get_implicit_uniform_src(inst)] =
1169 vir_uniform_ui(c, tlb_specifier | 0xffffff00);
1170 c->writes_z = true;
1171 }
1172
1173 /* XXX: Performance improvement: Merge Z write and color writes TLB
1174 * uniform setup
1175 */
1176
1177 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1178 if (!(c->fs_key->cbufs & (1 << rt)) || !c->output_color_var[rt])
1179 continue;
1180
1181 nir_variable *var = c->output_color_var[rt];
1182 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1183 int num_components = glsl_get_vector_elements(var->type);
1184 uint32_t conf = 0xffffff00;
1185 struct qinst *inst;
1186
1187 conf |= TLB_SAMPLE_MODE_PER_PIXEL;
1188 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1189
1190 if (c->fs_key->swap_color_rb & (1 << rt))
1191 num_components = MAX2(num_components, 3);
1192
1193 assert(num_components != 0);
1194 switch (glsl_get_base_type(var->type)) {
1195 case GLSL_TYPE_UINT:
1196 case GLSL_TYPE_INT:
1197 /* The F32 vs I32 distinction was dropped in 4.2. */
1198 if (c->devinfo->ver < 42)
1199 conf |= TLB_TYPE_I32_COLOR;
1200 else
1201 conf |= TLB_TYPE_F32_COLOR;
1202 conf |= ((num_components - 1) <<
1203 TLB_VEC_SIZE_MINUS_1_SHIFT);
1204
1205 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
1206 inst->src[vir_get_implicit_uniform_src(inst)] =
1207 vir_uniform_ui(c, conf);
1208
1209 for (int i = 1; i < num_components; i++) {
1210 inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
1211 color[i]);
1212 }
1213 break;
1214
1215 default: {
1216 struct qreg r = color[0];
1217 struct qreg g = color[1];
1218 struct qreg b = color[2];
1219 struct qreg a = color[3];
1220
1221 if (c->fs_key->f32_color_rb & (1 << rt)) {
1222 conf |= TLB_TYPE_F32_COLOR;
1223 conf |= ((num_components - 1) <<
1224 TLB_VEC_SIZE_MINUS_1_SHIFT);
1225 } else {
1226 conf |= TLB_TYPE_F16_COLOR;
1227 conf |= TLB_F16_SWAP_HI_LO;
1228 if (num_components >= 3)
1229 conf |= TLB_VEC_SIZE_4_F16;
1230 else
1231 conf |= TLB_VEC_SIZE_2_F16;
1232 }
1233
1234 if (c->fs_key->swap_color_rb & (1 << rt)) {
1235 r = color[2];
1236 b = color[0];
1237 }
1238
1239 if (c->fs_key->sample_alpha_to_one)
1240 a = vir_uniform_f(c, 1.0);
1241
1242 if (c->fs_key->f32_color_rb & (1 << rt)) {
1243 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), r);
1244 inst->src[vir_get_implicit_uniform_src(inst)] =
1245 vir_uniform_ui(c, conf);
1246
1247 if (num_components >= 2)
1248 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), g);
1249 if (num_components >= 3)
1250 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), b);
1251 if (num_components >= 4)
1252 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), a);
1253 } else {
1254 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), r, g);
1255 if (conf != ~0) {
1256 inst->dst.file = QFILE_TLBU;
1257 inst->src[vir_get_implicit_uniform_src(inst)] =
1258 vir_uniform_ui(c, conf);
1259 }
1260
1261 if (num_components >= 3)
1262 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), b, a);
1263 }
1264 break;
1265 }
1266 }
1267 }
1268 }
1269
1270 static void
1271 vir_VPM_WRITE(struct v3d_compile *c, struct qreg val, uint32_t *vpm_index)
1272 {
1273 if (c->devinfo->ver >= 40) {
1274 vir_STVPMV(c, vir_uniform_ui(c, *vpm_index), val);
1275 *vpm_index = *vpm_index + 1;
1276 } else {
1277 vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM), val);
1278 }
1279
1280 c->num_vpm_writes++;
1281 }
1282
1283 static void
1284 emit_scaled_viewport_write(struct v3d_compile *c, struct qreg rcp_w,
1285 uint32_t *vpm_index)
1286 {
1287 for (int i = 0; i < 2; i++) {
1288 struct qreg coord = c->outputs[c->output_position_index + i];
1289 coord = vir_FMUL(c, coord,
1290 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i,
1291 0));
1292 coord = vir_FMUL(c, coord, rcp_w);
1293 vir_VPM_WRITE(c, vir_FTOIN(c, coord), vpm_index);
1294 }
1295
1296 }
1297
1298 static void
1299 emit_zs_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index)
1300 {
1301 struct qreg zscale = vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1302 struct qreg zoffset = vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1303
1304 struct qreg z = c->outputs[c->output_position_index + 2];
1305 z = vir_FMUL(c, z, zscale);
1306 z = vir_FMUL(c, z, rcp_w);
1307 z = vir_FADD(c, z, zoffset);
1308 vir_VPM_WRITE(c, z, vpm_index);
1309 }
1310
1311 static void
1312 emit_rcp_wc_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index)
1313 {
1314 vir_VPM_WRITE(c, rcp_w, vpm_index);
1315 }
1316
1317 static void
1318 emit_point_size_write(struct v3d_compile *c, uint32_t *vpm_index)
1319 {
1320 struct qreg point_size;
1321
1322 if (c->output_point_size_index != -1)
1323 point_size = c->outputs[c->output_point_size_index];
1324 else
1325 point_size = vir_uniform_f(c, 1.0);
1326
1327 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1328 * BCM21553).
1329 */
1330 point_size = vir_FMAX(c, point_size, vir_uniform_f(c, .125));
1331
1332 vir_VPM_WRITE(c, point_size, vpm_index);
1333 }
1334
1335 static void
1336 emit_vpm_write_setup(struct v3d_compile *c)
1337 {
1338 if (c->devinfo->ver >= 40)
1339 return;
1340
1341 v3d33_vir_vpm_write_setup(c);
1342 }
1343
1344 /**
1345 * Sets up c->outputs[c->output_position_index] for the vertex shader
1346 * epilogue, if an output vertex position wasn't specified in the user's
1347 * shader. This may be the case for transform feedback with rasterizer
1348 * discard enabled.
1349 */
1350 static void
1351 setup_default_position(struct v3d_compile *c)
1352 {
1353 if (c->output_position_index != -1)
1354 return;
1355
1356 c->output_position_index = c->outputs_array_size;
1357 for (int i = 0; i < 4; i++) {
1358 add_output(c,
1359 c->output_position_index + i,
1360 VARYING_SLOT_POS, i);
1361 }
1362 }
1363
1364 static void
1365 emit_vert_end(struct v3d_compile *c)
1366 {
1367 setup_default_position(c);
1368
1369 uint32_t vpm_index = 0;
1370 struct qreg rcp_w = vir_RECIP(c,
1371 c->outputs[c->output_position_index + 3]);
1372
1373 emit_vpm_write_setup(c);
1374
1375 if (c->vs_key->is_coord) {
1376 for (int i = 0; i < 4; i++)
1377 vir_VPM_WRITE(c, c->outputs[c->output_position_index + i],
1378 &vpm_index);
1379 emit_scaled_viewport_write(c, rcp_w, &vpm_index);
1380 if (c->vs_key->per_vertex_point_size) {
1381 emit_point_size_write(c, &vpm_index);
1382 /* emit_rcp_wc_write(c, rcp_w); */
1383 }
1384 /* XXX: Z-only rendering */
1385 if (0)
1386 emit_zs_write(c, rcp_w, &vpm_index);
1387 } else {
1388 emit_scaled_viewport_write(c, rcp_w, &vpm_index);
1389 emit_zs_write(c, rcp_w, &vpm_index);
1390 emit_rcp_wc_write(c, rcp_w, &vpm_index);
1391 if (c->vs_key->per_vertex_point_size)
1392 emit_point_size_write(c, &vpm_index);
1393 }
1394
1395 for (int i = 0; i < c->vs_key->num_fs_inputs; i++) {
1396 struct v3d_varying_slot input = c->vs_key->fs_inputs[i];
1397 int j;
1398
1399 for (j = 0; j < c->num_outputs; j++) {
1400 struct v3d_varying_slot output = c->output_slots[j];
1401
1402 if (!memcmp(&input, &output, sizeof(input))) {
1403 vir_VPM_WRITE(c, c->outputs[j],
1404 &vpm_index);
1405 break;
1406 }
1407 }
1408 /* Emit padding if we didn't find a declared VS output for
1409 * this FS input.
1410 */
1411 if (j == c->num_outputs)
1412 vir_VPM_WRITE(c, vir_uniform_f(c, 0.0),
1413 &vpm_index);
1414 }
1415
1416 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1417 */
1418 if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
1419 vir_VPMWT(c);
1420 }
1421
1422 void
1423 v3d_optimize_nir(struct nir_shader *s)
1424 {
1425 bool progress;
1426
1427 do {
1428 progress = false;
1429
1430 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1431 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1432 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1433 NIR_PASS(progress, s, nir_copy_prop);
1434 NIR_PASS(progress, s, nir_opt_remove_phis);
1435 NIR_PASS(progress, s, nir_opt_dce);
1436 NIR_PASS(progress, s, nir_opt_dead_cf);
1437 NIR_PASS(progress, s, nir_opt_cse);
1438 NIR_PASS(progress, s, nir_opt_peephole_select, 8, true, true);
1439 NIR_PASS(progress, s, nir_opt_algebraic);
1440 NIR_PASS(progress, s, nir_opt_constant_folding);
1441 NIR_PASS(progress, s, nir_opt_undef);
1442 } while (progress);
1443
1444 NIR_PASS(progress, s, nir_opt_move_load_ubo);
1445 }
1446
1447 static int
1448 driver_location_compare(const void *in_a, const void *in_b)
1449 {
1450 const nir_variable *const *a = in_a;
1451 const nir_variable *const *b = in_b;
1452
1453 return (*a)->data.driver_location - (*b)->data.driver_location;
1454 }
1455
1456 static struct qreg
1457 ntq_emit_vpm_read(struct v3d_compile *c,
1458 uint32_t *num_components_queued,
1459 uint32_t *remaining,
1460 uint32_t vpm_index)
1461 {
1462 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1463
1464 if (c->devinfo->ver >= 40 ) {
1465 return vir_LDVPMV_IN(c,
1466 vir_uniform_ui(c,
1467 (*num_components_queued)++));
1468 }
1469
1470 if (*num_components_queued != 0) {
1471 (*num_components_queued)--;
1472 c->num_inputs++;
1473 return vir_MOV(c, vpm);
1474 }
1475
1476 uint32_t num_components = MIN2(*remaining, 32);
1477
1478 v3d33_vir_vpm_read_setup(c, num_components);
1479
1480 *num_components_queued = num_components - 1;
1481 *remaining -= num_components;
1482 c->num_inputs++;
1483
1484 return vir_MOV(c, vpm);
1485 }
1486
1487 static void
1488 ntq_setup_vpm_inputs(struct v3d_compile *c)
1489 {
1490 /* Figure out how many components of each vertex attribute the shader
1491 * uses. Each variable should have been split to individual
1492 * components and unused ones DCEed. The vertex fetcher will load
1493 * from the start of the attribute to the number of components we
1494 * declare we need in c->vattr_sizes[].
1495 */
1496 nir_foreach_variable(var, &c->s->inputs) {
1497 /* No VS attribute array support. */
1498 assert(MAX2(glsl_get_length(var->type), 1) == 1);
1499
1500 unsigned loc = var->data.driver_location;
1501 int start_component = var->data.location_frac;
1502 int num_components = glsl_get_components(var->type);
1503
1504 c->vattr_sizes[loc] = MAX2(c->vattr_sizes[loc],
1505 start_component + num_components);
1506 }
1507
1508 unsigned num_components = 0;
1509 uint32_t vpm_components_queued = 0;
1510 bool uses_iid = c->s->info.system_values_read &
1511 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1512 bool uses_vid = c->s->info.system_values_read &
1513 (1ull << SYSTEM_VALUE_VERTEX_ID);
1514 num_components += uses_iid;
1515 num_components += uses_vid;
1516
1517 for (int i = 0; i < ARRAY_SIZE(c->vattr_sizes); i++)
1518 num_components += c->vattr_sizes[i];
1519
1520 if (uses_iid) {
1521 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1522 &num_components, ~0);
1523 }
1524
1525 if (uses_vid) {
1526 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1527 &num_components, ~0);
1528 }
1529
1530 for (int loc = 0; loc < ARRAY_SIZE(c->vattr_sizes); loc++) {
1531 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1532 (loc + 1) * 4);
1533
1534 for (int i = 0; i < c->vattr_sizes[loc]; i++) {
1535 c->inputs[loc * 4 + i] =
1536 ntq_emit_vpm_read(c,
1537 &vpm_components_queued,
1538 &num_components,
1539 loc * 4 + i);
1540
1541 }
1542 }
1543
1544 if (c->devinfo->ver >= 40) {
1545 assert(vpm_components_queued == num_components);
1546 } else {
1547 assert(vpm_components_queued == 0);
1548 assert(num_components == 0);
1549 }
1550 }
1551
1552 static void
1553 ntq_setup_fs_inputs(struct v3d_compile *c)
1554 {
1555 unsigned num_entries = 0;
1556 unsigned num_components = 0;
1557 nir_foreach_variable(var, &c->s->inputs) {
1558 num_entries++;
1559 num_components += glsl_get_components(var->type);
1560 }
1561
1562 nir_variable *vars[num_entries];
1563
1564 unsigned i = 0;
1565 nir_foreach_variable(var, &c->s->inputs)
1566 vars[i++] = var;
1567
1568 /* Sort the variables so that we emit the input setup in
1569 * driver_location order. This is required for VPM reads, whose data
1570 * is fetched into the VPM in driver_location (TGSI register index)
1571 * order.
1572 */
1573 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1574
1575 for (unsigned i = 0; i < num_entries; i++) {
1576 nir_variable *var = vars[i];
1577 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1578 unsigned loc = var->data.driver_location;
1579
1580 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1581 (loc + array_len) * 4);
1582
1583 if (var->data.location == VARYING_SLOT_POS) {
1584 emit_fragcoord_input(c, loc);
1585 } else if (var->data.location == VARYING_SLOT_PNTC ||
1586 (var->data.location >= VARYING_SLOT_VAR0 &&
1587 (c->fs_key->point_sprite_mask &
1588 (1 << (var->data.location -
1589 VARYING_SLOT_VAR0))))) {
1590 c->inputs[loc * 4 + 0] = c->point_x;
1591 c->inputs[loc * 4 + 1] = c->point_y;
1592 } else {
1593 for (int j = 0; j < array_len; j++)
1594 emit_fragment_input(c, loc + j, var, j);
1595 }
1596 }
1597 }
1598
1599 static void
1600 ntq_setup_outputs(struct v3d_compile *c)
1601 {
1602 nir_foreach_variable(var, &c->s->outputs) {
1603 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1604 unsigned loc = var->data.driver_location * 4;
1605
1606 assert(array_len == 1);
1607 (void)array_len;
1608
1609 for (int i = 0; i < 4 - var->data.location_frac; i++) {
1610 add_output(c, loc + var->data.location_frac + i,
1611 var->data.location,
1612 var->data.location_frac + i);
1613 }
1614
1615 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1616 switch (var->data.location) {
1617 case FRAG_RESULT_COLOR:
1618 c->output_color_var[0] = var;
1619 c->output_color_var[1] = var;
1620 c->output_color_var[2] = var;
1621 c->output_color_var[3] = var;
1622 break;
1623 case FRAG_RESULT_DATA0:
1624 case FRAG_RESULT_DATA1:
1625 case FRAG_RESULT_DATA2:
1626 case FRAG_RESULT_DATA3:
1627 c->output_color_var[var->data.location -
1628 FRAG_RESULT_DATA0] = var;
1629 break;
1630 case FRAG_RESULT_DEPTH:
1631 c->output_position_index = loc;
1632 break;
1633 case FRAG_RESULT_SAMPLE_MASK:
1634 c->output_sample_mask_index = loc;
1635 break;
1636 }
1637 } else {
1638 switch (var->data.location) {
1639 case VARYING_SLOT_POS:
1640 c->output_position_index = loc;
1641 break;
1642 case VARYING_SLOT_PSIZ:
1643 c->output_point_size_index = loc;
1644 break;
1645 }
1646 }
1647 }
1648 }
1649
1650 static void
1651 ntq_setup_uniforms(struct v3d_compile *c)
1652 {
1653 nir_foreach_variable(var, &c->s->uniforms) {
1654 uint32_t vec4_count = glsl_count_attribute_slots(var->type,
1655 false);
1656 unsigned vec4_size = 4 * sizeof(float);
1657
1658 if (var->data.mode != nir_var_uniform)
1659 continue;
1660
1661 declare_uniform_range(c, var->data.driver_location * vec4_size,
1662 vec4_count * vec4_size);
1663
1664 }
1665 }
1666
1667 /**
1668 * Sets up the mapping from nir_register to struct qreg *.
1669 *
1670 * Each nir_register gets a struct qreg per 32-bit component being stored.
1671 */
1672 static void
1673 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1674 {
1675 foreach_list_typed(nir_register, nir_reg, node, list) {
1676 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1677 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1678 array_len *
1679 nir_reg->num_components);
1680
1681 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1682
1683 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1684 qregs[i] = vir_get_temp(c);
1685 }
1686 }
1687
1688 static void
1689 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1690 {
1691 /* XXX perf: Experiment with using immediate loads to avoid having
1692 * these end up in the uniform stream. Watch out for breaking the
1693 * small immediates optimization in the process!
1694 */
1695 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1696 for (int i = 0; i < instr->def.num_components; i++)
1697 qregs[i] = vir_uniform_ui(c, instr->value.u32[i]);
1698
1699 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1700 }
1701
1702 static void
1703 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1704 {
1705 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1706
1707 /* VIR needs there to be *some* value, so pick 0 (same as for
1708 * ntq_setup_registers().
1709 */
1710 for (int i = 0; i < instr->def.num_components; i++)
1711 qregs[i] = vir_uniform_ui(c, 0);
1712 }
1713
1714 static void
1715 ntq_emit_image_size(struct v3d_compile *c, nir_intrinsic_instr *instr)
1716 {
1717 assert(instr->intrinsic == nir_intrinsic_image_deref_size);
1718 nir_variable *var = nir_intrinsic_get_var(instr, 0);
1719 unsigned image_index = var->data.driver_location;
1720 const struct glsl_type *sampler_type = glsl_without_array(var->type);
1721 bool is_array = glsl_sampler_type_is_array(sampler_type);
1722
1723 ntq_store_dest(c, &instr->dest, 0,
1724 vir_uniform(c, QUNIFORM_IMAGE_WIDTH, image_index));
1725 if (instr->num_components > 1) {
1726 ntq_store_dest(c, &instr->dest, 1,
1727 vir_uniform(c, QUNIFORM_IMAGE_HEIGHT,
1728 image_index));
1729 }
1730 if (instr->num_components > 2) {
1731 ntq_store_dest(c, &instr->dest, 2,
1732 vir_uniform(c,
1733 is_array ?
1734 QUNIFORM_IMAGE_ARRAY_SIZE :
1735 QUNIFORM_IMAGE_DEPTH,
1736 image_index));
1737 }
1738 }
1739
1740 static void
1741 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
1742 {
1743 unsigned offset;
1744
1745 switch (instr->intrinsic) {
1746 case nir_intrinsic_load_uniform:
1747 if (nir_src_is_const(instr->src[0])) {
1748 int offset = (nir_intrinsic_base(instr) +
1749 nir_src_as_uint(instr->src[0]));
1750 assert(offset % 4 == 0);
1751 /* We need dwords */
1752 offset = offset / 4;
1753 for (int i = 0; i < instr->num_components; i++) {
1754 ntq_store_dest(c, &instr->dest, i,
1755 vir_uniform(c, QUNIFORM_UNIFORM,
1756 offset + i));
1757 }
1758 } else {
1759 ntq_emit_tmu_general(c, instr, false);
1760 }
1761 break;
1762
1763 case nir_intrinsic_load_ubo:
1764 ntq_emit_tmu_general(c, instr, false);
1765 break;
1766
1767 case nir_intrinsic_ssbo_atomic_add:
1768 case nir_intrinsic_ssbo_atomic_imin:
1769 case nir_intrinsic_ssbo_atomic_umin:
1770 case nir_intrinsic_ssbo_atomic_imax:
1771 case nir_intrinsic_ssbo_atomic_umax:
1772 case nir_intrinsic_ssbo_atomic_and:
1773 case nir_intrinsic_ssbo_atomic_or:
1774 case nir_intrinsic_ssbo_atomic_xor:
1775 case nir_intrinsic_ssbo_atomic_exchange:
1776 case nir_intrinsic_ssbo_atomic_comp_swap:
1777 case nir_intrinsic_load_ssbo:
1778 case nir_intrinsic_store_ssbo:
1779 ntq_emit_tmu_general(c, instr, false);
1780 break;
1781
1782 case nir_intrinsic_shared_atomic_add:
1783 case nir_intrinsic_shared_atomic_imin:
1784 case nir_intrinsic_shared_atomic_umin:
1785 case nir_intrinsic_shared_atomic_imax:
1786 case nir_intrinsic_shared_atomic_umax:
1787 case nir_intrinsic_shared_atomic_and:
1788 case nir_intrinsic_shared_atomic_or:
1789 case nir_intrinsic_shared_atomic_xor:
1790 case nir_intrinsic_shared_atomic_exchange:
1791 case nir_intrinsic_shared_atomic_comp_swap:
1792 case nir_intrinsic_load_shared:
1793 case nir_intrinsic_store_shared:
1794 ntq_emit_tmu_general(c, instr, true);
1795 break;
1796
1797 case nir_intrinsic_image_deref_load:
1798 case nir_intrinsic_image_deref_store:
1799 case nir_intrinsic_image_deref_atomic_add:
1800 case nir_intrinsic_image_deref_atomic_min:
1801 case nir_intrinsic_image_deref_atomic_max:
1802 case nir_intrinsic_image_deref_atomic_and:
1803 case nir_intrinsic_image_deref_atomic_or:
1804 case nir_intrinsic_image_deref_atomic_xor:
1805 case nir_intrinsic_image_deref_atomic_exchange:
1806 case nir_intrinsic_image_deref_atomic_comp_swap:
1807 v3d40_vir_emit_image_load_store(c, instr);
1808 break;
1809
1810 case nir_intrinsic_get_buffer_size:
1811 ntq_store_dest(c, &instr->dest, 0,
1812 vir_uniform(c, QUNIFORM_GET_BUFFER_SIZE,
1813 nir_src_as_uint(instr->src[0])));
1814 break;
1815
1816 case nir_intrinsic_load_user_clip_plane:
1817 for (int i = 0; i < instr->num_components; i++) {
1818 ntq_store_dest(c, &instr->dest, i,
1819 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1820 nir_intrinsic_ucp_id(instr) *
1821 4 + i));
1822 }
1823 break;
1824
1825 case nir_intrinsic_load_alpha_ref_float:
1826 ntq_store_dest(c, &instr->dest, 0,
1827 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1828 break;
1829
1830 case nir_intrinsic_load_sample_mask_in:
1831 ntq_store_dest(c, &instr->dest, 0, vir_MSF(c));
1832 break;
1833
1834 case nir_intrinsic_load_helper_invocation:
1835 vir_PF(c, vir_MSF(c), V3D_QPU_PF_PUSHZ);
1836 ntq_store_dest(c, &instr->dest, 0,
1837 vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1838 vir_uniform_ui(c, ~0),
1839 vir_uniform_ui(c, 0))));
1840 break;
1841
1842 case nir_intrinsic_load_front_face:
1843 /* The register contains 0 (front) or 1 (back), and we need to
1844 * turn it into a NIR bool where true means front.
1845 */
1846 ntq_store_dest(c, &instr->dest, 0,
1847 vir_ADD(c,
1848 vir_uniform_ui(c, -1),
1849 vir_REVF(c)));
1850 break;
1851
1852 case nir_intrinsic_load_instance_id:
1853 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
1854 break;
1855
1856 case nir_intrinsic_load_vertex_id:
1857 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
1858 break;
1859
1860 case nir_intrinsic_load_input:
1861 for (int i = 0; i < instr->num_components; i++) {
1862 offset = (nir_intrinsic_base(instr) +
1863 nir_src_as_uint(instr->src[0]));
1864 int comp = nir_intrinsic_component(instr) + i;
1865 ntq_store_dest(c, &instr->dest, i,
1866 vir_MOV(c, c->inputs[offset * 4 + comp]));
1867 }
1868 break;
1869
1870 case nir_intrinsic_store_output:
1871 offset = ((nir_intrinsic_base(instr) +
1872 nir_src_as_uint(instr->src[1])) * 4 +
1873 nir_intrinsic_component(instr));
1874
1875 for (int i = 0; i < instr->num_components; i++) {
1876 c->outputs[offset + i] =
1877 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
1878 }
1879 c->num_outputs = MAX2(c->num_outputs,
1880 offset + instr->num_components);
1881 break;
1882
1883 case nir_intrinsic_image_deref_size:
1884 ntq_emit_image_size(c, instr);
1885 break;
1886
1887 case nir_intrinsic_discard:
1888 if (c->execute.file != QFILE_NULL) {
1889 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1890 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
1891 vir_uniform_ui(c, 0)),
1892 V3D_QPU_COND_IFA);
1893 } else {
1894 vir_SETMSF_dest(c, vir_nop_reg(),
1895 vir_uniform_ui(c, 0));
1896 }
1897 break;
1898
1899 case nir_intrinsic_discard_if: {
1900 /* true (~0) if we're discarding */
1901 struct qreg cond = ntq_get_src(c, instr->src[0], 0);
1902
1903 if (c->execute.file != QFILE_NULL) {
1904 /* execute == 0 means the channel is active. Invert
1905 * the condition so that we can use zero as "executing
1906 * and discarding."
1907 */
1908 vir_PF(c, vir_OR(c, c->execute, vir_NOT(c, cond)),
1909 V3D_QPU_PF_PUSHZ);
1910 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
1911 vir_uniform_ui(c, 0)),
1912 V3D_QPU_COND_IFA);
1913 } else {
1914 vir_PF(c, cond, V3D_QPU_PF_PUSHZ);
1915 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
1916 vir_uniform_ui(c, 0)),
1917 V3D_QPU_COND_IFNA);
1918 }
1919
1920 break;
1921 }
1922
1923 case nir_intrinsic_memory_barrier:
1924 case nir_intrinsic_memory_barrier_atomic_counter:
1925 case nir_intrinsic_memory_barrier_buffer:
1926 case nir_intrinsic_memory_barrier_image:
1927 case nir_intrinsic_memory_barrier_shared:
1928 /* We don't do any instruction scheduling of these NIR
1929 * instructions between each other, so we just need to make
1930 * sure that the TMU operations before the barrier are flushed
1931 * before the ones after the barrier. That is currently
1932 * handled by having a THRSW in each of them and a LDTMU
1933 * series or a TMUWT after.
1934 */
1935 break;
1936
1937 case nir_intrinsic_barrier:
1938 /* Emit a TSY op to get all invocations in the workgroup
1939 * (actually supergroup) to block until the last invocation
1940 * reaches the TSY op.
1941 */
1942 if (c->devinfo->ver >= 42) {
1943 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
1944 V3D_QPU_WADDR_SYNCB));
1945 } else {
1946 struct qinst *sync =
1947 vir_BARRIERID_dest(c,
1948 vir_reg(QFILE_MAGIC,
1949 V3D_QPU_WADDR_SYNCU));
1950 sync->src[vir_get_implicit_uniform_src(sync)] =
1951 vir_uniform_ui(c,
1952 0xffffff00 |
1953 V3D_TSY_WAIT_INC_CHECK);
1954
1955 }
1956
1957 /* The blocking of a TSY op only happens at the next thread
1958 * switch. No texturing may be outstanding at the time of a
1959 * TSY blocking operation.
1960 */
1961 vir_emit_thrsw(c);
1962 break;
1963
1964 case nir_intrinsic_load_num_work_groups:
1965 for (int i = 0; i < 3; i++) {
1966 ntq_store_dest(c, &instr->dest, i,
1967 vir_uniform(c, QUNIFORM_NUM_WORK_GROUPS,
1968 i));
1969 }
1970 break;
1971
1972 case nir_intrinsic_load_local_invocation_index:
1973 ntq_store_dest(c, &instr->dest, 0,
1974 vir_SHR(c, c->cs_payload[1],
1975 vir_uniform_ui(c, 32 - c->local_invocation_index_bits)));
1976 break;
1977
1978 case nir_intrinsic_load_work_group_id:
1979 ntq_store_dest(c, &instr->dest, 0,
1980 vir_AND(c, c->cs_payload[0],
1981 vir_uniform_ui(c, 0xffff)));
1982 ntq_store_dest(c, &instr->dest, 1,
1983 vir_SHR(c, c->cs_payload[0],
1984 vir_uniform_ui(c, 16)));
1985 ntq_store_dest(c, &instr->dest, 2,
1986 vir_AND(c, c->cs_payload[1],
1987 vir_uniform_ui(c, 0xffff)));
1988 break;
1989
1990 default:
1991 fprintf(stderr, "Unknown intrinsic: ");
1992 nir_print_instr(&instr->instr, stderr);
1993 fprintf(stderr, "\n");
1994 break;
1995 }
1996 }
1997
1998 /* Clears (activates) the execute flags for any channels whose jump target
1999 * matches this block.
2000 *
2001 * XXX perf: Could we be using flpush/flpop somehow for our execution channel
2002 * enabling?
2003 *
2004 * XXX perf: For uniform control flow, we should be able to skip c->execute
2005 * handling entirely.
2006 */
2007 static void
2008 ntq_activate_execute_for_block(struct v3d_compile *c)
2009 {
2010 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
2011 c->execute, vir_uniform_ui(c, c->cur_block->index)),
2012 V3D_QPU_PF_PUSHZ);
2013
2014 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2015 }
2016
2017 static void
2018 ntq_emit_uniform_if(struct v3d_compile *c, nir_if *if_stmt)
2019 {
2020 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2021 bool empty_else_block =
2022 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2023 exec_list_is_empty(&nir_else_block->instr_list));
2024
2025 struct qblock *then_block = vir_new_block(c);
2026 struct qblock *after_block = vir_new_block(c);
2027 struct qblock *else_block;
2028 if (empty_else_block)
2029 else_block = after_block;
2030 else
2031 else_block = vir_new_block(c);
2032
2033 /* Set up the flags for the IF condition (taking the THEN branch). */
2034 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
2035
2036 /* Jump to ELSE. */
2037 vir_BRANCH(c, cond == V3D_QPU_COND_IFA ?
2038 V3D_QPU_BRANCH_COND_ALLNA :
2039 V3D_QPU_BRANCH_COND_ALLA);
2040 vir_link_blocks(c->cur_block, else_block);
2041 vir_link_blocks(c->cur_block, then_block);
2042
2043 /* Process the THEN block. */
2044 vir_set_emit_block(c, then_block);
2045 ntq_emit_cf_list(c, &if_stmt->then_list);
2046
2047 if (!empty_else_block) {
2048 /* At the end of the THEN block, jump to ENDIF */
2049 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALWAYS);
2050 vir_link_blocks(c->cur_block, after_block);
2051
2052 /* Emit the else block. */
2053 vir_set_emit_block(c, else_block);
2054 ntq_activate_execute_for_block(c);
2055 ntq_emit_cf_list(c, &if_stmt->else_list);
2056 }
2057
2058 vir_link_blocks(c->cur_block, after_block);
2059
2060 vir_set_emit_block(c, after_block);
2061 }
2062
2063 static void
2064 ntq_emit_nonuniform_if(struct v3d_compile *c, nir_if *if_stmt)
2065 {
2066 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2067 bool empty_else_block =
2068 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2069 exec_list_is_empty(&nir_else_block->instr_list));
2070
2071 struct qblock *then_block = vir_new_block(c);
2072 struct qblock *after_block = vir_new_block(c);
2073 struct qblock *else_block;
2074 if (empty_else_block)
2075 else_block = after_block;
2076 else
2077 else_block = vir_new_block(c);
2078
2079 bool was_top_level = false;
2080 if (c->execute.file == QFILE_NULL) {
2081 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2082 was_top_level = true;
2083 }
2084
2085 /* Set up the flags for the IF condition (taking the THEN branch). */
2086 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
2087
2088 /* Update the flags+cond to mean "Taking the ELSE branch (!cond) and
2089 * was previously active (execute Z) for updating the exec flags.
2090 */
2091 if (was_top_level) {
2092 cond = v3d_qpu_cond_invert(cond);
2093 } else {
2094 struct qinst *inst = vir_MOV_dest(c, vir_nop_reg(), c->execute);
2095 if (cond == V3D_QPU_COND_IFA) {
2096 vir_set_uf(inst, V3D_QPU_UF_NORNZ);
2097 } else {
2098 vir_set_uf(inst, V3D_QPU_UF_ANDZ);
2099 cond = V3D_QPU_COND_IFA;
2100 }
2101 }
2102
2103 vir_MOV_cond(c, cond,
2104 c->execute,
2105 vir_uniform_ui(c, else_block->index));
2106
2107 /* Jump to ELSE if nothing is active for THEN, otherwise fall
2108 * through.
2109 */
2110 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
2111 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
2112 vir_link_blocks(c->cur_block, else_block);
2113 vir_link_blocks(c->cur_block, then_block);
2114
2115 /* Process the THEN block. */
2116 vir_set_emit_block(c, then_block);
2117 ntq_emit_cf_list(c, &if_stmt->then_list);
2118
2119 if (!empty_else_block) {
2120 /* Handle the end of the THEN block. First, all currently
2121 * active channels update their execute flags to point to
2122 * ENDIF
2123 */
2124 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
2125 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2126 vir_uniform_ui(c, after_block->index));
2127
2128 /* If everything points at ENDIF, then jump there immediately. */
2129 vir_PF(c, vir_XOR(c, c->execute,
2130 vir_uniform_ui(c, after_block->index)),
2131 V3D_QPU_PF_PUSHZ);
2132 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
2133 vir_link_blocks(c->cur_block, after_block);
2134 vir_link_blocks(c->cur_block, else_block);
2135
2136 vir_set_emit_block(c, else_block);
2137 ntq_activate_execute_for_block(c);
2138 ntq_emit_cf_list(c, &if_stmt->else_list);
2139 }
2140
2141 vir_link_blocks(c->cur_block, after_block);
2142
2143 vir_set_emit_block(c, after_block);
2144 if (was_top_level)
2145 c->execute = c->undef;
2146 else
2147 ntq_activate_execute_for_block(c);
2148 }
2149
2150 static void
2151 ntq_emit_if(struct v3d_compile *c, nir_if *nif)
2152 {
2153 if (c->execute.file == QFILE_NULL &&
2154 nir_src_is_dynamically_uniform(nif->condition)) {
2155 ntq_emit_uniform_if(c, nif);
2156 } else {
2157 ntq_emit_nonuniform_if(c, nif);
2158 }
2159 }
2160
2161 static void
2162 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
2163 {
2164 switch (jump->type) {
2165 case nir_jump_break:
2166 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
2167 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2168 vir_uniform_ui(c, c->loop_break_block->index));
2169 break;
2170
2171 case nir_jump_continue:
2172 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
2173 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2174 vir_uniform_ui(c, c->loop_cont_block->index));
2175 break;
2176
2177 case nir_jump_return:
2178 unreachable("All returns shouold be lowered\n");
2179 }
2180 }
2181
2182 static void
2183 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
2184 {
2185 switch (instr->type) {
2186 case nir_instr_type_deref:
2187 /* ignored, will be walked by the intrinsic using it. */
2188 break;
2189
2190 case nir_instr_type_alu:
2191 ntq_emit_alu(c, nir_instr_as_alu(instr));
2192 break;
2193
2194 case nir_instr_type_intrinsic:
2195 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
2196 break;
2197
2198 case nir_instr_type_load_const:
2199 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
2200 break;
2201
2202 case nir_instr_type_ssa_undef:
2203 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
2204 break;
2205
2206 case nir_instr_type_tex:
2207 ntq_emit_tex(c, nir_instr_as_tex(instr));
2208 break;
2209
2210 case nir_instr_type_jump:
2211 ntq_emit_jump(c, nir_instr_as_jump(instr));
2212 break;
2213
2214 default:
2215 fprintf(stderr, "Unknown NIR instr type: ");
2216 nir_print_instr(instr, stderr);
2217 fprintf(stderr, "\n");
2218 abort();
2219 }
2220 }
2221
2222 static void
2223 ntq_emit_block(struct v3d_compile *c, nir_block *block)
2224 {
2225 nir_foreach_instr(instr, block) {
2226 ntq_emit_instr(c, instr);
2227 }
2228 }
2229
2230 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
2231
2232 static void
2233 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
2234 {
2235 bool was_top_level = false;
2236 if (c->execute.file == QFILE_NULL) {
2237 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2238 was_top_level = true;
2239 }
2240
2241 struct qblock *save_loop_cont_block = c->loop_cont_block;
2242 struct qblock *save_loop_break_block = c->loop_break_block;
2243
2244 c->loop_cont_block = vir_new_block(c);
2245 c->loop_break_block = vir_new_block(c);
2246
2247 vir_link_blocks(c->cur_block, c->loop_cont_block);
2248 vir_set_emit_block(c, c->loop_cont_block);
2249 ntq_activate_execute_for_block(c);
2250
2251 ntq_emit_cf_list(c, &loop->body);
2252
2253 /* Re-enable any previous continues now, so our ANYA check below
2254 * works.
2255 *
2256 * XXX: Use the .ORZ flags update, instead.
2257 */
2258 vir_PF(c, vir_XOR(c,
2259 c->execute,
2260 vir_uniform_ui(c, c->loop_cont_block->index)),
2261 V3D_QPU_PF_PUSHZ);
2262 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2263
2264 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
2265
2266 struct qinst *branch = vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
2267 /* Pixels that were not dispatched or have been discarded should not
2268 * contribute to looping again.
2269 */
2270 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P;
2271 vir_link_blocks(c->cur_block, c->loop_cont_block);
2272 vir_link_blocks(c->cur_block, c->loop_break_block);
2273
2274 vir_set_emit_block(c, c->loop_break_block);
2275 if (was_top_level)
2276 c->execute = c->undef;
2277 else
2278 ntq_activate_execute_for_block(c);
2279
2280 c->loop_break_block = save_loop_break_block;
2281 c->loop_cont_block = save_loop_cont_block;
2282
2283 c->loops++;
2284 }
2285
2286 static void
2287 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
2288 {
2289 fprintf(stderr, "FUNCTIONS not handled.\n");
2290 abort();
2291 }
2292
2293 static void
2294 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
2295 {
2296 foreach_list_typed(nir_cf_node, node, node, list) {
2297 switch (node->type) {
2298 case nir_cf_node_block:
2299 ntq_emit_block(c, nir_cf_node_as_block(node));
2300 break;
2301
2302 case nir_cf_node_if:
2303 ntq_emit_if(c, nir_cf_node_as_if(node));
2304 break;
2305
2306 case nir_cf_node_loop:
2307 ntq_emit_loop(c, nir_cf_node_as_loop(node));
2308 break;
2309
2310 case nir_cf_node_function:
2311 ntq_emit_function(c, nir_cf_node_as_function(node));
2312 break;
2313
2314 default:
2315 fprintf(stderr, "Unknown NIR node type\n");
2316 abort();
2317 }
2318 }
2319 }
2320
2321 static void
2322 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
2323 {
2324 ntq_setup_registers(c, &impl->registers);
2325 ntq_emit_cf_list(c, &impl->body);
2326 }
2327
2328 static void
2329 nir_to_vir(struct v3d_compile *c)
2330 {
2331 switch (c->s->info.stage) {
2332 case MESA_SHADER_FRAGMENT:
2333 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
2334 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
2335 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
2336
2337 /* XXX perf: We could set the "disable implicit point/line
2338 * varyings" field in the shader record and not emit these, if
2339 * they're not going to be used.
2340 */
2341 if (c->fs_key->is_points) {
2342 c->point_x = emit_fragment_varying(c, NULL, 0, 0);
2343 c->point_y = emit_fragment_varying(c, NULL, 0, 0);
2344 } else if (c->fs_key->is_lines) {
2345 c->line_x = emit_fragment_varying(c, NULL, 0, 0);
2346 }
2347 break;
2348 case MESA_SHADER_COMPUTE:
2349 /* Set up the TSO for barriers, assuming we do some. */
2350 if (c->devinfo->ver < 42) {
2351 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
2352 V3D_QPU_WADDR_SYNC));
2353 }
2354
2355 if (c->s->info.system_values_read &
2356 ((1ull << SYSTEM_VALUE_LOCAL_INVOCATION_INDEX) |
2357 (1ull << SYSTEM_VALUE_WORK_GROUP_ID))) {
2358 c->cs_payload[0] = vir_MOV(c, vir_reg(QFILE_REG, 0));
2359 }
2360 if ((c->s->info.system_values_read &
2361 ((1ull << SYSTEM_VALUE_WORK_GROUP_ID))) ||
2362 c->s->info.cs.shared_size) {
2363 c->cs_payload[1] = vir_MOV(c, vir_reg(QFILE_REG, 2));
2364 }
2365
2366 /* Set up the division between gl_LocalInvocationIndex and
2367 * wg_in_mem in the payload reg.
2368 */
2369 int wg_size = (c->s->info.cs.local_size[0] *
2370 c->s->info.cs.local_size[1] *
2371 c->s->info.cs.local_size[2]);
2372 c->local_invocation_index_bits =
2373 ffs(util_next_power_of_two(MAX2(wg_size, 64))) - 1;
2374 assert(c->local_invocation_index_bits <= 8);
2375
2376 if (c->s->info.cs.shared_size) {
2377 struct qreg wg_in_mem = vir_SHR(c, c->cs_payload[1],
2378 vir_uniform_ui(c, 16));
2379 if (c->s->info.cs.local_size[0] != 1 ||
2380 c->s->info.cs.local_size[1] != 1 ||
2381 c->s->info.cs.local_size[2] != 1) {
2382 int wg_bits = (16 -
2383 c->local_invocation_index_bits);
2384 int wg_mask = (1 << wg_bits) - 1;
2385 wg_in_mem = vir_AND(c, wg_in_mem,
2386 vir_uniform_ui(c, wg_mask));
2387 }
2388 struct qreg shared_per_wg =
2389 vir_uniform_ui(c, c->s->info.cs.shared_size);
2390
2391 c->cs_shared_offset =
2392 vir_ADD(c,
2393 vir_uniform(c, QUNIFORM_SHARED_OFFSET,0),
2394 vir_UMUL(c, wg_in_mem, shared_per_wg));
2395 }
2396 break;
2397 default:
2398 break;
2399 }
2400
2401 if (c->s->info.stage == MESA_SHADER_FRAGMENT)
2402 ntq_setup_fs_inputs(c);
2403 else
2404 ntq_setup_vpm_inputs(c);
2405
2406 ntq_setup_outputs(c);
2407 ntq_setup_uniforms(c);
2408 ntq_setup_registers(c, &c->s->registers);
2409
2410 /* Find the main function and emit the body. */
2411 nir_foreach_function(function, c->s) {
2412 assert(strcmp(function->name, "main") == 0);
2413 assert(function->impl);
2414 ntq_emit_impl(c, function->impl);
2415 }
2416 }
2417
2418 const nir_shader_compiler_options v3d_nir_options = {
2419 .lower_all_io_to_temps = true,
2420 .lower_extract_byte = true,
2421 .lower_extract_word = true,
2422 .lower_bfm = true,
2423 .lower_bitfield_insert_to_shifts = true,
2424 .lower_bitfield_extract_to_shifts = true,
2425 .lower_bitfield_reverse = true,
2426 .lower_bit_count = true,
2427 .lower_cs_local_id_from_index = true,
2428 .lower_ffract = true,
2429 .lower_pack_unorm_2x16 = true,
2430 .lower_pack_snorm_2x16 = true,
2431 .lower_pack_unorm_4x8 = true,
2432 .lower_pack_snorm_4x8 = true,
2433 .lower_unpack_unorm_4x8 = true,
2434 .lower_unpack_snorm_4x8 = true,
2435 .lower_pack_half_2x16 = true,
2436 .lower_unpack_half_2x16 = true,
2437 .lower_fdiv = true,
2438 .lower_find_lsb = true,
2439 .lower_ffma = true,
2440 .lower_flrp32 = true,
2441 .lower_fpow = true,
2442 .lower_fsat = true,
2443 .lower_fsqrt = true,
2444 .lower_ifind_msb = true,
2445 .lower_isign = true,
2446 .lower_ldexp = true,
2447 .lower_mul_high = true,
2448 .lower_wpos_pntc = true,
2449 .native_integers = true,
2450 };
2451
2452 /**
2453 * When demoting a shader down to single-threaded, removes the THRSW
2454 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
2455 * program end).
2456 */
2457 static void
2458 vir_remove_thrsw(struct v3d_compile *c)
2459 {
2460 vir_for_each_block(block, c) {
2461 vir_for_each_inst_safe(inst, block) {
2462 if (inst->qpu.sig.thrsw)
2463 vir_remove_instruction(c, inst);
2464 }
2465 }
2466
2467 c->last_thrsw = NULL;
2468 }
2469
2470 void
2471 vir_emit_last_thrsw(struct v3d_compile *c)
2472 {
2473 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
2474 * switching, so disable threads if we didn't do any TMU ops (each of
2475 * which would have emitted a THRSW).
2476 */
2477 if (!c->last_thrsw_at_top_level && c->devinfo->ver < 41) {
2478 c->threads = 1;
2479 if (c->last_thrsw)
2480 vir_remove_thrsw(c);
2481 return;
2482 }
2483
2484 /* If we're threaded and the last THRSW was in conditional code, then
2485 * we need to emit another one so that we can flag it as the last
2486 * thrsw.
2487 */
2488 if (c->last_thrsw && !c->last_thrsw_at_top_level) {
2489 assert(c->devinfo->ver >= 41);
2490 vir_emit_thrsw(c);
2491 }
2492
2493 /* If we're threaded, then we need to mark the last THRSW instruction
2494 * so we can emit a pair of them at QPU emit time.
2495 *
2496 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2497 * post-last-THRSW state, so we can skip this.
2498 */
2499 if (!c->last_thrsw && c->s->info.stage == MESA_SHADER_FRAGMENT) {
2500 assert(c->devinfo->ver >= 41);
2501 vir_emit_thrsw(c);
2502 }
2503
2504 if (c->last_thrsw)
2505 c->last_thrsw->is_last_thrsw = true;
2506 }
2507
2508 /* There's a flag in the shader for "center W is needed for reasons other than
2509 * non-centroid varyings", so we just walk the program after VIR optimization
2510 * to see if it's used. It should be harmless to set even if we only use
2511 * center W for varyings.
2512 */
2513 static void
2514 vir_check_payload_w(struct v3d_compile *c)
2515 {
2516 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
2517 return;
2518
2519 vir_for_each_inst_inorder(inst, c) {
2520 for (int i = 0; i < vir_get_nsrc(inst); i++) {
2521 if (inst->src[i].file == QFILE_REG &&
2522 inst->src[i].index == 0) {
2523 c->uses_center_w = true;
2524 return;
2525 }
2526 }
2527 }
2528
2529 }
2530
2531 void
2532 v3d_nir_to_vir(struct v3d_compile *c)
2533 {
2534 if (V3D_DEBUG & (V3D_DEBUG_NIR |
2535 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2536 fprintf(stderr, "%s prog %d/%d NIR:\n",
2537 vir_get_stage_name(c),
2538 c->program_id, c->variant_id);
2539 nir_print_shader(c->s, stderr);
2540 }
2541
2542 nir_to_vir(c);
2543
2544 /* Emit the last THRSW before STVPM and TLB writes. */
2545 vir_emit_last_thrsw(c);
2546
2547 switch (c->s->info.stage) {
2548 case MESA_SHADER_FRAGMENT:
2549 emit_frag_end(c);
2550 break;
2551 case MESA_SHADER_VERTEX:
2552 emit_vert_end(c);
2553 break;
2554 default:
2555 unreachable("bad stage");
2556 }
2557
2558 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2559 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2560 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
2561 vir_get_stage_name(c),
2562 c->program_id, c->variant_id);
2563 vir_dump(c);
2564 fprintf(stderr, "\n");
2565 }
2566
2567 vir_optimize(c);
2568 vir_lower_uniforms(c);
2569
2570 vir_check_payload_w(c);
2571
2572 /* XXX perf: On VC4, we do a VIR-level instruction scheduling here.
2573 * We used that on that platform to pipeline TMU writes and reduce the
2574 * number of thread switches, as well as try (mostly successfully) to
2575 * reduce maximum register pressure to allow more threads. We should
2576 * do something of that sort for V3D -- either instruction scheduling
2577 * here, or delay the the THRSW and LDTMUs from our texture
2578 * instructions until the results are needed.
2579 */
2580
2581 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2582 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2583 fprintf(stderr, "%s prog %d/%d VIR:\n",
2584 vir_get_stage_name(c),
2585 c->program_id, c->variant_id);
2586 vir_dump(c);
2587 fprintf(stderr, "\n");
2588 }
2589
2590 /* Attempt to allocate registers for the temporaries. If we fail,
2591 * reduce thread count and try again.
2592 */
2593 int min_threads = (c->devinfo->ver >= 41) ? 2 : 1;
2594 struct qpu_reg *temp_registers;
2595 while (true) {
2596 bool spilled;
2597 temp_registers = v3d_register_allocate(c, &spilled);
2598 if (spilled)
2599 continue;
2600
2601 if (temp_registers)
2602 break;
2603
2604 if (c->threads == min_threads) {
2605 fprintf(stderr, "Failed to register allocate at %d threads:\n",
2606 c->threads);
2607 vir_dump(c);
2608 c->failed = true;
2609 return;
2610 }
2611
2612 c->threads /= 2;
2613
2614 if (c->threads == 1)
2615 vir_remove_thrsw(c);
2616 }
2617
2618 v3d_vir_to_qpu(c, temp_registers);
2619 }