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broadcom/compiler: Set up passthrough Z when doing FS discards.
[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "v3d_compiler.h"
33
34 /* We don't do any address packing. */
35 #define __gen_user_data void
36 #define __gen_address_type uint32_t
37 #define __gen_address_offset(reloc) (*reloc)
38 #define __gen_emit_reloc(cl, reloc)
39 #include "cle/v3d_packet_v33_pack.h"
40
41 static struct qreg
42 ntq_get_src(struct v3d_compile *c, nir_src src, int i);
43 static void
44 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
45
46 static void
47 resize_qreg_array(struct v3d_compile *c,
48 struct qreg **regs,
49 uint32_t *size,
50 uint32_t decl_size)
51 {
52 if (*size >= decl_size)
53 return;
54
55 uint32_t old_size = *size;
56 *size = MAX2(*size * 2, decl_size);
57 *regs = reralloc(c, *regs, struct qreg, *size);
58 if (!*regs) {
59 fprintf(stderr, "Malloc failure\n");
60 abort();
61 }
62
63 for (uint32_t i = old_size; i < *size; i++)
64 (*regs)[i] = c->undef;
65 }
66
67 static struct qreg
68 vir_SFU(struct v3d_compile *c, int waddr, struct qreg src)
69 {
70 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, waddr), src);
71 return vir_FMOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4));
72 }
73
74 static struct qreg
75 vir_LDTMU(struct v3d_compile *c)
76 {
77 vir_NOP(c)->qpu.sig.ldtmu = true;
78 return vir_MOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4));
79 }
80
81 static struct qreg
82 indirect_uniform_load(struct v3d_compile *c, nir_intrinsic_instr *intr)
83 {
84 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
85 uint32_t offset = nir_intrinsic_base(intr);
86 struct v3d_ubo_range *range = NULL;
87 unsigned i;
88
89 for (i = 0; i < c->num_ubo_ranges; i++) {
90 range = &c->ubo_ranges[i];
91 if (offset >= range->src_offset &&
92 offset < range->src_offset + range->size) {
93 break;
94 }
95 }
96 /* The driver-location-based offset always has to be within a declared
97 * uniform range.
98 */
99 assert(i != c->num_ubo_ranges);
100 if (!c->ubo_range_used[i]) {
101 c->ubo_range_used[i] = true;
102 range->dst_offset = c->next_ubo_dst_offset;
103 c->next_ubo_dst_offset += range->size;
104 }
105
106 offset -= range->src_offset;
107
108 if (range->dst_offset + offset != 0) {
109 indirect_offset = vir_ADD(c, indirect_offset,
110 vir_uniform_ui(c, range->dst_offset +
111 offset));
112 }
113
114 /* Adjust for where we stored the TGSI register base. */
115 vir_ADD_dest(c,
116 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA),
117 vir_uniform(c, QUNIFORM_UBO_ADDR, 0),
118 indirect_offset);
119
120 return vir_LDTMU(c);
121 }
122
123 static struct qreg *
124 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
125 {
126 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
127 def->num_components);
128 _mesa_hash_table_insert(c->def_ht, def, qregs);
129 return qregs;
130 }
131
132 /**
133 * This function is responsible for getting VIR results into the associated
134 * storage for a NIR instruction.
135 *
136 * If it's a NIR SSA def, then we just set the associated hash table entry to
137 * the new result.
138 *
139 * If it's a NIR reg, then we need to update the existing qreg assigned to the
140 * NIR destination with the incoming value. To do that without introducing
141 * new MOVs, we require that the incoming qreg either be a uniform, or be
142 * SSA-defined by the previous VIR instruction in the block and rewritable by
143 * this function. That lets us sneak ahead and insert the SF flag beforehand
144 * (knowing that the previous instruction doesn't depend on flags) and rewrite
145 * its destination to be the NIR reg's destination
146 */
147 static void
148 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
149 struct qreg result)
150 {
151 struct qinst *last_inst = NULL;
152 if (!list_empty(&c->cur_block->instructions))
153 last_inst = (struct qinst *)c->cur_block->instructions.prev;
154
155 assert(result.file == QFILE_UNIF ||
156 (result.file == QFILE_TEMP &&
157 last_inst && last_inst == c->defs[result.index]));
158
159 if (dest->is_ssa) {
160 assert(chan < dest->ssa.num_components);
161
162 struct qreg *qregs;
163 struct hash_entry *entry =
164 _mesa_hash_table_search(c->def_ht, &dest->ssa);
165
166 if (entry)
167 qregs = entry->data;
168 else
169 qregs = ntq_init_ssa_def(c, &dest->ssa);
170
171 qregs[chan] = result;
172 } else {
173 nir_register *reg = dest->reg.reg;
174 assert(dest->reg.base_offset == 0);
175 assert(reg->num_array_elems == 0);
176 struct hash_entry *entry =
177 _mesa_hash_table_search(c->def_ht, reg);
178 struct qreg *qregs = entry->data;
179
180 /* Insert a MOV if the source wasn't an SSA def in the
181 * previous instruction.
182 */
183 if (result.file == QFILE_UNIF) {
184 result = vir_MOV(c, result);
185 last_inst = c->defs[result.index];
186 }
187
188 /* We know they're both temps, so just rewrite index. */
189 c->defs[last_inst->dst.index] = NULL;
190 last_inst->dst.index = qregs[chan].index;
191
192 /* If we're in control flow, then make this update of the reg
193 * conditional on the execution mask.
194 */
195 if (c->execute.file != QFILE_NULL) {
196 last_inst->dst.index = qregs[chan].index;
197
198 /* Set the flags to the current exec mask. To insert
199 * the flags push, we temporarily remove our SSA
200 * instruction.
201 */
202 list_del(&last_inst->link);
203 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
204 list_addtail(&last_inst->link,
205 &c->cur_block->instructions);
206
207 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
208 last_inst->cond_is_exec_mask = true;
209 }
210 }
211 }
212
213 static struct qreg
214 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
215 {
216 struct hash_entry *entry;
217 if (src.is_ssa) {
218 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
219 assert(i < src.ssa->num_components);
220 } else {
221 nir_register *reg = src.reg.reg;
222 entry = _mesa_hash_table_search(c->def_ht, reg);
223 assert(reg->num_array_elems == 0);
224 assert(src.reg.base_offset == 0);
225 assert(i < reg->num_components);
226 }
227
228 struct qreg *qregs = entry->data;
229 return qregs[i];
230 }
231
232 static struct qreg
233 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
234 unsigned src)
235 {
236 assert(util_is_power_of_two(instr->dest.write_mask));
237 unsigned chan = ffs(instr->dest.write_mask) - 1;
238 struct qreg r = ntq_get_src(c, instr->src[src].src,
239 instr->src[src].swizzle[chan]);
240
241 assert(!instr->src[src].abs);
242 assert(!instr->src[src].negate);
243
244 return r;
245 };
246
247 static inline struct qreg
248 vir_SAT(struct v3d_compile *c, struct qreg val)
249 {
250 return vir_FMAX(c,
251 vir_FMIN(c, val, vir_uniform_f(c, 1.0)),
252 vir_uniform_f(c, 0.0));
253 }
254
255 static struct qreg
256 ntq_umul(struct v3d_compile *c, struct qreg src0, struct qreg src1)
257 {
258 vir_MULTOP(c, src0, src1);
259 return vir_UMUL24(c, src0, src1);
260 }
261
262 static struct qreg
263 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
264 {
265 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
266 }
267
268 static void
269 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
270 {
271 unsigned unit = instr->texture_index;
272 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
273 int dest_size = nir_tex_instr_dest_size(instr);
274
275 struct qreg lod = c->undef;
276 if (lod_index != -1)
277 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
278
279 for (int i = 0; i < dest_size; i++) {
280 assert(i < 3);
281 enum quniform_contents contents;
282
283 if (instr->is_array && i == dest_size - 1)
284 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
285 else
286 contents = QUNIFORM_TEXTURE_WIDTH + i;
287
288 struct qreg size = vir_uniform(c, contents, unit);
289
290 switch (instr->sampler_dim) {
291 case GLSL_SAMPLER_DIM_1D:
292 case GLSL_SAMPLER_DIM_2D:
293 case GLSL_SAMPLER_DIM_3D:
294 case GLSL_SAMPLER_DIM_CUBE:
295 /* Don't minify the array size. */
296 if (!(instr->is_array && i == dest_size - 1)) {
297 size = ntq_minify(c, size, lod);
298 }
299 break;
300
301 case GLSL_SAMPLER_DIM_RECT:
302 /* There's no LOD field for rects */
303 break;
304
305 default:
306 unreachable("Bad sampler type");
307 }
308
309 ntq_store_dest(c, &instr->dest, i, size);
310 }
311 }
312
313 static void
314 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
315 {
316 unsigned unit = instr->texture_index;
317
318 /* Since each texture sampling op requires uploading uniforms to
319 * reference the texture, there's no HW support for texture size and
320 * you just upload uniforms containing the size.
321 */
322 switch (instr->op) {
323 case nir_texop_query_levels:
324 ntq_store_dest(c, &instr->dest, 0,
325 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
326 return;
327 case nir_texop_txs:
328 ntq_emit_txs(c, instr);
329 return;
330 default:
331 break;
332 }
333
334 struct V3D33_TEXTURE_UNIFORM_PARAMETER_0_CFG_MODE1 p0_unpacked = {
335 V3D33_TEXTURE_UNIFORM_PARAMETER_0_CFG_MODE1_header,
336
337 .fetch_sample_mode = instr->op == nir_texop_txf,
338 };
339
340 switch (instr->sampler_dim) {
341 case GLSL_SAMPLER_DIM_1D:
342 if (instr->is_array)
343 p0_unpacked.lookup_type = TEXTURE_1D_ARRAY;
344 else
345 p0_unpacked.lookup_type = TEXTURE_1D;
346 break;
347 case GLSL_SAMPLER_DIM_2D:
348 case GLSL_SAMPLER_DIM_RECT:
349 if (instr->is_array)
350 p0_unpacked.lookup_type = TEXTURE_2D_ARRAY;
351 else
352 p0_unpacked.lookup_type = TEXTURE_2D;
353 break;
354 case GLSL_SAMPLER_DIM_3D:
355 p0_unpacked.lookup_type = TEXTURE_3D;
356 break;
357 case GLSL_SAMPLER_DIM_CUBE:
358 p0_unpacked.lookup_type = TEXTURE_CUBE_MAP;
359 break;
360 default:
361 unreachable("Bad sampler type");
362 }
363
364 struct qreg coords[5];
365 int next_coord = 0;
366 for (unsigned i = 0; i < instr->num_srcs; i++) {
367 switch (instr->src[i].src_type) {
368 case nir_tex_src_coord:
369 for (int j = 0; j < instr->coord_components; j++) {
370 coords[next_coord++] =
371 ntq_get_src(c, instr->src[i].src, j);
372 }
373 if (instr->coord_components < 2)
374 coords[next_coord++] = vir_uniform_f(c, 0.5);
375 break;
376 case nir_tex_src_bias:
377 coords[next_coord++] =
378 ntq_get_src(c, instr->src[i].src, 0);
379
380 p0_unpacked.bias_supplied = true;
381 break;
382 case nir_tex_src_lod:
383 /* XXX: Needs base level addition */
384 coords[next_coord++] =
385 ntq_get_src(c, instr->src[i].src, 0);
386
387 if (instr->op != nir_texop_txf &&
388 instr->op != nir_texop_tg4) {
389 p0_unpacked.disable_autolod_use_bias_only = true;
390 }
391 break;
392 case nir_tex_src_comparator:
393 coords[next_coord++] =
394 ntq_get_src(c, instr->src[i].src, 0);
395
396 p0_unpacked.shadow = true;
397 break;
398
399 case nir_tex_src_offset: {
400 nir_const_value *offset =
401 nir_src_as_const_value(instr->src[i].src);
402 p0_unpacked.texel_offset_for_s_coordinate =
403 offset->i32[0];
404
405 if (instr->coord_components >= 2)
406 p0_unpacked.texel_offset_for_t_coordinate =
407 offset->i32[1];
408
409 if (instr->coord_components >= 3)
410 p0_unpacked.texel_offset_for_r_coordinate =
411 offset->i32[2];
412 break;
413 }
414
415 default:
416 unreachable("unknown texture source");
417 }
418 }
419
420 uint32_t p0_packed;
421 V3D33_TEXTURE_UNIFORM_PARAMETER_0_CFG_MODE1_pack(NULL,
422 (uint8_t *)&p0_packed,
423 &p0_unpacked);
424
425 /* There is no native support for GL texture rectangle coordinates, so
426 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
427 * 1]).
428 */
429 if (instr->sampler_dim == GLSL_SAMPLER_DIM_RECT) {
430 coords[0] = vir_FMUL(c, coords[0],
431 vir_uniform(c, QUNIFORM_TEXRECT_SCALE_X,
432 unit));
433 coords[1] = vir_FMUL(c, coords[1],
434 vir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y,
435 unit));
436 }
437
438 struct qreg texture_u[] = {
439 vir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0_0 + unit, p0_packed),
440 vir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
441 };
442 uint32_t next_texture_u = 0;
443
444 for (int i = 0; i < next_coord; i++) {
445 struct qreg dst;
446
447 if (i == next_coord - 1)
448 dst = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUL);
449 else
450 dst = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMU);
451
452 struct qinst *tmu = vir_MOV_dest(c, dst, coords[i]);
453
454 if (i < 2) {
455 tmu->has_implicit_uniform = true;
456 tmu->src[vir_get_implicit_uniform_src(tmu)] =
457 texture_u[next_texture_u++];
458 }
459 }
460
461 bool return_16 = (c->key->tex[unit].return_size == 16 ||
462 p0_unpacked.shadow);
463
464 struct qreg return_values[4];
465 for (int i = 0; i < c->key->tex[unit].return_channels; i++)
466 return_values[i] = vir_LDTMU(c);
467 /* Swizzling .zw of an RG texture should give undefined results, not
468 * crash the compiler.
469 */
470 for (int i = c->key->tex[unit].return_channels; i < 4; i++)
471 return_values[i] = c->undef;
472
473 for (int i = 0; i < nir_tex_instr_dest_size(instr); i++) {
474 struct qreg chan;
475
476 if (return_16) {
477 STATIC_ASSERT(PIPE_SWIZZLE_X == 0);
478 chan = return_values[i / 2];
479
480 enum v3d_qpu_input_unpack unpack;
481 if (i & 1)
482 unpack = V3D_QPU_UNPACK_H;
483 else
484 unpack = V3D_QPU_UNPACK_L;
485
486 chan = vir_FMOV(c, chan);
487 vir_set_unpack(c->defs[chan.index], 0, unpack);
488 } else {
489 chan = vir_MOV(c, return_values[i]);
490 }
491 ntq_store_dest(c, &instr->dest, i, chan);
492 }
493 }
494
495 static struct qreg
496 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
497 {
498 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
499 if (is_cos)
500 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
501
502 struct qreg periods = vir_FROUND(c, input);
503 struct qreg sin_output = vir_SFU(c, V3D_QPU_WADDR_SIN,
504 vir_FSUB(c, input, periods));
505 return vir_XOR(c, sin_output, vir_SHL(c,
506 vir_FTOIN(c, periods),
507 vir_uniform_ui(c, -1)));
508 }
509
510 static struct qreg
511 ntq_fsign(struct v3d_compile *c, struct qreg src)
512 {
513 struct qreg t = vir_get_temp(c);
514
515 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
516 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHZ);
517 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
518 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHN);
519 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
520 return vir_MOV(c, t);
521 }
522
523 static struct qreg
524 ntq_isign(struct v3d_compile *c, struct qreg src)
525 {
526 struct qreg t = vir_get_temp(c);
527
528 vir_MOV_dest(c, t, vir_uniform_ui(c, 0));
529 vir_PF(c, vir_MOV(c, src), V3D_QPU_PF_PUSHZ);
530 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_ui(c, 1));
531 vir_PF(c, vir_MOV(c, src), V3D_QPU_PF_PUSHN);
532 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_ui(c, -1));
533 return vir_MOV(c, t);
534 }
535
536 static void
537 emit_fragcoord_input(struct v3d_compile *c, int attr)
538 {
539 c->inputs[attr * 4 + 0] = vir_FXCD(c);
540 c->inputs[attr * 4 + 1] = vir_FYCD(c);
541 c->inputs[attr * 4 + 2] = c->payload_z;
542 c->inputs[attr * 4 + 3] = vir_SFU(c, V3D_QPU_WADDR_RECIP,
543 c->payload_w);
544 }
545
546 static struct qreg
547 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
548 uint8_t swizzle)
549 {
550 struct qreg vary = vir_reg(QFILE_VARY, ~0);
551 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
552
553 /* For gl_PointCoord input or distance along a line, we'll be called
554 * with no nir_variable, and we don't count toward VPM size so we
555 * don't track an input slot.
556 */
557 if (!var) {
558 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
559 }
560
561 int i = c->num_inputs++;
562 c->input_slots[i] = v3d_slot_from_slot_and_component(var->data.location,
563 swizzle);
564
565 switch (var->data.interpolation) {
566 case INTERP_MODE_NONE:
567 case INTERP_MODE_SMOOTH:
568 if (var->data.centroid) {
569 return vir_FADD(c, vir_FMUL(c, vary,
570 c->payload_w_centroid), r5);
571 } else {
572 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
573 }
574 case INTERP_MODE_NOPERSPECTIVE:
575 /* C appears after the mov from the varying.
576 XXX: improve ldvary setup.
577 */
578 return vir_FADD(c, vir_MOV(c, vary), r5);
579 case INTERP_MODE_FLAT:
580 BITSET_SET(c->flat_shade_flags, i);
581 vir_MOV_dest(c, c->undef, vary);
582 return vir_MOV(c, r5);
583 default:
584 unreachable("Bad interp mode");
585 }
586 }
587
588 static void
589 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var)
590 {
591 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
592 c->inputs[attr * 4 + i] =
593 emit_fragment_varying(c, var, i);
594 }
595 }
596
597 static void
598 add_output(struct v3d_compile *c,
599 uint32_t decl_offset,
600 uint8_t slot,
601 uint8_t swizzle)
602 {
603 uint32_t old_array_size = c->outputs_array_size;
604 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
605 decl_offset + 1);
606
607 if (old_array_size != c->outputs_array_size) {
608 c->output_slots = reralloc(c,
609 c->output_slots,
610 struct v3d_varying_slot,
611 c->outputs_array_size);
612 }
613
614 c->output_slots[decl_offset] =
615 v3d_slot_from_slot_and_component(slot, swizzle);
616 }
617
618 static void
619 declare_uniform_range(struct v3d_compile *c, uint32_t start, uint32_t size)
620 {
621 unsigned array_id = c->num_ubo_ranges++;
622 if (array_id >= c->ubo_ranges_array_size) {
623 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
624 array_id + 1);
625 c->ubo_ranges = reralloc(c, c->ubo_ranges,
626 struct v3d_ubo_range,
627 c->ubo_ranges_array_size);
628 c->ubo_range_used = reralloc(c, c->ubo_range_used,
629 bool,
630 c->ubo_ranges_array_size);
631 }
632
633 c->ubo_ranges[array_id].dst_offset = 0;
634 c->ubo_ranges[array_id].src_offset = start;
635 c->ubo_ranges[array_id].size = size;
636 c->ubo_range_used[array_id] = false;
637 }
638
639 /**
640 * If compare_instr is a valid comparison instruction, emits the
641 * compare_instr's comparison and returns the sel_instr's return value based
642 * on the compare_instr's result.
643 */
644 static bool
645 ntq_emit_comparison(struct v3d_compile *c, struct qreg *dest,
646 nir_alu_instr *compare_instr,
647 nir_alu_instr *sel_instr)
648 {
649 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
650 struct qreg src1 = ntq_get_alu_src(c, compare_instr, 1);
651 bool cond_invert = false;
652
653 switch (compare_instr->op) {
654 case nir_op_feq:
655 case nir_op_seq:
656 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHZ);
657 break;
658 case nir_op_ieq:
659 vir_PF(c, vir_XOR(c, src0, src1), V3D_QPU_PF_PUSHZ);
660 break;
661
662 case nir_op_fne:
663 case nir_op_sne:
664 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHZ);
665 cond_invert = true;
666 break;
667 case nir_op_ine:
668 vir_PF(c, vir_XOR(c, src0, src1), V3D_QPU_PF_PUSHZ);
669 cond_invert = true;
670 break;
671
672 case nir_op_fge:
673 case nir_op_sge:
674 vir_PF(c, vir_FCMP(c, src1, src0), V3D_QPU_PF_PUSHC);
675 break;
676 case nir_op_ige:
677 vir_PF(c, vir_MIN(c, src1, src0), V3D_QPU_PF_PUSHC);
678 cond_invert = true;
679 break;
680 case nir_op_uge:
681 vir_PF(c, vir_SUB(c, src0, src1), V3D_QPU_PF_PUSHC);
682 cond_invert = true;
683 break;
684
685 case nir_op_slt:
686 case nir_op_flt:
687 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHN);
688 break;
689 case nir_op_ilt:
690 vir_PF(c, vir_MIN(c, src1, src0), V3D_QPU_PF_PUSHC);
691 break;
692 case nir_op_ult:
693 vir_PF(c, vir_SUB(c, src0, src1), V3D_QPU_PF_PUSHC);
694 break;
695
696 default:
697 return false;
698 }
699
700 enum v3d_qpu_cond cond = (cond_invert ?
701 V3D_QPU_COND_IFNA :
702 V3D_QPU_COND_IFA);
703
704 switch (sel_instr->op) {
705 case nir_op_seq:
706 case nir_op_sne:
707 case nir_op_sge:
708 case nir_op_slt:
709 *dest = vir_SEL(c, cond,
710 vir_uniform_f(c, 1.0), vir_uniform_f(c, 0.0));
711 break;
712
713 case nir_op_bcsel:
714 *dest = vir_SEL(c, cond,
715 ntq_get_alu_src(c, sel_instr, 1),
716 ntq_get_alu_src(c, sel_instr, 2));
717 break;
718
719 default:
720 *dest = vir_SEL(c, cond,
721 vir_uniform_ui(c, ~0), vir_uniform_ui(c, 0));
722 break;
723 }
724
725 /* Make the temporary for nir_store_dest(). */
726 *dest = vir_MOV(c, *dest);
727
728 return true;
729 }
730
731 /**
732 * Attempts to fold a comparison generating a boolean result into the
733 * condition code for selecting between two values, instead of comparing the
734 * boolean result against 0 to generate the condition code.
735 */
736 static struct qreg ntq_emit_bcsel(struct v3d_compile *c, nir_alu_instr *instr,
737 struct qreg *src)
738 {
739 if (!instr->src[0].src.is_ssa)
740 goto out;
741 if (instr->src[0].src.ssa->parent_instr->type != nir_instr_type_alu)
742 goto out;
743 nir_alu_instr *compare =
744 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
745 if (!compare)
746 goto out;
747
748 struct qreg dest;
749 if (ntq_emit_comparison(c, &dest, compare, instr))
750 return dest;
751
752 out:
753 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
754 return vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA, src[1], src[2]));
755 }
756
757
758 static void
759 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
760 {
761 /* This should always be lowered to ALU operations for V3D. */
762 assert(!instr->dest.saturate);
763
764 /* Vectors are special in that they have non-scalarized writemasks,
765 * and just take the first swizzle channel for each argument in order
766 * into each writemask channel.
767 */
768 if (instr->op == nir_op_vec2 ||
769 instr->op == nir_op_vec3 ||
770 instr->op == nir_op_vec4) {
771 struct qreg srcs[4];
772 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
773 srcs[i] = ntq_get_src(c, instr->src[i].src,
774 instr->src[i].swizzle[0]);
775 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
776 ntq_store_dest(c, &instr->dest.dest, i,
777 vir_MOV(c, srcs[i]));
778 return;
779 }
780
781 /* General case: We can just grab the one used channel per src. */
782 struct qreg src[nir_op_infos[instr->op].num_inputs];
783 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
784 src[i] = ntq_get_alu_src(c, instr, i);
785 }
786
787 struct qreg result;
788
789 switch (instr->op) {
790 case nir_op_fmov:
791 case nir_op_imov:
792 result = vir_MOV(c, src[0]);
793 break;
794 case nir_op_fmul:
795 result = vir_FMUL(c, src[0], src[1]);
796 break;
797 case nir_op_fadd:
798 result = vir_FADD(c, src[0], src[1]);
799 break;
800 case nir_op_fsub:
801 result = vir_FSUB(c, src[0], src[1]);
802 break;
803 case nir_op_fmin:
804 result = vir_FMIN(c, src[0], src[1]);
805 break;
806 case nir_op_fmax:
807 result = vir_FMAX(c, src[0], src[1]);
808 break;
809
810 case nir_op_f2i32:
811 result = vir_FTOIZ(c, src[0]);
812 break;
813 case nir_op_f2u32:
814 result = vir_FTOUZ(c, src[0]);
815 break;
816 case nir_op_i2f32:
817 result = vir_ITOF(c, src[0]);
818 break;
819 case nir_op_u2f32:
820 result = vir_UTOF(c, src[0]);
821 break;
822 case nir_op_b2f:
823 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
824 break;
825 case nir_op_b2i:
826 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
827 break;
828 case nir_op_i2b:
829 case nir_op_f2b:
830 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
831 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
832 vir_uniform_ui(c, ~0),
833 vir_uniform_ui(c, 0)));
834 break;
835
836 case nir_op_iadd:
837 result = vir_ADD(c, src[0], src[1]);
838 break;
839 case nir_op_ushr:
840 result = vir_SHR(c, src[0], src[1]);
841 break;
842 case nir_op_isub:
843 result = vir_SUB(c, src[0], src[1]);
844 break;
845 case nir_op_ishr:
846 result = vir_ASR(c, src[0], src[1]);
847 break;
848 case nir_op_ishl:
849 result = vir_SHL(c, src[0], src[1]);
850 break;
851 case nir_op_imin:
852 result = vir_MIN(c, src[0], src[1]);
853 break;
854 case nir_op_umin:
855 result = vir_UMIN(c, src[0], src[1]);
856 break;
857 case nir_op_imax:
858 result = vir_MAX(c, src[0], src[1]);
859 break;
860 case nir_op_umax:
861 result = vir_UMAX(c, src[0], src[1]);
862 break;
863 case nir_op_iand:
864 result = vir_AND(c, src[0], src[1]);
865 break;
866 case nir_op_ior:
867 result = vir_OR(c, src[0], src[1]);
868 break;
869 case nir_op_ixor:
870 result = vir_XOR(c, src[0], src[1]);
871 break;
872 case nir_op_inot:
873 result = vir_NOT(c, src[0]);
874 break;
875
876 case nir_op_imul:
877 result = ntq_umul(c, src[0], src[1]);
878 break;
879
880 case nir_op_seq:
881 case nir_op_sne:
882 case nir_op_sge:
883 case nir_op_slt:
884 case nir_op_feq:
885 case nir_op_fne:
886 case nir_op_fge:
887 case nir_op_flt:
888 case nir_op_ieq:
889 case nir_op_ine:
890 case nir_op_ige:
891 case nir_op_uge:
892 case nir_op_ilt:
893 case nir_op_ult:
894 if (!ntq_emit_comparison(c, &result, instr, instr)) {
895 fprintf(stderr, "Bad comparison instruction\n");
896 }
897 break;
898
899 case nir_op_bcsel:
900 result = ntq_emit_bcsel(c, instr, src);
901 break;
902 case nir_op_fcsel:
903 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
904 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
905 src[1], src[2]));
906 break;
907
908 case nir_op_frcp:
909 result = vir_SFU(c, V3D_QPU_WADDR_RECIP, src[0]);
910 break;
911 case nir_op_frsq:
912 result = vir_SFU(c, V3D_QPU_WADDR_RSQRT, src[0]);
913 break;
914 case nir_op_fexp2:
915 result = vir_SFU(c, V3D_QPU_WADDR_EXP, src[0]);
916 break;
917 case nir_op_flog2:
918 result = vir_SFU(c, V3D_QPU_WADDR_LOG, src[0]);
919 break;
920
921 case nir_op_fceil:
922 result = vir_FCEIL(c, src[0]);
923 break;
924 case nir_op_ffloor:
925 result = vir_FFLOOR(c, src[0]);
926 break;
927 case nir_op_fround_even:
928 result = vir_FROUND(c, src[0]);
929 break;
930 case nir_op_ftrunc:
931 result = vir_FTRUNC(c, src[0]);
932 break;
933 case nir_op_ffract:
934 result = vir_FSUB(c, src[0], vir_FFLOOR(c, src[0]));
935 break;
936
937 case nir_op_fsin:
938 result = ntq_fsincos(c, src[0], false);
939 break;
940 case nir_op_fcos:
941 result = ntq_fsincos(c, src[0], true);
942 break;
943
944 case nir_op_fsign:
945 result = ntq_fsign(c, src[0]);
946 break;
947 case nir_op_isign:
948 result = ntq_isign(c, src[0]);
949 break;
950
951 case nir_op_fabs: {
952 result = vir_FMOV(c, src[0]);
953 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
954 break;
955 }
956
957 case nir_op_iabs:
958 result = vir_MAX(c, src[0],
959 vir_SUB(c, vir_uniform_ui(c, 0), src[0]));
960 break;
961
962 case nir_op_fddx:
963 case nir_op_fddx_coarse:
964 case nir_op_fddx_fine:
965 result = vir_FDX(c, src[0]);
966 break;
967
968 case nir_op_fddy:
969 case nir_op_fddy_coarse:
970 case nir_op_fddy_fine:
971 result = vir_FDY(c, src[0]);
972 break;
973
974 default:
975 fprintf(stderr, "unknown NIR ALU inst: ");
976 nir_print_instr(&instr->instr, stderr);
977 fprintf(stderr, "\n");
978 abort();
979 }
980
981 /* We have a scalar result, so the instruction should only have a
982 * single channel written to.
983 */
984 assert(util_is_power_of_two(instr->dest.write_mask));
985 ntq_store_dest(c, &instr->dest.dest,
986 ffs(instr->dest.write_mask) - 1, result);
987 }
988
989 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
990 * specifier. They come from a register that's preloaded with 0xffffffff
991 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
992 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
993 */
994 #define TLB_TYPE_F16_COLOR (3 << 6)
995 #define TLB_TYPE_I32_COLOR (1 << 6)
996 #define TLB_TYPE_F32_COLOR (0 << 6)
997 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
998 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
999 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
1000 #define TLB_F16_SWAP_HI_LO (1 << 1)
1001 #define TLB_VEC_SIZE_4_F16 (1 << 0)
1002 #define TLB_VEC_SIZE_2_F16 (0 << 0)
1003 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
1004
1005 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
1006 * flag is set.
1007 */
1008 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
1009 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
1010 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
1011
1012 /* Stencil is a single 32-bit write. */
1013 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1014
1015 static void
1016 emit_frag_end(struct v3d_compile *c)
1017 {
1018 uint32_t discard_cond = V3D_QPU_COND_NONE;
1019 if (c->s->info.fs.uses_discard) {
1020 vir_PF(c, vir_MOV(c, c->discard), V3D_QPU_PF_PUSHZ);
1021 discard_cond = V3D_QPU_COND_IFA;
1022 }
1023
1024 /* XXX
1025 if (c->output_sample_mask_index != -1) {
1026 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1027 }
1028 */
1029
1030 if (c->output_position_index != -1) {
1031 struct qinst *inst = vir_MOV_dest(c,
1032 vir_reg(QFILE_TLBU, 0),
1033 c->outputs[c->output_position_index]);
1034 vir_set_cond(inst, discard_cond);
1035
1036 inst->src[vir_get_implicit_uniform_src(inst)] =
1037 vir_uniform_ui(c,
1038 TLB_TYPE_DEPTH |
1039 TLB_DEPTH_TYPE_PER_PIXEL |
1040 0xffffff00);
1041 } else if (c->s->info.fs.uses_discard) {
1042 struct qinst *inst = vir_MOV_dest(c,
1043 vir_reg(QFILE_TLBU, 0),
1044 vir_reg(QFILE_NULL, 0));
1045 vir_set_cond(inst, discard_cond);
1046
1047 inst->src[vir_get_implicit_uniform_src(inst)] =
1048 vir_uniform_ui(c,
1049 TLB_TYPE_DEPTH |
1050 TLB_DEPTH_TYPE_INVARIANT |
1051 0xffffff00);
1052 }
1053
1054 /* XXX: Performance improvement: Merge Z write and color writes TLB
1055 * uniform setup
1056 */
1057
1058 if (c->output_color_var) {
1059 nir_variable *var = c->output_color_var;
1060 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1061 int num_components = glsl_get_vector_elements(var->type);
1062 uint32_t conf = ~0;
1063 struct qinst *inst;
1064
1065 assert(num_components != 0);
1066 switch (glsl_get_base_type(var->type)) {
1067 case GLSL_TYPE_UINT:
1068 case GLSL_TYPE_INT:
1069 conf = (TLB_TYPE_I32_COLOR |
1070 TLB_SAMPLE_MODE_PER_PIXEL |
1071 ((7 - 0) << TLB_RENDER_TARGET_SHIFT) |
1072 ((num_components - 1) <<
1073 TLB_VEC_SIZE_MINUS_1_SHIFT) |
1074 0xffffff00);
1075
1076
1077 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
1078 vir_set_cond(inst, discard_cond);
1079 inst->src[vir_get_implicit_uniform_src(inst)] =
1080 vir_uniform_ui(c, conf);
1081
1082 for (int i = 1; i < num_components; i++) {
1083 inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
1084 color[i]);
1085 vir_set_cond(inst, discard_cond);
1086 }
1087 break;
1088
1089 default: {
1090 struct qreg r = color[0];
1091 struct qreg g = color[1];
1092 struct qreg b = color[2];
1093 struct qreg a = color[3];
1094
1095 if (c->fs_key->swap_color_rb) {
1096 r = color[2];
1097 b = color[0];
1098 }
1099
1100 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), r, g);
1101 vir_set_cond(inst, discard_cond);
1102 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), b, a);
1103 vir_set_cond(inst, discard_cond);
1104 break;
1105 }
1106 }
1107 }
1108 }
1109
1110 static void
1111 emit_scaled_viewport_write(struct v3d_compile *c, struct qreg rcp_w)
1112 {
1113 for (int i = 0; i < 2; i++) {
1114 struct qreg coord = c->outputs[c->output_position_index + i];
1115 coord = vir_FMUL(c, coord,
1116 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i,
1117 0));
1118 coord = vir_FMUL(c, coord, rcp_w);
1119 vir_FTOIN_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM),
1120 coord);
1121 }
1122
1123 }
1124
1125 static void
1126 emit_zs_write(struct v3d_compile *c, struct qreg rcp_w)
1127 {
1128 struct qreg zscale = vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1129 struct qreg zoffset = vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1130
1131 vir_FADD_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM),
1132 vir_FMUL(c, vir_FMUL(c,
1133 c->outputs[c->output_position_index + 2],
1134 zscale),
1135 rcp_w),
1136 zoffset);
1137 }
1138
1139 static void
1140 emit_rcp_wc_write(struct v3d_compile *c, struct qreg rcp_w)
1141 {
1142 vir_VPM_WRITE(c, rcp_w);
1143 }
1144
1145 static void
1146 emit_point_size_write(struct v3d_compile *c)
1147 {
1148 struct qreg point_size;
1149
1150 if (c->output_point_size_index != -1)
1151 point_size = c->outputs[c->output_point_size_index];
1152 else
1153 point_size = vir_uniform_f(c, 1.0);
1154
1155 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1156 * BCM21553).
1157 */
1158 point_size = vir_FMAX(c, point_size, vir_uniform_f(c, .125));
1159
1160 vir_VPM_WRITE(c, point_size);
1161 }
1162
1163 static void
1164 emit_vpm_write_setup(struct v3d_compile *c)
1165 {
1166 uint32_t packed;
1167 struct V3D33_VPM_GENERIC_BLOCK_WRITE_SETUP unpacked = {
1168 V3D33_VPM_GENERIC_BLOCK_WRITE_SETUP_header,
1169
1170 .horiz = true,
1171 .laned = false,
1172 .segs = true,
1173 .stride = 1,
1174 .size = VPM_SETUP_SIZE_32_BIT,
1175 .addr = 0,
1176 };
1177
1178 V3D33_VPM_GENERIC_BLOCK_WRITE_SETUP_pack(NULL,
1179 (uint8_t *)&packed,
1180 &unpacked);
1181 vir_VPMSETUP(c, vir_uniform_ui(c, packed));
1182 }
1183
1184 static void
1185 emit_vert_end(struct v3d_compile *c)
1186 {
1187 struct qreg rcp_w = vir_SFU(c, V3D_QPU_WADDR_RECIP,
1188 c->outputs[c->output_position_index + 3]);
1189
1190 emit_vpm_write_setup(c);
1191
1192 if (c->vs_key->is_coord) {
1193 for (int i = 0; i < 4; i++)
1194 vir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1195 emit_scaled_viewport_write(c, rcp_w);
1196 if (c->vs_key->per_vertex_point_size) {
1197 emit_point_size_write(c);
1198 /* emit_rcp_wc_write(c, rcp_w); */
1199 }
1200 /* XXX: Z-only rendering */
1201 if (0)
1202 emit_zs_write(c, rcp_w);
1203 } else {
1204 emit_scaled_viewport_write(c, rcp_w);
1205 emit_zs_write(c, rcp_w);
1206 emit_rcp_wc_write(c, rcp_w);
1207 if (c->vs_key->per_vertex_point_size)
1208 emit_point_size_write(c);
1209 }
1210
1211 for (int i = 0; i < c->vs_key->num_fs_inputs; i++) {
1212 struct v3d_varying_slot input = c->vs_key->fs_inputs[i];
1213 int j;
1214
1215 for (j = 0; j < c->num_outputs; j++) {
1216 struct v3d_varying_slot output = c->output_slots[j];
1217
1218 if (!memcmp(&input, &output, sizeof(input))) {
1219 vir_VPM_WRITE(c, c->outputs[j]);
1220 break;
1221 }
1222 }
1223 /* Emit padding if we didn't find a declared VS output for
1224 * this FS input.
1225 */
1226 if (j == c->num_outputs)
1227 vir_VPM_WRITE(c, vir_uniform_f(c, 0.0));
1228 }
1229 }
1230
1231 void
1232 v3d_optimize_nir(struct nir_shader *s)
1233 {
1234 bool progress;
1235
1236 do {
1237 progress = false;
1238
1239 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1240 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1241 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1242 NIR_PASS(progress, s, nir_copy_prop);
1243 NIR_PASS(progress, s, nir_opt_remove_phis);
1244 NIR_PASS(progress, s, nir_opt_dce);
1245 NIR_PASS(progress, s, nir_opt_dead_cf);
1246 NIR_PASS(progress, s, nir_opt_cse);
1247 NIR_PASS(progress, s, nir_opt_peephole_select, 8);
1248 NIR_PASS(progress, s, nir_opt_algebraic);
1249 NIR_PASS(progress, s, nir_opt_constant_folding);
1250 NIR_PASS(progress, s, nir_opt_undef);
1251 } while (progress);
1252 }
1253
1254 static int
1255 driver_location_compare(const void *in_a, const void *in_b)
1256 {
1257 const nir_variable *const *a = in_a;
1258 const nir_variable *const *b = in_b;
1259
1260 return (*a)->data.driver_location - (*b)->data.driver_location;
1261 }
1262
1263 static struct qreg
1264 ntq_emit_vpm_read(struct v3d_compile *c,
1265 uint32_t *num_components_queued,
1266 uint32_t *remaining,
1267 uint32_t vpm_index)
1268 {
1269 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1270
1271 if (*num_components_queued != 0) {
1272 (*num_components_queued)--;
1273 c->num_inputs++;
1274 return vir_MOV(c, vpm);
1275 }
1276
1277 uint32_t num_components = MIN2(*remaining, 32);
1278
1279 struct V3D33_VPM_GENERIC_BLOCK_READ_SETUP unpacked = {
1280 V3D33_VPM_GENERIC_BLOCK_READ_SETUP_header,
1281
1282 .horiz = true,
1283 .laned = false,
1284 /* If the field is 0, that means a read count of 32. */
1285 .num = num_components & 31,
1286 .segs = true,
1287 .stride = 1,
1288 .size = VPM_SETUP_SIZE_32_BIT,
1289 .addr = c->num_inputs,
1290 };
1291
1292 uint32_t packed;
1293 V3D33_VPM_GENERIC_BLOCK_READ_SETUP_pack(NULL,
1294 (uint8_t *)&packed,
1295 &unpacked);
1296 vir_VPMSETUP(c, vir_uniform_ui(c, packed));
1297
1298 *num_components_queued = num_components - 1;
1299 *remaining -= num_components;
1300 c->num_inputs++;
1301
1302 return vir_MOV(c, vpm);
1303 }
1304
1305 static void
1306 ntq_setup_inputs(struct v3d_compile *c)
1307 {
1308 unsigned num_entries = 0;
1309 unsigned num_components = 0;
1310 nir_foreach_variable(var, &c->s->inputs) {
1311 num_entries++;
1312 num_components += glsl_get_components(var->type);
1313 }
1314
1315 nir_variable *vars[num_entries];
1316
1317 unsigned i = 0;
1318 nir_foreach_variable(var, &c->s->inputs)
1319 vars[i++] = var;
1320
1321 /* Sort the variables so that we emit the input setup in
1322 * driver_location order. This is required for VPM reads, whose data
1323 * is fetched into the VPM in driver_location (TGSI register index)
1324 * order.
1325 */
1326 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1327
1328 uint32_t vpm_components_queued = 0;
1329 if (c->s->stage == MESA_SHADER_VERTEX) {
1330 bool uses_iid = c->s->info.system_values_read &
1331 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1332 bool uses_vid = c->s->info.system_values_read &
1333 (1ull << SYSTEM_VALUE_VERTEX_ID);
1334
1335 num_components += uses_iid;
1336 num_components += uses_vid;
1337
1338 if (uses_iid) {
1339 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1340 &num_components, ~0);
1341 }
1342
1343 if (uses_vid) {
1344 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1345 &num_components, ~0);
1346 }
1347 }
1348
1349 for (unsigned i = 0; i < num_entries; i++) {
1350 nir_variable *var = vars[i];
1351 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1352 unsigned loc = var->data.driver_location;
1353
1354 assert(array_len == 1);
1355 (void)array_len;
1356 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1357 (loc + 1) * 4);
1358
1359 if (c->s->stage == MESA_SHADER_FRAGMENT) {
1360 if (var->data.location == VARYING_SLOT_POS) {
1361 emit_fragcoord_input(c, loc);
1362 } else if (var->data.location == VARYING_SLOT_PNTC ||
1363 (var->data.location >= VARYING_SLOT_VAR0 &&
1364 (c->fs_key->point_sprite_mask &
1365 (1 << (var->data.location -
1366 VARYING_SLOT_VAR0))))) {
1367 c->inputs[loc * 4 + 0] = c->point_x;
1368 c->inputs[loc * 4 + 1] = c->point_y;
1369 } else {
1370 emit_fragment_input(c, loc, var);
1371 }
1372 } else {
1373 int var_components = glsl_get_components(var->type);
1374
1375 for (int i = 0; i < var_components; i++) {
1376 c->inputs[loc * 4 + i] =
1377 ntq_emit_vpm_read(c,
1378 &vpm_components_queued,
1379 &num_components,
1380 loc * 4 + i);
1381
1382 }
1383 c->vattr_sizes[loc] = var_components;
1384 }
1385 }
1386
1387 if (c->s->stage == MESA_SHADER_VERTEX) {
1388 assert(vpm_components_queued == 0);
1389 assert(num_components == 0);
1390 }
1391 }
1392
1393 static void
1394 ntq_setup_outputs(struct v3d_compile *c)
1395 {
1396 nir_foreach_variable(var, &c->s->outputs) {
1397 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1398 unsigned loc = var->data.driver_location * 4;
1399
1400 assert(array_len == 1);
1401 (void)array_len;
1402
1403 for (int i = 0; i < 4; i++)
1404 add_output(c, loc + i, var->data.location, i);
1405
1406 if (c->s->stage == MESA_SHADER_FRAGMENT) {
1407 switch (var->data.location) {
1408 case FRAG_RESULT_COLOR:
1409 case FRAG_RESULT_DATA0:
1410 c->output_color_var = var;
1411 break;
1412 case FRAG_RESULT_DEPTH:
1413 c->output_position_index = loc;
1414 break;
1415 case FRAG_RESULT_SAMPLE_MASK:
1416 c->output_sample_mask_index = loc;
1417 break;
1418 }
1419 } else {
1420 switch (var->data.location) {
1421 case VARYING_SLOT_POS:
1422 c->output_position_index = loc;
1423 break;
1424 case VARYING_SLOT_PSIZ:
1425 c->output_point_size_index = loc;
1426 break;
1427 }
1428 }
1429 }
1430 }
1431
1432 static void
1433 ntq_setup_uniforms(struct v3d_compile *c)
1434 {
1435 nir_foreach_variable(var, &c->s->uniforms) {
1436 uint32_t vec4_count = glsl_count_attribute_slots(var->type,
1437 false);
1438 unsigned vec4_size = 4 * sizeof(float);
1439
1440 declare_uniform_range(c, var->data.driver_location * vec4_size,
1441 vec4_count * vec4_size);
1442
1443 }
1444 }
1445
1446 /**
1447 * Sets up the mapping from nir_register to struct qreg *.
1448 *
1449 * Each nir_register gets a struct qreg per 32-bit component being stored.
1450 */
1451 static void
1452 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1453 {
1454 foreach_list_typed(nir_register, nir_reg, node, list) {
1455 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1456 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1457 array_len *
1458 nir_reg->num_components);
1459
1460 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1461
1462 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1463 qregs[i] = vir_get_temp(c);
1464 }
1465 }
1466
1467 static void
1468 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1469 {
1470 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1471 for (int i = 0; i < instr->def.num_components; i++)
1472 qregs[i] = vir_uniform_ui(c, instr->value.u32[i]);
1473
1474 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1475 }
1476
1477 static void
1478 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1479 {
1480 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1481
1482 /* VIR needs there to be *some* value, so pick 0 (same as for
1483 * ntq_setup_registers().
1484 */
1485 for (int i = 0; i < instr->def.num_components; i++)
1486 qregs[i] = vir_uniform_ui(c, 0);
1487 }
1488
1489 static void
1490 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
1491 {
1492 nir_const_value *const_offset;
1493 unsigned offset;
1494
1495 switch (instr->intrinsic) {
1496 case nir_intrinsic_load_uniform:
1497 assert(instr->num_components == 1);
1498 const_offset = nir_src_as_const_value(instr->src[0]);
1499 if (const_offset) {
1500 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1501 assert(offset % 4 == 0);
1502 /* We need dwords */
1503 offset = offset / 4;
1504 ntq_store_dest(c, &instr->dest, 0,
1505 vir_uniform(c, QUNIFORM_UNIFORM,
1506 offset));
1507 } else {
1508 ntq_store_dest(c, &instr->dest, 0,
1509 indirect_uniform_load(c, instr));
1510 }
1511 break;
1512
1513 case nir_intrinsic_load_ubo:
1514 for (int i = 0; i < instr->num_components; i++) {
1515 int ubo = nir_src_as_const_value(instr->src[0])->u32[0];
1516
1517 /* Adjust for where we stored the TGSI register base. */
1518 vir_ADD_dest(c,
1519 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA),
1520 vir_uniform(c, QUNIFORM_UBO_ADDR, 1 + ubo),
1521 vir_ADD(c,
1522 ntq_get_src(c, instr->src[1], 0),
1523 vir_uniform_ui(c, i * 4)));
1524
1525 ntq_store_dest(c, &instr->dest, i, vir_LDTMU(c));
1526 }
1527 break;
1528
1529 const_offset = nir_src_as_const_value(instr->src[0]);
1530 if (const_offset) {
1531 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1532 assert(offset % 4 == 0);
1533 /* We need dwords */
1534 offset = offset / 4;
1535 ntq_store_dest(c, &instr->dest, 0,
1536 vir_uniform(c, QUNIFORM_UNIFORM,
1537 offset));
1538 } else {
1539 ntq_store_dest(c, &instr->dest, 0,
1540 indirect_uniform_load(c, instr));
1541 }
1542 break;
1543
1544 case nir_intrinsic_load_user_clip_plane:
1545 for (int i = 0; i < instr->num_components; i++) {
1546 ntq_store_dest(c, &instr->dest, i,
1547 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1548 nir_intrinsic_ucp_id(instr) *
1549 4 + i));
1550 }
1551 break;
1552
1553 case nir_intrinsic_load_alpha_ref_float:
1554 ntq_store_dest(c, &instr->dest, 0,
1555 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1556 break;
1557
1558 case nir_intrinsic_load_sample_mask_in:
1559 ntq_store_dest(c, &instr->dest, 0,
1560 vir_uniform(c, QUNIFORM_SAMPLE_MASK, 0));
1561 break;
1562
1563 case nir_intrinsic_load_front_face:
1564 /* The register contains 0 (front) or 1 (back), and we need to
1565 * turn it into a NIR bool where true means front.
1566 */
1567 ntq_store_dest(c, &instr->dest, 0,
1568 vir_ADD(c,
1569 vir_uniform_ui(c, -1),
1570 vir_REVF(c)));
1571 break;
1572
1573 case nir_intrinsic_load_instance_id:
1574 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
1575 break;
1576
1577 case nir_intrinsic_load_vertex_id:
1578 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
1579 break;
1580
1581 case nir_intrinsic_load_input:
1582 const_offset = nir_src_as_const_value(instr->src[0]);
1583 assert(const_offset && "v3d doesn't support indirect inputs");
1584 for (int i = 0; i < instr->num_components; i++) {
1585 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1586 int comp = nir_intrinsic_component(instr) + i;
1587 ntq_store_dest(c, &instr->dest, i,
1588 vir_MOV(c, c->inputs[offset * 4 + comp]));
1589 }
1590 break;
1591
1592 case nir_intrinsic_store_output:
1593 const_offset = nir_src_as_const_value(instr->src[1]);
1594 assert(const_offset && "v3d doesn't support indirect outputs");
1595 offset = ((nir_intrinsic_base(instr) +
1596 const_offset->u32[0]) * 4 +
1597 nir_intrinsic_component(instr));
1598
1599 for (int i = 0; i < instr->num_components; i++) {
1600 c->outputs[offset + i] =
1601 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
1602 }
1603 c->num_outputs = MAX2(c->num_outputs,
1604 offset + instr->num_components);
1605 break;
1606
1607 case nir_intrinsic_discard:
1608 if (c->execute.file != QFILE_NULL) {
1609 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1610 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->discard,
1611 vir_uniform_ui(c, ~0));
1612 } else {
1613 vir_MOV_dest(c, c->discard, vir_uniform_ui(c, ~0));
1614 }
1615 break;
1616
1617 case nir_intrinsic_discard_if: {
1618 /* true (~0) if we're discarding */
1619 struct qreg cond = ntq_get_src(c, instr->src[0], 0);
1620
1621 if (c->execute.file != QFILE_NULL) {
1622 /* execute == 0 means the channel is active. Invert
1623 * the condition so that we can use zero as "executing
1624 * and discarding."
1625 */
1626 vir_PF(c, vir_AND(c, c->execute, vir_NOT(c, cond)),
1627 V3D_QPU_PF_PUSHZ);
1628 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->discard, cond);
1629 } else {
1630 vir_OR_dest(c, c->discard, c->discard, cond);
1631 }
1632
1633 break;
1634 }
1635
1636 default:
1637 fprintf(stderr, "Unknown intrinsic: ");
1638 nir_print_instr(&instr->instr, stderr);
1639 fprintf(stderr, "\n");
1640 break;
1641 }
1642 }
1643
1644 /* Clears (activates) the execute flags for any channels whose jump target
1645 * matches this block.
1646 */
1647 static void
1648 ntq_activate_execute_for_block(struct v3d_compile *c)
1649 {
1650 vir_PF(c, vir_SUB(c, c->execute, vir_uniform_ui(c, c->cur_block->index)),
1651 V3D_QPU_PF_PUSHZ);
1652
1653 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
1654 }
1655
1656 static void
1657 ntq_emit_if(struct v3d_compile *c, nir_if *if_stmt)
1658 {
1659 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
1660 bool empty_else_block =
1661 (nir_else_block == nir_if_last_else_block(if_stmt) &&
1662 exec_list_is_empty(&nir_else_block->instr_list));
1663
1664 struct qblock *then_block = vir_new_block(c);
1665 struct qblock *after_block = vir_new_block(c);
1666 struct qblock *else_block;
1667 if (empty_else_block)
1668 else_block = after_block;
1669 else
1670 else_block = vir_new_block(c);
1671
1672 bool was_top_level = false;
1673 if (c->execute.file == QFILE_NULL) {
1674 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
1675 was_top_level = true;
1676 }
1677
1678 /* Set A for executing (execute == 0) and jumping (if->condition ==
1679 * 0) channels, and then update execute flags for those to point to
1680 * the ELSE block.
1681 */
1682 vir_PF(c, vir_OR(c,
1683 c->execute,
1684 ntq_get_src(c, if_stmt->condition, 0)),
1685 V3D_QPU_PF_PUSHZ);
1686 vir_MOV_cond(c, V3D_QPU_COND_IFA,
1687 c->execute,
1688 vir_uniform_ui(c, else_block->index));
1689
1690 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1691 * through.
1692 */
1693 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1694 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
1695 vir_link_blocks(c->cur_block, else_block);
1696 vir_link_blocks(c->cur_block, then_block);
1697
1698 /* Process the THEN block. */
1699 vir_set_emit_block(c, then_block);
1700 ntq_emit_cf_list(c, &if_stmt->then_list);
1701
1702 if (!empty_else_block) {
1703 /* Handle the end of the THEN block. First, all currently
1704 * active channels update their execute flags to point to
1705 * ENDIF
1706 */
1707 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1708 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1709 vir_uniform_ui(c, after_block->index));
1710
1711 /* If everything points at ENDIF, then jump there immediately. */
1712 vir_PF(c, vir_SUB(c, c->execute,
1713 vir_uniform_ui(c, after_block->index)),
1714 V3D_QPU_PF_PUSHZ);
1715 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
1716 vir_link_blocks(c->cur_block, after_block);
1717 vir_link_blocks(c->cur_block, else_block);
1718
1719 vir_set_emit_block(c, else_block);
1720 ntq_activate_execute_for_block(c);
1721 ntq_emit_cf_list(c, &if_stmt->else_list);
1722 }
1723
1724 vir_link_blocks(c->cur_block, after_block);
1725
1726 vir_set_emit_block(c, after_block);
1727 if (was_top_level)
1728 c->execute = c->undef;
1729 else
1730 ntq_activate_execute_for_block(c);
1731 }
1732
1733 static void
1734 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
1735 {
1736 switch (jump->type) {
1737 case nir_jump_break:
1738 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1739 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1740 vir_uniform_ui(c, c->loop_break_block->index));
1741 break;
1742
1743 case nir_jump_continue:
1744 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1745 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1746 vir_uniform_ui(c, c->loop_cont_block->index));
1747 break;
1748
1749 case nir_jump_return:
1750 unreachable("All returns shouold be lowered\n");
1751 }
1752 }
1753
1754 static void
1755 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
1756 {
1757 switch (instr->type) {
1758 case nir_instr_type_alu:
1759 ntq_emit_alu(c, nir_instr_as_alu(instr));
1760 break;
1761
1762 case nir_instr_type_intrinsic:
1763 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
1764 break;
1765
1766 case nir_instr_type_load_const:
1767 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
1768 break;
1769
1770 case nir_instr_type_ssa_undef:
1771 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
1772 break;
1773
1774 case nir_instr_type_tex:
1775 ntq_emit_tex(c, nir_instr_as_tex(instr));
1776 break;
1777
1778 case nir_instr_type_jump:
1779 ntq_emit_jump(c, nir_instr_as_jump(instr));
1780 break;
1781
1782 default:
1783 fprintf(stderr, "Unknown NIR instr type: ");
1784 nir_print_instr(instr, stderr);
1785 fprintf(stderr, "\n");
1786 abort();
1787 }
1788 }
1789
1790 static void
1791 ntq_emit_block(struct v3d_compile *c, nir_block *block)
1792 {
1793 nir_foreach_instr(instr, block) {
1794 ntq_emit_instr(c, instr);
1795 }
1796 }
1797
1798 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
1799
1800 static void
1801 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
1802 {
1803 bool was_top_level = false;
1804 if (c->execute.file == QFILE_NULL) {
1805 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
1806 was_top_level = true;
1807 }
1808
1809 struct qblock *save_loop_cont_block = c->loop_cont_block;
1810 struct qblock *save_loop_break_block = c->loop_break_block;
1811
1812 c->loop_cont_block = vir_new_block(c);
1813 c->loop_break_block = vir_new_block(c);
1814
1815 vir_link_blocks(c->cur_block, c->loop_cont_block);
1816 vir_set_emit_block(c, c->loop_cont_block);
1817 ntq_activate_execute_for_block(c);
1818
1819 ntq_emit_cf_list(c, &loop->body);
1820
1821 /* Re-enable any previous continues now, so our ANYA check below
1822 * works.
1823 *
1824 * XXX: Use the .ORZ flags update, instead.
1825 */
1826 vir_PF(c, vir_SUB(c,
1827 c->execute,
1828 vir_uniform_ui(c, c->loop_cont_block->index)),
1829 V3D_QPU_PF_PUSHZ);
1830 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
1831
1832 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1833
1834 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
1835 vir_link_blocks(c->cur_block, c->loop_cont_block);
1836 vir_link_blocks(c->cur_block, c->loop_break_block);
1837
1838 vir_set_emit_block(c, c->loop_break_block);
1839 if (was_top_level)
1840 c->execute = c->undef;
1841 else
1842 ntq_activate_execute_for_block(c);
1843
1844 c->loop_break_block = save_loop_break_block;
1845 c->loop_cont_block = save_loop_cont_block;
1846 }
1847
1848 static void
1849 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
1850 {
1851 fprintf(stderr, "FUNCTIONS not handled.\n");
1852 abort();
1853 }
1854
1855 static void
1856 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
1857 {
1858 foreach_list_typed(nir_cf_node, node, node, list) {
1859 switch (node->type) {
1860 case nir_cf_node_block:
1861 ntq_emit_block(c, nir_cf_node_as_block(node));
1862 break;
1863
1864 case nir_cf_node_if:
1865 ntq_emit_if(c, nir_cf_node_as_if(node));
1866 break;
1867
1868 case nir_cf_node_loop:
1869 ntq_emit_loop(c, nir_cf_node_as_loop(node));
1870 break;
1871
1872 case nir_cf_node_function:
1873 ntq_emit_function(c, nir_cf_node_as_function(node));
1874 break;
1875
1876 default:
1877 fprintf(stderr, "Unknown NIR node type\n");
1878 abort();
1879 }
1880 }
1881 }
1882
1883 static void
1884 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
1885 {
1886 ntq_setup_registers(c, &impl->registers);
1887 ntq_emit_cf_list(c, &impl->body);
1888 }
1889
1890 static void
1891 nir_to_vir(struct v3d_compile *c)
1892 {
1893 if (c->s->stage == MESA_SHADER_FRAGMENT) {
1894 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
1895 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
1896 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
1897
1898 if (c->s->info.fs.uses_discard)
1899 c->discard = vir_MOV(c, vir_uniform_ui(c, 0));
1900
1901 if (c->fs_key->is_points) {
1902 c->point_x = emit_fragment_varying(c, NULL, 0);
1903 c->point_y = emit_fragment_varying(c, NULL, 0);
1904 } else if (c->fs_key->is_lines) {
1905 c->line_x = emit_fragment_varying(c, NULL, 0);
1906 }
1907 }
1908
1909 ntq_setup_inputs(c);
1910 ntq_setup_outputs(c);
1911 ntq_setup_uniforms(c);
1912 ntq_setup_registers(c, &c->s->registers);
1913
1914 /* Find the main function and emit the body. */
1915 nir_foreach_function(function, c->s) {
1916 assert(strcmp(function->name, "main") == 0);
1917 assert(function->impl);
1918 ntq_emit_impl(c, function->impl);
1919 }
1920 }
1921
1922 const nir_shader_compiler_options v3d_nir_options = {
1923 .lower_extract_byte = true,
1924 .lower_extract_word = true,
1925 .lower_bitfield_insert = true,
1926 .lower_bitfield_extract = true,
1927 .lower_ffma = true,
1928 .lower_flrp32 = true,
1929 .lower_fpow = true,
1930 .lower_fsat = true,
1931 .lower_fsqrt = true,
1932 .lower_negate = true,
1933 .native_integers = true,
1934 };
1935
1936
1937 #if 0
1938 static int
1939 count_nir_instrs(nir_shader *nir)
1940 {
1941 int count = 0;
1942 nir_foreach_function(function, nir) {
1943 if (!function->impl)
1944 continue;
1945 nir_foreach_block(block, function->impl) {
1946 nir_foreach_instr(instr, block)
1947 count++;
1948 }
1949 }
1950 return count;
1951 }
1952 #endif
1953
1954 void
1955 v3d_nir_to_vir(struct v3d_compile *c)
1956 {
1957 if (V3D_DEBUG & (V3D_DEBUG_NIR |
1958 v3d_debug_flag_for_shader_stage(c->s->stage))) {
1959 fprintf(stderr, "%s prog %d/%d NIR:\n",
1960 vir_get_stage_name(c),
1961 c->program_id, c->variant_id);
1962 nir_print_shader(c->s, stderr);
1963 }
1964
1965 nir_to_vir(c);
1966
1967 switch (c->s->stage) {
1968 case MESA_SHADER_FRAGMENT:
1969 emit_frag_end(c);
1970 break;
1971 case MESA_SHADER_VERTEX:
1972 emit_vert_end(c);
1973 break;
1974 default:
1975 unreachable("bad stage");
1976 }
1977
1978 if (V3D_DEBUG & (V3D_DEBUG_VIR |
1979 v3d_debug_flag_for_shader_stage(c->s->stage))) {
1980 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
1981 vir_get_stage_name(c),
1982 c->program_id, c->variant_id);
1983 vir_dump(c);
1984 fprintf(stderr, "\n");
1985 }
1986
1987 vir_optimize(c);
1988 vir_lower_uniforms(c);
1989
1990 /* XXX: vir_schedule_instructions(c); */
1991
1992 if (V3D_DEBUG & (V3D_DEBUG_VIR |
1993 v3d_debug_flag_for_shader_stage(c->s->stage))) {
1994 fprintf(stderr, "%s prog %d/%d VIR:\n",
1995 vir_get_stage_name(c),
1996 c->program_id, c->variant_id);
1997 vir_dump(c);
1998 fprintf(stderr, "\n");
1999 }
2000
2001 v3d_vir_to_qpu(c);
2002 }