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v3d: Add support for gl_HelperInvocation.
[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
34
35 static void
36 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
37
38 static void
39 resize_qreg_array(struct v3d_compile *c,
40 struct qreg **regs,
41 uint32_t *size,
42 uint32_t decl_size)
43 {
44 if (*size >= decl_size)
45 return;
46
47 uint32_t old_size = *size;
48 *size = MAX2(*size * 2, decl_size);
49 *regs = reralloc(c, *regs, struct qreg, *size);
50 if (!*regs) {
51 fprintf(stderr, "Malloc failure\n");
52 abort();
53 }
54
55 for (uint32_t i = old_size; i < *size; i++)
56 (*regs)[i] = c->undef;
57 }
58
59 void
60 vir_emit_thrsw(struct v3d_compile *c)
61 {
62 if (c->threads == 1)
63 return;
64
65 /* Always thread switch after each texture operation for now.
66 *
67 * We could do better by batching a bunch of texture fetches up and
68 * then doing one thread switch and collecting all their results
69 * afterward.
70 */
71 c->last_thrsw = vir_NOP(c);
72 c->last_thrsw->qpu.sig.thrsw = true;
73 c->last_thrsw_at_top_level = (c->execute.file == QFILE_NULL);
74 }
75
76 static struct qreg
77 indirect_uniform_load(struct v3d_compile *c, nir_intrinsic_instr *intr)
78 {
79 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
80 uint32_t offset = nir_intrinsic_base(intr);
81 struct v3d_ubo_range *range = NULL;
82 unsigned i;
83
84 for (i = 0; i < c->num_ubo_ranges; i++) {
85 range = &c->ubo_ranges[i];
86 if (offset >= range->src_offset &&
87 offset < range->src_offset + range->size) {
88 break;
89 }
90 }
91 /* The driver-location-based offset always has to be within a declared
92 * uniform range.
93 */
94 assert(i != c->num_ubo_ranges);
95 if (!c->ubo_range_used[i]) {
96 c->ubo_range_used[i] = true;
97 range->dst_offset = c->next_ubo_dst_offset;
98 c->next_ubo_dst_offset += range->size;
99 }
100
101 offset -= range->src_offset;
102
103 if (range->dst_offset + offset != 0) {
104 indirect_offset = vir_ADD(c, indirect_offset,
105 vir_uniform_ui(c, range->dst_offset +
106 offset));
107 }
108
109 /* Adjust for where we stored the TGSI register base. */
110 vir_ADD_dest(c,
111 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA),
112 vir_uniform(c, QUNIFORM_UBO_ADDR, 0),
113 indirect_offset);
114
115 vir_emit_thrsw(c);
116 return vir_LDTMU(c);
117 }
118
119 static struct qreg *
120 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
121 {
122 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
123 def->num_components);
124 _mesa_hash_table_insert(c->def_ht, def, qregs);
125 return qregs;
126 }
127
128 /**
129 * This function is responsible for getting VIR results into the associated
130 * storage for a NIR instruction.
131 *
132 * If it's a NIR SSA def, then we just set the associated hash table entry to
133 * the new result.
134 *
135 * If it's a NIR reg, then we need to update the existing qreg assigned to the
136 * NIR destination with the incoming value. To do that without introducing
137 * new MOVs, we require that the incoming qreg either be a uniform, or be
138 * SSA-defined by the previous VIR instruction in the block and rewritable by
139 * this function. That lets us sneak ahead and insert the SF flag beforehand
140 * (knowing that the previous instruction doesn't depend on flags) and rewrite
141 * its destination to be the NIR reg's destination
142 */
143 void
144 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
145 struct qreg result)
146 {
147 struct qinst *last_inst = NULL;
148 if (!list_empty(&c->cur_block->instructions))
149 last_inst = (struct qinst *)c->cur_block->instructions.prev;
150
151 assert(result.file == QFILE_UNIF ||
152 (result.file == QFILE_TEMP &&
153 last_inst && last_inst == c->defs[result.index]));
154
155 if (dest->is_ssa) {
156 assert(chan < dest->ssa.num_components);
157
158 struct qreg *qregs;
159 struct hash_entry *entry =
160 _mesa_hash_table_search(c->def_ht, &dest->ssa);
161
162 if (entry)
163 qregs = entry->data;
164 else
165 qregs = ntq_init_ssa_def(c, &dest->ssa);
166
167 qregs[chan] = result;
168 } else {
169 nir_register *reg = dest->reg.reg;
170 assert(dest->reg.base_offset == 0);
171 assert(reg->num_array_elems == 0);
172 struct hash_entry *entry =
173 _mesa_hash_table_search(c->def_ht, reg);
174 struct qreg *qregs = entry->data;
175
176 /* Insert a MOV if the source wasn't an SSA def in the
177 * previous instruction.
178 */
179 if (result.file == QFILE_UNIF) {
180 result = vir_MOV(c, result);
181 last_inst = c->defs[result.index];
182 }
183
184 /* We know they're both temps, so just rewrite index. */
185 c->defs[last_inst->dst.index] = NULL;
186 last_inst->dst.index = qregs[chan].index;
187
188 /* If we're in control flow, then make this update of the reg
189 * conditional on the execution mask.
190 */
191 if (c->execute.file != QFILE_NULL) {
192 last_inst->dst.index = qregs[chan].index;
193
194 /* Set the flags to the current exec mask.
195 */
196 c->cursor = vir_before_inst(last_inst);
197 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
198 c->cursor = vir_after_inst(last_inst);
199
200 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
201 last_inst->cond_is_exec_mask = true;
202 }
203 }
204 }
205
206 struct qreg
207 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
208 {
209 struct hash_entry *entry;
210 if (src.is_ssa) {
211 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
212 assert(i < src.ssa->num_components);
213 } else {
214 nir_register *reg = src.reg.reg;
215 entry = _mesa_hash_table_search(c->def_ht, reg);
216 assert(reg->num_array_elems == 0);
217 assert(src.reg.base_offset == 0);
218 assert(i < reg->num_components);
219 }
220
221 struct qreg *qregs = entry->data;
222 return qregs[i];
223 }
224
225 static struct qreg
226 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
227 unsigned src)
228 {
229 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
230 unsigned chan = ffs(instr->dest.write_mask) - 1;
231 struct qreg r = ntq_get_src(c, instr->src[src].src,
232 instr->src[src].swizzle[chan]);
233
234 assert(!instr->src[src].abs);
235 assert(!instr->src[src].negate);
236
237 return r;
238 };
239
240 static struct qreg
241 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
242 {
243 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
244 }
245
246 static void
247 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
248 {
249 unsigned unit = instr->texture_index;
250 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
251 int dest_size = nir_tex_instr_dest_size(instr);
252
253 struct qreg lod = c->undef;
254 if (lod_index != -1)
255 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
256
257 for (int i = 0; i < dest_size; i++) {
258 assert(i < 3);
259 enum quniform_contents contents;
260
261 if (instr->is_array && i == dest_size - 1)
262 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
263 else
264 contents = QUNIFORM_TEXTURE_WIDTH + i;
265
266 struct qreg size = vir_uniform(c, contents, unit);
267
268 switch (instr->sampler_dim) {
269 case GLSL_SAMPLER_DIM_1D:
270 case GLSL_SAMPLER_DIM_2D:
271 case GLSL_SAMPLER_DIM_MS:
272 case GLSL_SAMPLER_DIM_3D:
273 case GLSL_SAMPLER_DIM_CUBE:
274 /* Don't minify the array size. */
275 if (!(instr->is_array && i == dest_size - 1)) {
276 size = ntq_minify(c, size, lod);
277 }
278 break;
279
280 case GLSL_SAMPLER_DIM_RECT:
281 /* There's no LOD field for rects */
282 break;
283
284 default:
285 unreachable("Bad sampler type");
286 }
287
288 ntq_store_dest(c, &instr->dest, i, size);
289 }
290 }
291
292 static void
293 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
294 {
295 unsigned unit = instr->texture_index;
296
297 /* Since each texture sampling op requires uploading uniforms to
298 * reference the texture, there's no HW support for texture size and
299 * you just upload uniforms containing the size.
300 */
301 switch (instr->op) {
302 case nir_texop_query_levels:
303 ntq_store_dest(c, &instr->dest, 0,
304 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
305 return;
306 case nir_texop_txs:
307 ntq_emit_txs(c, instr);
308 return;
309 default:
310 break;
311 }
312
313 if (c->devinfo->ver >= 40)
314 v3d40_vir_emit_tex(c, instr);
315 else
316 v3d33_vir_emit_tex(c, instr);
317 }
318
319 static struct qreg
320 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
321 {
322 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
323 if (is_cos)
324 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
325
326 struct qreg periods = vir_FROUND(c, input);
327 struct qreg sin_output = vir_SIN(c, vir_FSUB(c, input, periods));
328 return vir_XOR(c, sin_output, vir_SHL(c,
329 vir_FTOIN(c, periods),
330 vir_uniform_ui(c, -1)));
331 }
332
333 static struct qreg
334 ntq_fsign(struct v3d_compile *c, struct qreg src)
335 {
336 struct qreg t = vir_get_temp(c);
337
338 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
339 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHZ);
340 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
341 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHN);
342 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
343 return vir_MOV(c, t);
344 }
345
346 static struct qreg
347 ntq_isign(struct v3d_compile *c, struct qreg src)
348 {
349 struct qreg t = vir_get_temp(c);
350
351 vir_MOV_dest(c, t, vir_uniform_ui(c, 0));
352 vir_PF(c, vir_MOV(c, src), V3D_QPU_PF_PUSHZ);
353 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_ui(c, 1));
354 vir_PF(c, vir_MOV(c, src), V3D_QPU_PF_PUSHN);
355 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_ui(c, -1));
356 return vir_MOV(c, t);
357 }
358
359 static void
360 emit_fragcoord_input(struct v3d_compile *c, int attr)
361 {
362 c->inputs[attr * 4 + 0] = vir_FXCD(c);
363 c->inputs[attr * 4 + 1] = vir_FYCD(c);
364 c->inputs[attr * 4 + 2] = c->payload_z;
365 c->inputs[attr * 4 + 3] = vir_RECIP(c, c->payload_w);
366 }
367
368 static struct qreg
369 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
370 uint8_t swizzle)
371 {
372 struct qreg r3 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R3);
373 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
374
375 struct qreg vary;
376 if (c->devinfo->ver >= 41) {
377 struct qinst *ldvary = vir_add_inst(V3D_QPU_A_NOP, c->undef,
378 c->undef, c->undef);
379 ldvary->qpu.sig.ldvary = true;
380 vary = vir_emit_def(c, ldvary);
381 } else {
382 vir_NOP(c)->qpu.sig.ldvary = true;
383 vary = r3;
384 }
385
386 /* For gl_PointCoord input or distance along a line, we'll be called
387 * with no nir_variable, and we don't count toward VPM size so we
388 * don't track an input slot.
389 */
390 if (!var) {
391 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
392 }
393
394 int i = c->num_inputs++;
395 c->input_slots[i] = v3d_slot_from_slot_and_component(var->data.location,
396 swizzle);
397
398 switch (var->data.interpolation) {
399 case INTERP_MODE_NONE:
400 /* If a gl_FrontColor or gl_BackColor input has no interp
401 * qualifier, then if we're using glShadeModel(GL_FLAT) it
402 * needs to be flat shaded.
403 */
404 switch (var->data.location) {
405 case VARYING_SLOT_COL0:
406 case VARYING_SLOT_COL1:
407 case VARYING_SLOT_BFC0:
408 case VARYING_SLOT_BFC1:
409 if (c->fs_key->shade_model_flat) {
410 BITSET_SET(c->flat_shade_flags, i);
411 vir_MOV_dest(c, c->undef, vary);
412 return vir_MOV(c, r5);
413 } else {
414 return vir_FADD(c, vir_FMUL(c, vary,
415 c->payload_w), r5);
416 }
417 default:
418 break;
419 }
420 /* FALLTHROUGH */
421 case INTERP_MODE_SMOOTH:
422 if (var->data.centroid) {
423 BITSET_SET(c->centroid_flags, i);
424 return vir_FADD(c, vir_FMUL(c, vary,
425 c->payload_w_centroid), r5);
426 } else {
427 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
428 }
429 case INTERP_MODE_NOPERSPECTIVE:
430 BITSET_SET(c->noperspective_flags, i);
431 return vir_FADD(c, vir_MOV(c, vary), r5);
432 case INTERP_MODE_FLAT:
433 BITSET_SET(c->flat_shade_flags, i);
434 vir_MOV_dest(c, c->undef, vary);
435 return vir_MOV(c, r5);
436 default:
437 unreachable("Bad interp mode");
438 }
439 }
440
441 static void
442 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var)
443 {
444 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
445 int chan = var->data.location_frac + i;
446 c->inputs[attr * 4 + chan] =
447 emit_fragment_varying(c, var, chan);
448 }
449 }
450
451 static void
452 add_output(struct v3d_compile *c,
453 uint32_t decl_offset,
454 uint8_t slot,
455 uint8_t swizzle)
456 {
457 uint32_t old_array_size = c->outputs_array_size;
458 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
459 decl_offset + 1);
460
461 if (old_array_size != c->outputs_array_size) {
462 c->output_slots = reralloc(c,
463 c->output_slots,
464 struct v3d_varying_slot,
465 c->outputs_array_size);
466 }
467
468 c->output_slots[decl_offset] =
469 v3d_slot_from_slot_and_component(slot, swizzle);
470 }
471
472 static void
473 declare_uniform_range(struct v3d_compile *c, uint32_t start, uint32_t size)
474 {
475 unsigned array_id = c->num_ubo_ranges++;
476 if (array_id >= c->ubo_ranges_array_size) {
477 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
478 array_id + 1);
479 c->ubo_ranges = reralloc(c, c->ubo_ranges,
480 struct v3d_ubo_range,
481 c->ubo_ranges_array_size);
482 c->ubo_range_used = reralloc(c, c->ubo_range_used,
483 bool,
484 c->ubo_ranges_array_size);
485 }
486
487 c->ubo_ranges[array_id].dst_offset = 0;
488 c->ubo_ranges[array_id].src_offset = start;
489 c->ubo_ranges[array_id].size = size;
490 c->ubo_range_used[array_id] = false;
491 }
492
493 /**
494 * If compare_instr is a valid comparison instruction, emits the
495 * compare_instr's comparison and returns the sel_instr's return value based
496 * on the compare_instr's result.
497 */
498 static bool
499 ntq_emit_comparison(struct v3d_compile *c, struct qreg *dest,
500 nir_alu_instr *compare_instr,
501 nir_alu_instr *sel_instr)
502 {
503 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
504 struct qreg src1;
505 if (nir_op_infos[compare_instr->op].num_inputs > 1)
506 src1 = ntq_get_alu_src(c, compare_instr, 1);
507 bool cond_invert = false;
508 struct qreg nop = vir_reg(QFILE_NULL, 0);
509
510 switch (compare_instr->op) {
511 case nir_op_feq32:
512 case nir_op_seq:
513 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
514 break;
515 case nir_op_ieq32:
516 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
517 break;
518
519 case nir_op_fne32:
520 case nir_op_sne:
521 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
522 cond_invert = true;
523 break;
524 case nir_op_ine32:
525 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
526 cond_invert = true;
527 break;
528
529 case nir_op_fge32:
530 case nir_op_sge:
531 vir_set_pf(vir_FCMP_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
532 break;
533 case nir_op_ige32:
534 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
535 cond_invert = true;
536 break;
537 case nir_op_uge32:
538 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
539 cond_invert = true;
540 break;
541
542 case nir_op_slt:
543 case nir_op_flt32:
544 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHN);
545 break;
546 case nir_op_ilt32:
547 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
548 break;
549 case nir_op_ult32:
550 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
551 break;
552
553 default:
554 return false;
555 }
556
557 enum v3d_qpu_cond cond = (cond_invert ?
558 V3D_QPU_COND_IFNA :
559 V3D_QPU_COND_IFA);
560
561 switch (sel_instr->op) {
562 case nir_op_seq:
563 case nir_op_sne:
564 case nir_op_sge:
565 case nir_op_slt:
566 *dest = vir_SEL(c, cond,
567 vir_uniform_f(c, 1.0), vir_uniform_f(c, 0.0));
568 break;
569
570 case nir_op_b32csel:
571 *dest = vir_SEL(c, cond,
572 ntq_get_alu_src(c, sel_instr, 1),
573 ntq_get_alu_src(c, sel_instr, 2));
574 break;
575
576 default:
577 *dest = vir_SEL(c, cond,
578 vir_uniform_ui(c, ~0), vir_uniform_ui(c, 0));
579 break;
580 }
581
582 /* Make the temporary for nir_store_dest(). */
583 *dest = vir_MOV(c, *dest);
584
585 return true;
586 }
587
588 /**
589 * Attempts to fold a comparison generating a boolean result into the
590 * condition code for selecting between two values, instead of comparing the
591 * boolean result against 0 to generate the condition code.
592 */
593 static struct qreg ntq_emit_bcsel(struct v3d_compile *c, nir_alu_instr *instr,
594 struct qreg *src)
595 {
596 if (!instr->src[0].src.is_ssa)
597 goto out;
598 if (instr->src[0].src.ssa->parent_instr->type != nir_instr_type_alu)
599 goto out;
600 nir_alu_instr *compare =
601 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
602 if (!compare)
603 goto out;
604
605 struct qreg dest;
606 if (ntq_emit_comparison(c, &dest, compare, instr))
607 return dest;
608
609 out:
610 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
611 return vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA, src[1], src[2]));
612 }
613
614
615 static void
616 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
617 {
618 /* This should always be lowered to ALU operations for V3D. */
619 assert(!instr->dest.saturate);
620
621 /* Vectors are special in that they have non-scalarized writemasks,
622 * and just take the first swizzle channel for each argument in order
623 * into each writemask channel.
624 */
625 if (instr->op == nir_op_vec2 ||
626 instr->op == nir_op_vec3 ||
627 instr->op == nir_op_vec4) {
628 struct qreg srcs[4];
629 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
630 srcs[i] = ntq_get_src(c, instr->src[i].src,
631 instr->src[i].swizzle[0]);
632 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
633 ntq_store_dest(c, &instr->dest.dest, i,
634 vir_MOV(c, srcs[i]));
635 return;
636 }
637
638 /* General case: We can just grab the one used channel per src. */
639 struct qreg src[nir_op_infos[instr->op].num_inputs];
640 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
641 src[i] = ntq_get_alu_src(c, instr, i);
642 }
643
644 struct qreg result;
645
646 switch (instr->op) {
647 case nir_op_fmov:
648 case nir_op_imov:
649 result = vir_MOV(c, src[0]);
650 break;
651
652 case nir_op_fneg:
653 result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
654 break;
655 case nir_op_ineg:
656 result = vir_NEG(c, src[0]);
657 break;
658
659 case nir_op_fmul:
660 result = vir_FMUL(c, src[0], src[1]);
661 break;
662 case nir_op_fadd:
663 result = vir_FADD(c, src[0], src[1]);
664 break;
665 case nir_op_fsub:
666 result = vir_FSUB(c, src[0], src[1]);
667 break;
668 case nir_op_fmin:
669 result = vir_FMIN(c, src[0], src[1]);
670 break;
671 case nir_op_fmax:
672 result = vir_FMAX(c, src[0], src[1]);
673 break;
674
675 case nir_op_f2i32:
676 result = vir_FTOIZ(c, src[0]);
677 break;
678 case nir_op_f2u32:
679 result = vir_FTOUZ(c, src[0]);
680 break;
681 case nir_op_i2f32:
682 result = vir_ITOF(c, src[0]);
683 break;
684 case nir_op_u2f32:
685 result = vir_UTOF(c, src[0]);
686 break;
687 case nir_op_b2f32:
688 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
689 break;
690 case nir_op_b2i32:
691 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
692 break;
693 case nir_op_i2b32:
694 case nir_op_f2b32:
695 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
696 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
697 vir_uniform_ui(c, ~0),
698 vir_uniform_ui(c, 0)));
699 break;
700
701 case nir_op_iadd:
702 result = vir_ADD(c, src[0], src[1]);
703 break;
704 case nir_op_ushr:
705 result = vir_SHR(c, src[0], src[1]);
706 break;
707 case nir_op_isub:
708 result = vir_SUB(c, src[0], src[1]);
709 break;
710 case nir_op_ishr:
711 result = vir_ASR(c, src[0], src[1]);
712 break;
713 case nir_op_ishl:
714 result = vir_SHL(c, src[0], src[1]);
715 break;
716 case nir_op_imin:
717 result = vir_MIN(c, src[0], src[1]);
718 break;
719 case nir_op_umin:
720 result = vir_UMIN(c, src[0], src[1]);
721 break;
722 case nir_op_imax:
723 result = vir_MAX(c, src[0], src[1]);
724 break;
725 case nir_op_umax:
726 result = vir_UMAX(c, src[0], src[1]);
727 break;
728 case nir_op_iand:
729 result = vir_AND(c, src[0], src[1]);
730 break;
731 case nir_op_ior:
732 result = vir_OR(c, src[0], src[1]);
733 break;
734 case nir_op_ixor:
735 result = vir_XOR(c, src[0], src[1]);
736 break;
737 case nir_op_inot:
738 result = vir_NOT(c, src[0]);
739 break;
740
741 case nir_op_ufind_msb:
742 result = vir_SUB(c, vir_uniform_ui(c, 31), vir_CLZ(c, src[0]));
743 break;
744
745 case nir_op_imul:
746 result = vir_UMUL(c, src[0], src[1]);
747 break;
748
749 case nir_op_seq:
750 case nir_op_sne:
751 case nir_op_sge:
752 case nir_op_slt:
753 case nir_op_feq32:
754 case nir_op_fne32:
755 case nir_op_fge32:
756 case nir_op_flt32:
757 case nir_op_ieq32:
758 case nir_op_ine32:
759 case nir_op_ige32:
760 case nir_op_uge32:
761 case nir_op_ilt32:
762 case nir_op_ult32:
763 if (!ntq_emit_comparison(c, &result, instr, instr)) {
764 fprintf(stderr, "Bad comparison instruction\n");
765 }
766 break;
767
768 case nir_op_b32csel:
769 result = ntq_emit_bcsel(c, instr, src);
770 break;
771 case nir_op_fcsel:
772 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
773 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
774 src[1], src[2]));
775 break;
776
777 case nir_op_frcp:
778 result = vir_RECIP(c, src[0]);
779 break;
780 case nir_op_frsq:
781 result = vir_RSQRT(c, src[0]);
782 break;
783 case nir_op_fexp2:
784 result = vir_EXP(c, src[0]);
785 break;
786 case nir_op_flog2:
787 result = vir_LOG(c, src[0]);
788 break;
789
790 case nir_op_fceil:
791 result = vir_FCEIL(c, src[0]);
792 break;
793 case nir_op_ffloor:
794 result = vir_FFLOOR(c, src[0]);
795 break;
796 case nir_op_fround_even:
797 result = vir_FROUND(c, src[0]);
798 break;
799 case nir_op_ftrunc:
800 result = vir_FTRUNC(c, src[0]);
801 break;
802 case nir_op_ffract:
803 result = vir_FSUB(c, src[0], vir_FFLOOR(c, src[0]));
804 break;
805
806 case nir_op_fsin:
807 result = ntq_fsincos(c, src[0], false);
808 break;
809 case nir_op_fcos:
810 result = ntq_fsincos(c, src[0], true);
811 break;
812
813 case nir_op_fsign:
814 result = ntq_fsign(c, src[0]);
815 break;
816 case nir_op_isign:
817 result = ntq_isign(c, src[0]);
818 break;
819
820 case nir_op_fabs: {
821 result = vir_FMOV(c, src[0]);
822 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
823 break;
824 }
825
826 case nir_op_iabs:
827 result = vir_MAX(c, src[0],
828 vir_SUB(c, vir_uniform_ui(c, 0), src[0]));
829 break;
830
831 case nir_op_fddx:
832 case nir_op_fddx_coarse:
833 case nir_op_fddx_fine:
834 result = vir_FDX(c, src[0]);
835 break;
836
837 case nir_op_fddy:
838 case nir_op_fddy_coarse:
839 case nir_op_fddy_fine:
840 result = vir_FDY(c, src[0]);
841 break;
842
843 case nir_op_uadd_carry:
844 vir_PF(c, vir_ADD(c, src[0], src[1]), V3D_QPU_PF_PUSHC);
845 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
846 vir_uniform_ui(c, ~0),
847 vir_uniform_ui(c, 0)));
848 break;
849
850 case nir_op_pack_half_2x16_split:
851 result = vir_VFPACK(c, src[0], src[1]);
852 break;
853
854 case nir_op_unpack_half_2x16_split_x:
855 /* XXX perf: It would be good to be able to merge this unpack
856 * with whatever uses our result.
857 */
858 result = vir_FMOV(c, src[0]);
859 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_L);
860 break;
861
862 case nir_op_unpack_half_2x16_split_y:
863 result = vir_FMOV(c, src[0]);
864 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_H);
865 break;
866
867 default:
868 fprintf(stderr, "unknown NIR ALU inst: ");
869 nir_print_instr(&instr->instr, stderr);
870 fprintf(stderr, "\n");
871 abort();
872 }
873
874 /* We have a scalar result, so the instruction should only have a
875 * single channel written to.
876 */
877 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
878 ntq_store_dest(c, &instr->dest.dest,
879 ffs(instr->dest.write_mask) - 1, result);
880 }
881
882 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
883 * specifier. They come from a register that's preloaded with 0xffffffff
884 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
885 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
886 */
887 #define TLB_TYPE_F16_COLOR (3 << 6)
888 #define TLB_TYPE_I32_COLOR (1 << 6)
889 #define TLB_TYPE_F32_COLOR (0 << 6)
890 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
891 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
892 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
893 #define TLB_F16_SWAP_HI_LO (1 << 1)
894 #define TLB_VEC_SIZE_4_F16 (1 << 0)
895 #define TLB_VEC_SIZE_2_F16 (0 << 0)
896 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
897
898 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
899 * flag is set.
900 */
901 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
902 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
903 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
904 #define TLB_V42_DEPTH_TYPE_INVARIANT (0 << 3) /* Unmodified sideband input used */
905 #define TLB_V42_DEPTH_TYPE_PER_PIXEL (1 << 3) /* QPU result used */
906
907 /* Stencil is a single 32-bit write. */
908 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
909
910 static void
911 emit_frag_end(struct v3d_compile *c)
912 {
913 /* XXX
914 if (c->output_sample_mask_index != -1) {
915 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
916 }
917 */
918
919 bool has_any_tlb_color_write = false;
920 for (int rt = 0; rt < c->fs_key->nr_cbufs; rt++) {
921 if (c->output_color_var[rt])
922 has_any_tlb_color_write = true;
923 }
924
925 if (c->fs_key->sample_alpha_to_coverage && c->output_color_var[0]) {
926 struct nir_variable *var = c->output_color_var[0];
927 struct qreg *color = &c->outputs[var->data.driver_location * 4];
928
929 vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
930 vir_AND(c,
931 vir_MSF(c),
932 vir_FTOC(c, color[3])));
933 }
934
935 if (c->output_position_index != -1) {
936 struct qinst *inst = vir_MOV_dest(c,
937 vir_reg(QFILE_TLBU, 0),
938 c->outputs[c->output_position_index]);
939 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
940
941 if (c->devinfo->ver >= 42) {
942 tlb_specifier |= (TLB_V42_DEPTH_TYPE_PER_PIXEL |
943 TLB_SAMPLE_MODE_PER_PIXEL);
944 } else
945 tlb_specifier |= TLB_DEPTH_TYPE_PER_PIXEL;
946
947 inst->src[vir_get_implicit_uniform_src(inst)] =
948 vir_uniform_ui(c, tlb_specifier | 0xffffff00);
949 } else if (c->s->info.fs.uses_discard ||
950 c->fs_key->sample_alpha_to_coverage ||
951 !has_any_tlb_color_write) {
952 /* Emit passthrough Z if it needed to be delayed until shader
953 * end due to potential discards.
954 *
955 * Since (single-threaded) fragment shaders always need a TLB
956 * write, emit passthrouh Z if we didn't have any color
957 * buffers and flag us as potentially discarding, so that we
958 * can use Z as the TLB write.
959 */
960 c->s->info.fs.uses_discard = true;
961
962 struct qinst *inst = vir_MOV_dest(c,
963 vir_reg(QFILE_TLBU, 0),
964 vir_reg(QFILE_NULL, 0));
965 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
966
967 if (c->devinfo->ver >= 42) {
968 /* The spec says the PER_PIXEL flag is ignored for
969 * invariant writes, but the simulator demands it.
970 */
971 tlb_specifier |= (TLB_V42_DEPTH_TYPE_INVARIANT |
972 TLB_SAMPLE_MODE_PER_PIXEL);
973 } else {
974 tlb_specifier |= TLB_DEPTH_TYPE_INVARIANT;
975 }
976
977 inst->src[vir_get_implicit_uniform_src(inst)] =
978 vir_uniform_ui(c, tlb_specifier | 0xffffff00);
979 }
980
981 /* XXX: Performance improvement: Merge Z write and color writes TLB
982 * uniform setup
983 */
984
985 for (int rt = 0; rt < c->fs_key->nr_cbufs; rt++) {
986 if (!c->output_color_var[rt])
987 continue;
988
989 nir_variable *var = c->output_color_var[rt];
990 struct qreg *color = &c->outputs[var->data.driver_location * 4];
991 int num_components = glsl_get_vector_elements(var->type);
992 uint32_t conf = 0xffffff00;
993 struct qinst *inst;
994
995 conf |= TLB_SAMPLE_MODE_PER_PIXEL;
996 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
997
998 if (c->fs_key->swap_color_rb & (1 << rt))
999 num_components = MAX2(num_components, 3);
1000
1001 assert(num_components != 0);
1002 switch (glsl_get_base_type(var->type)) {
1003 case GLSL_TYPE_UINT:
1004 case GLSL_TYPE_INT:
1005 /* The F32 vs I32 distinction was dropped in 4.2. */
1006 if (c->devinfo->ver < 42)
1007 conf |= TLB_TYPE_I32_COLOR;
1008 else
1009 conf |= TLB_TYPE_F32_COLOR;
1010 conf |= ((num_components - 1) <<
1011 TLB_VEC_SIZE_MINUS_1_SHIFT);
1012
1013 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
1014 inst->src[vir_get_implicit_uniform_src(inst)] =
1015 vir_uniform_ui(c, conf);
1016
1017 for (int i = 1; i < num_components; i++) {
1018 inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
1019 color[i]);
1020 }
1021 break;
1022
1023 default: {
1024 struct qreg r = color[0];
1025 struct qreg g = color[1];
1026 struct qreg b = color[2];
1027 struct qreg a = color[3];
1028
1029 if (c->fs_key->f32_color_rb & (1 << rt)) {
1030 conf |= TLB_TYPE_F32_COLOR;
1031 conf |= ((num_components - 1) <<
1032 TLB_VEC_SIZE_MINUS_1_SHIFT);
1033 } else {
1034 conf |= TLB_TYPE_F16_COLOR;
1035 conf |= TLB_F16_SWAP_HI_LO;
1036 if (num_components >= 3)
1037 conf |= TLB_VEC_SIZE_4_F16;
1038 else
1039 conf |= TLB_VEC_SIZE_2_F16;
1040 }
1041
1042 if (c->fs_key->swap_color_rb & (1 << rt)) {
1043 r = color[2];
1044 b = color[0];
1045 }
1046
1047 if (c->fs_key->sample_alpha_to_one)
1048 a = vir_uniform_f(c, 1.0);
1049
1050 if (c->fs_key->f32_color_rb & (1 << rt)) {
1051 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), r);
1052 inst->src[vir_get_implicit_uniform_src(inst)] =
1053 vir_uniform_ui(c, conf);
1054
1055 if (num_components >= 2)
1056 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), g);
1057 if (num_components >= 3)
1058 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), b);
1059 if (num_components >= 4)
1060 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), a);
1061 } else {
1062 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), r, g);
1063 if (conf != ~0) {
1064 inst->dst.file = QFILE_TLBU;
1065 inst->src[vir_get_implicit_uniform_src(inst)] =
1066 vir_uniform_ui(c, conf);
1067 }
1068
1069 if (num_components >= 3)
1070 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), b, a);
1071 }
1072 break;
1073 }
1074 }
1075 }
1076 }
1077
1078 static void
1079 vir_VPM_WRITE(struct v3d_compile *c, struct qreg val, uint32_t *vpm_index)
1080 {
1081 if (c->devinfo->ver >= 40) {
1082 vir_STVPMV(c, vir_uniform_ui(c, *vpm_index), val);
1083 *vpm_index = *vpm_index + 1;
1084 } else {
1085 vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM), val);
1086 }
1087
1088 c->num_vpm_writes++;
1089 }
1090
1091 static void
1092 emit_scaled_viewport_write(struct v3d_compile *c, struct qreg rcp_w,
1093 uint32_t *vpm_index)
1094 {
1095 for (int i = 0; i < 2; i++) {
1096 struct qreg coord = c->outputs[c->output_position_index + i];
1097 coord = vir_FMUL(c, coord,
1098 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i,
1099 0));
1100 coord = vir_FMUL(c, coord, rcp_w);
1101 vir_VPM_WRITE(c, vir_FTOIN(c, coord), vpm_index);
1102 }
1103
1104 }
1105
1106 static void
1107 emit_zs_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index)
1108 {
1109 struct qreg zscale = vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1110 struct qreg zoffset = vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1111
1112 struct qreg z = c->outputs[c->output_position_index + 2];
1113 z = vir_FMUL(c, z, zscale);
1114 z = vir_FMUL(c, z, rcp_w);
1115 z = vir_FADD(c, z, zoffset);
1116 vir_VPM_WRITE(c, z, vpm_index);
1117 }
1118
1119 static void
1120 emit_rcp_wc_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index)
1121 {
1122 vir_VPM_WRITE(c, rcp_w, vpm_index);
1123 }
1124
1125 static void
1126 emit_point_size_write(struct v3d_compile *c, uint32_t *vpm_index)
1127 {
1128 struct qreg point_size;
1129
1130 if (c->output_point_size_index != -1)
1131 point_size = c->outputs[c->output_point_size_index];
1132 else
1133 point_size = vir_uniform_f(c, 1.0);
1134
1135 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1136 * BCM21553).
1137 */
1138 point_size = vir_FMAX(c, point_size, vir_uniform_f(c, .125));
1139
1140 vir_VPM_WRITE(c, point_size, vpm_index);
1141 }
1142
1143 static void
1144 emit_vpm_write_setup(struct v3d_compile *c)
1145 {
1146 if (c->devinfo->ver >= 40)
1147 return;
1148
1149 v3d33_vir_vpm_write_setup(c);
1150 }
1151
1152 /**
1153 * Sets up c->outputs[c->output_position_index] for the vertex shader
1154 * epilogue, if an output vertex position wasn't specified in the user's
1155 * shader. This may be the case for transform feedback with rasterizer
1156 * discard enabled.
1157 */
1158 static void
1159 setup_default_position(struct v3d_compile *c)
1160 {
1161 if (c->output_position_index != -1)
1162 return;
1163
1164 c->output_position_index = c->outputs_array_size;
1165 for (int i = 0; i < 4; i++) {
1166 add_output(c,
1167 c->output_position_index + i,
1168 VARYING_SLOT_POS, i);
1169 }
1170 }
1171
1172 static void
1173 emit_vert_end(struct v3d_compile *c)
1174 {
1175 setup_default_position(c);
1176
1177 uint32_t vpm_index = 0;
1178 struct qreg rcp_w = vir_RECIP(c,
1179 c->outputs[c->output_position_index + 3]);
1180
1181 emit_vpm_write_setup(c);
1182
1183 if (c->vs_key->is_coord) {
1184 for (int i = 0; i < 4; i++)
1185 vir_VPM_WRITE(c, c->outputs[c->output_position_index + i],
1186 &vpm_index);
1187 emit_scaled_viewport_write(c, rcp_w, &vpm_index);
1188 if (c->vs_key->per_vertex_point_size) {
1189 emit_point_size_write(c, &vpm_index);
1190 /* emit_rcp_wc_write(c, rcp_w); */
1191 }
1192 /* XXX: Z-only rendering */
1193 if (0)
1194 emit_zs_write(c, rcp_w, &vpm_index);
1195 } else {
1196 emit_scaled_viewport_write(c, rcp_w, &vpm_index);
1197 emit_zs_write(c, rcp_w, &vpm_index);
1198 emit_rcp_wc_write(c, rcp_w, &vpm_index);
1199 if (c->vs_key->per_vertex_point_size)
1200 emit_point_size_write(c, &vpm_index);
1201 }
1202
1203 for (int i = 0; i < c->vs_key->num_fs_inputs; i++) {
1204 struct v3d_varying_slot input = c->vs_key->fs_inputs[i];
1205 int j;
1206
1207 for (j = 0; j < c->num_outputs; j++) {
1208 struct v3d_varying_slot output = c->output_slots[j];
1209
1210 if (!memcmp(&input, &output, sizeof(input))) {
1211 vir_VPM_WRITE(c, c->outputs[j],
1212 &vpm_index);
1213 break;
1214 }
1215 }
1216 /* Emit padding if we didn't find a declared VS output for
1217 * this FS input.
1218 */
1219 if (j == c->num_outputs)
1220 vir_VPM_WRITE(c, vir_uniform_f(c, 0.0),
1221 &vpm_index);
1222 }
1223
1224 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1225 */
1226 if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
1227 vir_VPMWT(c);
1228 }
1229
1230 void
1231 v3d_optimize_nir(struct nir_shader *s)
1232 {
1233 bool progress;
1234
1235 do {
1236 progress = false;
1237
1238 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1239 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1240 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1241 NIR_PASS(progress, s, nir_copy_prop);
1242 NIR_PASS(progress, s, nir_opt_remove_phis);
1243 NIR_PASS(progress, s, nir_opt_dce);
1244 NIR_PASS(progress, s, nir_opt_dead_cf);
1245 NIR_PASS(progress, s, nir_opt_cse);
1246 NIR_PASS(progress, s, nir_opt_peephole_select, 8, true, true);
1247 NIR_PASS(progress, s, nir_opt_algebraic);
1248 NIR_PASS(progress, s, nir_opt_constant_folding);
1249 NIR_PASS(progress, s, nir_opt_undef);
1250 } while (progress);
1251
1252 NIR_PASS(progress, s, nir_opt_move_load_ubo);
1253 }
1254
1255 static int
1256 driver_location_compare(const void *in_a, const void *in_b)
1257 {
1258 const nir_variable *const *a = in_a;
1259 const nir_variable *const *b = in_b;
1260
1261 return (*a)->data.driver_location - (*b)->data.driver_location;
1262 }
1263
1264 static struct qreg
1265 ntq_emit_vpm_read(struct v3d_compile *c,
1266 uint32_t *num_components_queued,
1267 uint32_t *remaining,
1268 uint32_t vpm_index)
1269 {
1270 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1271
1272 if (c->devinfo->ver >= 40 ) {
1273 return vir_LDVPMV_IN(c,
1274 vir_uniform_ui(c,
1275 (*num_components_queued)++));
1276 }
1277
1278 if (*num_components_queued != 0) {
1279 (*num_components_queued)--;
1280 c->num_inputs++;
1281 return vir_MOV(c, vpm);
1282 }
1283
1284 uint32_t num_components = MIN2(*remaining, 32);
1285
1286 v3d33_vir_vpm_read_setup(c, num_components);
1287
1288 *num_components_queued = num_components - 1;
1289 *remaining -= num_components;
1290 c->num_inputs++;
1291
1292 return vir_MOV(c, vpm);
1293 }
1294
1295 static void
1296 ntq_setup_vpm_inputs(struct v3d_compile *c)
1297 {
1298 /* Figure out how many components of each vertex attribute the shader
1299 * uses. Each variable should have been split to individual
1300 * components and unused ones DCEed. The vertex fetcher will load
1301 * from the start of the attribute to the number of components we
1302 * declare we need in c->vattr_sizes[].
1303 */
1304 nir_foreach_variable(var, &c->s->inputs) {
1305 /* No VS attribute array support. */
1306 assert(MAX2(glsl_get_length(var->type), 1) == 1);
1307
1308 unsigned loc = var->data.driver_location;
1309 int start_component = var->data.location_frac;
1310 int num_components = glsl_get_components(var->type);
1311
1312 c->vattr_sizes[loc] = MAX2(c->vattr_sizes[loc],
1313 start_component + num_components);
1314 }
1315
1316 unsigned num_components = 0;
1317 uint32_t vpm_components_queued = 0;
1318 bool uses_iid = c->s->info.system_values_read &
1319 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1320 bool uses_vid = c->s->info.system_values_read &
1321 (1ull << SYSTEM_VALUE_VERTEX_ID);
1322 num_components += uses_iid;
1323 num_components += uses_vid;
1324
1325 for (int i = 0; i < ARRAY_SIZE(c->vattr_sizes); i++)
1326 num_components += c->vattr_sizes[i];
1327
1328 if (uses_iid) {
1329 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1330 &num_components, ~0);
1331 }
1332
1333 if (uses_vid) {
1334 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1335 &num_components, ~0);
1336 }
1337
1338 for (int loc = 0; loc < ARRAY_SIZE(c->vattr_sizes); loc++) {
1339 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1340 (loc + 1) * 4);
1341
1342 for (int i = 0; i < c->vattr_sizes[loc]; i++) {
1343 c->inputs[loc * 4 + i] =
1344 ntq_emit_vpm_read(c,
1345 &vpm_components_queued,
1346 &num_components,
1347 loc * 4 + i);
1348
1349 }
1350 }
1351
1352 if (c->devinfo->ver >= 40) {
1353 assert(vpm_components_queued == num_components);
1354 } else {
1355 assert(vpm_components_queued == 0);
1356 assert(num_components == 0);
1357 }
1358 }
1359
1360 static void
1361 ntq_setup_fs_inputs(struct v3d_compile *c)
1362 {
1363 unsigned num_entries = 0;
1364 unsigned num_components = 0;
1365 nir_foreach_variable(var, &c->s->inputs) {
1366 num_entries++;
1367 num_components += glsl_get_components(var->type);
1368 }
1369
1370 nir_variable *vars[num_entries];
1371
1372 unsigned i = 0;
1373 nir_foreach_variable(var, &c->s->inputs)
1374 vars[i++] = var;
1375
1376 /* Sort the variables so that we emit the input setup in
1377 * driver_location order. This is required for VPM reads, whose data
1378 * is fetched into the VPM in driver_location (TGSI register index)
1379 * order.
1380 */
1381 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1382
1383 for (unsigned i = 0; i < num_entries; i++) {
1384 nir_variable *var = vars[i];
1385 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1386 unsigned loc = var->data.driver_location;
1387
1388 assert(array_len == 1);
1389 (void)array_len;
1390 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1391 (loc + 1) * 4);
1392
1393 if (var->data.location == VARYING_SLOT_POS) {
1394 emit_fragcoord_input(c, loc);
1395 } else if (var->data.location == VARYING_SLOT_PNTC ||
1396 (var->data.location >= VARYING_SLOT_VAR0 &&
1397 (c->fs_key->point_sprite_mask &
1398 (1 << (var->data.location -
1399 VARYING_SLOT_VAR0))))) {
1400 c->inputs[loc * 4 + 0] = c->point_x;
1401 c->inputs[loc * 4 + 1] = c->point_y;
1402 } else {
1403 emit_fragment_input(c, loc, var);
1404 }
1405 }
1406 }
1407
1408 static void
1409 ntq_setup_outputs(struct v3d_compile *c)
1410 {
1411 nir_foreach_variable(var, &c->s->outputs) {
1412 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1413 unsigned loc = var->data.driver_location * 4;
1414
1415 assert(array_len == 1);
1416 (void)array_len;
1417
1418 for (int i = 0; i < 4 - var->data.location_frac; i++) {
1419 add_output(c, loc + var->data.location_frac + i,
1420 var->data.location,
1421 var->data.location_frac + i);
1422 }
1423
1424 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1425 switch (var->data.location) {
1426 case FRAG_RESULT_COLOR:
1427 c->output_color_var[0] = var;
1428 c->output_color_var[1] = var;
1429 c->output_color_var[2] = var;
1430 c->output_color_var[3] = var;
1431 break;
1432 case FRAG_RESULT_DATA0:
1433 case FRAG_RESULT_DATA1:
1434 case FRAG_RESULT_DATA2:
1435 case FRAG_RESULT_DATA3:
1436 c->output_color_var[var->data.location -
1437 FRAG_RESULT_DATA0] = var;
1438 break;
1439 case FRAG_RESULT_DEPTH:
1440 c->output_position_index = loc;
1441 break;
1442 case FRAG_RESULT_SAMPLE_MASK:
1443 c->output_sample_mask_index = loc;
1444 break;
1445 }
1446 } else {
1447 switch (var->data.location) {
1448 case VARYING_SLOT_POS:
1449 c->output_position_index = loc;
1450 break;
1451 case VARYING_SLOT_PSIZ:
1452 c->output_point_size_index = loc;
1453 break;
1454 }
1455 }
1456 }
1457 }
1458
1459 static void
1460 ntq_setup_uniforms(struct v3d_compile *c)
1461 {
1462 nir_foreach_variable(var, &c->s->uniforms) {
1463 uint32_t vec4_count = glsl_count_attribute_slots(var->type,
1464 false);
1465 unsigned vec4_size = 4 * sizeof(float);
1466
1467 declare_uniform_range(c, var->data.driver_location * vec4_size,
1468 vec4_count * vec4_size);
1469
1470 }
1471 }
1472
1473 /**
1474 * Sets up the mapping from nir_register to struct qreg *.
1475 *
1476 * Each nir_register gets a struct qreg per 32-bit component being stored.
1477 */
1478 static void
1479 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1480 {
1481 foreach_list_typed(nir_register, nir_reg, node, list) {
1482 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1483 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1484 array_len *
1485 nir_reg->num_components);
1486
1487 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1488
1489 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1490 qregs[i] = vir_get_temp(c);
1491 }
1492 }
1493
1494 static void
1495 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1496 {
1497 /* XXX perf: Experiment with using immediate loads to avoid having
1498 * these end up in the uniform stream. Watch out for breaking the
1499 * small immediates optimization in the process!
1500 */
1501 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1502 for (int i = 0; i < instr->def.num_components; i++)
1503 qregs[i] = vir_uniform_ui(c, instr->value.u32[i]);
1504
1505 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1506 }
1507
1508 static void
1509 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1510 {
1511 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1512
1513 /* VIR needs there to be *some* value, so pick 0 (same as for
1514 * ntq_setup_registers().
1515 */
1516 for (int i = 0; i < instr->def.num_components; i++)
1517 qregs[i] = vir_uniform_ui(c, 0);
1518 }
1519
1520 static void
1521 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
1522 {
1523 unsigned offset;
1524
1525 switch (instr->intrinsic) {
1526 case nir_intrinsic_load_uniform:
1527 assert(instr->num_components == 1);
1528 if (nir_src_is_const(instr->src[0])) {
1529 offset = (nir_intrinsic_base(instr) +
1530 nir_src_as_uint(instr->src[0]));
1531 assert(offset % 4 == 0);
1532 /* We need dwords */
1533 offset = offset / 4;
1534 ntq_store_dest(c, &instr->dest, 0,
1535 vir_uniform(c, QUNIFORM_UNIFORM,
1536 offset));
1537 } else {
1538 ntq_store_dest(c, &instr->dest, 0,
1539 indirect_uniform_load(c, instr));
1540 }
1541 break;
1542
1543 case nir_intrinsic_load_ubo:
1544 for (int i = 0; i < instr->num_components; i++) {
1545 int ubo = nir_src_as_uint(instr->src[0]);
1546
1547 /* XXX perf: On V3D 4.x with uniform offsets, we
1548 * should probably try setting UBOs up in the A
1549 * register file and doing a sequence of loads that
1550 * way.
1551 */
1552 /* Adjust for where we stored the TGSI register base. */
1553 vir_ADD_dest(c,
1554 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA),
1555 vir_uniform(c, QUNIFORM_UBO_ADDR, 1 + ubo),
1556 vir_ADD(c,
1557 ntq_get_src(c, instr->src[1], 0),
1558 vir_uniform_ui(c, i * 4)));
1559
1560 vir_emit_thrsw(c);
1561
1562 ntq_store_dest(c, &instr->dest, i, vir_LDTMU(c));
1563 }
1564 break;
1565
1566 if (nir_src_is_const(instr->src[0])) {
1567 offset = (nir_intrinsic_base(instr) +
1568 nir_src_as_uint(instr->src[0]));
1569 assert(offset % 4 == 0);
1570 /* We need dwords */
1571 offset = offset / 4;
1572 ntq_store_dest(c, &instr->dest, 0,
1573 vir_uniform(c, QUNIFORM_UNIFORM,
1574 offset));
1575 } else {
1576 ntq_store_dest(c, &instr->dest, 0,
1577 indirect_uniform_load(c, instr));
1578 }
1579 break;
1580
1581 case nir_intrinsic_load_user_clip_plane:
1582 for (int i = 0; i < instr->num_components; i++) {
1583 ntq_store_dest(c, &instr->dest, i,
1584 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1585 nir_intrinsic_ucp_id(instr) *
1586 4 + i));
1587 }
1588 break;
1589
1590 case nir_intrinsic_load_alpha_ref_float:
1591 ntq_store_dest(c, &instr->dest, 0,
1592 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1593 break;
1594
1595 case nir_intrinsic_load_sample_mask_in:
1596 ntq_store_dest(c, &instr->dest, 0, vir_MSF(c));
1597 break;
1598
1599 case nir_intrinsic_load_helper_invocation:
1600 vir_PF(c, vir_MSF(c), V3D_QPU_PF_PUSHZ);
1601 ntq_store_dest(c, &instr->dest, 0,
1602 vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1603 vir_uniform_ui(c, ~0),
1604 vir_uniform_ui(c, 0))));
1605 break;
1606
1607 case nir_intrinsic_load_front_face:
1608 /* The register contains 0 (front) or 1 (back), and we need to
1609 * turn it into a NIR bool where true means front.
1610 */
1611 ntq_store_dest(c, &instr->dest, 0,
1612 vir_ADD(c,
1613 vir_uniform_ui(c, -1),
1614 vir_REVF(c)));
1615 break;
1616
1617 case nir_intrinsic_load_instance_id:
1618 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
1619 break;
1620
1621 case nir_intrinsic_load_vertex_id:
1622 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
1623 break;
1624
1625 case nir_intrinsic_load_input:
1626 for (int i = 0; i < instr->num_components; i++) {
1627 offset = (nir_intrinsic_base(instr) +
1628 nir_src_as_uint(instr->src[0]));
1629 int comp = nir_intrinsic_component(instr) + i;
1630 ntq_store_dest(c, &instr->dest, i,
1631 vir_MOV(c, c->inputs[offset * 4 + comp]));
1632 }
1633 break;
1634
1635 case nir_intrinsic_store_output:
1636 offset = ((nir_intrinsic_base(instr) +
1637 nir_src_as_uint(instr->src[1])) * 4 +
1638 nir_intrinsic_component(instr));
1639
1640 for (int i = 0; i < instr->num_components; i++) {
1641 c->outputs[offset + i] =
1642 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
1643 }
1644 c->num_outputs = MAX2(c->num_outputs,
1645 offset + instr->num_components);
1646 break;
1647
1648 case nir_intrinsic_discard:
1649 if (c->execute.file != QFILE_NULL) {
1650 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1651 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1652 vir_uniform_ui(c, 0)),
1653 V3D_QPU_COND_IFA);
1654 } else {
1655 vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1656 vir_uniform_ui(c, 0));
1657 }
1658 break;
1659
1660 case nir_intrinsic_discard_if: {
1661 /* true (~0) if we're discarding */
1662 struct qreg cond = ntq_get_src(c, instr->src[0], 0);
1663
1664 if (c->execute.file != QFILE_NULL) {
1665 /* execute == 0 means the channel is active. Invert
1666 * the condition so that we can use zero as "executing
1667 * and discarding."
1668 */
1669 vir_PF(c, vir_OR(c, c->execute, vir_NOT(c, cond)),
1670 V3D_QPU_PF_PUSHZ);
1671 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1672 vir_uniform_ui(c, 0)),
1673 V3D_QPU_COND_IFA);
1674 } else {
1675 vir_PF(c, cond, V3D_QPU_PF_PUSHZ);
1676 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1677 vir_uniform_ui(c, 0)),
1678 V3D_QPU_COND_IFNA);
1679 }
1680
1681 break;
1682 }
1683
1684 default:
1685 fprintf(stderr, "Unknown intrinsic: ");
1686 nir_print_instr(&instr->instr, stderr);
1687 fprintf(stderr, "\n");
1688 break;
1689 }
1690 }
1691
1692 /* Clears (activates) the execute flags for any channels whose jump target
1693 * matches this block.
1694 *
1695 * XXX perf: Could we be using flpush/flpop somehow for our execution channel
1696 * enabling?
1697 *
1698 * XXX perf: For uniform control flow, we should be able to skip c->execute
1699 * handling entirely.
1700 */
1701 static void
1702 ntq_activate_execute_for_block(struct v3d_compile *c)
1703 {
1704 vir_set_pf(vir_XOR_dest(c, vir_reg(QFILE_NULL, 0),
1705 c->execute, vir_uniform_ui(c, c->cur_block->index)),
1706 V3D_QPU_PF_PUSHZ);
1707
1708 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
1709 }
1710
1711 static void
1712 ntq_emit_if(struct v3d_compile *c, nir_if *if_stmt)
1713 {
1714 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
1715 bool empty_else_block =
1716 (nir_else_block == nir_if_last_else_block(if_stmt) &&
1717 exec_list_is_empty(&nir_else_block->instr_list));
1718
1719 struct qblock *then_block = vir_new_block(c);
1720 struct qblock *after_block = vir_new_block(c);
1721 struct qblock *else_block;
1722 if (empty_else_block)
1723 else_block = after_block;
1724 else
1725 else_block = vir_new_block(c);
1726
1727 bool was_top_level = false;
1728 if (c->execute.file == QFILE_NULL) {
1729 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
1730 was_top_level = true;
1731 }
1732
1733 /* Set A for executing (execute == 0) and jumping (if->condition ==
1734 * 0) channels, and then update execute flags for those to point to
1735 * the ELSE block.
1736 *
1737 * XXX perf: we could reuse ntq_emit_comparison() to generate our if
1738 * condition, and the .uf field to ignore non-executing channels, to
1739 * reduce the overhead of if statements.
1740 */
1741 vir_PF(c, vir_OR(c,
1742 c->execute,
1743 ntq_get_src(c, if_stmt->condition, 0)),
1744 V3D_QPU_PF_PUSHZ);
1745 vir_MOV_cond(c, V3D_QPU_COND_IFA,
1746 c->execute,
1747 vir_uniform_ui(c, else_block->index));
1748
1749 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1750 * through.
1751 */
1752 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1753 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
1754 vir_link_blocks(c->cur_block, else_block);
1755 vir_link_blocks(c->cur_block, then_block);
1756
1757 /* Process the THEN block. */
1758 vir_set_emit_block(c, then_block);
1759 ntq_emit_cf_list(c, &if_stmt->then_list);
1760
1761 if (!empty_else_block) {
1762 /* Handle the end of the THEN block. First, all currently
1763 * active channels update their execute flags to point to
1764 * ENDIF
1765 */
1766 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1767 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1768 vir_uniform_ui(c, after_block->index));
1769
1770 /* If everything points at ENDIF, then jump there immediately. */
1771 vir_PF(c, vir_XOR(c, c->execute,
1772 vir_uniform_ui(c, after_block->index)),
1773 V3D_QPU_PF_PUSHZ);
1774 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
1775 vir_link_blocks(c->cur_block, after_block);
1776 vir_link_blocks(c->cur_block, else_block);
1777
1778 vir_set_emit_block(c, else_block);
1779 ntq_activate_execute_for_block(c);
1780 ntq_emit_cf_list(c, &if_stmt->else_list);
1781 }
1782
1783 vir_link_blocks(c->cur_block, after_block);
1784
1785 vir_set_emit_block(c, after_block);
1786 if (was_top_level)
1787 c->execute = c->undef;
1788 else
1789 ntq_activate_execute_for_block(c);
1790 }
1791
1792 static void
1793 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
1794 {
1795 switch (jump->type) {
1796 case nir_jump_break:
1797 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1798 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1799 vir_uniform_ui(c, c->loop_break_block->index));
1800 break;
1801
1802 case nir_jump_continue:
1803 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1804 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1805 vir_uniform_ui(c, c->loop_cont_block->index));
1806 break;
1807
1808 case nir_jump_return:
1809 unreachable("All returns shouold be lowered\n");
1810 }
1811 }
1812
1813 static void
1814 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
1815 {
1816 switch (instr->type) {
1817 case nir_instr_type_alu:
1818 ntq_emit_alu(c, nir_instr_as_alu(instr));
1819 break;
1820
1821 case nir_instr_type_intrinsic:
1822 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
1823 break;
1824
1825 case nir_instr_type_load_const:
1826 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
1827 break;
1828
1829 case nir_instr_type_ssa_undef:
1830 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
1831 break;
1832
1833 case nir_instr_type_tex:
1834 ntq_emit_tex(c, nir_instr_as_tex(instr));
1835 break;
1836
1837 case nir_instr_type_jump:
1838 ntq_emit_jump(c, nir_instr_as_jump(instr));
1839 break;
1840
1841 default:
1842 fprintf(stderr, "Unknown NIR instr type: ");
1843 nir_print_instr(instr, stderr);
1844 fprintf(stderr, "\n");
1845 abort();
1846 }
1847 }
1848
1849 static void
1850 ntq_emit_block(struct v3d_compile *c, nir_block *block)
1851 {
1852 nir_foreach_instr(instr, block) {
1853 ntq_emit_instr(c, instr);
1854 }
1855 }
1856
1857 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
1858
1859 static void
1860 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
1861 {
1862 bool was_top_level = false;
1863 if (c->execute.file == QFILE_NULL) {
1864 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
1865 was_top_level = true;
1866 }
1867
1868 struct qblock *save_loop_cont_block = c->loop_cont_block;
1869 struct qblock *save_loop_break_block = c->loop_break_block;
1870
1871 c->loop_cont_block = vir_new_block(c);
1872 c->loop_break_block = vir_new_block(c);
1873
1874 vir_link_blocks(c->cur_block, c->loop_cont_block);
1875 vir_set_emit_block(c, c->loop_cont_block);
1876 ntq_activate_execute_for_block(c);
1877
1878 ntq_emit_cf_list(c, &loop->body);
1879
1880 /* Re-enable any previous continues now, so our ANYA check below
1881 * works.
1882 *
1883 * XXX: Use the .ORZ flags update, instead.
1884 */
1885 vir_PF(c, vir_XOR(c,
1886 c->execute,
1887 vir_uniform_ui(c, c->loop_cont_block->index)),
1888 V3D_QPU_PF_PUSHZ);
1889 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
1890
1891 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1892
1893 struct qinst *branch = vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
1894 /* Pixels that were not dispatched or have been discarded should not
1895 * contribute to looping again.
1896 */
1897 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P;
1898 vir_link_blocks(c->cur_block, c->loop_cont_block);
1899 vir_link_blocks(c->cur_block, c->loop_break_block);
1900
1901 vir_set_emit_block(c, c->loop_break_block);
1902 if (was_top_level)
1903 c->execute = c->undef;
1904 else
1905 ntq_activate_execute_for_block(c);
1906
1907 c->loop_break_block = save_loop_break_block;
1908 c->loop_cont_block = save_loop_cont_block;
1909
1910 c->loops++;
1911 }
1912
1913 static void
1914 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
1915 {
1916 fprintf(stderr, "FUNCTIONS not handled.\n");
1917 abort();
1918 }
1919
1920 static void
1921 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
1922 {
1923 foreach_list_typed(nir_cf_node, node, node, list) {
1924 switch (node->type) {
1925 case nir_cf_node_block:
1926 ntq_emit_block(c, nir_cf_node_as_block(node));
1927 break;
1928
1929 case nir_cf_node_if:
1930 ntq_emit_if(c, nir_cf_node_as_if(node));
1931 break;
1932
1933 case nir_cf_node_loop:
1934 ntq_emit_loop(c, nir_cf_node_as_loop(node));
1935 break;
1936
1937 case nir_cf_node_function:
1938 ntq_emit_function(c, nir_cf_node_as_function(node));
1939 break;
1940
1941 default:
1942 fprintf(stderr, "Unknown NIR node type\n");
1943 abort();
1944 }
1945 }
1946 }
1947
1948 static void
1949 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
1950 {
1951 ntq_setup_registers(c, &impl->registers);
1952 ntq_emit_cf_list(c, &impl->body);
1953 }
1954
1955 static void
1956 nir_to_vir(struct v3d_compile *c)
1957 {
1958 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1959 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
1960 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
1961 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
1962
1963 /* XXX perf: We could set the "disable implicit point/line
1964 * varyings" field in the shader record and not emit these, if
1965 * they're not going to be used.
1966 */
1967 if (c->fs_key->is_points) {
1968 c->point_x = emit_fragment_varying(c, NULL, 0);
1969 c->point_y = emit_fragment_varying(c, NULL, 0);
1970 } else if (c->fs_key->is_lines) {
1971 c->line_x = emit_fragment_varying(c, NULL, 0);
1972 }
1973 }
1974
1975 if (c->s->info.stage == MESA_SHADER_FRAGMENT)
1976 ntq_setup_fs_inputs(c);
1977 else
1978 ntq_setup_vpm_inputs(c);
1979
1980 ntq_setup_outputs(c);
1981 ntq_setup_uniforms(c);
1982 ntq_setup_registers(c, &c->s->registers);
1983
1984 /* Find the main function and emit the body. */
1985 nir_foreach_function(function, c->s) {
1986 assert(strcmp(function->name, "main") == 0);
1987 assert(function->impl);
1988 ntq_emit_impl(c, function->impl);
1989 }
1990 }
1991
1992 const nir_shader_compiler_options v3d_nir_options = {
1993 .lower_all_io_to_temps = true,
1994 .lower_extract_byte = true,
1995 .lower_extract_word = true,
1996 .lower_bfm = true,
1997 .lower_bitfield_insert_to_shifts = true,
1998 .lower_bitfield_extract_to_shifts = true,
1999 .lower_bitfield_reverse = true,
2000 .lower_bit_count = true,
2001 .lower_pack_unorm_2x16 = true,
2002 .lower_pack_snorm_2x16 = true,
2003 .lower_pack_unorm_4x8 = true,
2004 .lower_pack_snorm_4x8 = true,
2005 .lower_unpack_unorm_4x8 = true,
2006 .lower_unpack_snorm_4x8 = true,
2007 .lower_pack_half_2x16 = true,
2008 .lower_unpack_half_2x16 = true,
2009 .lower_fdiv = true,
2010 .lower_find_lsb = true,
2011 .lower_ffma = true,
2012 .lower_flrp32 = true,
2013 .lower_fpow = true,
2014 .lower_fsat = true,
2015 .lower_fsqrt = true,
2016 .lower_ifind_msb = true,
2017 .lower_ldexp = true,
2018 .lower_mul_high = true,
2019 .lower_wpos_pntc = true,
2020 .native_integers = true,
2021 };
2022
2023 /**
2024 * When demoting a shader down to single-threaded, removes the THRSW
2025 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
2026 * program end).
2027 */
2028 static void
2029 vir_remove_thrsw(struct v3d_compile *c)
2030 {
2031 vir_for_each_block(block, c) {
2032 vir_for_each_inst_safe(inst, block) {
2033 if (inst->qpu.sig.thrsw)
2034 vir_remove_instruction(c, inst);
2035 }
2036 }
2037
2038 c->last_thrsw = NULL;
2039 }
2040
2041 void
2042 vir_emit_last_thrsw(struct v3d_compile *c)
2043 {
2044 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
2045 * switching, so disable threads if we didn't do any TMU ops (each of
2046 * which would have emitted a THRSW).
2047 */
2048 if (!c->last_thrsw_at_top_level && c->devinfo->ver < 41) {
2049 c->threads = 1;
2050 if (c->last_thrsw)
2051 vir_remove_thrsw(c);
2052 return;
2053 }
2054
2055 /* If we're threaded and the last THRSW was in conditional code, then
2056 * we need to emit another one so that we can flag it as the last
2057 * thrsw.
2058 */
2059 if (c->last_thrsw && !c->last_thrsw_at_top_level) {
2060 assert(c->devinfo->ver >= 41);
2061 vir_emit_thrsw(c);
2062 }
2063
2064 /* If we're threaded, then we need to mark the last THRSW instruction
2065 * so we can emit a pair of them at QPU emit time.
2066 *
2067 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2068 * post-last-THRSW state, so we can skip this.
2069 */
2070 if (!c->last_thrsw && c->s->info.stage == MESA_SHADER_FRAGMENT) {
2071 assert(c->devinfo->ver >= 41);
2072 vir_emit_thrsw(c);
2073 }
2074
2075 if (c->last_thrsw)
2076 c->last_thrsw->is_last_thrsw = true;
2077 }
2078
2079 /* There's a flag in the shader for "center W is needed for reasons other than
2080 * non-centroid varyings", so we just walk the program after VIR optimization
2081 * to see if it's used. It should be harmless to set even if we only use
2082 * center W for varyings.
2083 */
2084 static void
2085 vir_check_payload_w(struct v3d_compile *c)
2086 {
2087 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
2088 return;
2089
2090 vir_for_each_inst_inorder(inst, c) {
2091 for (int i = 0; i < vir_get_nsrc(inst); i++) {
2092 if (inst->src[i].file == QFILE_REG &&
2093 inst->src[i].index == 0) {
2094 c->uses_center_w = true;
2095 return;
2096 }
2097 }
2098 }
2099
2100 }
2101
2102 void
2103 v3d_nir_to_vir(struct v3d_compile *c)
2104 {
2105 if (V3D_DEBUG & (V3D_DEBUG_NIR |
2106 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2107 fprintf(stderr, "%s prog %d/%d NIR:\n",
2108 vir_get_stage_name(c),
2109 c->program_id, c->variant_id);
2110 nir_print_shader(c->s, stderr);
2111 }
2112
2113 nir_to_vir(c);
2114
2115 /* Emit the last THRSW before STVPM and TLB writes. */
2116 vir_emit_last_thrsw(c);
2117
2118 switch (c->s->info.stage) {
2119 case MESA_SHADER_FRAGMENT:
2120 emit_frag_end(c);
2121 break;
2122 case MESA_SHADER_VERTEX:
2123 emit_vert_end(c);
2124 break;
2125 default:
2126 unreachable("bad stage");
2127 }
2128
2129 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2130 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2131 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
2132 vir_get_stage_name(c),
2133 c->program_id, c->variant_id);
2134 vir_dump(c);
2135 fprintf(stderr, "\n");
2136 }
2137
2138 vir_optimize(c);
2139 vir_lower_uniforms(c);
2140
2141 vir_check_payload_w(c);
2142
2143 /* XXX perf: On VC4, we do a VIR-level instruction scheduling here.
2144 * We used that on that platform to pipeline TMU writes and reduce the
2145 * number of thread switches, as well as try (mostly successfully) to
2146 * reduce maximum register pressure to allow more threads. We should
2147 * do something of that sort for V3D -- either instruction scheduling
2148 * here, or delay the the THRSW and LDTMUs from our texture
2149 * instructions until the results are needed.
2150 */
2151
2152 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2153 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2154 fprintf(stderr, "%s prog %d/%d VIR:\n",
2155 vir_get_stage_name(c),
2156 c->program_id, c->variant_id);
2157 vir_dump(c);
2158 fprintf(stderr, "\n");
2159 }
2160
2161 /* Attempt to allocate registers for the temporaries. If we fail,
2162 * reduce thread count and try again.
2163 */
2164 int min_threads = (c->devinfo->ver >= 41) ? 2 : 1;
2165 struct qpu_reg *temp_registers;
2166 while (true) {
2167 bool spilled;
2168 temp_registers = v3d_register_allocate(c, &spilled);
2169 if (spilled)
2170 continue;
2171
2172 if (temp_registers)
2173 break;
2174
2175 if (c->threads == min_threads) {
2176 fprintf(stderr, "Failed to register allocate at %d threads:\n",
2177 c->threads);
2178 vir_dump(c);
2179 c->failed = true;
2180 return;
2181 }
2182
2183 c->threads /= 2;
2184
2185 if (c->threads == 1)
2186 vir_remove_thrsw(c);
2187 }
2188
2189 v3d_vir_to_qpu(c, temp_registers);
2190 }