2 * Copyright © 2016 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
35 #define GENERAL_TMU_LOOKUP_PER_QUAD (0 << 7)
36 #define GENERAL_TMU_LOOKUP_PER_PIXEL (1 << 7)
37 #define GENERAL_TMU_READ_OP_PREFETCH (0 << 3)
38 #define GENERAL_TMU_READ_OP_CACHE_CLEAR (1 << 3)
39 #define GENERAL_TMU_READ_OP_CACHE_FLUSH (3 << 3)
40 #define GENERAL_TMU_READ_OP_CACHE_CLEAN (3 << 3)
41 #define GENERAL_TMU_READ_OP_CACHE_L1T_CLEAR (4 << 3)
42 #define GENERAL_TMU_READ_OP_CACHE_L1T_FLUSH_AGGREGATION (5 << 3)
43 #define GENERAL_TMU_READ_OP_ATOMIC_INC (8 << 3)
44 #define GENERAL_TMU_READ_OP_ATOMIC_DEC (9 << 3)
45 #define GENERAL_TMU_READ_OP_ATOMIC_NOT (10 << 3)
46 #define GENERAL_TMU_READ_OP_READ (15 << 3)
47 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_I (0 << 0)
48 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_I (1 << 0)
49 #define GENERAL_TMU_LOOKUP_TYPE_VEC2 (2 << 0)
50 #define GENERAL_TMU_LOOKUP_TYPE_VEC3 (3 << 0)
51 #define GENERAL_TMU_LOOKUP_TYPE_VEC4 (4 << 0)
52 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_UI (5 << 0)
53 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_UI (6 << 0)
54 #define GENERAL_TMU_LOOKUP_TYPE_32BIT_UI (7 << 0)
56 #define GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP (0 << 3)
57 #define GENERAL_TMU_WRITE_OP_ATOMIC_SUB_WRAP (1 << 3)
58 #define GENERAL_TMU_WRITE_OP_ATOMIC_XCHG (2 << 3)
59 #define GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG (3 << 3)
60 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMIN (4 << 3)
61 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMAX (5 << 3)
62 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMIN (6 << 3)
63 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMAX (7 << 3)
64 #define GENERAL_TMU_WRITE_OP_ATOMIC_AND (8 << 3)
65 #define GENERAL_TMU_WRITE_OP_ATOMIC_OR (9 << 3)
66 #define GENERAL_TMU_WRITE_OP_ATOMIC_XOR (10 << 3)
67 #define GENERAL_TMU_WRITE_OP_WRITE (15 << 3)
69 #define V3D_TSY_SET_QUORUM 0
70 #define V3D_TSY_INC_WAITERS 1
71 #define V3D_TSY_DEC_WAITERS 2
72 #define V3D_TSY_INC_QUORUM 3
73 #define V3D_TSY_DEC_QUORUM 4
74 #define V3D_TSY_FREE_ALL 5
75 #define V3D_TSY_RELEASE 6
76 #define V3D_TSY_ACQUIRE 7
77 #define V3D_TSY_WAIT 8
78 #define V3D_TSY_WAIT_INC 9
79 #define V3D_TSY_WAIT_CHECK 10
80 #define V3D_TSY_WAIT_INC_CHECK 11
81 #define V3D_TSY_WAIT_CV 12
82 #define V3D_TSY_INC_SEMAPHORE 13
83 #define V3D_TSY_DEC_SEMAPHORE 14
84 #define V3D_TSY_SET_QUORUM_FREE_ALL 15
87 ntq_emit_cf_list(struct v3d_compile
*c
, struct exec_list
*list
);
90 resize_qreg_array(struct v3d_compile
*c
,
95 if (*size
>= decl_size
)
98 uint32_t old_size
= *size
;
99 *size
= MAX2(*size
* 2, decl_size
);
100 *regs
= reralloc(c
, *regs
, struct qreg
, *size
);
102 fprintf(stderr
, "Malloc failure\n");
106 for (uint32_t i
= old_size
; i
< *size
; i
++)
107 (*regs
)[i
] = c
->undef
;
111 vir_emit_thrsw(struct v3d_compile
*c
)
116 /* Always thread switch after each texture operation for now.
118 * We could do better by batching a bunch of texture fetches up and
119 * then doing one thread switch and collecting all their results
122 c
->last_thrsw
= vir_NOP(c
);
123 c
->last_thrsw
->qpu
.sig
.thrsw
= true;
124 c
->last_thrsw_at_top_level
= !c
->in_control_flow
;
128 v3d_general_tmu_op(nir_intrinsic_instr
*instr
)
130 switch (instr
->intrinsic
) {
131 case nir_intrinsic_load_ssbo
:
132 case nir_intrinsic_load_ubo
:
133 case nir_intrinsic_load_uniform
:
134 case nir_intrinsic_load_shared
:
135 case nir_intrinsic_load_scratch
:
136 return GENERAL_TMU_READ_OP_READ
;
137 case nir_intrinsic_store_ssbo
:
138 case nir_intrinsic_store_shared
:
139 case nir_intrinsic_store_scratch
:
140 return GENERAL_TMU_WRITE_OP_WRITE
;
141 case nir_intrinsic_ssbo_atomic_add
:
142 case nir_intrinsic_shared_atomic_add
:
143 return GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP
;
144 case nir_intrinsic_ssbo_atomic_imin
:
145 case nir_intrinsic_shared_atomic_imin
:
146 return GENERAL_TMU_WRITE_OP_ATOMIC_SMIN
;
147 case nir_intrinsic_ssbo_atomic_umin
:
148 case nir_intrinsic_shared_atomic_umin
:
149 return GENERAL_TMU_WRITE_OP_ATOMIC_UMIN
;
150 case nir_intrinsic_ssbo_atomic_imax
:
151 case nir_intrinsic_shared_atomic_imax
:
152 return GENERAL_TMU_WRITE_OP_ATOMIC_SMAX
;
153 case nir_intrinsic_ssbo_atomic_umax
:
154 case nir_intrinsic_shared_atomic_umax
:
155 return GENERAL_TMU_WRITE_OP_ATOMIC_UMAX
;
156 case nir_intrinsic_ssbo_atomic_and
:
157 case nir_intrinsic_shared_atomic_and
:
158 return GENERAL_TMU_WRITE_OP_ATOMIC_AND
;
159 case nir_intrinsic_ssbo_atomic_or
:
160 case nir_intrinsic_shared_atomic_or
:
161 return GENERAL_TMU_WRITE_OP_ATOMIC_OR
;
162 case nir_intrinsic_ssbo_atomic_xor
:
163 case nir_intrinsic_shared_atomic_xor
:
164 return GENERAL_TMU_WRITE_OP_ATOMIC_XOR
;
165 case nir_intrinsic_ssbo_atomic_exchange
:
166 case nir_intrinsic_shared_atomic_exchange
:
167 return GENERAL_TMU_WRITE_OP_ATOMIC_XCHG
;
168 case nir_intrinsic_ssbo_atomic_comp_swap
:
169 case nir_intrinsic_shared_atomic_comp_swap
:
170 return GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG
;
172 unreachable("unknown intrinsic op");
177 * Implements indirect uniform loads and SSBO accesses through the TMU general
178 * memory access interface.
181 ntq_emit_tmu_general(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
,
182 bool is_shared_or_scratch
)
184 /* XXX perf: We should turn add/sub of 1 to inc/dec. Perhaps NIR
185 * wants to have support for inc/dec?
188 uint32_t tmu_op
= v3d_general_tmu_op(instr
);
189 bool is_store
= (instr
->intrinsic
== nir_intrinsic_store_ssbo
||
190 instr
->intrinsic
== nir_intrinsic_store_scratch
||
191 instr
->intrinsic
== nir_intrinsic_store_shared
);
192 bool has_index
= !is_shared_or_scratch
;
195 int tmu_writes
= 1; /* address */
196 if (instr
->intrinsic
== nir_intrinsic_load_uniform
) {
198 } else if (instr
->intrinsic
== nir_intrinsic_load_ssbo
||
199 instr
->intrinsic
== nir_intrinsic_load_ubo
||
200 instr
->intrinsic
== nir_intrinsic_load_scratch
||
201 instr
->intrinsic
== nir_intrinsic_load_shared
) {
202 offset_src
= 0 + has_index
;
203 } else if (is_store
) {
204 offset_src
= 1 + has_index
;
205 for (int i
= 0; i
< instr
->num_components
; i
++) {
207 vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_TMUD
),
208 ntq_get_src(c
, instr
->src
[0], i
));
212 offset_src
= 0 + has_index
;
214 vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_TMUD
),
215 ntq_get_src(c
, instr
->src
[1 + has_index
], 0));
217 if (tmu_op
== GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG
) {
219 vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_TMUD
),
220 ntq_get_src(c
, instr
->src
[2 + has_index
],
226 bool dynamic_src
= !nir_src_is_const(instr
->src
[offset_src
]);
227 uint32_t const_offset
= 0;
229 const_offset
= nir_src_as_uint(instr
->src
[offset_src
]);
231 /* Make sure we won't exceed the 16-entry TMU fifo if each thread is
232 * storing at the same time.
234 while (tmu_writes
> 16 / c
->threads
)
238 if (instr
->intrinsic
== nir_intrinsic_load_uniform
) {
239 const_offset
+= nir_intrinsic_base(instr
);
240 offset
= vir_uniform(c
, QUNIFORM_UBO_ADDR
,
241 v3d_unit_data_create(0, const_offset
));
243 } else if (instr
->intrinsic
== nir_intrinsic_load_ubo
) {
244 uint32_t index
= nir_src_as_uint(instr
->src
[0]) + 1;
245 /* Note that QUNIFORM_UBO_ADDR takes a UBO index shifted up by
246 * 1 (0 is gallium's constant buffer 0).
248 offset
= vir_uniform(c
, QUNIFORM_UBO_ADDR
,
249 v3d_unit_data_create(index
, const_offset
));
251 } else if (is_shared_or_scratch
) {
252 /* Shared and scratch variables have no buffer index, and all
253 * start from a common base that we set up at the start of
256 if (instr
->intrinsic
== nir_intrinsic_load_scratch
||
257 instr
->intrinsic
== nir_intrinsic_store_scratch
) {
258 offset
= c
->spill_base
;
260 offset
= c
->cs_shared_offset
;
261 const_offset
+= nir_intrinsic_base(instr
);
264 offset
= vir_uniform(c
, QUNIFORM_SSBO_OFFSET
,
265 nir_src_as_uint(instr
->src
[is_store
?
269 /* The spec says that for atomics, the TYPE field is ignored, but that
270 * doesn't seem to be the case for CMPXCHG. Just use the number of
271 * tmud writes we did to decide the type (or choose "32bit" for atomic
272 * reads, which has been fine).
275 if (tmu_op
== GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG
)
278 num_components
= instr
->num_components
;
280 uint32_t config
= (0xffffff00 |
282 GENERAL_TMU_LOOKUP_PER_PIXEL
);
283 if (num_components
== 1) {
284 config
|= GENERAL_TMU_LOOKUP_TYPE_32BIT_UI
;
286 config
|= GENERAL_TMU_LOOKUP_TYPE_VEC2
+ num_components
- 2;
289 if (vir_in_nonuniform_control_flow(c
)) {
290 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
),
296 tmua
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_TMUA
);
298 tmua
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_TMUAU
);
302 if (const_offset
!= 0) {
303 offset
= vir_ADD(c
, offset
,
304 vir_uniform_ui(c
, const_offset
));
306 tmu
= vir_ADD_dest(c
, tmua
, offset
,
307 ntq_get_src(c
, instr
->src
[offset_src
], 0));
309 if (const_offset
!= 0) {
310 tmu
= vir_ADD_dest(c
, tmua
, offset
,
311 vir_uniform_ui(c
, const_offset
));
313 tmu
= vir_MOV_dest(c
, tmua
, offset
);
318 tmu
->uniform
= vir_get_uniform_index(c
, QUNIFORM_CONSTANT
,
322 if (vir_in_nonuniform_control_flow(c
))
323 vir_set_cond(tmu
, V3D_QPU_COND_IFA
);
327 /* Read the result, or wait for the TMU op to complete. */
328 for (int i
= 0; i
< nir_intrinsic_dest_components(instr
); i
++)
329 ntq_store_dest(c
, &instr
->dest
, i
, vir_MOV(c
, vir_LDTMU(c
)));
331 if (nir_intrinsic_dest_components(instr
) == 0)
336 ntq_init_ssa_def(struct v3d_compile
*c
, nir_ssa_def
*def
)
338 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
339 def
->num_components
);
340 _mesa_hash_table_insert(c
->def_ht
, def
, qregs
);
345 * This function is responsible for getting VIR results into the associated
346 * storage for a NIR instruction.
348 * If it's a NIR SSA def, then we just set the associated hash table entry to
351 * If it's a NIR reg, then we need to update the existing qreg assigned to the
352 * NIR destination with the incoming value. To do that without introducing
353 * new MOVs, we require that the incoming qreg either be a uniform, or be
354 * SSA-defined by the previous VIR instruction in the block and rewritable by
355 * this function. That lets us sneak ahead and insert the SF flag beforehand
356 * (knowing that the previous instruction doesn't depend on flags) and rewrite
357 * its destination to be the NIR reg's destination
360 ntq_store_dest(struct v3d_compile
*c
, nir_dest
*dest
, int chan
,
363 struct qinst
*last_inst
= NULL
;
364 if (!list_empty(&c
->cur_block
->instructions
))
365 last_inst
= (struct qinst
*)c
->cur_block
->instructions
.prev
;
367 assert((result
.file
== QFILE_TEMP
&&
368 last_inst
&& last_inst
== c
->defs
[result
.index
]));
371 assert(chan
< dest
->ssa
.num_components
);
374 struct hash_entry
*entry
=
375 _mesa_hash_table_search(c
->def_ht
, &dest
->ssa
);
380 qregs
= ntq_init_ssa_def(c
, &dest
->ssa
);
382 qregs
[chan
] = result
;
384 nir_register
*reg
= dest
->reg
.reg
;
385 assert(dest
->reg
.base_offset
== 0);
386 assert(reg
->num_array_elems
== 0);
387 struct hash_entry
*entry
=
388 _mesa_hash_table_search(c
->def_ht
, reg
);
389 struct qreg
*qregs
= entry
->data
;
391 /* Insert a MOV if the source wasn't an SSA def in the
392 * previous instruction.
394 if ((vir_in_nonuniform_control_flow(c
) &&
395 c
->defs
[last_inst
->dst
.index
]->qpu
.sig
.ldunif
)) {
396 result
= vir_MOV(c
, result
);
397 last_inst
= c
->defs
[result
.index
];
400 /* We know they're both temps, so just rewrite index. */
401 c
->defs
[last_inst
->dst
.index
] = NULL
;
402 last_inst
->dst
.index
= qregs
[chan
].index
;
404 /* If we're in control flow, then make this update of the reg
405 * conditional on the execution mask.
407 if (vir_in_nonuniform_control_flow(c
)) {
408 last_inst
->dst
.index
= qregs
[chan
].index
;
410 /* Set the flags to the current exec mask.
412 c
->cursor
= vir_before_inst(last_inst
);
413 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
),
415 c
->cursor
= vir_after_inst(last_inst
);
417 vir_set_cond(last_inst
, V3D_QPU_COND_IFA
);
423 ntq_get_src(struct v3d_compile
*c
, nir_src src
, int i
)
425 struct hash_entry
*entry
;
427 entry
= _mesa_hash_table_search(c
->def_ht
, src
.ssa
);
428 assert(i
< src
.ssa
->num_components
);
430 nir_register
*reg
= src
.reg
.reg
;
431 entry
= _mesa_hash_table_search(c
->def_ht
, reg
);
432 assert(reg
->num_array_elems
== 0);
433 assert(src
.reg
.base_offset
== 0);
434 assert(i
< reg
->num_components
);
437 struct qreg
*qregs
= entry
->data
;
442 ntq_get_alu_src(struct v3d_compile
*c
, nir_alu_instr
*instr
,
445 assert(util_is_power_of_two_or_zero(instr
->dest
.write_mask
));
446 unsigned chan
= ffs(instr
->dest
.write_mask
) - 1;
447 struct qreg r
= ntq_get_src(c
, instr
->src
[src
].src
,
448 instr
->src
[src
].swizzle
[chan
]);
450 assert(!instr
->src
[src
].abs
);
451 assert(!instr
->src
[src
].negate
);
457 ntq_minify(struct v3d_compile
*c
, struct qreg size
, struct qreg level
)
459 return vir_MAX(c
, vir_SHR(c
, size
, level
), vir_uniform_ui(c
, 1));
463 ntq_emit_txs(struct v3d_compile
*c
, nir_tex_instr
*instr
)
465 unsigned unit
= instr
->texture_index
;
466 int lod_index
= nir_tex_instr_src_index(instr
, nir_tex_src_lod
);
467 int dest_size
= nir_tex_instr_dest_size(instr
);
469 struct qreg lod
= c
->undef
;
471 lod
= ntq_get_src(c
, instr
->src
[lod_index
].src
, 0);
473 for (int i
= 0; i
< dest_size
; i
++) {
475 enum quniform_contents contents
;
477 if (instr
->is_array
&& i
== dest_size
- 1)
478 contents
= QUNIFORM_TEXTURE_ARRAY_SIZE
;
480 contents
= QUNIFORM_TEXTURE_WIDTH
+ i
;
482 struct qreg size
= vir_uniform(c
, contents
, unit
);
484 switch (instr
->sampler_dim
) {
485 case GLSL_SAMPLER_DIM_1D
:
486 case GLSL_SAMPLER_DIM_2D
:
487 case GLSL_SAMPLER_DIM_MS
:
488 case GLSL_SAMPLER_DIM_3D
:
489 case GLSL_SAMPLER_DIM_CUBE
:
490 /* Don't minify the array size. */
491 if (!(instr
->is_array
&& i
== dest_size
- 1)) {
492 size
= ntq_minify(c
, size
, lod
);
496 case GLSL_SAMPLER_DIM_RECT
:
497 /* There's no LOD field for rects */
501 unreachable("Bad sampler type");
504 ntq_store_dest(c
, &instr
->dest
, i
, size
);
509 ntq_emit_tex(struct v3d_compile
*c
, nir_tex_instr
*instr
)
511 unsigned unit
= instr
->texture_index
;
513 /* Since each texture sampling op requires uploading uniforms to
514 * reference the texture, there's no HW support for texture size and
515 * you just upload uniforms containing the size.
518 case nir_texop_query_levels
:
519 ntq_store_dest(c
, &instr
->dest
, 0,
520 vir_uniform(c
, QUNIFORM_TEXTURE_LEVELS
, unit
));
523 ntq_emit_txs(c
, instr
);
529 if (c
->devinfo
->ver
>= 40)
530 v3d40_vir_emit_tex(c
, instr
);
532 v3d33_vir_emit_tex(c
, instr
);
536 ntq_fsincos(struct v3d_compile
*c
, struct qreg src
, bool is_cos
)
538 struct qreg input
= vir_FMUL(c
, src
, vir_uniform_f(c
, 1.0f
/ M_PI
));
540 input
= vir_FADD(c
, input
, vir_uniform_f(c
, 0.5));
542 struct qreg periods
= vir_FROUND(c
, input
);
543 struct qreg sin_output
= vir_SIN(c
, vir_FSUB(c
, input
, periods
));
544 return vir_XOR(c
, sin_output
, vir_SHL(c
,
545 vir_FTOIN(c
, periods
),
546 vir_uniform_ui(c
, -1)));
550 ntq_fsign(struct v3d_compile
*c
, struct qreg src
)
552 struct qreg t
= vir_get_temp(c
);
554 vir_MOV_dest(c
, t
, vir_uniform_f(c
, 0.0));
555 vir_set_pf(vir_FMOV_dest(c
, vir_nop_reg(), src
), V3D_QPU_PF_PUSHZ
);
556 vir_MOV_cond(c
, V3D_QPU_COND_IFNA
, t
, vir_uniform_f(c
, 1.0));
557 vir_set_pf(vir_FMOV_dest(c
, vir_nop_reg(), src
), V3D_QPU_PF_PUSHN
);
558 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, t
, vir_uniform_f(c
, -1.0));
559 return vir_MOV(c
, t
);
563 emit_fragcoord_input(struct v3d_compile
*c
, int attr
)
565 c
->inputs
[attr
* 4 + 0] = vir_FXCD(c
);
566 c
->inputs
[attr
* 4 + 1] = vir_FYCD(c
);
567 c
->inputs
[attr
* 4 + 2] = c
->payload_z
;
568 c
->inputs
[attr
* 4 + 3] = vir_RECIP(c
, c
->payload_w
);
572 emit_fragment_varying(struct v3d_compile
*c
, nir_variable
*var
,
573 uint8_t swizzle
, int array_index
)
575 struct qreg r3
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_R3
);
576 struct qreg r5
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_R5
);
579 if (c
->devinfo
->ver
>= 41) {
580 struct qinst
*ldvary
= vir_add_inst(V3D_QPU_A_NOP
, c
->undef
,
582 ldvary
->qpu
.sig
.ldvary
= true;
583 vary
= vir_emit_def(c
, ldvary
);
585 vir_NOP(c
)->qpu
.sig
.ldvary
= true;
589 /* For gl_PointCoord input or distance along a line, we'll be called
590 * with no nir_variable, and we don't count toward VPM size so we
591 * don't track an input slot.
594 return vir_FADD(c
, vir_FMUL(c
, vary
, c
->payload_w
), r5
);
597 int i
= c
->num_inputs
++;
599 v3d_slot_from_slot_and_component(var
->data
.location
+
600 array_index
, swizzle
);
602 switch (var
->data
.interpolation
) {
603 case INTERP_MODE_NONE
:
604 /* If a gl_FrontColor or gl_BackColor input has no interp
605 * qualifier, then if we're using glShadeModel(GL_FLAT) it
606 * needs to be flat shaded.
608 switch (var
->data
.location
+ array_index
) {
609 case VARYING_SLOT_COL0
:
610 case VARYING_SLOT_COL1
:
611 case VARYING_SLOT_BFC0
:
612 case VARYING_SLOT_BFC1
:
613 if (c
->fs_key
->shade_model_flat
) {
614 BITSET_SET(c
->flat_shade_flags
, i
);
615 vir_MOV_dest(c
, c
->undef
, vary
);
616 return vir_MOV(c
, r5
);
618 return vir_FADD(c
, vir_FMUL(c
, vary
,
625 case INTERP_MODE_SMOOTH
:
626 if (var
->data
.centroid
) {
627 BITSET_SET(c
->centroid_flags
, i
);
628 return vir_FADD(c
, vir_FMUL(c
, vary
,
629 c
->payload_w_centroid
), r5
);
631 return vir_FADD(c
, vir_FMUL(c
, vary
, c
->payload_w
), r5
);
633 case INTERP_MODE_NOPERSPECTIVE
:
634 BITSET_SET(c
->noperspective_flags
, i
);
635 return vir_FADD(c
, vir_MOV(c
, vary
), r5
);
636 case INTERP_MODE_FLAT
:
637 BITSET_SET(c
->flat_shade_flags
, i
);
638 vir_MOV_dest(c
, c
->undef
, vary
);
639 return vir_MOV(c
, r5
);
641 unreachable("Bad interp mode");
646 emit_fragment_input(struct v3d_compile
*c
, int attr
, nir_variable
*var
,
649 for (int i
= 0; i
< glsl_get_vector_elements(var
->type
); i
++) {
650 int chan
= var
->data
.location_frac
+ i
;
651 c
->inputs
[attr
* 4 + chan
] =
652 emit_fragment_varying(c
, var
, chan
, array_index
);
657 add_output(struct v3d_compile
*c
,
658 uint32_t decl_offset
,
662 uint32_t old_array_size
= c
->outputs_array_size
;
663 resize_qreg_array(c
, &c
->outputs
, &c
->outputs_array_size
,
666 if (old_array_size
!= c
->outputs_array_size
) {
667 c
->output_slots
= reralloc(c
,
669 struct v3d_varying_slot
,
670 c
->outputs_array_size
);
673 c
->output_slots
[decl_offset
] =
674 v3d_slot_from_slot_and_component(slot
, swizzle
);
678 * If compare_instr is a valid comparison instruction, emits the
679 * compare_instr's comparison and returns the sel_instr's return value based
680 * on the compare_instr's result.
683 ntq_emit_comparison(struct v3d_compile
*c
,
684 nir_alu_instr
*compare_instr
,
685 enum v3d_qpu_cond
*out_cond
)
687 struct qreg src0
= ntq_get_alu_src(c
, compare_instr
, 0);
689 if (nir_op_infos
[compare_instr
->op
].num_inputs
> 1)
690 src1
= ntq_get_alu_src(c
, compare_instr
, 1);
691 bool cond_invert
= false;
692 struct qreg nop
= vir_nop_reg();
694 switch (compare_instr
->op
) {
697 vir_set_pf(vir_FCMP_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
700 vir_set_pf(vir_XOR_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
705 vir_set_pf(vir_FCMP_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
709 vir_set_pf(vir_XOR_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
715 vir_set_pf(vir_FCMP_dest(c
, nop
, src1
, src0
), V3D_QPU_PF_PUSHC
);
718 vir_set_pf(vir_MIN_dest(c
, nop
, src1
, src0
), V3D_QPU_PF_PUSHC
);
722 vir_set_pf(vir_SUB_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHC
);
728 vir_set_pf(vir_FCMP_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHN
);
731 vir_set_pf(vir_MIN_dest(c
, nop
, src1
, src0
), V3D_QPU_PF_PUSHC
);
734 vir_set_pf(vir_SUB_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHC
);
738 vir_set_pf(vir_MOV_dest(c
, nop
, src0
), V3D_QPU_PF_PUSHZ
);
743 vir_set_pf(vir_FMOV_dest(c
, nop
, src0
), V3D_QPU_PF_PUSHZ
);
751 *out_cond
= cond_invert
? V3D_QPU_COND_IFNA
: V3D_QPU_COND_IFA
;
756 /* Finds an ALU instruction that generates our src value that could
757 * (potentially) be greedily emitted in the consuming instruction.
759 static struct nir_alu_instr
*
760 ntq_get_alu_parent(nir_src src
)
762 if (!src
.is_ssa
|| src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
764 nir_alu_instr
*instr
= nir_instr_as_alu(src
.ssa
->parent_instr
);
768 /* If the ALU instr's srcs are non-SSA, then we would have to avoid
769 * moving emission of the ALU instr down past another write of the
772 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
773 if (!instr
->src
[i
].src
.is_ssa
)
780 /* Turns a NIR bool into a condition code to predicate on. */
781 static enum v3d_qpu_cond
782 ntq_emit_bool_to_cond(struct v3d_compile
*c
, nir_src src
)
784 nir_alu_instr
*compare
= ntq_get_alu_parent(src
);
788 enum v3d_qpu_cond cond
;
789 if (ntq_emit_comparison(c
, compare
, &cond
))
793 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), ntq_get_src(c
, src
, 0)),
795 return V3D_QPU_COND_IFNA
;
799 ntq_emit_alu(struct v3d_compile
*c
, nir_alu_instr
*instr
)
801 /* This should always be lowered to ALU operations for V3D. */
802 assert(!instr
->dest
.saturate
);
804 /* Vectors are special in that they have non-scalarized writemasks,
805 * and just take the first swizzle channel for each argument in order
806 * into each writemask channel.
808 if (instr
->op
== nir_op_vec2
||
809 instr
->op
== nir_op_vec3
||
810 instr
->op
== nir_op_vec4
) {
812 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
813 srcs
[i
] = ntq_get_src(c
, instr
->src
[i
].src
,
814 instr
->src
[i
].swizzle
[0]);
815 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
816 ntq_store_dest(c
, &instr
->dest
.dest
, i
,
817 vir_MOV(c
, srcs
[i
]));
821 /* General case: We can just grab the one used channel per src. */
822 struct qreg src
[nir_op_infos
[instr
->op
].num_inputs
];
823 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
824 src
[i
] = ntq_get_alu_src(c
, instr
, i
);
832 result
= vir_MOV(c
, src
[0]);
836 result
= vir_XOR(c
, src
[0], vir_uniform_ui(c
, 1 << 31));
839 result
= vir_NEG(c
, src
[0]);
843 result
= vir_FMUL(c
, src
[0], src
[1]);
846 result
= vir_FADD(c
, src
[0], src
[1]);
849 result
= vir_FSUB(c
, src
[0], src
[1]);
852 result
= vir_FMIN(c
, src
[0], src
[1]);
855 result
= vir_FMAX(c
, src
[0], src
[1]);
859 nir_alu_instr
*src0_alu
= ntq_get_alu_parent(instr
->src
[0].src
);
860 if (src0_alu
&& src0_alu
->op
== nir_op_fround_even
) {
861 result
= vir_FTOIN(c
, ntq_get_alu_src(c
, src0_alu
, 0));
863 result
= vir_FTOIZ(c
, src
[0]);
869 result
= vir_FTOUZ(c
, src
[0]);
872 result
= vir_ITOF(c
, src
[0]);
875 result
= vir_UTOF(c
, src
[0]);
878 result
= vir_AND(c
, src
[0], vir_uniform_f(c
, 1.0));
881 result
= vir_AND(c
, src
[0], vir_uniform_ui(c
, 1));
885 result
= vir_ADD(c
, src
[0], src
[1]);
888 result
= vir_SHR(c
, src
[0], src
[1]);
891 result
= vir_SUB(c
, src
[0], src
[1]);
894 result
= vir_ASR(c
, src
[0], src
[1]);
897 result
= vir_SHL(c
, src
[0], src
[1]);
900 result
= vir_MIN(c
, src
[0], src
[1]);
903 result
= vir_UMIN(c
, src
[0], src
[1]);
906 result
= vir_MAX(c
, src
[0], src
[1]);
909 result
= vir_UMAX(c
, src
[0], src
[1]);
912 result
= vir_AND(c
, src
[0], src
[1]);
915 result
= vir_OR(c
, src
[0], src
[1]);
918 result
= vir_XOR(c
, src
[0], src
[1]);
921 result
= vir_NOT(c
, src
[0]);
924 case nir_op_ufind_msb
:
925 result
= vir_SUB(c
, vir_uniform_ui(c
, 31), vir_CLZ(c
, src
[0]));
929 result
= vir_UMUL(c
, src
[0], src
[1]);
936 enum v3d_qpu_cond cond
;
937 MAYBE_UNUSED
bool ok
= ntq_emit_comparison(c
, instr
, &cond
);
939 result
= vir_MOV(c
, vir_SEL(c
, cond
,
940 vir_uniform_f(c
, 1.0),
941 vir_uniform_f(c
, 0.0)));
957 enum v3d_qpu_cond cond
;
958 MAYBE_UNUSED
bool ok
= ntq_emit_comparison(c
, instr
, &cond
);
960 result
= vir_MOV(c
, vir_SEL(c
, cond
,
961 vir_uniform_ui(c
, ~0),
962 vir_uniform_ui(c
, 0)));
969 ntq_emit_bool_to_cond(c
, instr
->src
[0].src
),
974 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), src
[0]),
976 result
= vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFNA
,
981 result
= vir_RECIP(c
, src
[0]);
984 result
= vir_RSQRT(c
, src
[0]);
987 result
= vir_EXP(c
, src
[0]);
990 result
= vir_LOG(c
, src
[0]);
994 result
= vir_FCEIL(c
, src
[0]);
997 result
= vir_FFLOOR(c
, src
[0]);
999 case nir_op_fround_even
:
1000 result
= vir_FROUND(c
, src
[0]);
1003 result
= vir_FTRUNC(c
, src
[0]);
1007 result
= ntq_fsincos(c
, src
[0], false);
1010 result
= ntq_fsincos(c
, src
[0], true);
1014 result
= ntq_fsign(c
, src
[0]);
1018 result
= vir_FMOV(c
, src
[0]);
1019 vir_set_unpack(c
->defs
[result
.index
], 0, V3D_QPU_UNPACK_ABS
);
1024 result
= vir_MAX(c
, src
[0], vir_NEG(c
, src
[0]));
1028 case nir_op_fddx_coarse
:
1029 case nir_op_fddx_fine
:
1030 result
= vir_FDX(c
, src
[0]);
1034 case nir_op_fddy_coarse
:
1035 case nir_op_fddy_fine
:
1036 result
= vir_FDY(c
, src
[0]);
1039 case nir_op_uadd_carry
:
1040 vir_set_pf(vir_ADD_dest(c
, vir_nop_reg(), src
[0], src
[1]),
1042 result
= vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFA
,
1043 vir_uniform_ui(c
, ~0),
1044 vir_uniform_ui(c
, 0)));
1047 case nir_op_pack_half_2x16_split
:
1048 result
= vir_VFPACK(c
, src
[0], src
[1]);
1051 case nir_op_unpack_half_2x16_split_x
:
1052 result
= vir_FMOV(c
, src
[0]);
1053 vir_set_unpack(c
->defs
[result
.index
], 0, V3D_QPU_UNPACK_L
);
1056 case nir_op_unpack_half_2x16_split_y
:
1057 result
= vir_FMOV(c
, src
[0]);
1058 vir_set_unpack(c
->defs
[result
.index
], 0, V3D_QPU_UNPACK_H
);
1062 fprintf(stderr
, "unknown NIR ALU inst: ");
1063 nir_print_instr(&instr
->instr
, stderr
);
1064 fprintf(stderr
, "\n");
1068 /* We have a scalar result, so the instruction should only have a
1069 * single channel written to.
1071 assert(util_is_power_of_two_or_zero(instr
->dest
.write_mask
));
1072 ntq_store_dest(c
, &instr
->dest
.dest
,
1073 ffs(instr
->dest
.write_mask
) - 1, result
);
1076 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
1077 * specifier. They come from a register that's preloaded with 0xffffffff
1078 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
1079 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
1081 #define TLB_TYPE_F16_COLOR (3 << 6)
1082 #define TLB_TYPE_I32_COLOR (1 << 6)
1083 #define TLB_TYPE_F32_COLOR (0 << 6)
1084 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
1085 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
1086 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
1087 #define TLB_F16_SWAP_HI_LO (1 << 1)
1088 #define TLB_VEC_SIZE_4_F16 (1 << 0)
1089 #define TLB_VEC_SIZE_2_F16 (0 << 0)
1090 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
1092 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
1095 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
1096 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
1097 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
1098 #define TLB_V42_DEPTH_TYPE_INVARIANT (0 << 3) /* Unmodified sideband input used */
1099 #define TLB_V42_DEPTH_TYPE_PER_PIXEL (1 << 3) /* QPU result used */
1101 /* Stencil is a single 32-bit write. */
1102 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1105 emit_frag_end(struct v3d_compile
*c
)
1108 if (c->output_sample_mask_index != -1) {
1109 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1113 bool has_any_tlb_color_write
= false;
1114 for (int rt
= 0; rt
< V3D_MAX_DRAW_BUFFERS
; rt
++) {
1115 if (c
->fs_key
->cbufs
& (1 << rt
) && c
->output_color_var
[rt
])
1116 has_any_tlb_color_write
= true;
1119 if (c
->fs_key
->sample_alpha_to_coverage
&& c
->output_color_var
[0]) {
1120 struct nir_variable
*var
= c
->output_color_var
[0];
1121 struct qreg
*color
= &c
->outputs
[var
->data
.driver_location
* 4];
1123 vir_SETMSF_dest(c
, vir_nop_reg(),
1126 vir_FTOC(c
, color
[3])));
1129 struct qreg tlb_reg
= vir_magic_reg(V3D_QPU_WADDR_TLB
);
1130 struct qreg tlbu_reg
= vir_magic_reg(V3D_QPU_WADDR_TLBU
);
1131 if (c
->output_position_index
!= -1) {
1132 struct qinst
*inst
= vir_MOV_dest(c
, tlbu_reg
,
1133 c
->outputs
[c
->output_position_index
]);
1134 uint8_t tlb_specifier
= TLB_TYPE_DEPTH
;
1136 if (c
->devinfo
->ver
>= 42) {
1137 tlb_specifier
|= (TLB_V42_DEPTH_TYPE_PER_PIXEL
|
1138 TLB_SAMPLE_MODE_PER_PIXEL
);
1140 tlb_specifier
|= TLB_DEPTH_TYPE_PER_PIXEL
;
1142 inst
->uniform
= vir_get_uniform_index(c
, QUNIFORM_CONSTANT
,
1146 } else if (c
->s
->info
.fs
.uses_discard
||
1147 !c
->s
->info
.fs
.early_fragment_tests
||
1148 c
->fs_key
->sample_alpha_to_coverage
||
1149 !has_any_tlb_color_write
) {
1150 /* Emit passthrough Z if it needed to be delayed until shader
1151 * end due to potential discards.
1153 * Since (single-threaded) fragment shaders always need a TLB
1154 * write, emit passthrouh Z if we didn't have any color
1155 * buffers and flag us as potentially discarding, so that we
1156 * can use Z as the TLB write.
1158 c
->s
->info
.fs
.uses_discard
= true;
1160 struct qinst
*inst
= vir_MOV_dest(c
, tlbu_reg
,
1162 uint8_t tlb_specifier
= TLB_TYPE_DEPTH
;
1164 if (c
->devinfo
->ver
>= 42) {
1165 /* The spec says the PER_PIXEL flag is ignored for
1166 * invariant writes, but the simulator demands it.
1168 tlb_specifier
|= (TLB_V42_DEPTH_TYPE_INVARIANT
|
1169 TLB_SAMPLE_MODE_PER_PIXEL
);
1171 tlb_specifier
|= TLB_DEPTH_TYPE_INVARIANT
;
1174 inst
->uniform
= vir_get_uniform_index(c
,
1181 /* XXX: Performance improvement: Merge Z write and color writes TLB
1185 for (int rt
= 0; rt
< V3D_MAX_DRAW_BUFFERS
; rt
++) {
1186 if (!(c
->fs_key
->cbufs
& (1 << rt
)) || !c
->output_color_var
[rt
])
1189 nir_variable
*var
= c
->output_color_var
[rt
];
1190 struct qreg
*color
= &c
->outputs
[var
->data
.driver_location
* 4];
1191 int num_components
= glsl_get_vector_elements(var
->type
);
1192 uint32_t conf
= 0xffffff00;
1195 conf
|= TLB_SAMPLE_MODE_PER_PIXEL
;
1196 conf
|= (7 - rt
) << TLB_RENDER_TARGET_SHIFT
;
1198 if (c
->fs_key
->swap_color_rb
& (1 << rt
))
1199 num_components
= MAX2(num_components
, 3);
1201 assert(num_components
!= 0);
1202 switch (glsl_get_base_type(var
->type
)) {
1203 case GLSL_TYPE_UINT
:
1205 /* The F32 vs I32 distinction was dropped in 4.2. */
1206 if (c
->devinfo
->ver
< 42)
1207 conf
|= TLB_TYPE_I32_COLOR
;
1209 conf
|= TLB_TYPE_F32_COLOR
;
1210 conf
|= ((num_components
- 1) <<
1211 TLB_VEC_SIZE_MINUS_1_SHIFT
);
1213 inst
= vir_MOV_dest(c
, tlbu_reg
, color
[0]);
1214 inst
->uniform
= vir_get_uniform_index(c
,
1218 for (int i
= 1; i
< num_components
; i
++) {
1219 inst
= vir_MOV_dest(c
, tlb_reg
, color
[i
]);
1224 struct qreg r
= color
[0];
1225 struct qreg g
= color
[1];
1226 struct qreg b
= color
[2];
1227 struct qreg a
= color
[3];
1229 if (c
->fs_key
->f32_color_rb
& (1 << rt
)) {
1230 conf
|= TLB_TYPE_F32_COLOR
;
1231 conf
|= ((num_components
- 1) <<
1232 TLB_VEC_SIZE_MINUS_1_SHIFT
);
1234 conf
|= TLB_TYPE_F16_COLOR
;
1235 conf
|= TLB_F16_SWAP_HI_LO
;
1236 if (num_components
>= 3)
1237 conf
|= TLB_VEC_SIZE_4_F16
;
1239 conf
|= TLB_VEC_SIZE_2_F16
;
1242 if (c
->fs_key
->swap_color_rb
& (1 << rt
)) {
1247 if (c
->fs_key
->sample_alpha_to_one
)
1248 a
= vir_uniform_f(c
, 1.0);
1250 if (c
->fs_key
->f32_color_rb
& (1 << rt
)) {
1251 inst
= vir_MOV_dest(c
, tlbu_reg
, r
);
1252 inst
->uniform
= vir_get_uniform_index(c
,
1256 if (num_components
>= 2)
1257 vir_MOV_dest(c
, tlb_reg
, g
);
1258 if (num_components
>= 3)
1259 vir_MOV_dest(c
, tlb_reg
, b
);
1260 if (num_components
>= 4)
1261 vir_MOV_dest(c
, tlb_reg
, a
);
1263 inst
= vir_VFPACK_dest(c
, tlb_reg
, r
, g
);
1265 inst
->dst
= tlbu_reg
;
1266 inst
->uniform
= vir_get_uniform_index(c
,
1271 if (num_components
>= 3)
1272 inst
= vir_VFPACK_dest(c
, tlb_reg
, b
, a
);
1281 vir_VPM_WRITE(struct v3d_compile
*c
, struct qreg val
, uint32_t vpm_index
)
1283 if (c
->devinfo
->ver
>= 40) {
1284 vir_STVPMV(c
, vir_uniform_ui(c
, vpm_index
), val
);
1286 /* XXX: v3d33_vir_vpm_write_setup(c); */
1287 vir_MOV_dest(c
, vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_VPM
), val
);
1292 emit_vert_end(struct v3d_compile
*c
)
1294 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1296 if (c
->devinfo
->ver
>= 40 && c
->devinfo
->ver
<= 42)
1301 v3d_optimize_nir(struct nir_shader
*s
)
1304 unsigned lower_flrp
=
1305 (s
->options
->lower_flrp16
? 16 : 0) |
1306 (s
->options
->lower_flrp32
? 32 : 0) |
1307 (s
->options
->lower_flrp64
? 64 : 0);
1312 NIR_PASS_V(s
, nir_lower_vars_to_ssa
);
1313 NIR_PASS(progress
, s
, nir_lower_alu_to_scalar
);
1314 NIR_PASS(progress
, s
, nir_lower_phis_to_scalar
);
1315 NIR_PASS(progress
, s
, nir_copy_prop
);
1316 NIR_PASS(progress
, s
, nir_opt_remove_phis
);
1317 NIR_PASS(progress
, s
, nir_opt_dce
);
1318 NIR_PASS(progress
, s
, nir_opt_dead_cf
);
1319 NIR_PASS(progress
, s
, nir_opt_cse
);
1320 NIR_PASS(progress
, s
, nir_opt_peephole_select
, 8, true, true);
1321 NIR_PASS(progress
, s
, nir_opt_algebraic
);
1322 NIR_PASS(progress
, s
, nir_opt_constant_folding
);
1324 if (lower_flrp
!= 0) {
1325 bool lower_flrp_progress
;
1327 NIR_PASS(lower_flrp_progress
, s
, nir_lower_flrp
,
1329 false /* always_precise */,
1330 s
->options
->lower_ffma
);
1331 if (lower_flrp_progress
) {
1332 NIR_PASS(progress
, s
, nir_opt_constant_folding
);
1336 /* Nothing should rematerialize any flrps, so we only
1337 * need to do this lowering once.
1342 NIR_PASS(progress
, s
, nir_opt_undef
);
1345 NIR_PASS(progress
, s
, nir_opt_move_load_ubo
);
1349 driver_location_compare(const void *in_a
, const void *in_b
)
1351 const nir_variable
*const *a
= in_a
;
1352 const nir_variable
*const *b
= in_b
;
1354 return (*a
)->data
.driver_location
- (*b
)->data
.driver_location
;
1358 ntq_emit_vpm_read(struct v3d_compile
*c
,
1359 uint32_t *num_components_queued
,
1360 uint32_t *remaining
,
1363 struct qreg vpm
= vir_reg(QFILE_VPM
, vpm_index
);
1365 if (c
->devinfo
->ver
>= 40 ) {
1366 return vir_LDVPMV_IN(c
,
1368 (*num_components_queued
)++));
1371 if (*num_components_queued
!= 0) {
1372 (*num_components_queued
)--;
1373 return vir_MOV(c
, vpm
);
1376 uint32_t num_components
= MIN2(*remaining
, 32);
1378 v3d33_vir_vpm_read_setup(c
, num_components
);
1380 *num_components_queued
= num_components
- 1;
1381 *remaining
-= num_components
;
1383 return vir_MOV(c
, vpm
);
1387 ntq_setup_vpm_inputs(struct v3d_compile
*c
)
1389 /* Figure out how many components of each vertex attribute the shader
1390 * uses. Each variable should have been split to individual
1391 * components and unused ones DCEed. The vertex fetcher will load
1392 * from the start of the attribute to the number of components we
1393 * declare we need in c->vattr_sizes[].
1395 nir_foreach_variable(var
, &c
->s
->inputs
) {
1396 /* No VS attribute array support. */
1397 assert(MAX2(glsl_get_length(var
->type
), 1) == 1);
1399 unsigned loc
= var
->data
.driver_location
;
1400 int start_component
= var
->data
.location_frac
;
1401 int num_components
= glsl_get_components(var
->type
);
1403 c
->vattr_sizes
[loc
] = MAX2(c
->vattr_sizes
[loc
],
1404 start_component
+ num_components
);
1407 unsigned num_components
= 0;
1408 uint32_t vpm_components_queued
= 0;
1409 bool uses_iid
= c
->s
->info
.system_values_read
&
1410 (1ull << SYSTEM_VALUE_INSTANCE_ID
);
1411 bool uses_vid
= c
->s
->info
.system_values_read
&
1412 (1ull << SYSTEM_VALUE_VERTEX_ID
);
1413 num_components
+= uses_iid
;
1414 num_components
+= uses_vid
;
1416 for (int i
= 0; i
< ARRAY_SIZE(c
->vattr_sizes
); i
++)
1417 num_components
+= c
->vattr_sizes
[i
];
1420 c
->iid
= ntq_emit_vpm_read(c
, &vpm_components_queued
,
1421 &num_components
, ~0);
1425 c
->vid
= ntq_emit_vpm_read(c
, &vpm_components_queued
,
1426 &num_components
, ~0);
1429 /* The actual loads will happen directly in nir_intrinsic_load_input
1430 * on newer versions.
1432 if (c
->devinfo
->ver
>= 40)
1435 for (int loc
= 0; loc
< ARRAY_SIZE(c
->vattr_sizes
); loc
++) {
1436 resize_qreg_array(c
, &c
->inputs
, &c
->inputs_array_size
,
1439 for (int i
= 0; i
< c
->vattr_sizes
[loc
]; i
++) {
1440 c
->inputs
[loc
* 4 + i
] =
1441 ntq_emit_vpm_read(c
,
1442 &vpm_components_queued
,
1449 if (c
->devinfo
->ver
>= 40) {
1450 assert(vpm_components_queued
== num_components
);
1452 assert(vpm_components_queued
== 0);
1453 assert(num_components
== 0);
1458 ntq_setup_fs_inputs(struct v3d_compile
*c
)
1460 unsigned num_entries
= 0;
1461 unsigned num_components
= 0;
1462 nir_foreach_variable(var
, &c
->s
->inputs
) {
1464 num_components
+= glsl_get_components(var
->type
);
1467 nir_variable
*vars
[num_entries
];
1470 nir_foreach_variable(var
, &c
->s
->inputs
)
1473 /* Sort the variables so that we emit the input setup in
1474 * driver_location order. This is required for VPM reads, whose data
1475 * is fetched into the VPM in driver_location (TGSI register index)
1478 qsort(&vars
, num_entries
, sizeof(*vars
), driver_location_compare
);
1480 for (unsigned i
= 0; i
< num_entries
; i
++) {
1481 nir_variable
*var
= vars
[i
];
1482 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1483 unsigned loc
= var
->data
.driver_location
;
1485 resize_qreg_array(c
, &c
->inputs
, &c
->inputs_array_size
,
1486 (loc
+ array_len
) * 4);
1488 if (var
->data
.location
== VARYING_SLOT_POS
) {
1489 emit_fragcoord_input(c
, loc
);
1490 } else if (var
->data
.location
== VARYING_SLOT_PNTC
||
1491 (var
->data
.location
>= VARYING_SLOT_VAR0
&&
1492 (c
->fs_key
->point_sprite_mask
&
1493 (1 << (var
->data
.location
-
1494 VARYING_SLOT_VAR0
))))) {
1495 c
->inputs
[loc
* 4 + 0] = c
->point_x
;
1496 c
->inputs
[loc
* 4 + 1] = c
->point_y
;
1498 for (int j
= 0; j
< array_len
; j
++)
1499 emit_fragment_input(c
, loc
+ j
, var
, j
);
1505 ntq_setup_outputs(struct v3d_compile
*c
)
1507 if (c
->s
->info
.stage
!= MESA_SHADER_FRAGMENT
)
1510 nir_foreach_variable(var
, &c
->s
->outputs
) {
1511 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1512 unsigned loc
= var
->data
.driver_location
* 4;
1514 assert(array_len
== 1);
1517 for (int i
= 0; i
< 4 - var
->data
.location_frac
; i
++) {
1518 add_output(c
, loc
+ var
->data
.location_frac
+ i
,
1520 var
->data
.location_frac
+ i
);
1523 switch (var
->data
.location
) {
1524 case FRAG_RESULT_COLOR
:
1525 c
->output_color_var
[0] = var
;
1526 c
->output_color_var
[1] = var
;
1527 c
->output_color_var
[2] = var
;
1528 c
->output_color_var
[3] = var
;
1530 case FRAG_RESULT_DATA0
:
1531 case FRAG_RESULT_DATA1
:
1532 case FRAG_RESULT_DATA2
:
1533 case FRAG_RESULT_DATA3
:
1534 c
->output_color_var
[var
->data
.location
-
1535 FRAG_RESULT_DATA0
] = var
;
1537 case FRAG_RESULT_DEPTH
:
1538 c
->output_position_index
= loc
;
1540 case FRAG_RESULT_SAMPLE_MASK
:
1541 c
->output_sample_mask_index
= loc
;
1548 * Sets up the mapping from nir_register to struct qreg *.
1550 * Each nir_register gets a struct qreg per 32-bit component being stored.
1553 ntq_setup_registers(struct v3d_compile
*c
, struct exec_list
*list
)
1555 foreach_list_typed(nir_register
, nir_reg
, node
, list
) {
1556 unsigned array_len
= MAX2(nir_reg
->num_array_elems
, 1);
1557 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
1559 nir_reg
->num_components
);
1561 _mesa_hash_table_insert(c
->def_ht
, nir_reg
, qregs
);
1563 for (int i
= 0; i
< array_len
* nir_reg
->num_components
; i
++)
1564 qregs
[i
] = vir_get_temp(c
);
1569 ntq_emit_load_const(struct v3d_compile
*c
, nir_load_const_instr
*instr
)
1571 /* XXX perf: Experiment with using immediate loads to avoid having
1572 * these end up in the uniform stream. Watch out for breaking the
1573 * small immediates optimization in the process!
1575 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1576 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1577 qregs
[i
] = vir_uniform_ui(c
, instr
->value
[i
].u32
);
1579 _mesa_hash_table_insert(c
->def_ht
, &instr
->def
, qregs
);
1583 ntq_emit_ssa_undef(struct v3d_compile
*c
, nir_ssa_undef_instr
*instr
)
1585 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1587 /* VIR needs there to be *some* value, so pick 0 (same as for
1588 * ntq_setup_registers().
1590 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1591 qregs
[i
] = vir_uniform_ui(c
, 0);
1595 ntq_emit_image_size(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
)
1597 assert(instr
->intrinsic
== nir_intrinsic_image_deref_size
);
1598 nir_variable
*var
= nir_intrinsic_get_var(instr
, 0);
1599 unsigned image_index
= var
->data
.driver_location
;
1600 const struct glsl_type
*sampler_type
= glsl_without_array(var
->type
);
1601 bool is_array
= glsl_sampler_type_is_array(sampler_type
);
1603 ntq_store_dest(c
, &instr
->dest
, 0,
1604 vir_uniform(c
, QUNIFORM_IMAGE_WIDTH
, image_index
));
1605 if (instr
->num_components
> 1) {
1606 ntq_store_dest(c
, &instr
->dest
, 1,
1607 vir_uniform(c
, QUNIFORM_IMAGE_HEIGHT
,
1610 if (instr
->num_components
> 2) {
1611 ntq_store_dest(c
, &instr
->dest
, 2,
1614 QUNIFORM_IMAGE_ARRAY_SIZE
:
1615 QUNIFORM_IMAGE_DEPTH
,
1621 ntq_emit_intrinsic(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
)
1625 switch (instr
->intrinsic
) {
1626 case nir_intrinsic_load_uniform
:
1627 if (nir_src_is_const(instr
->src
[0])) {
1628 int offset
= (nir_intrinsic_base(instr
) +
1629 nir_src_as_uint(instr
->src
[0]));
1630 assert(offset
% 4 == 0);
1631 /* We need dwords */
1632 offset
= offset
/ 4;
1633 for (int i
= 0; i
< instr
->num_components
; i
++) {
1634 ntq_store_dest(c
, &instr
->dest
, i
,
1635 vir_uniform(c
, QUNIFORM_UNIFORM
,
1639 ntq_emit_tmu_general(c
, instr
, false);
1643 case nir_intrinsic_load_ubo
:
1644 ntq_emit_tmu_general(c
, instr
, false);
1647 case nir_intrinsic_ssbo_atomic_add
:
1648 case nir_intrinsic_ssbo_atomic_imin
:
1649 case nir_intrinsic_ssbo_atomic_umin
:
1650 case nir_intrinsic_ssbo_atomic_imax
:
1651 case nir_intrinsic_ssbo_atomic_umax
:
1652 case nir_intrinsic_ssbo_atomic_and
:
1653 case nir_intrinsic_ssbo_atomic_or
:
1654 case nir_intrinsic_ssbo_atomic_xor
:
1655 case nir_intrinsic_ssbo_atomic_exchange
:
1656 case nir_intrinsic_ssbo_atomic_comp_swap
:
1657 case nir_intrinsic_load_ssbo
:
1658 case nir_intrinsic_store_ssbo
:
1659 ntq_emit_tmu_general(c
, instr
, false);
1662 case nir_intrinsic_shared_atomic_add
:
1663 case nir_intrinsic_shared_atomic_imin
:
1664 case nir_intrinsic_shared_atomic_umin
:
1665 case nir_intrinsic_shared_atomic_imax
:
1666 case nir_intrinsic_shared_atomic_umax
:
1667 case nir_intrinsic_shared_atomic_and
:
1668 case nir_intrinsic_shared_atomic_or
:
1669 case nir_intrinsic_shared_atomic_xor
:
1670 case nir_intrinsic_shared_atomic_exchange
:
1671 case nir_intrinsic_shared_atomic_comp_swap
:
1672 case nir_intrinsic_load_shared
:
1673 case nir_intrinsic_store_shared
:
1674 case nir_intrinsic_load_scratch
:
1675 case nir_intrinsic_store_scratch
:
1676 ntq_emit_tmu_general(c
, instr
, true);
1679 case nir_intrinsic_image_deref_load
:
1680 case nir_intrinsic_image_deref_store
:
1681 case nir_intrinsic_image_deref_atomic_add
:
1682 case nir_intrinsic_image_deref_atomic_min
:
1683 case nir_intrinsic_image_deref_atomic_max
:
1684 case nir_intrinsic_image_deref_atomic_and
:
1685 case nir_intrinsic_image_deref_atomic_or
:
1686 case nir_intrinsic_image_deref_atomic_xor
:
1687 case nir_intrinsic_image_deref_atomic_exchange
:
1688 case nir_intrinsic_image_deref_atomic_comp_swap
:
1689 v3d40_vir_emit_image_load_store(c
, instr
);
1692 case nir_intrinsic_get_buffer_size
:
1693 ntq_store_dest(c
, &instr
->dest
, 0,
1694 vir_uniform(c
, QUNIFORM_GET_BUFFER_SIZE
,
1695 nir_src_as_uint(instr
->src
[0])));
1698 case nir_intrinsic_load_user_clip_plane
:
1699 for (int i
= 0; i
< instr
->num_components
; i
++) {
1700 ntq_store_dest(c
, &instr
->dest
, i
,
1701 vir_uniform(c
, QUNIFORM_USER_CLIP_PLANE
,
1702 nir_intrinsic_ucp_id(instr
) *
1707 case nir_intrinsic_load_viewport_x_scale
:
1708 ntq_store_dest(c
, &instr
->dest
, 0,
1709 vir_uniform(c
, QUNIFORM_VIEWPORT_X_SCALE
, 0));
1712 case nir_intrinsic_load_viewport_y_scale
:
1713 ntq_store_dest(c
, &instr
->dest
, 0,
1714 vir_uniform(c
, QUNIFORM_VIEWPORT_Y_SCALE
, 0));
1717 case nir_intrinsic_load_viewport_z_scale
:
1718 ntq_store_dest(c
, &instr
->dest
, 0,
1719 vir_uniform(c
, QUNIFORM_VIEWPORT_Z_SCALE
, 0));
1722 case nir_intrinsic_load_viewport_z_offset
:
1723 ntq_store_dest(c
, &instr
->dest
, 0,
1724 vir_uniform(c
, QUNIFORM_VIEWPORT_Z_OFFSET
, 0));
1727 case nir_intrinsic_load_alpha_ref_float
:
1728 ntq_store_dest(c
, &instr
->dest
, 0,
1729 vir_uniform(c
, QUNIFORM_ALPHA_REF
, 0));
1732 case nir_intrinsic_load_sample_mask_in
:
1733 ntq_store_dest(c
, &instr
->dest
, 0, vir_MSF(c
));
1736 case nir_intrinsic_load_helper_invocation
:
1737 vir_set_pf(vir_MSF_dest(c
, vir_nop_reg()), V3D_QPU_PF_PUSHZ
);
1738 ntq_store_dest(c
, &instr
->dest
, 0,
1739 vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFA
,
1740 vir_uniform_ui(c
, ~0),
1741 vir_uniform_ui(c
, 0))));
1744 case nir_intrinsic_load_front_face
:
1745 /* The register contains 0 (front) or 1 (back), and we need to
1746 * turn it into a NIR bool where true means front.
1748 ntq_store_dest(c
, &instr
->dest
, 0,
1750 vir_uniform_ui(c
, -1),
1754 case nir_intrinsic_load_instance_id
:
1755 ntq_store_dest(c
, &instr
->dest
, 0, vir_MOV(c
, c
->iid
));
1758 case nir_intrinsic_load_vertex_id
:
1759 ntq_store_dest(c
, &instr
->dest
, 0, vir_MOV(c
, c
->vid
));
1762 case nir_intrinsic_load_input
:
1763 /* Use ldvpmv (uniform offset) or ldvpmd (non-uniform offset)
1764 * and enable PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR.
1766 offset
= (nir_intrinsic_base(instr
) +
1767 nir_src_as_uint(instr
->src
[0]));
1768 if (c
->s
->info
.stage
!= MESA_SHADER_FRAGMENT
&&
1769 c
->devinfo
->ver
>= 40) {
1770 /* Emit the LDVPM directly now, rather than at the top
1771 * of the shader like we did for V3D 3.x (which needs
1772 * vpmsetup when not just taking the next offset).
1774 * Note that delaying like this may introduce stalls,
1775 * as LDVPMV takes a minimum of 1 instruction but may
1776 * be slower if the VPM unit is busy with another QPU.
1779 if (c
->s
->info
.system_values_read
&
1780 (1ull << SYSTEM_VALUE_INSTANCE_ID
)) {
1783 if (c
->s
->info
.system_values_read
&
1784 (1ull << SYSTEM_VALUE_VERTEX_ID
)) {
1787 for (int i
= 0; i
< offset
; i
++)
1788 index
+= c
->vattr_sizes
[i
];
1789 index
+= nir_intrinsic_component(instr
);
1790 for (int i
= 0; i
< instr
->num_components
; i
++) {
1791 struct qreg vpm_offset
=
1792 vir_uniform_ui(c
, index
++);
1793 ntq_store_dest(c
, &instr
->dest
, i
,
1794 vir_LDVPMV_IN(c
, vpm_offset
));
1797 for (int i
= 0; i
< instr
->num_components
; i
++) {
1798 int comp
= nir_intrinsic_component(instr
) + i
;
1799 ntq_store_dest(c
, &instr
->dest
, i
,
1800 vir_MOV(c
, c
->inputs
[offset
* 4 +
1806 case nir_intrinsic_store_output
:
1807 /* XXX perf: Use stvpmv with uniform non-constant offsets and
1808 * stvpmd with non-uniform offsets and enable
1809 * PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR.
1811 if (c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
) {
1812 offset
= ((nir_intrinsic_base(instr
) +
1813 nir_src_as_uint(instr
->src
[1])) * 4 +
1814 nir_intrinsic_component(instr
));
1815 for (int i
= 0; i
< instr
->num_components
; i
++) {
1816 c
->outputs
[offset
+ i
] =
1822 assert(instr
->num_components
== 1);
1825 ntq_get_src(c
, instr
->src
[0], 0),
1826 nir_intrinsic_base(instr
));
1830 case nir_intrinsic_image_deref_size
:
1831 ntq_emit_image_size(c
, instr
);
1834 case nir_intrinsic_discard
:
1835 if (vir_in_nonuniform_control_flow(c
)) {
1836 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
),
1838 vir_set_cond(vir_SETMSF_dest(c
, vir_nop_reg(),
1839 vir_uniform_ui(c
, 0)),
1842 vir_SETMSF_dest(c
, vir_nop_reg(),
1843 vir_uniform_ui(c
, 0));
1847 case nir_intrinsic_discard_if
: {
1848 enum v3d_qpu_cond cond
= ntq_emit_bool_to_cond(c
, instr
->src
[0]);
1850 if (vir_in_nonuniform_control_flow(c
)) {
1851 struct qinst
*exec_flag
= vir_MOV_dest(c
, vir_nop_reg(),
1853 if (cond
== V3D_QPU_COND_IFA
) {
1854 vir_set_uf(exec_flag
, V3D_QPU_UF_ANDZ
);
1856 vir_set_uf(exec_flag
, V3D_QPU_UF_NORNZ
);
1857 cond
= V3D_QPU_COND_IFA
;
1861 vir_set_cond(vir_SETMSF_dest(c
, vir_nop_reg(),
1862 vir_uniform_ui(c
, 0)), cond
);
1867 case nir_intrinsic_memory_barrier
:
1868 case nir_intrinsic_memory_barrier_atomic_counter
:
1869 case nir_intrinsic_memory_barrier_buffer
:
1870 case nir_intrinsic_memory_barrier_image
:
1871 case nir_intrinsic_memory_barrier_shared
:
1872 case nir_intrinsic_group_memory_barrier
:
1873 /* We don't do any instruction scheduling of these NIR
1874 * instructions between each other, so we just need to make
1875 * sure that the TMU operations before the barrier are flushed
1876 * before the ones after the barrier. That is currently
1877 * handled by having a THRSW in each of them and a LDTMU
1878 * series or a TMUWT after.
1882 case nir_intrinsic_barrier
:
1883 /* Emit a TSY op to get all invocations in the workgroup
1884 * (actually supergroup) to block until the last invocation
1885 * reaches the TSY op.
1887 if (c
->devinfo
->ver
>= 42) {
1888 vir_BARRIERID_dest(c
, vir_reg(QFILE_MAGIC
,
1889 V3D_QPU_WADDR_SYNCB
));
1891 struct qinst
*sync
=
1892 vir_BARRIERID_dest(c
,
1893 vir_reg(QFILE_MAGIC
,
1894 V3D_QPU_WADDR_SYNCU
));
1896 vir_get_uniform_index(c
, QUNIFORM_CONSTANT
,
1898 V3D_TSY_WAIT_INC_CHECK
);
1902 /* The blocking of a TSY op only happens at the next thread
1903 * switch. No texturing may be outstanding at the time of a
1904 * TSY blocking operation.
1909 case nir_intrinsic_load_num_work_groups
:
1910 for (int i
= 0; i
< 3; i
++) {
1911 ntq_store_dest(c
, &instr
->dest
, i
,
1912 vir_uniform(c
, QUNIFORM_NUM_WORK_GROUPS
,
1917 case nir_intrinsic_load_local_invocation_index
:
1918 ntq_store_dest(c
, &instr
->dest
, 0,
1919 vir_SHR(c
, c
->cs_payload
[1],
1920 vir_uniform_ui(c
, 32 - c
->local_invocation_index_bits
)));
1923 case nir_intrinsic_load_work_group_id
:
1924 ntq_store_dest(c
, &instr
->dest
, 0,
1925 vir_AND(c
, c
->cs_payload
[0],
1926 vir_uniform_ui(c
, 0xffff)));
1927 ntq_store_dest(c
, &instr
->dest
, 1,
1928 vir_SHR(c
, c
->cs_payload
[0],
1929 vir_uniform_ui(c
, 16)));
1930 ntq_store_dest(c
, &instr
->dest
, 2,
1931 vir_AND(c
, c
->cs_payload
[1],
1932 vir_uniform_ui(c
, 0xffff)));
1935 case nir_intrinsic_load_subgroup_id
:
1936 ntq_store_dest(c
, &instr
->dest
, 0, vir_EIDX(c
));
1940 fprintf(stderr
, "Unknown intrinsic: ");
1941 nir_print_instr(&instr
->instr
, stderr
);
1942 fprintf(stderr
, "\n");
1947 /* Clears (activates) the execute flags for any channels whose jump target
1948 * matches this block.
1950 * XXX perf: Could we be using flpush/flpop somehow for our execution channel
1953 * XXX perf: For uniform control flow, we should be able to skip c->execute
1954 * handling entirely.
1957 ntq_activate_execute_for_block(struct v3d_compile
*c
)
1959 vir_set_pf(vir_XOR_dest(c
, vir_nop_reg(),
1960 c
->execute
, vir_uniform_ui(c
, c
->cur_block
->index
)),
1963 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
, vir_uniform_ui(c
, 0));
1967 ntq_emit_uniform_if(struct v3d_compile
*c
, nir_if
*if_stmt
)
1969 nir_block
*nir_else_block
= nir_if_first_else_block(if_stmt
);
1970 bool empty_else_block
=
1971 (nir_else_block
== nir_if_last_else_block(if_stmt
) &&
1972 exec_list_is_empty(&nir_else_block
->instr_list
));
1974 struct qblock
*then_block
= vir_new_block(c
);
1975 struct qblock
*after_block
= vir_new_block(c
);
1976 struct qblock
*else_block
;
1977 if (empty_else_block
)
1978 else_block
= after_block
;
1980 else_block
= vir_new_block(c
);
1982 /* Set up the flags for the IF condition (taking the THEN branch). */
1983 enum v3d_qpu_cond cond
= ntq_emit_bool_to_cond(c
, if_stmt
->condition
);
1986 vir_BRANCH(c
, cond
== V3D_QPU_COND_IFA
?
1987 V3D_QPU_BRANCH_COND_ALLNA
:
1988 V3D_QPU_BRANCH_COND_ALLA
);
1989 vir_link_blocks(c
->cur_block
, else_block
);
1990 vir_link_blocks(c
->cur_block
, then_block
);
1992 /* Process the THEN block. */
1993 vir_set_emit_block(c
, then_block
);
1994 ntq_emit_cf_list(c
, &if_stmt
->then_list
);
1996 if (!empty_else_block
) {
1997 /* At the end of the THEN block, jump to ENDIF */
1998 vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ALWAYS
);
1999 vir_link_blocks(c
->cur_block
, after_block
);
2001 /* Emit the else block. */
2002 vir_set_emit_block(c
, else_block
);
2003 ntq_activate_execute_for_block(c
);
2004 ntq_emit_cf_list(c
, &if_stmt
->else_list
);
2007 vir_link_blocks(c
->cur_block
, after_block
);
2009 vir_set_emit_block(c
, after_block
);
2013 ntq_emit_nonuniform_if(struct v3d_compile
*c
, nir_if
*if_stmt
)
2015 nir_block
*nir_else_block
= nir_if_first_else_block(if_stmt
);
2016 bool empty_else_block
=
2017 (nir_else_block
== nir_if_last_else_block(if_stmt
) &&
2018 exec_list_is_empty(&nir_else_block
->instr_list
));
2020 struct qblock
*then_block
= vir_new_block(c
);
2021 struct qblock
*after_block
= vir_new_block(c
);
2022 struct qblock
*else_block
;
2023 if (empty_else_block
)
2024 else_block
= after_block
;
2026 else_block
= vir_new_block(c
);
2028 bool was_uniform_control_flow
= false;
2029 if (!vir_in_nonuniform_control_flow(c
)) {
2030 c
->execute
= vir_MOV(c
, vir_uniform_ui(c
, 0));
2031 was_uniform_control_flow
= true;
2034 /* Set up the flags for the IF condition (taking the THEN branch). */
2035 enum v3d_qpu_cond cond
= ntq_emit_bool_to_cond(c
, if_stmt
->condition
);
2037 /* Update the flags+cond to mean "Taking the ELSE branch (!cond) and
2038 * was previously active (execute Z) for updating the exec flags.
2040 if (was_uniform_control_flow
) {
2041 cond
= v3d_qpu_cond_invert(cond
);
2043 struct qinst
*inst
= vir_MOV_dest(c
, vir_nop_reg(), c
->execute
);
2044 if (cond
== V3D_QPU_COND_IFA
) {
2045 vir_set_uf(inst
, V3D_QPU_UF_NORNZ
);
2047 vir_set_uf(inst
, V3D_QPU_UF_ANDZ
);
2048 cond
= V3D_QPU_COND_IFA
;
2052 vir_MOV_cond(c
, cond
,
2054 vir_uniform_ui(c
, else_block
->index
));
2056 /* Jump to ELSE if nothing is active for THEN, otherwise fall
2059 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
), V3D_QPU_PF_PUSHZ
);
2060 vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ALLNA
);
2061 vir_link_blocks(c
->cur_block
, else_block
);
2062 vir_link_blocks(c
->cur_block
, then_block
);
2064 /* Process the THEN block. */
2065 vir_set_emit_block(c
, then_block
);
2066 ntq_emit_cf_list(c
, &if_stmt
->then_list
);
2068 if (!empty_else_block
) {
2069 /* Handle the end of the THEN block. First, all currently
2070 * active channels update their execute flags to point to
2073 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
),
2075 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
,
2076 vir_uniform_ui(c
, after_block
->index
));
2078 /* If everything points at ENDIF, then jump there immediately. */
2079 vir_set_pf(vir_XOR_dest(c
, vir_nop_reg(),
2081 vir_uniform_ui(c
, after_block
->index
)),
2083 vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ALLA
);
2084 vir_link_blocks(c
->cur_block
, after_block
);
2085 vir_link_blocks(c
->cur_block
, else_block
);
2087 vir_set_emit_block(c
, else_block
);
2088 ntq_activate_execute_for_block(c
);
2089 ntq_emit_cf_list(c
, &if_stmt
->else_list
);
2092 vir_link_blocks(c
->cur_block
, after_block
);
2094 vir_set_emit_block(c
, after_block
);
2095 if (was_uniform_control_flow
)
2096 c
->execute
= c
->undef
;
2098 ntq_activate_execute_for_block(c
);
2102 ntq_emit_if(struct v3d_compile
*c
, nir_if
*nif
)
2104 bool was_in_control_flow
= c
->in_control_flow
;
2105 c
->in_control_flow
= true;
2106 if (!vir_in_nonuniform_control_flow(c
) &&
2107 nir_src_is_dynamically_uniform(nif
->condition
)) {
2108 ntq_emit_uniform_if(c
, nif
);
2110 ntq_emit_nonuniform_if(c
, nif
);
2112 c
->in_control_flow
= was_in_control_flow
;
2116 ntq_emit_jump(struct v3d_compile
*c
, nir_jump_instr
*jump
)
2118 switch (jump
->type
) {
2119 case nir_jump_break
:
2120 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
),
2122 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
,
2123 vir_uniform_ui(c
, c
->loop_break_block
->index
));
2126 case nir_jump_continue
:
2127 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
),
2129 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
,
2130 vir_uniform_ui(c
, c
->loop_cont_block
->index
));
2133 case nir_jump_return
:
2134 unreachable("All returns shouold be lowered\n");
2139 ntq_emit_instr(struct v3d_compile
*c
, nir_instr
*instr
)
2141 switch (instr
->type
) {
2142 case nir_instr_type_deref
:
2143 /* ignored, will be walked by the intrinsic using it. */
2146 case nir_instr_type_alu
:
2147 ntq_emit_alu(c
, nir_instr_as_alu(instr
));
2150 case nir_instr_type_intrinsic
:
2151 ntq_emit_intrinsic(c
, nir_instr_as_intrinsic(instr
));
2154 case nir_instr_type_load_const
:
2155 ntq_emit_load_const(c
, nir_instr_as_load_const(instr
));
2158 case nir_instr_type_ssa_undef
:
2159 ntq_emit_ssa_undef(c
, nir_instr_as_ssa_undef(instr
));
2162 case nir_instr_type_tex
:
2163 ntq_emit_tex(c
, nir_instr_as_tex(instr
));
2166 case nir_instr_type_jump
:
2167 ntq_emit_jump(c
, nir_instr_as_jump(instr
));
2171 fprintf(stderr
, "Unknown NIR instr type: ");
2172 nir_print_instr(instr
, stderr
);
2173 fprintf(stderr
, "\n");
2179 ntq_emit_block(struct v3d_compile
*c
, nir_block
*block
)
2181 nir_foreach_instr(instr
, block
) {
2182 ntq_emit_instr(c
, instr
);
2186 static void ntq_emit_cf_list(struct v3d_compile
*c
, struct exec_list
*list
);
2189 ntq_emit_loop(struct v3d_compile
*c
, nir_loop
*loop
)
2191 bool was_in_control_flow
= c
->in_control_flow
;
2192 c
->in_control_flow
= true;
2194 bool was_uniform_control_flow
= false;
2195 if (!vir_in_nonuniform_control_flow(c
)) {
2196 c
->execute
= vir_MOV(c
, vir_uniform_ui(c
, 0));
2197 was_uniform_control_flow
= true;
2200 struct qblock
*save_loop_cont_block
= c
->loop_cont_block
;
2201 struct qblock
*save_loop_break_block
= c
->loop_break_block
;
2203 c
->loop_cont_block
= vir_new_block(c
);
2204 c
->loop_break_block
= vir_new_block(c
);
2206 vir_link_blocks(c
->cur_block
, c
->loop_cont_block
);
2207 vir_set_emit_block(c
, c
->loop_cont_block
);
2208 ntq_activate_execute_for_block(c
);
2210 ntq_emit_cf_list(c
, &loop
->body
);
2212 /* Re-enable any previous continues now, so our ANYA check below
2215 * XXX: Use the .ORZ flags update, instead.
2217 vir_set_pf(vir_XOR_dest(c
,
2220 vir_uniform_ui(c
, c
->loop_cont_block
->index
)),
2222 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
, vir_uniform_ui(c
, 0));
2224 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
), V3D_QPU_PF_PUSHZ
);
2226 struct qinst
*branch
= vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ANYA
);
2227 /* Pixels that were not dispatched or have been discarded should not
2228 * contribute to looping again.
2230 branch
->qpu
.branch
.msfign
= V3D_QPU_MSFIGN_P
;
2231 vir_link_blocks(c
->cur_block
, c
->loop_cont_block
);
2232 vir_link_blocks(c
->cur_block
, c
->loop_break_block
);
2234 vir_set_emit_block(c
, c
->loop_break_block
);
2235 if (was_uniform_control_flow
)
2236 c
->execute
= c
->undef
;
2238 ntq_activate_execute_for_block(c
);
2240 c
->loop_break_block
= save_loop_break_block
;
2241 c
->loop_cont_block
= save_loop_cont_block
;
2245 c
->in_control_flow
= was_in_control_flow
;
2249 ntq_emit_function(struct v3d_compile
*c
, nir_function_impl
*func
)
2251 fprintf(stderr
, "FUNCTIONS not handled.\n");
2256 ntq_emit_cf_list(struct v3d_compile
*c
, struct exec_list
*list
)
2258 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2259 switch (node
->type
) {
2260 case nir_cf_node_block
:
2261 ntq_emit_block(c
, nir_cf_node_as_block(node
));
2264 case nir_cf_node_if
:
2265 ntq_emit_if(c
, nir_cf_node_as_if(node
));
2268 case nir_cf_node_loop
:
2269 ntq_emit_loop(c
, nir_cf_node_as_loop(node
));
2272 case nir_cf_node_function
:
2273 ntq_emit_function(c
, nir_cf_node_as_function(node
));
2277 fprintf(stderr
, "Unknown NIR node type\n");
2284 ntq_emit_impl(struct v3d_compile
*c
, nir_function_impl
*impl
)
2286 ntq_setup_registers(c
, &impl
->registers
);
2287 ntq_emit_cf_list(c
, &impl
->body
);
2291 nir_to_vir(struct v3d_compile
*c
)
2293 switch (c
->s
->info
.stage
) {
2294 case MESA_SHADER_FRAGMENT
:
2295 c
->payload_w
= vir_MOV(c
, vir_reg(QFILE_REG
, 0));
2296 c
->payload_w_centroid
= vir_MOV(c
, vir_reg(QFILE_REG
, 1));
2297 c
->payload_z
= vir_MOV(c
, vir_reg(QFILE_REG
, 2));
2299 /* XXX perf: We could set the "disable implicit point/line
2300 * varyings" field in the shader record and not emit these, if
2301 * they're not going to be used.
2303 if (c
->fs_key
->is_points
) {
2304 c
->point_x
= emit_fragment_varying(c
, NULL
, 0, 0);
2305 c
->point_y
= emit_fragment_varying(c
, NULL
, 0, 0);
2306 } else if (c
->fs_key
->is_lines
) {
2307 c
->line_x
= emit_fragment_varying(c
, NULL
, 0, 0);
2310 case MESA_SHADER_COMPUTE
:
2311 /* Set up the TSO for barriers, assuming we do some. */
2312 if (c
->devinfo
->ver
< 42) {
2313 vir_BARRIERID_dest(c
, vir_reg(QFILE_MAGIC
,
2314 V3D_QPU_WADDR_SYNC
));
2317 c
->cs_payload
[0] = vir_MOV(c
, vir_reg(QFILE_REG
, 0));
2318 c
->cs_payload
[1] = vir_MOV(c
, vir_reg(QFILE_REG
, 2));
2320 /* Set up the division between gl_LocalInvocationIndex and
2321 * wg_in_mem in the payload reg.
2323 int wg_size
= (c
->s
->info
.cs
.local_size
[0] *
2324 c
->s
->info
.cs
.local_size
[1] *
2325 c
->s
->info
.cs
.local_size
[2]);
2326 c
->local_invocation_index_bits
=
2327 ffs(util_next_power_of_two(MAX2(wg_size
, 64))) - 1;
2328 assert(c
->local_invocation_index_bits
<= 8);
2330 if (c
->s
->info
.cs
.shared_size
) {
2331 struct qreg wg_in_mem
= vir_SHR(c
, c
->cs_payload
[1],
2332 vir_uniform_ui(c
, 16));
2333 if (c
->s
->info
.cs
.local_size
[0] != 1 ||
2334 c
->s
->info
.cs
.local_size
[1] != 1 ||
2335 c
->s
->info
.cs
.local_size
[2] != 1) {
2337 c
->local_invocation_index_bits
);
2338 int wg_mask
= (1 << wg_bits
) - 1;
2339 wg_in_mem
= vir_AND(c
, wg_in_mem
,
2340 vir_uniform_ui(c
, wg_mask
));
2342 struct qreg shared_per_wg
=
2343 vir_uniform_ui(c
, c
->s
->info
.cs
.shared_size
);
2345 c
->cs_shared_offset
=
2347 vir_uniform(c
, QUNIFORM_SHARED_OFFSET
,0),
2348 vir_UMUL(c
, wg_in_mem
, shared_per_wg
));
2355 if (c
->s
->scratch_size
) {
2356 v3d_setup_spill_base(c
);
2357 c
->spill_size
+= V3D_CHANNELS
* c
->s
->scratch_size
;
2360 if (c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
)
2361 ntq_setup_fs_inputs(c
);
2363 ntq_setup_vpm_inputs(c
);
2365 ntq_setup_outputs(c
);
2367 /* Find the main function and emit the body. */
2368 nir_foreach_function(function
, c
->s
) {
2369 assert(strcmp(function
->name
, "main") == 0);
2370 assert(function
->impl
);
2371 ntq_emit_impl(c
, function
->impl
);
2375 const nir_shader_compiler_options v3d_nir_options
= {
2376 .lower_all_io_to_temps
= true,
2377 .lower_extract_byte
= true,
2378 .lower_extract_word
= true,
2380 .lower_bitfield_insert_to_shifts
= true,
2381 .lower_bitfield_extract_to_shifts
= true,
2382 .lower_bitfield_reverse
= true,
2383 .lower_bit_count
= true,
2384 .lower_cs_local_id_from_index
= true,
2385 .lower_ffract
= true,
2386 .lower_pack_unorm_2x16
= true,
2387 .lower_pack_snorm_2x16
= true,
2388 .lower_pack_unorm_4x8
= true,
2389 .lower_pack_snorm_4x8
= true,
2390 .lower_unpack_unorm_4x8
= true,
2391 .lower_unpack_snorm_4x8
= true,
2392 .lower_pack_half_2x16
= true,
2393 .lower_unpack_half_2x16
= true,
2395 .lower_find_lsb
= true,
2397 .lower_flrp32
= true,
2400 .lower_fsqrt
= true,
2401 .lower_ifind_msb
= true,
2402 .lower_isign
= true,
2403 .lower_ldexp
= true,
2404 .lower_mul_high
= true,
2405 .lower_wpos_pntc
= true,
2409 * When demoting a shader down to single-threaded, removes the THRSW
2410 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
2414 vir_remove_thrsw(struct v3d_compile
*c
)
2416 vir_for_each_block(block
, c
) {
2417 vir_for_each_inst_safe(inst
, block
) {
2418 if (inst
->qpu
.sig
.thrsw
)
2419 vir_remove_instruction(c
, inst
);
2423 c
->last_thrsw
= NULL
;
2427 vir_emit_last_thrsw(struct v3d_compile
*c
)
2429 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
2430 * switching, so disable threads if we didn't do any TMU ops (each of
2431 * which would have emitted a THRSW).
2433 if (!c
->last_thrsw_at_top_level
&& c
->devinfo
->ver
< 41) {
2436 vir_remove_thrsw(c
);
2440 /* If we're threaded and the last THRSW was in conditional code, then
2441 * we need to emit another one so that we can flag it as the last
2444 if (c
->last_thrsw
&& !c
->last_thrsw_at_top_level
) {
2445 assert(c
->devinfo
->ver
>= 41);
2449 /* If we're threaded, then we need to mark the last THRSW instruction
2450 * so we can emit a pair of them at QPU emit time.
2452 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2453 * post-last-THRSW state, so we can skip this.
2455 if (!c
->last_thrsw
&& c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
) {
2456 assert(c
->devinfo
->ver
>= 41);
2461 c
->last_thrsw
->is_last_thrsw
= true;
2464 /* There's a flag in the shader for "center W is needed for reasons other than
2465 * non-centroid varyings", so we just walk the program after VIR optimization
2466 * to see if it's used. It should be harmless to set even if we only use
2467 * center W for varyings.
2470 vir_check_payload_w(struct v3d_compile
*c
)
2472 if (c
->s
->info
.stage
!= MESA_SHADER_FRAGMENT
)
2475 vir_for_each_inst_inorder(inst
, c
) {
2476 for (int i
= 0; i
< vir_get_nsrc(inst
); i
++) {
2477 if (inst
->src
[i
].file
== QFILE_REG
&&
2478 inst
->src
[i
].index
== 0) {
2479 c
->uses_center_w
= true;
2488 v3d_nir_to_vir(struct v3d_compile
*c
)
2490 if (V3D_DEBUG
& (V3D_DEBUG_NIR
|
2491 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
))) {
2492 fprintf(stderr
, "%s prog %d/%d NIR:\n",
2493 vir_get_stage_name(c
),
2494 c
->program_id
, c
->variant_id
);
2495 nir_print_shader(c
->s
, stderr
);
2500 /* Emit the last THRSW before STVPM and TLB writes. */
2501 vir_emit_last_thrsw(c
);
2503 switch (c
->s
->info
.stage
) {
2504 case MESA_SHADER_FRAGMENT
:
2507 case MESA_SHADER_VERTEX
:
2510 case MESA_SHADER_COMPUTE
:
2513 unreachable("bad stage");
2516 if (V3D_DEBUG
& (V3D_DEBUG_VIR
|
2517 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
))) {
2518 fprintf(stderr
, "%s prog %d/%d pre-opt VIR:\n",
2519 vir_get_stage_name(c
),
2520 c
->program_id
, c
->variant_id
);
2522 fprintf(stderr
, "\n");
2527 vir_check_payload_w(c
);
2529 /* XXX perf: On VC4, we do a VIR-level instruction scheduling here.
2530 * We used that on that platform to pipeline TMU writes and reduce the
2531 * number of thread switches, as well as try (mostly successfully) to
2532 * reduce maximum register pressure to allow more threads. We should
2533 * do something of that sort for V3D -- either instruction scheduling
2534 * here, or delay the the THRSW and LDTMUs from our texture
2535 * instructions until the results are needed.
2538 if (V3D_DEBUG
& (V3D_DEBUG_VIR
|
2539 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
))) {
2540 fprintf(stderr
, "%s prog %d/%d VIR:\n",
2541 vir_get_stage_name(c
),
2542 c
->program_id
, c
->variant_id
);
2544 fprintf(stderr
, "\n");
2547 /* Attempt to allocate registers for the temporaries. If we fail,
2548 * reduce thread count and try again.
2550 int min_threads
= (c
->devinfo
->ver
>= 41) ? 2 : 1;
2551 struct qpu_reg
*temp_registers
;
2554 temp_registers
= v3d_register_allocate(c
, &spilled
);
2561 if (c
->threads
== min_threads
) {
2562 fprintf(stderr
, "Failed to register allocate at %d threads:\n",
2571 if (c
->threads
== 1)
2572 vir_remove_thrsw(c
);
2576 (V3D_DEBUG
& (V3D_DEBUG_VIR
|
2577 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
)))) {
2578 fprintf(stderr
, "%s prog %d/%d spilled VIR:\n",
2579 vir_get_stage_name(c
),
2580 c
->program_id
, c
->variant_id
);
2582 fprintf(stderr
, "\n");
2585 v3d_vir_to_qpu(c
, temp_registers
);