2 * Copyright © 2016 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
36 ntq_emit_cf_list(struct v3d_compile
*c
, struct exec_list
*list
);
39 resize_qreg_array(struct v3d_compile
*c
,
44 if (*size
>= decl_size
)
47 uint32_t old_size
= *size
;
48 *size
= MAX2(*size
* 2, decl_size
);
49 *regs
= reralloc(c
, *regs
, struct qreg
, *size
);
51 fprintf(stderr
, "Malloc failure\n");
55 for (uint32_t i
= old_size
; i
< *size
; i
++)
56 (*regs
)[i
] = c
->undef
;
60 vir_emit_thrsw(struct v3d_compile
*c
)
65 /* Always thread switch after each texture operation for now.
67 * We could do better by batching a bunch of texture fetches up and
68 * then doing one thread switch and collecting all their results
71 c
->last_thrsw
= vir_NOP(c
);
72 c
->last_thrsw
->qpu
.sig
.thrsw
= true;
73 c
->last_thrsw_at_top_level
= (c
->execute
.file
== QFILE_NULL
);
77 indirect_uniform_load(struct v3d_compile
*c
, nir_intrinsic_instr
*intr
)
79 struct qreg indirect_offset
= ntq_get_src(c
, intr
->src
[0], 0);
80 uint32_t offset
= nir_intrinsic_base(intr
);
81 struct v3d_ubo_range
*range
= NULL
;
84 for (i
= 0; i
< c
->num_ubo_ranges
; i
++) {
85 range
= &c
->ubo_ranges
[i
];
86 if (offset
>= range
->src_offset
&&
87 offset
< range
->src_offset
+ range
->size
) {
91 /* The driver-location-based offset always has to be within a declared
94 assert(i
!= c
->num_ubo_ranges
);
95 if (!c
->ubo_range_used
[i
]) {
96 c
->ubo_range_used
[i
] = true;
97 range
->dst_offset
= c
->next_ubo_dst_offset
;
98 c
->next_ubo_dst_offset
+= range
->size
;
101 offset
-= range
->src_offset
;
103 if (range
->dst_offset
+ offset
!= 0) {
104 indirect_offset
= vir_ADD(c
, indirect_offset
,
105 vir_uniform_ui(c
, range
->dst_offset
+
109 /* Adjust for where we stored the TGSI register base. */
111 vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_TMUA
),
112 vir_uniform(c
, QUNIFORM_UBO_ADDR
, 0),
120 ntq_init_ssa_def(struct v3d_compile
*c
, nir_ssa_def
*def
)
122 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
123 def
->num_components
);
124 _mesa_hash_table_insert(c
->def_ht
, def
, qregs
);
129 * This function is responsible for getting VIR results into the associated
130 * storage for a NIR instruction.
132 * If it's a NIR SSA def, then we just set the associated hash table entry to
135 * If it's a NIR reg, then we need to update the existing qreg assigned to the
136 * NIR destination with the incoming value. To do that without introducing
137 * new MOVs, we require that the incoming qreg either be a uniform, or be
138 * SSA-defined by the previous VIR instruction in the block and rewritable by
139 * this function. That lets us sneak ahead and insert the SF flag beforehand
140 * (knowing that the previous instruction doesn't depend on flags) and rewrite
141 * its destination to be the NIR reg's destination
144 ntq_store_dest(struct v3d_compile
*c
, nir_dest
*dest
, int chan
,
147 struct qinst
*last_inst
= NULL
;
148 if (!list_empty(&c
->cur_block
->instructions
))
149 last_inst
= (struct qinst
*)c
->cur_block
->instructions
.prev
;
151 assert(result
.file
== QFILE_UNIF
||
152 (result
.file
== QFILE_TEMP
&&
153 last_inst
&& last_inst
== c
->defs
[result
.index
]));
156 assert(chan
< dest
->ssa
.num_components
);
159 struct hash_entry
*entry
=
160 _mesa_hash_table_search(c
->def_ht
, &dest
->ssa
);
165 qregs
= ntq_init_ssa_def(c
, &dest
->ssa
);
167 qregs
[chan
] = result
;
169 nir_register
*reg
= dest
->reg
.reg
;
170 assert(dest
->reg
.base_offset
== 0);
171 assert(reg
->num_array_elems
== 0);
172 struct hash_entry
*entry
=
173 _mesa_hash_table_search(c
->def_ht
, reg
);
174 struct qreg
*qregs
= entry
->data
;
176 /* Insert a MOV if the source wasn't an SSA def in the
177 * previous instruction.
179 if (result
.file
== QFILE_UNIF
) {
180 result
= vir_MOV(c
, result
);
181 last_inst
= c
->defs
[result
.index
];
184 /* We know they're both temps, so just rewrite index. */
185 c
->defs
[last_inst
->dst
.index
] = NULL
;
186 last_inst
->dst
.index
= qregs
[chan
].index
;
188 /* If we're in control flow, then make this update of the reg
189 * conditional on the execution mask.
191 if (c
->execute
.file
!= QFILE_NULL
) {
192 last_inst
->dst
.index
= qregs
[chan
].index
;
194 /* Set the flags to the current exec mask.
196 c
->cursor
= vir_before_inst(last_inst
);
197 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
198 c
->cursor
= vir_after_inst(last_inst
);
200 vir_set_cond(last_inst
, V3D_QPU_COND_IFA
);
201 last_inst
->cond_is_exec_mask
= true;
207 ntq_get_src(struct v3d_compile
*c
, nir_src src
, int i
)
209 struct hash_entry
*entry
;
211 entry
= _mesa_hash_table_search(c
->def_ht
, src
.ssa
);
212 assert(i
< src
.ssa
->num_components
);
214 nir_register
*reg
= src
.reg
.reg
;
215 entry
= _mesa_hash_table_search(c
->def_ht
, reg
);
216 assert(reg
->num_array_elems
== 0);
217 assert(src
.reg
.base_offset
== 0);
218 assert(i
< reg
->num_components
);
221 struct qreg
*qregs
= entry
->data
;
226 ntq_get_alu_src(struct v3d_compile
*c
, nir_alu_instr
*instr
,
229 assert(util_is_power_of_two_or_zero(instr
->dest
.write_mask
));
230 unsigned chan
= ffs(instr
->dest
.write_mask
) - 1;
231 struct qreg r
= ntq_get_src(c
, instr
->src
[src
].src
,
232 instr
->src
[src
].swizzle
[chan
]);
234 assert(!instr
->src
[src
].abs
);
235 assert(!instr
->src
[src
].negate
);
241 ntq_minify(struct v3d_compile
*c
, struct qreg size
, struct qreg level
)
243 return vir_MAX(c
, vir_SHR(c
, size
, level
), vir_uniform_ui(c
, 1));
247 ntq_emit_txs(struct v3d_compile
*c
, nir_tex_instr
*instr
)
249 unsigned unit
= instr
->texture_index
;
250 int lod_index
= nir_tex_instr_src_index(instr
, nir_tex_src_lod
);
251 int dest_size
= nir_tex_instr_dest_size(instr
);
253 struct qreg lod
= c
->undef
;
255 lod
= ntq_get_src(c
, instr
->src
[lod_index
].src
, 0);
257 for (int i
= 0; i
< dest_size
; i
++) {
259 enum quniform_contents contents
;
261 if (instr
->is_array
&& i
== dest_size
- 1)
262 contents
= QUNIFORM_TEXTURE_ARRAY_SIZE
;
264 contents
= QUNIFORM_TEXTURE_WIDTH
+ i
;
266 struct qreg size
= vir_uniform(c
, contents
, unit
);
268 switch (instr
->sampler_dim
) {
269 case GLSL_SAMPLER_DIM_1D
:
270 case GLSL_SAMPLER_DIM_2D
:
271 case GLSL_SAMPLER_DIM_3D
:
272 case GLSL_SAMPLER_DIM_CUBE
:
273 /* Don't minify the array size. */
274 if (!(instr
->is_array
&& i
== dest_size
- 1)) {
275 size
= ntq_minify(c
, size
, lod
);
279 case GLSL_SAMPLER_DIM_RECT
:
280 /* There's no LOD field for rects */
284 unreachable("Bad sampler type");
287 ntq_store_dest(c
, &instr
->dest
, i
, size
);
292 ntq_emit_tex(struct v3d_compile
*c
, nir_tex_instr
*instr
)
294 unsigned unit
= instr
->texture_index
;
296 /* Since each texture sampling op requires uploading uniforms to
297 * reference the texture, there's no HW support for texture size and
298 * you just upload uniforms containing the size.
301 case nir_texop_query_levels
:
302 ntq_store_dest(c
, &instr
->dest
, 0,
303 vir_uniform(c
, QUNIFORM_TEXTURE_LEVELS
, unit
));
306 ntq_emit_txs(c
, instr
);
312 if (c
->devinfo
->ver
>= 40)
313 v3d40_vir_emit_tex(c
, instr
);
315 v3d33_vir_emit_tex(c
, instr
);
319 ntq_fsincos(struct v3d_compile
*c
, struct qreg src
, bool is_cos
)
321 struct qreg input
= vir_FMUL(c
, src
, vir_uniform_f(c
, 1.0f
/ M_PI
));
323 input
= vir_FADD(c
, input
, vir_uniform_f(c
, 0.5));
325 struct qreg periods
= vir_FROUND(c
, input
);
326 struct qreg sin_output
= vir_SIN(c
, vir_FSUB(c
, input
, periods
));
327 return vir_XOR(c
, sin_output
, vir_SHL(c
,
328 vir_FTOIN(c
, periods
),
329 vir_uniform_ui(c
, -1)));
333 ntq_fsign(struct v3d_compile
*c
, struct qreg src
)
335 struct qreg t
= vir_get_temp(c
);
337 vir_MOV_dest(c
, t
, vir_uniform_f(c
, 0.0));
338 vir_PF(c
, vir_FMOV(c
, src
), V3D_QPU_PF_PUSHZ
);
339 vir_MOV_cond(c
, V3D_QPU_COND_IFNA
, t
, vir_uniform_f(c
, 1.0));
340 vir_PF(c
, vir_FMOV(c
, src
), V3D_QPU_PF_PUSHN
);
341 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, t
, vir_uniform_f(c
, -1.0));
342 return vir_MOV(c
, t
);
346 ntq_isign(struct v3d_compile
*c
, struct qreg src
)
348 struct qreg t
= vir_get_temp(c
);
350 vir_MOV_dest(c
, t
, vir_uniform_ui(c
, 0));
351 vir_PF(c
, vir_MOV(c
, src
), V3D_QPU_PF_PUSHZ
);
352 vir_MOV_cond(c
, V3D_QPU_COND_IFNA
, t
, vir_uniform_ui(c
, 1));
353 vir_PF(c
, vir_MOV(c
, src
), V3D_QPU_PF_PUSHN
);
354 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, t
, vir_uniform_ui(c
, -1));
355 return vir_MOV(c
, t
);
359 emit_fragcoord_input(struct v3d_compile
*c
, int attr
)
361 c
->inputs
[attr
* 4 + 0] = vir_FXCD(c
);
362 c
->inputs
[attr
* 4 + 1] = vir_FYCD(c
);
363 c
->inputs
[attr
* 4 + 2] = c
->payload_z
;
364 c
->inputs
[attr
* 4 + 3] = vir_RECIP(c
, c
->payload_w
);
368 emit_fragment_varying(struct v3d_compile
*c
, nir_variable
*var
,
371 struct qreg r3
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_R3
);
372 struct qreg r5
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_R5
);
375 if (c
->devinfo
->ver
>= 41) {
376 struct qinst
*ldvary
= vir_add_inst(V3D_QPU_A_NOP
, c
->undef
,
378 ldvary
->qpu
.sig
.ldvary
= true;
379 vary
= vir_emit_def(c
, ldvary
);
381 vir_NOP(c
)->qpu
.sig
.ldvary
= true;
385 /* For gl_PointCoord input or distance along a line, we'll be called
386 * with no nir_variable, and we don't count toward VPM size so we
387 * don't track an input slot.
390 return vir_FADD(c
, vir_FMUL(c
, vary
, c
->payload_w
), r5
);
393 int i
= c
->num_inputs
++;
394 c
->input_slots
[i
] = v3d_slot_from_slot_and_component(var
->data
.location
,
397 switch (var
->data
.interpolation
) {
398 case INTERP_MODE_NONE
:
399 /* If a gl_FrontColor or gl_BackColor input has no interp
400 * qualifier, then if we're using glShadeModel(GL_FLAT) it
401 * needs to be flat shaded.
403 switch (var
->data
.location
) {
404 case VARYING_SLOT_COL0
:
405 case VARYING_SLOT_COL1
:
406 case VARYING_SLOT_BFC0
:
407 case VARYING_SLOT_BFC1
:
408 if (c
->fs_key
->shade_model_flat
) {
409 BITSET_SET(c
->flat_shade_flags
, i
);
410 vir_MOV_dest(c
, c
->undef
, vary
);
411 return vir_MOV(c
, r5
);
413 return vir_FADD(c
, vir_FMUL(c
, vary
,
420 case INTERP_MODE_SMOOTH
:
421 if (var
->data
.centroid
) {
422 BITSET_SET(c
->centroid_flags
, i
);
423 return vir_FADD(c
, vir_FMUL(c
, vary
,
424 c
->payload_w_centroid
), r5
);
426 return vir_FADD(c
, vir_FMUL(c
, vary
, c
->payload_w
), r5
);
428 case INTERP_MODE_NOPERSPECTIVE
:
429 BITSET_SET(c
->noperspective_flags
, i
);
430 return vir_FADD(c
, vir_MOV(c
, vary
), r5
);
431 case INTERP_MODE_FLAT
:
432 BITSET_SET(c
->flat_shade_flags
, i
);
433 vir_MOV_dest(c
, c
->undef
, vary
);
434 return vir_MOV(c
, r5
);
436 unreachable("Bad interp mode");
441 emit_fragment_input(struct v3d_compile
*c
, int attr
, nir_variable
*var
)
443 for (int i
= 0; i
< glsl_get_vector_elements(var
->type
); i
++) {
444 int chan
= var
->data
.location_frac
+ i
;
445 c
->inputs
[attr
* 4 + chan
] =
446 emit_fragment_varying(c
, var
, chan
);
451 add_output(struct v3d_compile
*c
,
452 uint32_t decl_offset
,
456 uint32_t old_array_size
= c
->outputs_array_size
;
457 resize_qreg_array(c
, &c
->outputs
, &c
->outputs_array_size
,
460 if (old_array_size
!= c
->outputs_array_size
) {
461 c
->output_slots
= reralloc(c
,
463 struct v3d_varying_slot
,
464 c
->outputs_array_size
);
467 c
->output_slots
[decl_offset
] =
468 v3d_slot_from_slot_and_component(slot
, swizzle
);
472 declare_uniform_range(struct v3d_compile
*c
, uint32_t start
, uint32_t size
)
474 unsigned array_id
= c
->num_ubo_ranges
++;
475 if (array_id
>= c
->ubo_ranges_array_size
) {
476 c
->ubo_ranges_array_size
= MAX2(c
->ubo_ranges_array_size
* 2,
478 c
->ubo_ranges
= reralloc(c
, c
->ubo_ranges
,
479 struct v3d_ubo_range
,
480 c
->ubo_ranges_array_size
);
481 c
->ubo_range_used
= reralloc(c
, c
->ubo_range_used
,
483 c
->ubo_ranges_array_size
);
486 c
->ubo_ranges
[array_id
].dst_offset
= 0;
487 c
->ubo_ranges
[array_id
].src_offset
= start
;
488 c
->ubo_ranges
[array_id
].size
= size
;
489 c
->ubo_range_used
[array_id
] = false;
493 * If compare_instr is a valid comparison instruction, emits the
494 * compare_instr's comparison and returns the sel_instr's return value based
495 * on the compare_instr's result.
498 ntq_emit_comparison(struct v3d_compile
*c
, struct qreg
*dest
,
499 nir_alu_instr
*compare_instr
,
500 nir_alu_instr
*sel_instr
)
502 struct qreg src0
= ntq_get_alu_src(c
, compare_instr
, 0);
504 if (nir_op_infos
[compare_instr
->op
].num_inputs
> 1)
505 src1
= ntq_get_alu_src(c
, compare_instr
, 1);
506 bool cond_invert
= false;
508 switch (compare_instr
->op
) {
511 vir_PF(c
, vir_FCMP(c
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
514 vir_PF(c
, vir_XOR(c
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
519 vir_PF(c
, vir_FCMP(c
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
523 vir_PF(c
, vir_XOR(c
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
529 vir_PF(c
, vir_FCMP(c
, src1
, src0
), V3D_QPU_PF_PUSHC
);
532 vir_PF(c
, vir_MIN(c
, src1
, src0
), V3D_QPU_PF_PUSHC
);
536 vir_PF(c
, vir_SUB(c
, src0
, src1
), V3D_QPU_PF_PUSHC
);
542 vir_PF(c
, vir_FCMP(c
, src0
, src1
), V3D_QPU_PF_PUSHN
);
545 vir_PF(c
, vir_MIN(c
, src1
, src0
), V3D_QPU_PF_PUSHC
);
548 vir_PF(c
, vir_SUB(c
, src0
, src1
), V3D_QPU_PF_PUSHC
);
555 enum v3d_qpu_cond cond
= (cond_invert
?
559 switch (sel_instr
->op
) {
564 *dest
= vir_SEL(c
, cond
,
565 vir_uniform_f(c
, 1.0), vir_uniform_f(c
, 0.0));
569 *dest
= vir_SEL(c
, cond
,
570 ntq_get_alu_src(c
, sel_instr
, 1),
571 ntq_get_alu_src(c
, sel_instr
, 2));
575 *dest
= vir_SEL(c
, cond
,
576 vir_uniform_ui(c
, ~0), vir_uniform_ui(c
, 0));
580 /* Make the temporary for nir_store_dest(). */
581 *dest
= vir_MOV(c
, *dest
);
587 * Attempts to fold a comparison generating a boolean result into the
588 * condition code for selecting between two values, instead of comparing the
589 * boolean result against 0 to generate the condition code.
591 static struct qreg
ntq_emit_bcsel(struct v3d_compile
*c
, nir_alu_instr
*instr
,
594 if (!instr
->src
[0].src
.is_ssa
)
596 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
598 nir_alu_instr
*compare
=
599 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
604 if (ntq_emit_comparison(c
, &dest
, compare
, instr
))
608 vir_PF(c
, src
[0], V3D_QPU_PF_PUSHZ
);
609 return vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFNA
, src
[1], src
[2]));
614 ntq_emit_alu(struct v3d_compile
*c
, nir_alu_instr
*instr
)
616 /* This should always be lowered to ALU operations for V3D. */
617 assert(!instr
->dest
.saturate
);
619 /* Vectors are special in that they have non-scalarized writemasks,
620 * and just take the first swizzle channel for each argument in order
621 * into each writemask channel.
623 if (instr
->op
== nir_op_vec2
||
624 instr
->op
== nir_op_vec3
||
625 instr
->op
== nir_op_vec4
) {
627 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
628 srcs
[i
] = ntq_get_src(c
, instr
->src
[i
].src
,
629 instr
->src
[i
].swizzle
[0]);
630 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
631 ntq_store_dest(c
, &instr
->dest
.dest
, i
,
632 vir_MOV(c
, srcs
[i
]));
636 /* General case: We can just grab the one used channel per src. */
637 struct qreg src
[nir_op_infos
[instr
->op
].num_inputs
];
638 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
639 src
[i
] = ntq_get_alu_src(c
, instr
, i
);
647 result
= vir_MOV(c
, src
[0]);
651 result
= vir_XOR(c
, src
[0], vir_uniform_ui(c
, 1 << 31));
654 result
= vir_NEG(c
, src
[0]);
658 result
= vir_FMUL(c
, src
[0], src
[1]);
661 result
= vir_FADD(c
, src
[0], src
[1]);
664 result
= vir_FSUB(c
, src
[0], src
[1]);
667 result
= vir_FMIN(c
, src
[0], src
[1]);
670 result
= vir_FMAX(c
, src
[0], src
[1]);
674 result
= vir_FTOIZ(c
, src
[0]);
677 result
= vir_FTOUZ(c
, src
[0]);
680 result
= vir_ITOF(c
, src
[0]);
683 result
= vir_UTOF(c
, src
[0]);
686 result
= vir_AND(c
, src
[0], vir_uniform_f(c
, 1.0));
689 result
= vir_AND(c
, src
[0], vir_uniform_ui(c
, 1));
693 vir_PF(c
, src
[0], V3D_QPU_PF_PUSHZ
);
694 result
= vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFNA
,
695 vir_uniform_ui(c
, ~0),
696 vir_uniform_ui(c
, 0)));
700 result
= vir_ADD(c
, src
[0], src
[1]);
703 result
= vir_SHR(c
, src
[0], src
[1]);
706 result
= vir_SUB(c
, src
[0], src
[1]);
709 result
= vir_ASR(c
, src
[0], src
[1]);
712 result
= vir_SHL(c
, src
[0], src
[1]);
715 result
= vir_MIN(c
, src
[0], src
[1]);
718 result
= vir_UMIN(c
, src
[0], src
[1]);
721 result
= vir_MAX(c
, src
[0], src
[1]);
724 result
= vir_UMAX(c
, src
[0], src
[1]);
727 result
= vir_AND(c
, src
[0], src
[1]);
730 result
= vir_OR(c
, src
[0], src
[1]);
733 result
= vir_XOR(c
, src
[0], src
[1]);
736 result
= vir_NOT(c
, src
[0]);
739 case nir_op_ufind_msb
:
740 result
= vir_SUB(c
, vir_uniform_ui(c
, 31), vir_CLZ(c
, src
[0]));
744 result
= vir_UMUL(c
, src
[0], src
[1]);
761 if (!ntq_emit_comparison(c
, &result
, instr
, instr
)) {
762 fprintf(stderr
, "Bad comparison instruction\n");
767 result
= ntq_emit_bcsel(c
, instr
, src
);
770 vir_PF(c
, src
[0], V3D_QPU_PF_PUSHZ
);
771 result
= vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFNA
,
776 result
= vir_RECIP(c
, src
[0]);
779 result
= vir_RSQRT(c
, src
[0]);
782 result
= vir_EXP(c
, src
[0]);
785 result
= vir_LOG(c
, src
[0]);
789 result
= vir_FCEIL(c
, src
[0]);
792 result
= vir_FFLOOR(c
, src
[0]);
794 case nir_op_fround_even
:
795 result
= vir_FROUND(c
, src
[0]);
798 result
= vir_FTRUNC(c
, src
[0]);
801 result
= vir_FSUB(c
, src
[0], vir_FFLOOR(c
, src
[0]));
805 result
= ntq_fsincos(c
, src
[0], false);
808 result
= ntq_fsincos(c
, src
[0], true);
812 result
= ntq_fsign(c
, src
[0]);
815 result
= ntq_isign(c
, src
[0]);
819 result
= vir_FMOV(c
, src
[0]);
820 vir_set_unpack(c
->defs
[result
.index
], 0, V3D_QPU_UNPACK_ABS
);
825 result
= vir_MAX(c
, src
[0],
826 vir_SUB(c
, vir_uniform_ui(c
, 0), src
[0]));
830 case nir_op_fddx_coarse
:
831 case nir_op_fddx_fine
:
832 result
= vir_FDX(c
, src
[0]);
836 case nir_op_fddy_coarse
:
837 case nir_op_fddy_fine
:
838 result
= vir_FDY(c
, src
[0]);
841 case nir_op_uadd_carry
:
842 vir_PF(c
, vir_ADD(c
, src
[0], src
[1]), V3D_QPU_PF_PUSHC
);
843 result
= vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFA
,
844 vir_uniform_ui(c
, ~0),
845 vir_uniform_ui(c
, 0)));
849 fprintf(stderr
, "unknown NIR ALU inst: ");
850 nir_print_instr(&instr
->instr
, stderr
);
851 fprintf(stderr
, "\n");
855 /* We have a scalar result, so the instruction should only have a
856 * single channel written to.
858 assert(util_is_power_of_two_or_zero(instr
->dest
.write_mask
));
859 ntq_store_dest(c
, &instr
->dest
.dest
,
860 ffs(instr
->dest
.write_mask
) - 1, result
);
863 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
864 * specifier. They come from a register that's preloaded with 0xffffffff
865 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
866 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
868 #define TLB_TYPE_F16_COLOR (3 << 6)
869 #define TLB_TYPE_I32_COLOR (1 << 6)
870 #define TLB_TYPE_F32_COLOR (0 << 6)
871 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
872 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
873 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
874 #define TLB_F16_SWAP_HI_LO (1 << 1)
875 #define TLB_VEC_SIZE_4_F16 (1 << 0)
876 #define TLB_VEC_SIZE_2_F16 (0 << 0)
877 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
879 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
882 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
883 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
884 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
886 /* Stencil is a single 32-bit write. */
887 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
890 emit_frag_end(struct v3d_compile
*c
)
893 if (c->output_sample_mask_index != -1) {
894 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
898 bool has_any_tlb_color_write
= false;
899 for (int rt
= 0; rt
< c
->fs_key
->nr_cbufs
; rt
++) {
900 if (c
->output_color_var
[rt
])
901 has_any_tlb_color_write
= true;
904 if (c
->fs_key
->sample_alpha_to_coverage
&& c
->output_color_var
[0]) {
905 struct nir_variable
*var
= c
->output_color_var
[0];
906 struct qreg
*color
= &c
->outputs
[var
->data
.driver_location
* 4];
908 vir_SETMSF_dest(c
, vir_reg(QFILE_NULL
, 0),
911 vir_FTOC(c
, color
[3])));
914 if (c
->output_position_index
!= -1) {
915 struct qinst
*inst
= vir_MOV_dest(c
,
916 vir_reg(QFILE_TLBU
, 0),
917 c
->outputs
[c
->output_position_index
]);
919 inst
->src
[vir_get_implicit_uniform_src(inst
)] =
922 TLB_DEPTH_TYPE_PER_PIXEL
|
924 } else if (c
->s
->info
.fs
.uses_discard
||
925 c
->fs_key
->sample_alpha_to_coverage
||
926 !has_any_tlb_color_write
) {
927 /* Emit passthrough Z if it needed to be delayed until shader
928 * end due to potential discards.
930 * Since (single-threaded) fragment shaders always need a TLB
931 * write, emit passthrouh Z if we didn't have any color
932 * buffers and flag us as potentially discarding, so that we
933 * can use Z as the TLB write.
935 c
->s
->info
.fs
.uses_discard
= true;
937 struct qinst
*inst
= vir_MOV_dest(c
,
938 vir_reg(QFILE_TLBU
, 0),
939 vir_reg(QFILE_NULL
, 0));
941 inst
->src
[vir_get_implicit_uniform_src(inst
)] =
944 TLB_DEPTH_TYPE_INVARIANT
|
948 /* XXX: Performance improvement: Merge Z write and color writes TLB
952 for (int rt
= 0; rt
< c
->fs_key
->nr_cbufs
; rt
++) {
953 if (!c
->output_color_var
[rt
])
956 nir_variable
*var
= c
->output_color_var
[rt
];
957 struct qreg
*color
= &c
->outputs
[var
->data
.driver_location
* 4];
958 int num_components
= glsl_get_vector_elements(var
->type
);
959 uint32_t conf
= 0xffffff00;
962 conf
|= TLB_SAMPLE_MODE_PER_PIXEL
;
963 conf
|= (7 - rt
) << TLB_RENDER_TARGET_SHIFT
;
965 if (c
->fs_key
->swap_color_rb
& (1 << rt
))
966 num_components
= MAX2(num_components
, 3);
968 assert(num_components
!= 0);
969 switch (glsl_get_base_type(var
->type
)) {
972 /* The F32 vs I32 distinction was dropped in 4.2. */
973 if (c
->devinfo
->ver
< 42)
974 conf
|= TLB_TYPE_I32_COLOR
;
976 conf
|= TLB_TYPE_F32_COLOR
;
977 conf
|= ((num_components
- 1) <<
978 TLB_VEC_SIZE_MINUS_1_SHIFT
);
980 inst
= vir_MOV_dest(c
, vir_reg(QFILE_TLBU
, 0), color
[0]);
981 inst
->src
[vir_get_implicit_uniform_src(inst
)] =
982 vir_uniform_ui(c
, conf
);
984 for (int i
= 1; i
< num_components
; i
++) {
985 inst
= vir_MOV_dest(c
, vir_reg(QFILE_TLB
, 0),
991 struct qreg r
= color
[0];
992 struct qreg g
= color
[1];
993 struct qreg b
= color
[2];
994 struct qreg a
= color
[3];
996 if (c
->fs_key
->f32_color_rb
& (1 << rt
)) {
997 conf
|= TLB_TYPE_F32_COLOR
;
998 conf
|= ((num_components
- 1) <<
999 TLB_VEC_SIZE_MINUS_1_SHIFT
);
1001 conf
|= TLB_TYPE_F16_COLOR
;
1002 conf
|= TLB_F16_SWAP_HI_LO
;
1003 if (num_components
>= 3)
1004 conf
|= TLB_VEC_SIZE_4_F16
;
1006 conf
|= TLB_VEC_SIZE_2_F16
;
1009 if (c
->fs_key
->swap_color_rb
& (1 << rt
)) {
1014 if (c
->fs_key
->sample_alpha_to_one
)
1015 a
= vir_uniform_f(c
, 1.0);
1017 if (c
->fs_key
->f32_color_rb
& (1 << rt
)) {
1018 inst
= vir_MOV_dest(c
, vir_reg(QFILE_TLBU
, 0), r
);
1019 inst
->src
[vir_get_implicit_uniform_src(inst
)] =
1020 vir_uniform_ui(c
, conf
);
1022 if (num_components
>= 2)
1023 vir_MOV_dest(c
, vir_reg(QFILE_TLB
, 0), g
);
1024 if (num_components
>= 3)
1025 vir_MOV_dest(c
, vir_reg(QFILE_TLB
, 0), b
);
1026 if (num_components
>= 4)
1027 vir_MOV_dest(c
, vir_reg(QFILE_TLB
, 0), a
);
1029 inst
= vir_VFPACK_dest(c
, vir_reg(QFILE_TLB
, 0), r
, g
);
1031 inst
->dst
.file
= QFILE_TLBU
;
1032 inst
->src
[vir_get_implicit_uniform_src(inst
)] =
1033 vir_uniform_ui(c
, conf
);
1036 if (num_components
>= 3)
1037 inst
= vir_VFPACK_dest(c
, vir_reg(QFILE_TLB
, 0), b
, a
);
1046 vir_VPM_WRITE(struct v3d_compile
*c
, struct qreg val
, uint32_t *vpm_index
)
1048 if (c
->devinfo
->ver
>= 40) {
1049 vir_STVPMV(c
, vir_uniform_ui(c
, *vpm_index
), val
);
1050 *vpm_index
= *vpm_index
+ 1;
1052 vir_MOV_dest(c
, vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_VPM
), val
);
1055 c
->num_vpm_writes
++;
1059 emit_scaled_viewport_write(struct v3d_compile
*c
, struct qreg rcp_w
,
1060 uint32_t *vpm_index
)
1062 for (int i
= 0; i
< 2; i
++) {
1063 struct qreg coord
= c
->outputs
[c
->output_position_index
+ i
];
1064 coord
= vir_FMUL(c
, coord
,
1065 vir_uniform(c
, QUNIFORM_VIEWPORT_X_SCALE
+ i
,
1067 coord
= vir_FMUL(c
, coord
, rcp_w
);
1068 vir_VPM_WRITE(c
, vir_FTOIN(c
, coord
), vpm_index
);
1074 emit_zs_write(struct v3d_compile
*c
, struct qreg rcp_w
, uint32_t *vpm_index
)
1076 struct qreg zscale
= vir_uniform(c
, QUNIFORM_VIEWPORT_Z_SCALE
, 0);
1077 struct qreg zoffset
= vir_uniform(c
, QUNIFORM_VIEWPORT_Z_OFFSET
, 0);
1079 struct qreg z
= c
->outputs
[c
->output_position_index
+ 2];
1080 z
= vir_FMUL(c
, z
, zscale
);
1081 z
= vir_FMUL(c
, z
, rcp_w
);
1082 z
= vir_FADD(c
, z
, zoffset
);
1083 vir_VPM_WRITE(c
, z
, vpm_index
);
1087 emit_rcp_wc_write(struct v3d_compile
*c
, struct qreg rcp_w
, uint32_t *vpm_index
)
1089 vir_VPM_WRITE(c
, rcp_w
, vpm_index
);
1093 emit_point_size_write(struct v3d_compile
*c
, uint32_t *vpm_index
)
1095 struct qreg point_size
;
1097 if (c
->output_point_size_index
!= -1)
1098 point_size
= c
->outputs
[c
->output_point_size_index
];
1100 point_size
= vir_uniform_f(c
, 1.0);
1102 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1105 point_size
= vir_FMAX(c
, point_size
, vir_uniform_f(c
, .125));
1107 vir_VPM_WRITE(c
, point_size
, vpm_index
);
1111 emit_vpm_write_setup(struct v3d_compile
*c
)
1113 if (c
->devinfo
->ver
>= 40)
1116 v3d33_vir_vpm_write_setup(c
);
1120 * Sets up c->outputs[c->output_position_index] for the vertex shader
1121 * epilogue, if an output vertex position wasn't specified in the user's
1122 * shader. This may be the case for transform feedback with rasterizer
1126 setup_default_position(struct v3d_compile
*c
)
1128 if (c
->output_position_index
!= -1)
1131 c
->output_position_index
= c
->outputs_array_size
;
1132 for (int i
= 0; i
< 4; i
++) {
1134 c
->output_position_index
+ i
,
1135 VARYING_SLOT_POS
, i
);
1140 emit_vert_end(struct v3d_compile
*c
)
1142 setup_default_position(c
);
1144 uint32_t vpm_index
= 0;
1145 struct qreg rcp_w
= vir_RECIP(c
,
1146 c
->outputs
[c
->output_position_index
+ 3]);
1148 emit_vpm_write_setup(c
);
1150 if (c
->vs_key
->is_coord
) {
1151 for (int i
= 0; i
< 4; i
++)
1152 vir_VPM_WRITE(c
, c
->outputs
[c
->output_position_index
+ i
],
1154 emit_scaled_viewport_write(c
, rcp_w
, &vpm_index
);
1155 if (c
->vs_key
->per_vertex_point_size
) {
1156 emit_point_size_write(c
, &vpm_index
);
1157 /* emit_rcp_wc_write(c, rcp_w); */
1159 /* XXX: Z-only rendering */
1161 emit_zs_write(c
, rcp_w
, &vpm_index
);
1163 emit_scaled_viewport_write(c
, rcp_w
, &vpm_index
);
1164 emit_zs_write(c
, rcp_w
, &vpm_index
);
1165 emit_rcp_wc_write(c
, rcp_w
, &vpm_index
);
1166 if (c
->vs_key
->per_vertex_point_size
)
1167 emit_point_size_write(c
, &vpm_index
);
1170 for (int i
= 0; i
< c
->vs_key
->num_fs_inputs
; i
++) {
1171 struct v3d_varying_slot input
= c
->vs_key
->fs_inputs
[i
];
1174 for (j
= 0; j
< c
->num_outputs
; j
++) {
1175 struct v3d_varying_slot output
= c
->output_slots
[j
];
1177 if (!memcmp(&input
, &output
, sizeof(input
))) {
1178 vir_VPM_WRITE(c
, c
->outputs
[j
],
1183 /* Emit padding if we didn't find a declared VS output for
1186 if (j
== c
->num_outputs
)
1187 vir_VPM_WRITE(c
, vir_uniform_f(c
, 0.0),
1191 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1193 if (c
->devinfo
->ver
>= 40 && c
->devinfo
->ver
<= 42)
1198 v3d_optimize_nir(struct nir_shader
*s
)
1205 NIR_PASS_V(s
, nir_lower_vars_to_ssa
);
1206 NIR_PASS(progress
, s
, nir_lower_alu_to_scalar
);
1207 NIR_PASS(progress
, s
, nir_lower_phis_to_scalar
);
1208 NIR_PASS(progress
, s
, nir_copy_prop
);
1209 NIR_PASS(progress
, s
, nir_opt_remove_phis
);
1210 NIR_PASS(progress
, s
, nir_opt_dce
);
1211 NIR_PASS(progress
, s
, nir_opt_dead_cf
);
1212 NIR_PASS(progress
, s
, nir_opt_cse
);
1213 NIR_PASS(progress
, s
, nir_opt_peephole_select
, 8);
1214 NIR_PASS(progress
, s
, nir_opt_algebraic
);
1215 NIR_PASS(progress
, s
, nir_opt_constant_folding
);
1216 NIR_PASS(progress
, s
, nir_opt_undef
);
1219 NIR_PASS(progress
, s
, nir_opt_move_load_ubo
);
1223 driver_location_compare(const void *in_a
, const void *in_b
)
1225 const nir_variable
*const *a
= in_a
;
1226 const nir_variable
*const *b
= in_b
;
1228 return (*a
)->data
.driver_location
- (*b
)->data
.driver_location
;
1232 ntq_emit_vpm_read(struct v3d_compile
*c
,
1233 uint32_t *num_components_queued
,
1234 uint32_t *remaining
,
1237 struct qreg vpm
= vir_reg(QFILE_VPM
, vpm_index
);
1239 if (c
->devinfo
->ver
>= 40 ) {
1240 return vir_LDVPMV_IN(c
,
1242 (*num_components_queued
)++));
1245 if (*num_components_queued
!= 0) {
1246 (*num_components_queued
)--;
1248 return vir_MOV(c
, vpm
);
1251 uint32_t num_components
= MIN2(*remaining
, 32);
1253 v3d33_vir_vpm_read_setup(c
, num_components
);
1255 *num_components_queued
= num_components
- 1;
1256 *remaining
-= num_components
;
1259 return vir_MOV(c
, vpm
);
1263 ntq_setup_inputs(struct v3d_compile
*c
)
1265 unsigned num_entries
= 0;
1266 unsigned num_components
= 0;
1267 nir_foreach_variable(var
, &c
->s
->inputs
) {
1269 num_components
+= glsl_get_components(var
->type
);
1272 nir_variable
*vars
[num_entries
];
1275 nir_foreach_variable(var
, &c
->s
->inputs
)
1278 /* Sort the variables so that we emit the input setup in
1279 * driver_location order. This is required for VPM reads, whose data
1280 * is fetched into the VPM in driver_location (TGSI register index)
1283 qsort(&vars
, num_entries
, sizeof(*vars
), driver_location_compare
);
1285 uint32_t vpm_components_queued
= 0;
1286 if (c
->s
->info
.stage
== MESA_SHADER_VERTEX
) {
1287 bool uses_iid
= c
->s
->info
.system_values_read
&
1288 (1ull << SYSTEM_VALUE_INSTANCE_ID
);
1289 bool uses_vid
= c
->s
->info
.system_values_read
&
1290 (1ull << SYSTEM_VALUE_VERTEX_ID
);
1292 num_components
+= uses_iid
;
1293 num_components
+= uses_vid
;
1296 c
->iid
= ntq_emit_vpm_read(c
, &vpm_components_queued
,
1297 &num_components
, ~0);
1301 c
->vid
= ntq_emit_vpm_read(c
, &vpm_components_queued
,
1302 &num_components
, ~0);
1306 for (unsigned i
= 0; i
< num_entries
; i
++) {
1307 nir_variable
*var
= vars
[i
];
1308 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1309 unsigned loc
= var
->data
.driver_location
;
1311 assert(array_len
== 1);
1313 resize_qreg_array(c
, &c
->inputs
, &c
->inputs_array_size
,
1316 if (c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
) {
1317 if (var
->data
.location
== VARYING_SLOT_POS
) {
1318 emit_fragcoord_input(c
, loc
);
1319 } else if (var
->data
.location
== VARYING_SLOT_PNTC
||
1320 (var
->data
.location
>= VARYING_SLOT_VAR0
&&
1321 (c
->fs_key
->point_sprite_mask
&
1322 (1 << (var
->data
.location
-
1323 VARYING_SLOT_VAR0
))))) {
1324 c
->inputs
[loc
* 4 + 0] = c
->point_x
;
1325 c
->inputs
[loc
* 4 + 1] = c
->point_y
;
1327 emit_fragment_input(c
, loc
, var
);
1330 int var_components
= glsl_get_components(var
->type
);
1332 for (int i
= 0; i
< var_components
; i
++) {
1333 c
->inputs
[loc
* 4 + i
] =
1334 ntq_emit_vpm_read(c
,
1335 &vpm_components_queued
,
1340 c
->vattr_sizes
[loc
] = var_components
;
1344 if (c
->s
->info
.stage
== MESA_SHADER_VERTEX
) {
1345 if (c
->devinfo
->ver
>= 40) {
1346 assert(vpm_components_queued
== num_components
);
1348 assert(vpm_components_queued
== 0);
1349 assert(num_components
== 0);
1355 ntq_setup_outputs(struct v3d_compile
*c
)
1357 nir_foreach_variable(var
, &c
->s
->outputs
) {
1358 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1359 unsigned loc
= var
->data
.driver_location
* 4;
1361 assert(array_len
== 1);
1364 for (int i
= 0; i
< 4; i
++) {
1365 add_output(c
, loc
+ var
->data
.location_frac
+ i
,
1367 var
->data
.location_frac
+ i
);
1370 if (c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
) {
1371 switch (var
->data
.location
) {
1372 case FRAG_RESULT_COLOR
:
1373 c
->output_color_var
[0] = var
;
1374 c
->output_color_var
[1] = var
;
1375 c
->output_color_var
[2] = var
;
1376 c
->output_color_var
[3] = var
;
1378 case FRAG_RESULT_DATA0
:
1379 case FRAG_RESULT_DATA1
:
1380 case FRAG_RESULT_DATA2
:
1381 case FRAG_RESULT_DATA3
:
1382 c
->output_color_var
[var
->data
.location
-
1383 FRAG_RESULT_DATA0
] = var
;
1385 case FRAG_RESULT_DEPTH
:
1386 c
->output_position_index
= loc
;
1388 case FRAG_RESULT_SAMPLE_MASK
:
1389 c
->output_sample_mask_index
= loc
;
1393 switch (var
->data
.location
) {
1394 case VARYING_SLOT_POS
:
1395 c
->output_position_index
= loc
;
1397 case VARYING_SLOT_PSIZ
:
1398 c
->output_point_size_index
= loc
;
1406 ntq_setup_uniforms(struct v3d_compile
*c
)
1408 nir_foreach_variable(var
, &c
->s
->uniforms
) {
1409 uint32_t vec4_count
= glsl_count_attribute_slots(var
->type
,
1411 unsigned vec4_size
= 4 * sizeof(float);
1413 declare_uniform_range(c
, var
->data
.driver_location
* vec4_size
,
1414 vec4_count
* vec4_size
);
1420 * Sets up the mapping from nir_register to struct qreg *.
1422 * Each nir_register gets a struct qreg per 32-bit component being stored.
1425 ntq_setup_registers(struct v3d_compile
*c
, struct exec_list
*list
)
1427 foreach_list_typed(nir_register
, nir_reg
, node
, list
) {
1428 unsigned array_len
= MAX2(nir_reg
->num_array_elems
, 1);
1429 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
1431 nir_reg
->num_components
);
1433 _mesa_hash_table_insert(c
->def_ht
, nir_reg
, qregs
);
1435 for (int i
= 0; i
< array_len
* nir_reg
->num_components
; i
++)
1436 qregs
[i
] = vir_get_temp(c
);
1441 ntq_emit_load_const(struct v3d_compile
*c
, nir_load_const_instr
*instr
)
1443 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1444 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1445 qregs
[i
] = vir_uniform_ui(c
, instr
->value
.u32
[i
]);
1447 _mesa_hash_table_insert(c
->def_ht
, &instr
->def
, qregs
);
1451 ntq_emit_ssa_undef(struct v3d_compile
*c
, nir_ssa_undef_instr
*instr
)
1453 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1455 /* VIR needs there to be *some* value, so pick 0 (same as for
1456 * ntq_setup_registers().
1458 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1459 qregs
[i
] = vir_uniform_ui(c
, 0);
1463 ntq_emit_intrinsic(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
)
1465 nir_const_value
*const_offset
;
1468 switch (instr
->intrinsic
) {
1469 case nir_intrinsic_load_uniform
:
1470 assert(instr
->num_components
== 1);
1471 const_offset
= nir_src_as_const_value(instr
->src
[0]);
1473 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1474 assert(offset
% 4 == 0);
1475 /* We need dwords */
1476 offset
= offset
/ 4;
1477 ntq_store_dest(c
, &instr
->dest
, 0,
1478 vir_uniform(c
, QUNIFORM_UNIFORM
,
1481 ntq_store_dest(c
, &instr
->dest
, 0,
1482 indirect_uniform_load(c
, instr
));
1486 case nir_intrinsic_load_ubo
:
1487 for (int i
= 0; i
< instr
->num_components
; i
++) {
1488 int ubo
= nir_src_as_const_value(instr
->src
[0])->u32
[0];
1490 /* Adjust for where we stored the TGSI register base. */
1492 vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_TMUA
),
1493 vir_uniform(c
, QUNIFORM_UBO_ADDR
, 1 + ubo
),
1495 ntq_get_src(c
, instr
->src
[1], 0),
1496 vir_uniform_ui(c
, i
* 4)));
1500 ntq_store_dest(c
, &instr
->dest
, i
, vir_LDTMU(c
));
1504 const_offset
= nir_src_as_const_value(instr
->src
[0]);
1506 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1507 assert(offset
% 4 == 0);
1508 /* We need dwords */
1509 offset
= offset
/ 4;
1510 ntq_store_dest(c
, &instr
->dest
, 0,
1511 vir_uniform(c
, QUNIFORM_UNIFORM
,
1514 ntq_store_dest(c
, &instr
->dest
, 0,
1515 indirect_uniform_load(c
, instr
));
1519 case nir_intrinsic_load_user_clip_plane
:
1520 for (int i
= 0; i
< instr
->num_components
; i
++) {
1521 ntq_store_dest(c
, &instr
->dest
, i
,
1522 vir_uniform(c
, QUNIFORM_USER_CLIP_PLANE
,
1523 nir_intrinsic_ucp_id(instr
) *
1528 case nir_intrinsic_load_alpha_ref_float
:
1529 ntq_store_dest(c
, &instr
->dest
, 0,
1530 vir_uniform(c
, QUNIFORM_ALPHA_REF
, 0));
1533 case nir_intrinsic_load_sample_mask_in
:
1534 ntq_store_dest(c
, &instr
->dest
, 0,
1535 vir_uniform(c
, QUNIFORM_SAMPLE_MASK
, 0));
1538 case nir_intrinsic_load_front_face
:
1539 /* The register contains 0 (front) or 1 (back), and we need to
1540 * turn it into a NIR bool where true means front.
1542 ntq_store_dest(c
, &instr
->dest
, 0,
1544 vir_uniform_ui(c
, -1),
1548 case nir_intrinsic_load_instance_id
:
1549 ntq_store_dest(c
, &instr
->dest
, 0, vir_MOV(c
, c
->iid
));
1552 case nir_intrinsic_load_vertex_id
:
1553 ntq_store_dest(c
, &instr
->dest
, 0, vir_MOV(c
, c
->vid
));
1556 case nir_intrinsic_load_input
:
1557 const_offset
= nir_src_as_const_value(instr
->src
[0]);
1558 assert(const_offset
&& "v3d doesn't support indirect inputs");
1559 for (int i
= 0; i
< instr
->num_components
; i
++) {
1560 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1561 int comp
= nir_intrinsic_component(instr
) + i
;
1562 ntq_store_dest(c
, &instr
->dest
, i
,
1563 vir_MOV(c
, c
->inputs
[offset
* 4 + comp
]));
1567 case nir_intrinsic_store_output
:
1568 const_offset
= nir_src_as_const_value(instr
->src
[1]);
1569 assert(const_offset
&& "v3d doesn't support indirect outputs");
1570 offset
= ((nir_intrinsic_base(instr
) +
1571 const_offset
->u32
[0]) * 4 +
1572 nir_intrinsic_component(instr
));
1574 for (int i
= 0; i
< instr
->num_components
; i
++) {
1575 c
->outputs
[offset
+ i
] =
1576 vir_MOV(c
, ntq_get_src(c
, instr
->src
[0], i
));
1578 c
->num_outputs
= MAX2(c
->num_outputs
,
1579 offset
+ instr
->num_components
);
1582 case nir_intrinsic_discard
:
1583 if (c
->execute
.file
!= QFILE_NULL
) {
1584 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
1585 vir_set_cond(vir_SETMSF_dest(c
, vir_reg(QFILE_NULL
, 0),
1586 vir_uniform_ui(c
, 0)),
1589 vir_SETMSF_dest(c
, vir_reg(QFILE_NULL
, 0),
1590 vir_uniform_ui(c
, 0));
1594 case nir_intrinsic_discard_if
: {
1595 /* true (~0) if we're discarding */
1596 struct qreg cond
= ntq_get_src(c
, instr
->src
[0], 0);
1598 if (c
->execute
.file
!= QFILE_NULL
) {
1599 /* execute == 0 means the channel is active. Invert
1600 * the condition so that we can use zero as "executing
1603 vir_PF(c
, vir_OR(c
, c
->execute
, vir_NOT(c
, cond
)),
1605 vir_set_cond(vir_SETMSF_dest(c
, vir_reg(QFILE_NULL
, 0),
1606 vir_uniform_ui(c
, 0)),
1609 vir_PF(c
, cond
, V3D_QPU_PF_PUSHZ
);
1610 vir_set_cond(vir_SETMSF_dest(c
, vir_reg(QFILE_NULL
, 0),
1611 vir_uniform_ui(c
, 0)),
1619 fprintf(stderr
, "Unknown intrinsic: ");
1620 nir_print_instr(&instr
->instr
, stderr
);
1621 fprintf(stderr
, "\n");
1626 /* Clears (activates) the execute flags for any channels whose jump target
1627 * matches this block.
1630 ntq_activate_execute_for_block(struct v3d_compile
*c
)
1632 vir_PF(c
, vir_XOR(c
, c
->execute
, vir_uniform_ui(c
, c
->cur_block
->index
)),
1635 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
, vir_uniform_ui(c
, 0));
1639 ntq_emit_if(struct v3d_compile
*c
, nir_if
*if_stmt
)
1641 nir_block
*nir_else_block
= nir_if_first_else_block(if_stmt
);
1642 bool empty_else_block
=
1643 (nir_else_block
== nir_if_last_else_block(if_stmt
) &&
1644 exec_list_is_empty(&nir_else_block
->instr_list
));
1646 struct qblock
*then_block
= vir_new_block(c
);
1647 struct qblock
*after_block
= vir_new_block(c
);
1648 struct qblock
*else_block
;
1649 if (empty_else_block
)
1650 else_block
= after_block
;
1652 else_block
= vir_new_block(c
);
1654 bool was_top_level
= false;
1655 if (c
->execute
.file
== QFILE_NULL
) {
1656 c
->execute
= vir_MOV(c
, vir_uniform_ui(c
, 0));
1657 was_top_level
= true;
1660 /* Set A for executing (execute == 0) and jumping (if->condition ==
1661 * 0) channels, and then update execute flags for those to point to
1666 ntq_get_src(c
, if_stmt
->condition
, 0)),
1668 vir_MOV_cond(c
, V3D_QPU_COND_IFA
,
1670 vir_uniform_ui(c
, else_block
->index
));
1672 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1675 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
1676 vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ALLNA
);
1677 vir_link_blocks(c
->cur_block
, else_block
);
1678 vir_link_blocks(c
->cur_block
, then_block
);
1680 /* Process the THEN block. */
1681 vir_set_emit_block(c
, then_block
);
1682 ntq_emit_cf_list(c
, &if_stmt
->then_list
);
1684 if (!empty_else_block
) {
1685 /* Handle the end of the THEN block. First, all currently
1686 * active channels update their execute flags to point to
1689 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
1690 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
,
1691 vir_uniform_ui(c
, after_block
->index
));
1693 /* If everything points at ENDIF, then jump there immediately. */
1694 vir_PF(c
, vir_XOR(c
, c
->execute
,
1695 vir_uniform_ui(c
, after_block
->index
)),
1697 vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ALLA
);
1698 vir_link_blocks(c
->cur_block
, after_block
);
1699 vir_link_blocks(c
->cur_block
, else_block
);
1701 vir_set_emit_block(c
, else_block
);
1702 ntq_activate_execute_for_block(c
);
1703 ntq_emit_cf_list(c
, &if_stmt
->else_list
);
1706 vir_link_blocks(c
->cur_block
, after_block
);
1708 vir_set_emit_block(c
, after_block
);
1710 c
->execute
= c
->undef
;
1712 ntq_activate_execute_for_block(c
);
1716 ntq_emit_jump(struct v3d_compile
*c
, nir_jump_instr
*jump
)
1718 switch (jump
->type
) {
1719 case nir_jump_break
:
1720 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
1721 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
,
1722 vir_uniform_ui(c
, c
->loop_break_block
->index
));
1725 case nir_jump_continue
:
1726 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
1727 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
,
1728 vir_uniform_ui(c
, c
->loop_cont_block
->index
));
1731 case nir_jump_return
:
1732 unreachable("All returns shouold be lowered\n");
1737 ntq_emit_instr(struct v3d_compile
*c
, nir_instr
*instr
)
1739 switch (instr
->type
) {
1740 case nir_instr_type_alu
:
1741 ntq_emit_alu(c
, nir_instr_as_alu(instr
));
1744 case nir_instr_type_intrinsic
:
1745 ntq_emit_intrinsic(c
, nir_instr_as_intrinsic(instr
));
1748 case nir_instr_type_load_const
:
1749 ntq_emit_load_const(c
, nir_instr_as_load_const(instr
));
1752 case nir_instr_type_ssa_undef
:
1753 ntq_emit_ssa_undef(c
, nir_instr_as_ssa_undef(instr
));
1756 case nir_instr_type_tex
:
1757 ntq_emit_tex(c
, nir_instr_as_tex(instr
));
1760 case nir_instr_type_jump
:
1761 ntq_emit_jump(c
, nir_instr_as_jump(instr
));
1765 fprintf(stderr
, "Unknown NIR instr type: ");
1766 nir_print_instr(instr
, stderr
);
1767 fprintf(stderr
, "\n");
1773 ntq_emit_block(struct v3d_compile
*c
, nir_block
*block
)
1775 nir_foreach_instr(instr
, block
) {
1776 ntq_emit_instr(c
, instr
);
1780 static void ntq_emit_cf_list(struct v3d_compile
*c
, struct exec_list
*list
);
1783 ntq_emit_loop(struct v3d_compile
*c
, nir_loop
*loop
)
1785 bool was_top_level
= false;
1786 if (c
->execute
.file
== QFILE_NULL
) {
1787 c
->execute
= vir_MOV(c
, vir_uniform_ui(c
, 0));
1788 was_top_level
= true;
1791 struct qblock
*save_loop_cont_block
= c
->loop_cont_block
;
1792 struct qblock
*save_loop_break_block
= c
->loop_break_block
;
1794 c
->loop_cont_block
= vir_new_block(c
);
1795 c
->loop_break_block
= vir_new_block(c
);
1797 vir_link_blocks(c
->cur_block
, c
->loop_cont_block
);
1798 vir_set_emit_block(c
, c
->loop_cont_block
);
1799 ntq_activate_execute_for_block(c
);
1801 ntq_emit_cf_list(c
, &loop
->body
);
1803 /* Re-enable any previous continues now, so our ANYA check below
1806 * XXX: Use the .ORZ flags update, instead.
1808 vir_PF(c
, vir_XOR(c
,
1810 vir_uniform_ui(c
, c
->loop_cont_block
->index
)),
1812 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
, vir_uniform_ui(c
, 0));
1814 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
1816 struct qinst
*branch
= vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ANYA
);
1817 /* Pixels that were not dispatched or have been discarded should not
1818 * contribute to looping again.
1820 branch
->qpu
.branch
.msfign
= V3D_QPU_MSFIGN_P
;
1821 vir_link_blocks(c
->cur_block
, c
->loop_cont_block
);
1822 vir_link_blocks(c
->cur_block
, c
->loop_break_block
);
1824 vir_set_emit_block(c
, c
->loop_break_block
);
1826 c
->execute
= c
->undef
;
1828 ntq_activate_execute_for_block(c
);
1830 c
->loop_break_block
= save_loop_break_block
;
1831 c
->loop_cont_block
= save_loop_cont_block
;
1835 ntq_emit_function(struct v3d_compile
*c
, nir_function_impl
*func
)
1837 fprintf(stderr
, "FUNCTIONS not handled.\n");
1842 ntq_emit_cf_list(struct v3d_compile
*c
, struct exec_list
*list
)
1844 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
1845 switch (node
->type
) {
1846 case nir_cf_node_block
:
1847 ntq_emit_block(c
, nir_cf_node_as_block(node
));
1850 case nir_cf_node_if
:
1851 ntq_emit_if(c
, nir_cf_node_as_if(node
));
1854 case nir_cf_node_loop
:
1855 ntq_emit_loop(c
, nir_cf_node_as_loop(node
));
1858 case nir_cf_node_function
:
1859 ntq_emit_function(c
, nir_cf_node_as_function(node
));
1863 fprintf(stderr
, "Unknown NIR node type\n");
1870 ntq_emit_impl(struct v3d_compile
*c
, nir_function_impl
*impl
)
1872 ntq_setup_registers(c
, &impl
->registers
);
1873 ntq_emit_cf_list(c
, &impl
->body
);
1877 nir_to_vir(struct v3d_compile
*c
)
1879 if (c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
) {
1880 c
->payload_w
= vir_MOV(c
, vir_reg(QFILE_REG
, 0));
1881 c
->payload_w_centroid
= vir_MOV(c
, vir_reg(QFILE_REG
, 1));
1882 c
->payload_z
= vir_MOV(c
, vir_reg(QFILE_REG
, 2));
1884 if (c
->fs_key
->is_points
) {
1885 c
->point_x
= emit_fragment_varying(c
, NULL
, 0);
1886 c
->point_y
= emit_fragment_varying(c
, NULL
, 0);
1887 } else if (c
->fs_key
->is_lines
) {
1888 c
->line_x
= emit_fragment_varying(c
, NULL
, 0);
1892 ntq_setup_inputs(c
);
1893 ntq_setup_outputs(c
);
1894 ntq_setup_uniforms(c
);
1895 ntq_setup_registers(c
, &c
->s
->registers
);
1897 /* Find the main function and emit the body. */
1898 nir_foreach_function(function
, c
->s
) {
1899 assert(strcmp(function
->name
, "main") == 0);
1900 assert(function
->impl
);
1901 ntq_emit_impl(c
, function
->impl
);
1905 const nir_shader_compiler_options v3d_nir_options
= {
1906 .lower_all_io_to_temps
= true,
1907 .lower_extract_byte
= true,
1908 .lower_extract_word
= true,
1910 .lower_bitfield_insert_to_shifts
= true,
1911 .lower_bitfield_extract_to_shifts
= true,
1912 .lower_bitfield_reverse
= true,
1913 .lower_bit_count
= true,
1914 .lower_pack_unorm_2x16
= true,
1915 .lower_pack_snorm_2x16
= true,
1916 .lower_pack_unorm_4x8
= true,
1917 .lower_pack_snorm_4x8
= true,
1918 .lower_unpack_unorm_4x8
= true,
1919 .lower_unpack_snorm_4x8
= true,
1921 .lower_find_lsb
= true,
1923 .lower_flrp32
= true,
1926 .lower_fsqrt
= true,
1927 .lower_ifind_msb
= true,
1928 .lower_ldexp
= true,
1929 .lower_mul_high
= true,
1930 .lower_wpos_pntc
= true,
1931 .native_integers
= true,
1937 count_nir_instrs(nir_shader
*nir
)
1940 nir_foreach_function(function
, nir
) {
1941 if (!function
->impl
)
1943 nir_foreach_block(block
, function
->impl
) {
1944 nir_foreach_instr(instr
, block
)
1953 * When demoting a shader down to single-threaded, removes the THRSW
1954 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
1958 vir_remove_thrsw(struct v3d_compile
*c
)
1960 vir_for_each_block(block
, c
) {
1961 vir_for_each_inst_safe(inst
, block
) {
1962 if (inst
->qpu
.sig
.thrsw
)
1963 vir_remove_instruction(c
, inst
);
1967 c
->last_thrsw
= NULL
;
1971 vir_emit_last_thrsw(struct v3d_compile
*c
)
1973 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
1974 * switching, so disable threads if we didn't do any TMU ops (each of
1975 * which would have emitted a THRSW).
1977 if (!c
->last_thrsw_at_top_level
&& c
->devinfo
->ver
< 41) {
1980 vir_remove_thrsw(c
);
1984 /* If we're threaded and the last THRSW was in conditional code, then
1985 * we need to emit another one so that we can flag it as the last
1988 if (c
->last_thrsw
&& !c
->last_thrsw_at_top_level
) {
1989 assert(c
->devinfo
->ver
>= 41);
1993 /* If we're threaded, then we need to mark the last THRSW instruction
1994 * so we can emit a pair of them at QPU emit time.
1996 * For V3D 4.x, we can spawn the non-fragment shaders already in the
1997 * post-last-THRSW state, so we can skip this.
1999 if (!c
->last_thrsw
&& c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
) {
2000 assert(c
->devinfo
->ver
>= 41);
2005 c
->last_thrsw
->is_last_thrsw
= true;
2008 /* There's a flag in the shader for "center W is needed for reasons other than
2009 * non-centroid varyings", so we just walk the program after VIR optimization
2010 * to see if it's used. It should be harmless to set even if we only use
2011 * center W for varyings.
2014 vir_check_payload_w(struct v3d_compile
*c
)
2016 if (c
->s
->info
.stage
!= MESA_SHADER_FRAGMENT
)
2019 vir_for_each_inst_inorder(inst
, c
) {
2020 for (int i
= 0; i
< vir_get_nsrc(inst
); i
++) {
2021 if (inst
->src
[i
].file
== QFILE_REG
&&
2022 inst
->src
[i
].index
== 0) {
2023 c
->uses_center_w
= true;
2032 v3d_nir_to_vir(struct v3d_compile
*c
)
2034 if (V3D_DEBUG
& (V3D_DEBUG_NIR
|
2035 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
))) {
2036 fprintf(stderr
, "%s prog %d/%d NIR:\n",
2037 vir_get_stage_name(c
),
2038 c
->program_id
, c
->variant_id
);
2039 nir_print_shader(c
->s
, stderr
);
2044 /* Emit the last THRSW before STVPM and TLB writes. */
2045 vir_emit_last_thrsw(c
);
2047 switch (c
->s
->info
.stage
) {
2048 case MESA_SHADER_FRAGMENT
:
2051 case MESA_SHADER_VERTEX
:
2055 unreachable("bad stage");
2058 if (V3D_DEBUG
& (V3D_DEBUG_VIR
|
2059 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
))) {
2060 fprintf(stderr
, "%s prog %d/%d pre-opt VIR:\n",
2061 vir_get_stage_name(c
),
2062 c
->program_id
, c
->variant_id
);
2064 fprintf(stderr
, "\n");
2068 vir_lower_uniforms(c
);
2070 vir_check_payload_w(c
);
2072 /* XXX: vir_schedule_instructions(c); */
2074 if (V3D_DEBUG
& (V3D_DEBUG_VIR
|
2075 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
))) {
2076 fprintf(stderr
, "%s prog %d/%d VIR:\n",
2077 vir_get_stage_name(c
),
2078 c
->program_id
, c
->variant_id
);
2080 fprintf(stderr
, "\n");
2083 /* Attempt to allocate registers for the temporaries. If we fail,
2084 * reduce thread count and try again.
2086 int min_threads
= (c
->devinfo
->ver
>= 41) ? 2 : 1;
2087 struct qpu_reg
*temp_registers
;
2090 temp_registers
= v3d_register_allocate(c
, &spilled
);
2097 if (c
->threads
== min_threads
) {
2098 fprintf(stderr
, "Failed to register allocate at %d threads:\n",
2107 if (c
->threads
== 1)
2108 vir_remove_thrsw(c
);
2111 v3d_vir_to_qpu(c
, temp_registers
);