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broadcom/vc5: Start hooking up multiple render targets support.
[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "v3d_compiler.h"
33
34 /* We don't do any address packing. */
35 #define __gen_user_data void
36 #define __gen_address_type uint32_t
37 #define __gen_address_offset(reloc) (*reloc)
38 #define __gen_emit_reloc(cl, reloc)
39 #include "cle/v3d_packet_v33_pack.h"
40
41 static struct qreg
42 ntq_get_src(struct v3d_compile *c, nir_src src, int i);
43 static void
44 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
45
46 static void
47 resize_qreg_array(struct v3d_compile *c,
48 struct qreg **regs,
49 uint32_t *size,
50 uint32_t decl_size)
51 {
52 if (*size >= decl_size)
53 return;
54
55 uint32_t old_size = *size;
56 *size = MAX2(*size * 2, decl_size);
57 *regs = reralloc(c, *regs, struct qreg, *size);
58 if (!*regs) {
59 fprintf(stderr, "Malloc failure\n");
60 abort();
61 }
62
63 for (uint32_t i = old_size; i < *size; i++)
64 (*regs)[i] = c->undef;
65 }
66
67 static struct qreg
68 vir_SFU(struct v3d_compile *c, int waddr, struct qreg src)
69 {
70 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, waddr), src);
71 return vir_FMOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4));
72 }
73
74 static struct qreg
75 vir_LDTMU(struct v3d_compile *c)
76 {
77 vir_NOP(c)->qpu.sig.ldtmu = true;
78 return vir_MOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4));
79 }
80
81 static struct qreg
82 indirect_uniform_load(struct v3d_compile *c, nir_intrinsic_instr *intr)
83 {
84 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
85 uint32_t offset = nir_intrinsic_base(intr);
86 struct v3d_ubo_range *range = NULL;
87 unsigned i;
88
89 for (i = 0; i < c->num_ubo_ranges; i++) {
90 range = &c->ubo_ranges[i];
91 if (offset >= range->src_offset &&
92 offset < range->src_offset + range->size) {
93 break;
94 }
95 }
96 /* The driver-location-based offset always has to be within a declared
97 * uniform range.
98 */
99 assert(i != c->num_ubo_ranges);
100 if (!c->ubo_range_used[i]) {
101 c->ubo_range_used[i] = true;
102 range->dst_offset = c->next_ubo_dst_offset;
103 c->next_ubo_dst_offset += range->size;
104 }
105
106 offset -= range->src_offset;
107
108 if (range->dst_offset + offset != 0) {
109 indirect_offset = vir_ADD(c, indirect_offset,
110 vir_uniform_ui(c, range->dst_offset +
111 offset));
112 }
113
114 /* Adjust for where we stored the TGSI register base. */
115 vir_ADD_dest(c,
116 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA),
117 vir_uniform(c, QUNIFORM_UBO_ADDR, 0),
118 indirect_offset);
119
120 return vir_LDTMU(c);
121 }
122
123 static struct qreg *
124 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
125 {
126 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
127 def->num_components);
128 _mesa_hash_table_insert(c->def_ht, def, qregs);
129 return qregs;
130 }
131
132 /**
133 * This function is responsible for getting VIR results into the associated
134 * storage for a NIR instruction.
135 *
136 * If it's a NIR SSA def, then we just set the associated hash table entry to
137 * the new result.
138 *
139 * If it's a NIR reg, then we need to update the existing qreg assigned to the
140 * NIR destination with the incoming value. To do that without introducing
141 * new MOVs, we require that the incoming qreg either be a uniform, or be
142 * SSA-defined by the previous VIR instruction in the block and rewritable by
143 * this function. That lets us sneak ahead and insert the SF flag beforehand
144 * (knowing that the previous instruction doesn't depend on flags) and rewrite
145 * its destination to be the NIR reg's destination
146 */
147 static void
148 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
149 struct qreg result)
150 {
151 struct qinst *last_inst = NULL;
152 if (!list_empty(&c->cur_block->instructions))
153 last_inst = (struct qinst *)c->cur_block->instructions.prev;
154
155 assert(result.file == QFILE_UNIF ||
156 (result.file == QFILE_TEMP &&
157 last_inst && last_inst == c->defs[result.index]));
158
159 if (dest->is_ssa) {
160 assert(chan < dest->ssa.num_components);
161
162 struct qreg *qregs;
163 struct hash_entry *entry =
164 _mesa_hash_table_search(c->def_ht, &dest->ssa);
165
166 if (entry)
167 qregs = entry->data;
168 else
169 qregs = ntq_init_ssa_def(c, &dest->ssa);
170
171 qregs[chan] = result;
172 } else {
173 nir_register *reg = dest->reg.reg;
174 assert(dest->reg.base_offset == 0);
175 assert(reg->num_array_elems == 0);
176 struct hash_entry *entry =
177 _mesa_hash_table_search(c->def_ht, reg);
178 struct qreg *qregs = entry->data;
179
180 /* Insert a MOV if the source wasn't an SSA def in the
181 * previous instruction.
182 */
183 if (result.file == QFILE_UNIF) {
184 result = vir_MOV(c, result);
185 last_inst = c->defs[result.index];
186 }
187
188 /* We know they're both temps, so just rewrite index. */
189 c->defs[last_inst->dst.index] = NULL;
190 last_inst->dst.index = qregs[chan].index;
191
192 /* If we're in control flow, then make this update of the reg
193 * conditional on the execution mask.
194 */
195 if (c->execute.file != QFILE_NULL) {
196 last_inst->dst.index = qregs[chan].index;
197
198 /* Set the flags to the current exec mask. To insert
199 * the flags push, we temporarily remove our SSA
200 * instruction.
201 */
202 list_del(&last_inst->link);
203 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
204 list_addtail(&last_inst->link,
205 &c->cur_block->instructions);
206
207 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
208 last_inst->cond_is_exec_mask = true;
209 }
210 }
211 }
212
213 static struct qreg
214 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
215 {
216 struct hash_entry *entry;
217 if (src.is_ssa) {
218 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
219 assert(i < src.ssa->num_components);
220 } else {
221 nir_register *reg = src.reg.reg;
222 entry = _mesa_hash_table_search(c->def_ht, reg);
223 assert(reg->num_array_elems == 0);
224 assert(src.reg.base_offset == 0);
225 assert(i < reg->num_components);
226 }
227
228 struct qreg *qregs = entry->data;
229 return qregs[i];
230 }
231
232 static struct qreg
233 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
234 unsigned src)
235 {
236 assert(util_is_power_of_two(instr->dest.write_mask));
237 unsigned chan = ffs(instr->dest.write_mask) - 1;
238 struct qreg r = ntq_get_src(c, instr->src[src].src,
239 instr->src[src].swizzle[chan]);
240
241 assert(!instr->src[src].abs);
242 assert(!instr->src[src].negate);
243
244 return r;
245 };
246
247 static inline struct qreg
248 vir_SAT(struct v3d_compile *c, struct qreg val)
249 {
250 return vir_FMAX(c,
251 vir_FMIN(c, val, vir_uniform_f(c, 1.0)),
252 vir_uniform_f(c, 0.0));
253 }
254
255 static struct qreg
256 ntq_umul(struct v3d_compile *c, struct qreg src0, struct qreg src1)
257 {
258 vir_MULTOP(c, src0, src1);
259 return vir_UMUL24(c, src0, src1);
260 }
261
262 static struct qreg
263 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
264 {
265 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
266 }
267
268 static void
269 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
270 {
271 unsigned unit = instr->texture_index;
272 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
273 int dest_size = nir_tex_instr_dest_size(instr);
274
275 struct qreg lod = c->undef;
276 if (lod_index != -1)
277 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
278
279 for (int i = 0; i < dest_size; i++) {
280 assert(i < 3);
281 enum quniform_contents contents;
282
283 if (instr->is_array && i == dest_size - 1)
284 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
285 else
286 contents = QUNIFORM_TEXTURE_WIDTH + i;
287
288 struct qreg size = vir_uniform(c, contents, unit);
289
290 switch (instr->sampler_dim) {
291 case GLSL_SAMPLER_DIM_1D:
292 case GLSL_SAMPLER_DIM_2D:
293 case GLSL_SAMPLER_DIM_3D:
294 case GLSL_SAMPLER_DIM_CUBE:
295 /* Don't minify the array size. */
296 if (!(instr->is_array && i == dest_size - 1)) {
297 size = ntq_minify(c, size, lod);
298 }
299 break;
300
301 case GLSL_SAMPLER_DIM_RECT:
302 /* There's no LOD field for rects */
303 break;
304
305 default:
306 unreachable("Bad sampler type");
307 }
308
309 ntq_store_dest(c, &instr->dest, i, size);
310 }
311 }
312
313 static void
314 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
315 {
316 unsigned unit = instr->texture_index;
317
318 /* Since each texture sampling op requires uploading uniforms to
319 * reference the texture, there's no HW support for texture size and
320 * you just upload uniforms containing the size.
321 */
322 switch (instr->op) {
323 case nir_texop_query_levels:
324 ntq_store_dest(c, &instr->dest, 0,
325 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
326 return;
327 case nir_texop_txs:
328 ntq_emit_txs(c, instr);
329 return;
330 default:
331 break;
332 }
333
334 struct V3D33_TEXTURE_UNIFORM_PARAMETER_0_CFG_MODE1 p0_unpacked = {
335 V3D33_TEXTURE_UNIFORM_PARAMETER_0_CFG_MODE1_header,
336
337 .fetch_sample_mode = instr->op == nir_texop_txf,
338 };
339
340 switch (instr->sampler_dim) {
341 case GLSL_SAMPLER_DIM_1D:
342 if (instr->is_array)
343 p0_unpacked.lookup_type = TEXTURE_1D_ARRAY;
344 else
345 p0_unpacked.lookup_type = TEXTURE_1D;
346 break;
347 case GLSL_SAMPLER_DIM_2D:
348 case GLSL_SAMPLER_DIM_RECT:
349 if (instr->is_array)
350 p0_unpacked.lookup_type = TEXTURE_2D_ARRAY;
351 else
352 p0_unpacked.lookup_type = TEXTURE_2D;
353 break;
354 case GLSL_SAMPLER_DIM_3D:
355 p0_unpacked.lookup_type = TEXTURE_3D;
356 break;
357 case GLSL_SAMPLER_DIM_CUBE:
358 p0_unpacked.lookup_type = TEXTURE_CUBE_MAP;
359 break;
360 default:
361 unreachable("Bad sampler type");
362 }
363
364 struct qreg coords[5];
365 int next_coord = 0;
366 for (unsigned i = 0; i < instr->num_srcs; i++) {
367 switch (instr->src[i].src_type) {
368 case nir_tex_src_coord:
369 for (int j = 0; j < instr->coord_components; j++) {
370 coords[next_coord++] =
371 ntq_get_src(c, instr->src[i].src, j);
372 }
373 if (instr->coord_components < 2)
374 coords[next_coord++] = vir_uniform_f(c, 0.5);
375 break;
376 case nir_tex_src_bias:
377 coords[next_coord++] =
378 ntq_get_src(c, instr->src[i].src, 0);
379
380 p0_unpacked.bias_supplied = true;
381 break;
382 case nir_tex_src_lod:
383 /* XXX: Needs base level addition */
384 coords[next_coord++] =
385 ntq_get_src(c, instr->src[i].src, 0);
386
387 if (instr->op != nir_texop_txf &&
388 instr->op != nir_texop_tg4) {
389 p0_unpacked.disable_autolod_use_bias_only = true;
390 }
391 break;
392 case nir_tex_src_comparator:
393 coords[next_coord++] =
394 ntq_get_src(c, instr->src[i].src, 0);
395
396 p0_unpacked.shadow = true;
397 break;
398
399 case nir_tex_src_offset: {
400 nir_const_value *offset =
401 nir_src_as_const_value(instr->src[i].src);
402 p0_unpacked.texel_offset_for_s_coordinate =
403 offset->i32[0];
404
405 if (instr->coord_components >= 2)
406 p0_unpacked.texel_offset_for_t_coordinate =
407 offset->i32[1];
408
409 if (instr->coord_components >= 3)
410 p0_unpacked.texel_offset_for_r_coordinate =
411 offset->i32[2];
412 break;
413 }
414
415 default:
416 unreachable("unknown texture source");
417 }
418 }
419
420 uint32_t p0_packed;
421 V3D33_TEXTURE_UNIFORM_PARAMETER_0_CFG_MODE1_pack(NULL,
422 (uint8_t *)&p0_packed,
423 &p0_unpacked);
424
425 /* There is no native support for GL texture rectangle coordinates, so
426 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
427 * 1]).
428 */
429 if (instr->sampler_dim == GLSL_SAMPLER_DIM_RECT) {
430 coords[0] = vir_FMUL(c, coords[0],
431 vir_uniform(c, QUNIFORM_TEXRECT_SCALE_X,
432 unit));
433 coords[1] = vir_FMUL(c, coords[1],
434 vir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y,
435 unit));
436 }
437
438 struct qreg texture_u[] = {
439 vir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0_0 + unit, p0_packed),
440 vir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
441 };
442 uint32_t next_texture_u = 0;
443
444 for (int i = 0; i < next_coord; i++) {
445 struct qreg dst;
446
447 if (i == next_coord - 1)
448 dst = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUL);
449 else
450 dst = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMU);
451
452 struct qinst *tmu = vir_MOV_dest(c, dst, coords[i]);
453
454 if (i < 2) {
455 tmu->has_implicit_uniform = true;
456 tmu->src[vir_get_implicit_uniform_src(tmu)] =
457 texture_u[next_texture_u++];
458 }
459 }
460
461 bool return_16 = (c->key->tex[unit].return_size == 16 ||
462 p0_unpacked.shadow);
463
464 struct qreg return_values[4];
465 for (int i = 0; i < c->key->tex[unit].return_channels; i++)
466 return_values[i] = vir_LDTMU(c);
467 /* Swizzling .zw of an RG texture should give undefined results, not
468 * crash the compiler.
469 */
470 for (int i = c->key->tex[unit].return_channels; i < 4; i++)
471 return_values[i] = c->undef;
472
473 for (int i = 0; i < nir_tex_instr_dest_size(instr); i++) {
474 struct qreg chan;
475
476 if (return_16) {
477 STATIC_ASSERT(PIPE_SWIZZLE_X == 0);
478 chan = return_values[i / 2];
479
480 enum v3d_qpu_input_unpack unpack;
481 if (i & 1)
482 unpack = V3D_QPU_UNPACK_H;
483 else
484 unpack = V3D_QPU_UNPACK_L;
485
486 chan = vir_FMOV(c, chan);
487 vir_set_unpack(c->defs[chan.index], 0, unpack);
488 } else {
489 chan = vir_MOV(c, return_values[i]);
490 }
491 ntq_store_dest(c, &instr->dest, i, chan);
492 }
493 }
494
495 static struct qreg
496 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
497 {
498 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
499 if (is_cos)
500 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
501
502 struct qreg periods = vir_FROUND(c, input);
503 struct qreg sin_output = vir_SFU(c, V3D_QPU_WADDR_SIN,
504 vir_FSUB(c, input, periods));
505 return vir_XOR(c, sin_output, vir_SHL(c,
506 vir_FTOIN(c, periods),
507 vir_uniform_ui(c, -1)));
508 }
509
510 static struct qreg
511 ntq_fsign(struct v3d_compile *c, struct qreg src)
512 {
513 struct qreg t = vir_get_temp(c);
514
515 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
516 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHZ);
517 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
518 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHN);
519 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
520 return vir_MOV(c, t);
521 }
522
523 static struct qreg
524 ntq_isign(struct v3d_compile *c, struct qreg src)
525 {
526 struct qreg t = vir_get_temp(c);
527
528 vir_MOV_dest(c, t, vir_uniform_ui(c, 0));
529 vir_PF(c, vir_MOV(c, src), V3D_QPU_PF_PUSHZ);
530 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_ui(c, 1));
531 vir_PF(c, vir_MOV(c, src), V3D_QPU_PF_PUSHN);
532 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_ui(c, -1));
533 return vir_MOV(c, t);
534 }
535
536 static void
537 emit_fragcoord_input(struct v3d_compile *c, int attr)
538 {
539 c->inputs[attr * 4 + 0] = vir_FXCD(c);
540 c->inputs[attr * 4 + 1] = vir_FYCD(c);
541 c->inputs[attr * 4 + 2] = c->payload_z;
542 c->inputs[attr * 4 + 3] = vir_SFU(c, V3D_QPU_WADDR_RECIP,
543 c->payload_w);
544 }
545
546 static struct qreg
547 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
548 uint8_t swizzle)
549 {
550 struct qreg vary = vir_reg(QFILE_VARY, ~0);
551 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
552
553 /* For gl_PointCoord input or distance along a line, we'll be called
554 * with no nir_variable, and we don't count toward VPM size so we
555 * don't track an input slot.
556 */
557 if (!var) {
558 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
559 }
560
561 int i = c->num_inputs++;
562 c->input_slots[i] = v3d_slot_from_slot_and_component(var->data.location,
563 swizzle);
564
565 switch (var->data.interpolation) {
566 case INTERP_MODE_NONE:
567 /* If a gl_FrontColor or gl_BackColor input has no interp
568 * qualifier, then flag it for glShadeModel() handling by the
569 * driver.
570 */
571 switch (var->data.location) {
572 case VARYING_SLOT_COL0:
573 case VARYING_SLOT_COL1:
574 case VARYING_SLOT_BFC0:
575 case VARYING_SLOT_BFC1:
576 BITSET_SET(c->shade_model_flags, i);
577 break;
578 default:
579 break;
580 }
581 /* FALLTHROUGH */
582 case INTERP_MODE_SMOOTH:
583 if (var->data.centroid) {
584 return vir_FADD(c, vir_FMUL(c, vary,
585 c->payload_w_centroid), r5);
586 } else {
587 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
588 }
589 case INTERP_MODE_NOPERSPECTIVE:
590 /* C appears after the mov from the varying.
591 XXX: improve ldvary setup.
592 */
593 return vir_FADD(c, vir_MOV(c, vary), r5);
594 case INTERP_MODE_FLAT:
595 BITSET_SET(c->flat_shade_flags, i);
596 vir_MOV_dest(c, c->undef, vary);
597 return vir_MOV(c, r5);
598 default:
599 unreachable("Bad interp mode");
600 }
601 }
602
603 static void
604 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var)
605 {
606 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
607 c->inputs[attr * 4 + i] =
608 emit_fragment_varying(c, var, i);
609 }
610 }
611
612 static void
613 add_output(struct v3d_compile *c,
614 uint32_t decl_offset,
615 uint8_t slot,
616 uint8_t swizzle)
617 {
618 uint32_t old_array_size = c->outputs_array_size;
619 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
620 decl_offset + 1);
621
622 if (old_array_size != c->outputs_array_size) {
623 c->output_slots = reralloc(c,
624 c->output_slots,
625 struct v3d_varying_slot,
626 c->outputs_array_size);
627 }
628
629 c->output_slots[decl_offset] =
630 v3d_slot_from_slot_and_component(slot, swizzle);
631 }
632
633 static void
634 declare_uniform_range(struct v3d_compile *c, uint32_t start, uint32_t size)
635 {
636 unsigned array_id = c->num_ubo_ranges++;
637 if (array_id >= c->ubo_ranges_array_size) {
638 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
639 array_id + 1);
640 c->ubo_ranges = reralloc(c, c->ubo_ranges,
641 struct v3d_ubo_range,
642 c->ubo_ranges_array_size);
643 c->ubo_range_used = reralloc(c, c->ubo_range_used,
644 bool,
645 c->ubo_ranges_array_size);
646 }
647
648 c->ubo_ranges[array_id].dst_offset = 0;
649 c->ubo_ranges[array_id].src_offset = start;
650 c->ubo_ranges[array_id].size = size;
651 c->ubo_range_used[array_id] = false;
652 }
653
654 /**
655 * If compare_instr is a valid comparison instruction, emits the
656 * compare_instr's comparison and returns the sel_instr's return value based
657 * on the compare_instr's result.
658 */
659 static bool
660 ntq_emit_comparison(struct v3d_compile *c, struct qreg *dest,
661 nir_alu_instr *compare_instr,
662 nir_alu_instr *sel_instr)
663 {
664 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
665 struct qreg src1 = ntq_get_alu_src(c, compare_instr, 1);
666 bool cond_invert = false;
667
668 switch (compare_instr->op) {
669 case nir_op_feq:
670 case nir_op_seq:
671 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHZ);
672 break;
673 case nir_op_ieq:
674 vir_PF(c, vir_XOR(c, src0, src1), V3D_QPU_PF_PUSHZ);
675 break;
676
677 case nir_op_fne:
678 case nir_op_sne:
679 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHZ);
680 cond_invert = true;
681 break;
682 case nir_op_ine:
683 vir_PF(c, vir_XOR(c, src0, src1), V3D_QPU_PF_PUSHZ);
684 cond_invert = true;
685 break;
686
687 case nir_op_fge:
688 case nir_op_sge:
689 vir_PF(c, vir_FCMP(c, src1, src0), V3D_QPU_PF_PUSHC);
690 break;
691 case nir_op_ige:
692 vir_PF(c, vir_MIN(c, src1, src0), V3D_QPU_PF_PUSHC);
693 cond_invert = true;
694 break;
695 case nir_op_uge:
696 vir_PF(c, vir_SUB(c, src0, src1), V3D_QPU_PF_PUSHC);
697 cond_invert = true;
698 break;
699
700 case nir_op_slt:
701 case nir_op_flt:
702 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHN);
703 break;
704 case nir_op_ilt:
705 vir_PF(c, vir_MIN(c, src1, src0), V3D_QPU_PF_PUSHC);
706 break;
707 case nir_op_ult:
708 vir_PF(c, vir_SUB(c, src0, src1), V3D_QPU_PF_PUSHC);
709 break;
710
711 default:
712 return false;
713 }
714
715 enum v3d_qpu_cond cond = (cond_invert ?
716 V3D_QPU_COND_IFNA :
717 V3D_QPU_COND_IFA);
718
719 switch (sel_instr->op) {
720 case nir_op_seq:
721 case nir_op_sne:
722 case nir_op_sge:
723 case nir_op_slt:
724 *dest = vir_SEL(c, cond,
725 vir_uniform_f(c, 1.0), vir_uniform_f(c, 0.0));
726 break;
727
728 case nir_op_bcsel:
729 *dest = vir_SEL(c, cond,
730 ntq_get_alu_src(c, sel_instr, 1),
731 ntq_get_alu_src(c, sel_instr, 2));
732 break;
733
734 default:
735 *dest = vir_SEL(c, cond,
736 vir_uniform_ui(c, ~0), vir_uniform_ui(c, 0));
737 break;
738 }
739
740 /* Make the temporary for nir_store_dest(). */
741 *dest = vir_MOV(c, *dest);
742
743 return true;
744 }
745
746 /**
747 * Attempts to fold a comparison generating a boolean result into the
748 * condition code for selecting between two values, instead of comparing the
749 * boolean result against 0 to generate the condition code.
750 */
751 static struct qreg ntq_emit_bcsel(struct v3d_compile *c, nir_alu_instr *instr,
752 struct qreg *src)
753 {
754 if (!instr->src[0].src.is_ssa)
755 goto out;
756 if (instr->src[0].src.ssa->parent_instr->type != nir_instr_type_alu)
757 goto out;
758 nir_alu_instr *compare =
759 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
760 if (!compare)
761 goto out;
762
763 struct qreg dest;
764 if (ntq_emit_comparison(c, &dest, compare, instr))
765 return dest;
766
767 out:
768 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
769 return vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA, src[1], src[2]));
770 }
771
772
773 static void
774 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
775 {
776 /* This should always be lowered to ALU operations for V3D. */
777 assert(!instr->dest.saturate);
778
779 /* Vectors are special in that they have non-scalarized writemasks,
780 * and just take the first swizzle channel for each argument in order
781 * into each writemask channel.
782 */
783 if (instr->op == nir_op_vec2 ||
784 instr->op == nir_op_vec3 ||
785 instr->op == nir_op_vec4) {
786 struct qreg srcs[4];
787 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
788 srcs[i] = ntq_get_src(c, instr->src[i].src,
789 instr->src[i].swizzle[0]);
790 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
791 ntq_store_dest(c, &instr->dest.dest, i,
792 vir_MOV(c, srcs[i]));
793 return;
794 }
795
796 /* General case: We can just grab the one used channel per src. */
797 struct qreg src[nir_op_infos[instr->op].num_inputs];
798 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
799 src[i] = ntq_get_alu_src(c, instr, i);
800 }
801
802 struct qreg result;
803
804 switch (instr->op) {
805 case nir_op_fmov:
806 case nir_op_imov:
807 result = vir_MOV(c, src[0]);
808 break;
809 case nir_op_fmul:
810 result = vir_FMUL(c, src[0], src[1]);
811 break;
812 case nir_op_fadd:
813 result = vir_FADD(c, src[0], src[1]);
814 break;
815 case nir_op_fsub:
816 result = vir_FSUB(c, src[0], src[1]);
817 break;
818 case nir_op_fmin:
819 result = vir_FMIN(c, src[0], src[1]);
820 break;
821 case nir_op_fmax:
822 result = vir_FMAX(c, src[0], src[1]);
823 break;
824
825 case nir_op_f2i32:
826 result = vir_FTOIZ(c, src[0]);
827 break;
828 case nir_op_f2u32:
829 result = vir_FTOUZ(c, src[0]);
830 break;
831 case nir_op_i2f32:
832 result = vir_ITOF(c, src[0]);
833 break;
834 case nir_op_u2f32:
835 result = vir_UTOF(c, src[0]);
836 break;
837 case nir_op_b2f:
838 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
839 break;
840 case nir_op_b2i:
841 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
842 break;
843 case nir_op_i2b:
844 case nir_op_f2b:
845 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
846 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
847 vir_uniform_ui(c, ~0),
848 vir_uniform_ui(c, 0)));
849 break;
850
851 case nir_op_iadd:
852 result = vir_ADD(c, src[0], src[1]);
853 break;
854 case nir_op_ushr:
855 result = vir_SHR(c, src[0], src[1]);
856 break;
857 case nir_op_isub:
858 result = vir_SUB(c, src[0], src[1]);
859 break;
860 case nir_op_ishr:
861 result = vir_ASR(c, src[0], src[1]);
862 break;
863 case nir_op_ishl:
864 result = vir_SHL(c, src[0], src[1]);
865 break;
866 case nir_op_imin:
867 result = vir_MIN(c, src[0], src[1]);
868 break;
869 case nir_op_umin:
870 result = vir_UMIN(c, src[0], src[1]);
871 break;
872 case nir_op_imax:
873 result = vir_MAX(c, src[0], src[1]);
874 break;
875 case nir_op_umax:
876 result = vir_UMAX(c, src[0], src[1]);
877 break;
878 case nir_op_iand:
879 result = vir_AND(c, src[0], src[1]);
880 break;
881 case nir_op_ior:
882 result = vir_OR(c, src[0], src[1]);
883 break;
884 case nir_op_ixor:
885 result = vir_XOR(c, src[0], src[1]);
886 break;
887 case nir_op_inot:
888 result = vir_NOT(c, src[0]);
889 break;
890
891 case nir_op_imul:
892 result = ntq_umul(c, src[0], src[1]);
893 break;
894
895 case nir_op_seq:
896 case nir_op_sne:
897 case nir_op_sge:
898 case nir_op_slt:
899 case nir_op_feq:
900 case nir_op_fne:
901 case nir_op_fge:
902 case nir_op_flt:
903 case nir_op_ieq:
904 case nir_op_ine:
905 case nir_op_ige:
906 case nir_op_uge:
907 case nir_op_ilt:
908 case nir_op_ult:
909 if (!ntq_emit_comparison(c, &result, instr, instr)) {
910 fprintf(stderr, "Bad comparison instruction\n");
911 }
912 break;
913
914 case nir_op_bcsel:
915 result = ntq_emit_bcsel(c, instr, src);
916 break;
917 case nir_op_fcsel:
918 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
919 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
920 src[1], src[2]));
921 break;
922
923 case nir_op_frcp:
924 result = vir_SFU(c, V3D_QPU_WADDR_RECIP, src[0]);
925 break;
926 case nir_op_frsq:
927 result = vir_SFU(c, V3D_QPU_WADDR_RSQRT, src[0]);
928 break;
929 case nir_op_fexp2:
930 result = vir_SFU(c, V3D_QPU_WADDR_EXP, src[0]);
931 break;
932 case nir_op_flog2:
933 result = vir_SFU(c, V3D_QPU_WADDR_LOG, src[0]);
934 break;
935
936 case nir_op_fceil:
937 result = vir_FCEIL(c, src[0]);
938 break;
939 case nir_op_ffloor:
940 result = vir_FFLOOR(c, src[0]);
941 break;
942 case nir_op_fround_even:
943 result = vir_FROUND(c, src[0]);
944 break;
945 case nir_op_ftrunc:
946 result = vir_FTRUNC(c, src[0]);
947 break;
948 case nir_op_ffract:
949 result = vir_FSUB(c, src[0], vir_FFLOOR(c, src[0]));
950 break;
951
952 case nir_op_fsin:
953 result = ntq_fsincos(c, src[0], false);
954 break;
955 case nir_op_fcos:
956 result = ntq_fsincos(c, src[0], true);
957 break;
958
959 case nir_op_fsign:
960 result = ntq_fsign(c, src[0]);
961 break;
962 case nir_op_isign:
963 result = ntq_isign(c, src[0]);
964 break;
965
966 case nir_op_fabs: {
967 result = vir_FMOV(c, src[0]);
968 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
969 break;
970 }
971
972 case nir_op_iabs:
973 result = vir_MAX(c, src[0],
974 vir_SUB(c, vir_uniform_ui(c, 0), src[0]));
975 break;
976
977 case nir_op_fddx:
978 case nir_op_fddx_coarse:
979 case nir_op_fddx_fine:
980 result = vir_FDX(c, src[0]);
981 break;
982
983 case nir_op_fddy:
984 case nir_op_fddy_coarse:
985 case nir_op_fddy_fine:
986 result = vir_FDY(c, src[0]);
987 break;
988
989 default:
990 fprintf(stderr, "unknown NIR ALU inst: ");
991 nir_print_instr(&instr->instr, stderr);
992 fprintf(stderr, "\n");
993 abort();
994 }
995
996 /* We have a scalar result, so the instruction should only have a
997 * single channel written to.
998 */
999 assert(util_is_power_of_two(instr->dest.write_mask));
1000 ntq_store_dest(c, &instr->dest.dest,
1001 ffs(instr->dest.write_mask) - 1, result);
1002 }
1003
1004 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
1005 * specifier. They come from a register that's preloaded with 0xffffffff
1006 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
1007 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
1008 */
1009 #define TLB_TYPE_F16_COLOR (3 << 6)
1010 #define TLB_TYPE_I32_COLOR (1 << 6)
1011 #define TLB_TYPE_F32_COLOR (0 << 6)
1012 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
1013 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
1014 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
1015 #define TLB_F16_SWAP_HI_LO (1 << 1)
1016 #define TLB_VEC_SIZE_4_F16 (1 << 0)
1017 #define TLB_VEC_SIZE_2_F16 (0 << 0)
1018 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
1019
1020 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
1021 * flag is set.
1022 */
1023 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
1024 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
1025 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
1026
1027 /* Stencil is a single 32-bit write. */
1028 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1029
1030 static void
1031 emit_frag_end(struct v3d_compile *c)
1032 {
1033 uint32_t discard_cond = V3D_QPU_COND_NONE;
1034 if (c->s->info.fs.uses_discard) {
1035 vir_PF(c, vir_MOV(c, c->discard), V3D_QPU_PF_PUSHZ);
1036 discard_cond = V3D_QPU_COND_IFA;
1037 }
1038
1039 /* XXX
1040 if (c->output_sample_mask_index != -1) {
1041 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1042 }
1043 */
1044
1045 if (c->output_position_index != -1) {
1046 struct qinst *inst = vir_MOV_dest(c,
1047 vir_reg(QFILE_TLBU, 0),
1048 c->outputs[c->output_position_index]);
1049 vir_set_cond(inst, discard_cond);
1050
1051 inst->src[vir_get_implicit_uniform_src(inst)] =
1052 vir_uniform_ui(c,
1053 TLB_TYPE_DEPTH |
1054 TLB_DEPTH_TYPE_PER_PIXEL |
1055 0xffffff00);
1056 } else if (c->s->info.fs.uses_discard) {
1057 struct qinst *inst = vir_MOV_dest(c,
1058 vir_reg(QFILE_TLBU, 0),
1059 vir_reg(QFILE_NULL, 0));
1060 vir_set_cond(inst, discard_cond);
1061
1062 inst->src[vir_get_implicit_uniform_src(inst)] =
1063 vir_uniform_ui(c,
1064 TLB_TYPE_DEPTH |
1065 TLB_DEPTH_TYPE_INVARIANT |
1066 0xffffff00);
1067 }
1068
1069 /* XXX: Performance improvement: Merge Z write and color writes TLB
1070 * uniform setup
1071 */
1072
1073 for (int rt = 0; rt < c->fs_key->nr_cbufs; rt++) {
1074 if (!c->output_color_var[rt])
1075 continue;
1076
1077 nir_variable *var = c->output_color_var[rt];
1078 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1079 int num_components = glsl_get_vector_elements(var->type);
1080 uint32_t conf = 0xffffff00;
1081 struct qinst *inst;
1082
1083 conf |= TLB_SAMPLE_MODE_PER_PIXEL;
1084 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1085
1086 assert(num_components != 0);
1087 switch (glsl_get_base_type(var->type)) {
1088 case GLSL_TYPE_UINT:
1089 case GLSL_TYPE_INT:
1090 conf |= TLB_TYPE_I32_COLOR;
1091 conf |= ((num_components - 1) <<
1092 TLB_VEC_SIZE_MINUS_1_SHIFT);
1093
1094 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
1095 vir_set_cond(inst, discard_cond);
1096 inst->src[vir_get_implicit_uniform_src(inst)] =
1097 vir_uniform_ui(c, conf);
1098
1099 for (int i = 1; i < num_components; i++) {
1100 inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
1101 color[i]);
1102 vir_set_cond(inst, discard_cond);
1103 }
1104 break;
1105
1106 default: {
1107 struct qreg r = color[0];
1108 struct qreg g = color[1];
1109 struct qreg b = color[2];
1110 struct qreg a = color[3];
1111
1112 conf |= TLB_TYPE_F16_COLOR;
1113 conf |= TLB_F16_SWAP_HI_LO;
1114 if (num_components >= 3)
1115 conf |= TLB_VEC_SIZE_4_F16;
1116 else
1117 conf |= TLB_VEC_SIZE_2_F16;
1118
1119 if (c->fs_key->swap_color_rb & (1 << rt)) {
1120 r = color[2];
1121 b = color[0];
1122 }
1123
1124 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), r, g);
1125 if (conf != ~0) {
1126 inst->dst.file = QFILE_TLBU;
1127 inst->src[vir_get_implicit_uniform_src(inst)] =
1128 vir_uniform_ui(c, conf);
1129 }
1130 vir_set_cond(inst, discard_cond);
1131
1132 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), b, a);
1133 vir_set_cond(inst, discard_cond);
1134 break;
1135 }
1136 }
1137 }
1138 }
1139
1140 static void
1141 emit_scaled_viewport_write(struct v3d_compile *c, struct qreg rcp_w)
1142 {
1143 for (int i = 0; i < 2; i++) {
1144 struct qreg coord = c->outputs[c->output_position_index + i];
1145 coord = vir_FMUL(c, coord,
1146 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i,
1147 0));
1148 coord = vir_FMUL(c, coord, rcp_w);
1149 vir_FTOIN_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM),
1150 coord);
1151 }
1152
1153 }
1154
1155 static void
1156 emit_zs_write(struct v3d_compile *c, struct qreg rcp_w)
1157 {
1158 struct qreg zscale = vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1159 struct qreg zoffset = vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1160
1161 vir_FADD_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM),
1162 vir_FMUL(c, vir_FMUL(c,
1163 c->outputs[c->output_position_index + 2],
1164 zscale),
1165 rcp_w),
1166 zoffset);
1167 }
1168
1169 static void
1170 emit_rcp_wc_write(struct v3d_compile *c, struct qreg rcp_w)
1171 {
1172 vir_VPM_WRITE(c, rcp_w);
1173 }
1174
1175 static void
1176 emit_point_size_write(struct v3d_compile *c)
1177 {
1178 struct qreg point_size;
1179
1180 if (c->output_point_size_index != -1)
1181 point_size = c->outputs[c->output_point_size_index];
1182 else
1183 point_size = vir_uniform_f(c, 1.0);
1184
1185 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1186 * BCM21553).
1187 */
1188 point_size = vir_FMAX(c, point_size, vir_uniform_f(c, .125));
1189
1190 vir_VPM_WRITE(c, point_size);
1191 }
1192
1193 static void
1194 emit_vpm_write_setup(struct v3d_compile *c)
1195 {
1196 uint32_t packed;
1197 struct V3D33_VPM_GENERIC_BLOCK_WRITE_SETUP unpacked = {
1198 V3D33_VPM_GENERIC_BLOCK_WRITE_SETUP_header,
1199
1200 .horiz = true,
1201 .laned = false,
1202 .segs = true,
1203 .stride = 1,
1204 .size = VPM_SETUP_SIZE_32_BIT,
1205 .addr = 0,
1206 };
1207
1208 V3D33_VPM_GENERIC_BLOCK_WRITE_SETUP_pack(NULL,
1209 (uint8_t *)&packed,
1210 &unpacked);
1211 vir_VPMSETUP(c, vir_uniform_ui(c, packed));
1212 }
1213
1214 static void
1215 emit_vert_end(struct v3d_compile *c)
1216 {
1217 struct qreg rcp_w = vir_SFU(c, V3D_QPU_WADDR_RECIP,
1218 c->outputs[c->output_position_index + 3]);
1219
1220 emit_vpm_write_setup(c);
1221
1222 if (c->vs_key->is_coord) {
1223 for (int i = 0; i < 4; i++)
1224 vir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1225 emit_scaled_viewport_write(c, rcp_w);
1226 if (c->vs_key->per_vertex_point_size) {
1227 emit_point_size_write(c);
1228 /* emit_rcp_wc_write(c, rcp_w); */
1229 }
1230 /* XXX: Z-only rendering */
1231 if (0)
1232 emit_zs_write(c, rcp_w);
1233 } else {
1234 emit_scaled_viewport_write(c, rcp_w);
1235 emit_zs_write(c, rcp_w);
1236 emit_rcp_wc_write(c, rcp_w);
1237 if (c->vs_key->per_vertex_point_size)
1238 emit_point_size_write(c);
1239 }
1240
1241 for (int i = 0; i < c->vs_key->num_fs_inputs; i++) {
1242 struct v3d_varying_slot input = c->vs_key->fs_inputs[i];
1243 int j;
1244
1245 for (j = 0; j < c->num_outputs; j++) {
1246 struct v3d_varying_slot output = c->output_slots[j];
1247
1248 if (!memcmp(&input, &output, sizeof(input))) {
1249 vir_VPM_WRITE(c, c->outputs[j]);
1250 break;
1251 }
1252 }
1253 /* Emit padding if we didn't find a declared VS output for
1254 * this FS input.
1255 */
1256 if (j == c->num_outputs)
1257 vir_VPM_WRITE(c, vir_uniform_f(c, 0.0));
1258 }
1259 }
1260
1261 void
1262 v3d_optimize_nir(struct nir_shader *s)
1263 {
1264 bool progress;
1265
1266 do {
1267 progress = false;
1268
1269 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1270 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1271 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1272 NIR_PASS(progress, s, nir_copy_prop);
1273 NIR_PASS(progress, s, nir_opt_remove_phis);
1274 NIR_PASS(progress, s, nir_opt_dce);
1275 NIR_PASS(progress, s, nir_opt_dead_cf);
1276 NIR_PASS(progress, s, nir_opt_cse);
1277 NIR_PASS(progress, s, nir_opt_peephole_select, 8);
1278 NIR_PASS(progress, s, nir_opt_algebraic);
1279 NIR_PASS(progress, s, nir_opt_constant_folding);
1280 NIR_PASS(progress, s, nir_opt_undef);
1281 } while (progress);
1282 }
1283
1284 static int
1285 driver_location_compare(const void *in_a, const void *in_b)
1286 {
1287 const nir_variable *const *a = in_a;
1288 const nir_variable *const *b = in_b;
1289
1290 return (*a)->data.driver_location - (*b)->data.driver_location;
1291 }
1292
1293 static struct qreg
1294 ntq_emit_vpm_read(struct v3d_compile *c,
1295 uint32_t *num_components_queued,
1296 uint32_t *remaining,
1297 uint32_t vpm_index)
1298 {
1299 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1300
1301 if (*num_components_queued != 0) {
1302 (*num_components_queued)--;
1303 c->num_inputs++;
1304 return vir_MOV(c, vpm);
1305 }
1306
1307 uint32_t num_components = MIN2(*remaining, 32);
1308
1309 struct V3D33_VPM_GENERIC_BLOCK_READ_SETUP unpacked = {
1310 V3D33_VPM_GENERIC_BLOCK_READ_SETUP_header,
1311
1312 .horiz = true,
1313 .laned = false,
1314 /* If the field is 0, that means a read count of 32. */
1315 .num = num_components & 31,
1316 .segs = true,
1317 .stride = 1,
1318 .size = VPM_SETUP_SIZE_32_BIT,
1319 .addr = c->num_inputs,
1320 };
1321
1322 uint32_t packed;
1323 V3D33_VPM_GENERIC_BLOCK_READ_SETUP_pack(NULL,
1324 (uint8_t *)&packed,
1325 &unpacked);
1326 vir_VPMSETUP(c, vir_uniform_ui(c, packed));
1327
1328 *num_components_queued = num_components - 1;
1329 *remaining -= num_components;
1330 c->num_inputs++;
1331
1332 return vir_MOV(c, vpm);
1333 }
1334
1335 static void
1336 ntq_setup_inputs(struct v3d_compile *c)
1337 {
1338 unsigned num_entries = 0;
1339 unsigned num_components = 0;
1340 nir_foreach_variable(var, &c->s->inputs) {
1341 num_entries++;
1342 num_components += glsl_get_components(var->type);
1343 }
1344
1345 nir_variable *vars[num_entries];
1346
1347 unsigned i = 0;
1348 nir_foreach_variable(var, &c->s->inputs)
1349 vars[i++] = var;
1350
1351 /* Sort the variables so that we emit the input setup in
1352 * driver_location order. This is required for VPM reads, whose data
1353 * is fetched into the VPM in driver_location (TGSI register index)
1354 * order.
1355 */
1356 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1357
1358 uint32_t vpm_components_queued = 0;
1359 if (c->s->stage == MESA_SHADER_VERTEX) {
1360 bool uses_iid = c->s->info.system_values_read &
1361 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1362 bool uses_vid = c->s->info.system_values_read &
1363 (1ull << SYSTEM_VALUE_VERTEX_ID);
1364
1365 num_components += uses_iid;
1366 num_components += uses_vid;
1367
1368 if (uses_iid) {
1369 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1370 &num_components, ~0);
1371 }
1372
1373 if (uses_vid) {
1374 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1375 &num_components, ~0);
1376 }
1377 }
1378
1379 for (unsigned i = 0; i < num_entries; i++) {
1380 nir_variable *var = vars[i];
1381 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1382 unsigned loc = var->data.driver_location;
1383
1384 assert(array_len == 1);
1385 (void)array_len;
1386 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1387 (loc + 1) * 4);
1388
1389 if (c->s->stage == MESA_SHADER_FRAGMENT) {
1390 if (var->data.location == VARYING_SLOT_POS) {
1391 emit_fragcoord_input(c, loc);
1392 } else if (var->data.location == VARYING_SLOT_PNTC ||
1393 (var->data.location >= VARYING_SLOT_VAR0 &&
1394 (c->fs_key->point_sprite_mask &
1395 (1 << (var->data.location -
1396 VARYING_SLOT_VAR0))))) {
1397 c->inputs[loc * 4 + 0] = c->point_x;
1398 c->inputs[loc * 4 + 1] = c->point_y;
1399 } else {
1400 emit_fragment_input(c, loc, var);
1401 }
1402 } else {
1403 int var_components = glsl_get_components(var->type);
1404
1405 for (int i = 0; i < var_components; i++) {
1406 c->inputs[loc * 4 + i] =
1407 ntq_emit_vpm_read(c,
1408 &vpm_components_queued,
1409 &num_components,
1410 loc * 4 + i);
1411
1412 }
1413 c->vattr_sizes[loc] = var_components;
1414 }
1415 }
1416
1417 if (c->s->stage == MESA_SHADER_VERTEX) {
1418 assert(vpm_components_queued == 0);
1419 assert(num_components == 0);
1420 }
1421 }
1422
1423 static void
1424 ntq_setup_outputs(struct v3d_compile *c)
1425 {
1426 nir_foreach_variable(var, &c->s->outputs) {
1427 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1428 unsigned loc = var->data.driver_location * 4;
1429
1430 assert(array_len == 1);
1431 (void)array_len;
1432
1433 for (int i = 0; i < 4; i++)
1434 add_output(c, loc + i, var->data.location, i);
1435
1436 if (c->s->stage == MESA_SHADER_FRAGMENT) {
1437 switch (var->data.location) {
1438 case FRAG_RESULT_COLOR:
1439 c->output_color_var[0] = var;
1440 c->output_color_var[1] = var;
1441 c->output_color_var[2] = var;
1442 c->output_color_var[3] = var;
1443 break;
1444 case FRAG_RESULT_DATA0:
1445 case FRAG_RESULT_DATA1:
1446 case FRAG_RESULT_DATA2:
1447 case FRAG_RESULT_DATA3:
1448 c->output_color_var[var->data.location -
1449 FRAG_RESULT_DATA0] = var;
1450 break;
1451 case FRAG_RESULT_DEPTH:
1452 c->output_position_index = loc;
1453 break;
1454 case FRAG_RESULT_SAMPLE_MASK:
1455 c->output_sample_mask_index = loc;
1456 break;
1457 }
1458 } else {
1459 switch (var->data.location) {
1460 case VARYING_SLOT_POS:
1461 c->output_position_index = loc;
1462 break;
1463 case VARYING_SLOT_PSIZ:
1464 c->output_point_size_index = loc;
1465 break;
1466 }
1467 }
1468 }
1469 }
1470
1471 static void
1472 ntq_setup_uniforms(struct v3d_compile *c)
1473 {
1474 nir_foreach_variable(var, &c->s->uniforms) {
1475 uint32_t vec4_count = glsl_count_attribute_slots(var->type,
1476 false);
1477 unsigned vec4_size = 4 * sizeof(float);
1478
1479 declare_uniform_range(c, var->data.driver_location * vec4_size,
1480 vec4_count * vec4_size);
1481
1482 }
1483 }
1484
1485 /**
1486 * Sets up the mapping from nir_register to struct qreg *.
1487 *
1488 * Each nir_register gets a struct qreg per 32-bit component being stored.
1489 */
1490 static void
1491 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1492 {
1493 foreach_list_typed(nir_register, nir_reg, node, list) {
1494 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1495 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1496 array_len *
1497 nir_reg->num_components);
1498
1499 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1500
1501 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1502 qregs[i] = vir_get_temp(c);
1503 }
1504 }
1505
1506 static void
1507 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1508 {
1509 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1510 for (int i = 0; i < instr->def.num_components; i++)
1511 qregs[i] = vir_uniform_ui(c, instr->value.u32[i]);
1512
1513 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1514 }
1515
1516 static void
1517 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1518 {
1519 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1520
1521 /* VIR needs there to be *some* value, so pick 0 (same as for
1522 * ntq_setup_registers().
1523 */
1524 for (int i = 0; i < instr->def.num_components; i++)
1525 qregs[i] = vir_uniform_ui(c, 0);
1526 }
1527
1528 static void
1529 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
1530 {
1531 nir_const_value *const_offset;
1532 unsigned offset;
1533
1534 switch (instr->intrinsic) {
1535 case nir_intrinsic_load_uniform:
1536 assert(instr->num_components == 1);
1537 const_offset = nir_src_as_const_value(instr->src[0]);
1538 if (const_offset) {
1539 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1540 assert(offset % 4 == 0);
1541 /* We need dwords */
1542 offset = offset / 4;
1543 ntq_store_dest(c, &instr->dest, 0,
1544 vir_uniform(c, QUNIFORM_UNIFORM,
1545 offset));
1546 } else {
1547 ntq_store_dest(c, &instr->dest, 0,
1548 indirect_uniform_load(c, instr));
1549 }
1550 break;
1551
1552 case nir_intrinsic_load_ubo:
1553 for (int i = 0; i < instr->num_components; i++) {
1554 int ubo = nir_src_as_const_value(instr->src[0])->u32[0];
1555
1556 /* Adjust for where we stored the TGSI register base. */
1557 vir_ADD_dest(c,
1558 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA),
1559 vir_uniform(c, QUNIFORM_UBO_ADDR, 1 + ubo),
1560 vir_ADD(c,
1561 ntq_get_src(c, instr->src[1], 0),
1562 vir_uniform_ui(c, i * 4)));
1563
1564 ntq_store_dest(c, &instr->dest, i, vir_LDTMU(c));
1565 }
1566 break;
1567
1568 const_offset = nir_src_as_const_value(instr->src[0]);
1569 if (const_offset) {
1570 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1571 assert(offset % 4 == 0);
1572 /* We need dwords */
1573 offset = offset / 4;
1574 ntq_store_dest(c, &instr->dest, 0,
1575 vir_uniform(c, QUNIFORM_UNIFORM,
1576 offset));
1577 } else {
1578 ntq_store_dest(c, &instr->dest, 0,
1579 indirect_uniform_load(c, instr));
1580 }
1581 break;
1582
1583 case nir_intrinsic_load_user_clip_plane:
1584 for (int i = 0; i < instr->num_components; i++) {
1585 ntq_store_dest(c, &instr->dest, i,
1586 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1587 nir_intrinsic_ucp_id(instr) *
1588 4 + i));
1589 }
1590 break;
1591
1592 case nir_intrinsic_load_alpha_ref_float:
1593 ntq_store_dest(c, &instr->dest, 0,
1594 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1595 break;
1596
1597 case nir_intrinsic_load_sample_mask_in:
1598 ntq_store_dest(c, &instr->dest, 0,
1599 vir_uniform(c, QUNIFORM_SAMPLE_MASK, 0));
1600 break;
1601
1602 case nir_intrinsic_load_front_face:
1603 /* The register contains 0 (front) or 1 (back), and we need to
1604 * turn it into a NIR bool where true means front.
1605 */
1606 ntq_store_dest(c, &instr->dest, 0,
1607 vir_ADD(c,
1608 vir_uniform_ui(c, -1),
1609 vir_REVF(c)));
1610 break;
1611
1612 case nir_intrinsic_load_instance_id:
1613 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
1614 break;
1615
1616 case nir_intrinsic_load_vertex_id:
1617 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
1618 break;
1619
1620 case nir_intrinsic_load_input:
1621 const_offset = nir_src_as_const_value(instr->src[0]);
1622 assert(const_offset && "v3d doesn't support indirect inputs");
1623 for (int i = 0; i < instr->num_components; i++) {
1624 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1625 int comp = nir_intrinsic_component(instr) + i;
1626 ntq_store_dest(c, &instr->dest, i,
1627 vir_MOV(c, c->inputs[offset * 4 + comp]));
1628 }
1629 break;
1630
1631 case nir_intrinsic_store_output:
1632 const_offset = nir_src_as_const_value(instr->src[1]);
1633 assert(const_offset && "v3d doesn't support indirect outputs");
1634 offset = ((nir_intrinsic_base(instr) +
1635 const_offset->u32[0]) * 4 +
1636 nir_intrinsic_component(instr));
1637
1638 for (int i = 0; i < instr->num_components; i++) {
1639 c->outputs[offset + i] =
1640 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
1641 }
1642 c->num_outputs = MAX2(c->num_outputs,
1643 offset + instr->num_components);
1644 break;
1645
1646 case nir_intrinsic_discard:
1647 if (c->execute.file != QFILE_NULL) {
1648 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1649 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->discard,
1650 vir_uniform_ui(c, ~0));
1651 } else {
1652 vir_MOV_dest(c, c->discard, vir_uniform_ui(c, ~0));
1653 }
1654 break;
1655
1656 case nir_intrinsic_discard_if: {
1657 /* true (~0) if we're discarding */
1658 struct qreg cond = ntq_get_src(c, instr->src[0], 0);
1659
1660 if (c->execute.file != QFILE_NULL) {
1661 /* execute == 0 means the channel is active. Invert
1662 * the condition so that we can use zero as "executing
1663 * and discarding."
1664 */
1665 vir_PF(c, vir_AND(c, c->execute, vir_NOT(c, cond)),
1666 V3D_QPU_PF_PUSHZ);
1667 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->discard, cond);
1668 } else {
1669 vir_OR_dest(c, c->discard, c->discard, cond);
1670 }
1671
1672 break;
1673 }
1674
1675 default:
1676 fprintf(stderr, "Unknown intrinsic: ");
1677 nir_print_instr(&instr->instr, stderr);
1678 fprintf(stderr, "\n");
1679 break;
1680 }
1681 }
1682
1683 /* Clears (activates) the execute flags for any channels whose jump target
1684 * matches this block.
1685 */
1686 static void
1687 ntq_activate_execute_for_block(struct v3d_compile *c)
1688 {
1689 vir_PF(c, vir_SUB(c, c->execute, vir_uniform_ui(c, c->cur_block->index)),
1690 V3D_QPU_PF_PUSHZ);
1691
1692 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
1693 }
1694
1695 static void
1696 ntq_emit_if(struct v3d_compile *c, nir_if *if_stmt)
1697 {
1698 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
1699 bool empty_else_block =
1700 (nir_else_block == nir_if_last_else_block(if_stmt) &&
1701 exec_list_is_empty(&nir_else_block->instr_list));
1702
1703 struct qblock *then_block = vir_new_block(c);
1704 struct qblock *after_block = vir_new_block(c);
1705 struct qblock *else_block;
1706 if (empty_else_block)
1707 else_block = after_block;
1708 else
1709 else_block = vir_new_block(c);
1710
1711 bool was_top_level = false;
1712 if (c->execute.file == QFILE_NULL) {
1713 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
1714 was_top_level = true;
1715 }
1716
1717 /* Set A for executing (execute == 0) and jumping (if->condition ==
1718 * 0) channels, and then update execute flags for those to point to
1719 * the ELSE block.
1720 */
1721 vir_PF(c, vir_OR(c,
1722 c->execute,
1723 ntq_get_src(c, if_stmt->condition, 0)),
1724 V3D_QPU_PF_PUSHZ);
1725 vir_MOV_cond(c, V3D_QPU_COND_IFA,
1726 c->execute,
1727 vir_uniform_ui(c, else_block->index));
1728
1729 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1730 * through.
1731 */
1732 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1733 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
1734 vir_link_blocks(c->cur_block, else_block);
1735 vir_link_blocks(c->cur_block, then_block);
1736
1737 /* Process the THEN block. */
1738 vir_set_emit_block(c, then_block);
1739 ntq_emit_cf_list(c, &if_stmt->then_list);
1740
1741 if (!empty_else_block) {
1742 /* Handle the end of the THEN block. First, all currently
1743 * active channels update their execute flags to point to
1744 * ENDIF
1745 */
1746 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1747 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1748 vir_uniform_ui(c, after_block->index));
1749
1750 /* If everything points at ENDIF, then jump there immediately. */
1751 vir_PF(c, vir_SUB(c, c->execute,
1752 vir_uniform_ui(c, after_block->index)),
1753 V3D_QPU_PF_PUSHZ);
1754 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
1755 vir_link_blocks(c->cur_block, after_block);
1756 vir_link_blocks(c->cur_block, else_block);
1757
1758 vir_set_emit_block(c, else_block);
1759 ntq_activate_execute_for_block(c);
1760 ntq_emit_cf_list(c, &if_stmt->else_list);
1761 }
1762
1763 vir_link_blocks(c->cur_block, after_block);
1764
1765 vir_set_emit_block(c, after_block);
1766 if (was_top_level)
1767 c->execute = c->undef;
1768 else
1769 ntq_activate_execute_for_block(c);
1770 }
1771
1772 static void
1773 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
1774 {
1775 switch (jump->type) {
1776 case nir_jump_break:
1777 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1778 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1779 vir_uniform_ui(c, c->loop_break_block->index));
1780 break;
1781
1782 case nir_jump_continue:
1783 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1784 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1785 vir_uniform_ui(c, c->loop_cont_block->index));
1786 break;
1787
1788 case nir_jump_return:
1789 unreachable("All returns shouold be lowered\n");
1790 }
1791 }
1792
1793 static void
1794 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
1795 {
1796 switch (instr->type) {
1797 case nir_instr_type_alu:
1798 ntq_emit_alu(c, nir_instr_as_alu(instr));
1799 break;
1800
1801 case nir_instr_type_intrinsic:
1802 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
1803 break;
1804
1805 case nir_instr_type_load_const:
1806 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
1807 break;
1808
1809 case nir_instr_type_ssa_undef:
1810 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
1811 break;
1812
1813 case nir_instr_type_tex:
1814 ntq_emit_tex(c, nir_instr_as_tex(instr));
1815 break;
1816
1817 case nir_instr_type_jump:
1818 ntq_emit_jump(c, nir_instr_as_jump(instr));
1819 break;
1820
1821 default:
1822 fprintf(stderr, "Unknown NIR instr type: ");
1823 nir_print_instr(instr, stderr);
1824 fprintf(stderr, "\n");
1825 abort();
1826 }
1827 }
1828
1829 static void
1830 ntq_emit_block(struct v3d_compile *c, nir_block *block)
1831 {
1832 nir_foreach_instr(instr, block) {
1833 ntq_emit_instr(c, instr);
1834 }
1835 }
1836
1837 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
1838
1839 static void
1840 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
1841 {
1842 bool was_top_level = false;
1843 if (c->execute.file == QFILE_NULL) {
1844 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
1845 was_top_level = true;
1846 }
1847
1848 struct qblock *save_loop_cont_block = c->loop_cont_block;
1849 struct qblock *save_loop_break_block = c->loop_break_block;
1850
1851 c->loop_cont_block = vir_new_block(c);
1852 c->loop_break_block = vir_new_block(c);
1853
1854 vir_link_blocks(c->cur_block, c->loop_cont_block);
1855 vir_set_emit_block(c, c->loop_cont_block);
1856 ntq_activate_execute_for_block(c);
1857
1858 ntq_emit_cf_list(c, &loop->body);
1859
1860 /* Re-enable any previous continues now, so our ANYA check below
1861 * works.
1862 *
1863 * XXX: Use the .ORZ flags update, instead.
1864 */
1865 vir_PF(c, vir_SUB(c,
1866 c->execute,
1867 vir_uniform_ui(c, c->loop_cont_block->index)),
1868 V3D_QPU_PF_PUSHZ);
1869 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
1870
1871 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1872
1873 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
1874 vir_link_blocks(c->cur_block, c->loop_cont_block);
1875 vir_link_blocks(c->cur_block, c->loop_break_block);
1876
1877 vir_set_emit_block(c, c->loop_break_block);
1878 if (was_top_level)
1879 c->execute = c->undef;
1880 else
1881 ntq_activate_execute_for_block(c);
1882
1883 c->loop_break_block = save_loop_break_block;
1884 c->loop_cont_block = save_loop_cont_block;
1885 }
1886
1887 static void
1888 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
1889 {
1890 fprintf(stderr, "FUNCTIONS not handled.\n");
1891 abort();
1892 }
1893
1894 static void
1895 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
1896 {
1897 foreach_list_typed(nir_cf_node, node, node, list) {
1898 switch (node->type) {
1899 case nir_cf_node_block:
1900 ntq_emit_block(c, nir_cf_node_as_block(node));
1901 break;
1902
1903 case nir_cf_node_if:
1904 ntq_emit_if(c, nir_cf_node_as_if(node));
1905 break;
1906
1907 case nir_cf_node_loop:
1908 ntq_emit_loop(c, nir_cf_node_as_loop(node));
1909 break;
1910
1911 case nir_cf_node_function:
1912 ntq_emit_function(c, nir_cf_node_as_function(node));
1913 break;
1914
1915 default:
1916 fprintf(stderr, "Unknown NIR node type\n");
1917 abort();
1918 }
1919 }
1920 }
1921
1922 static void
1923 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
1924 {
1925 ntq_setup_registers(c, &impl->registers);
1926 ntq_emit_cf_list(c, &impl->body);
1927 }
1928
1929 static void
1930 nir_to_vir(struct v3d_compile *c)
1931 {
1932 if (c->s->stage == MESA_SHADER_FRAGMENT) {
1933 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
1934 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
1935 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
1936
1937 if (c->s->info.fs.uses_discard)
1938 c->discard = vir_MOV(c, vir_uniform_ui(c, 0));
1939
1940 if (c->fs_key->is_points) {
1941 c->point_x = emit_fragment_varying(c, NULL, 0);
1942 c->point_y = emit_fragment_varying(c, NULL, 0);
1943 } else if (c->fs_key->is_lines) {
1944 c->line_x = emit_fragment_varying(c, NULL, 0);
1945 }
1946 }
1947
1948 ntq_setup_inputs(c);
1949 ntq_setup_outputs(c);
1950 ntq_setup_uniforms(c);
1951 ntq_setup_registers(c, &c->s->registers);
1952
1953 /* Find the main function and emit the body. */
1954 nir_foreach_function(function, c->s) {
1955 assert(strcmp(function->name, "main") == 0);
1956 assert(function->impl);
1957 ntq_emit_impl(c, function->impl);
1958 }
1959 }
1960
1961 const nir_shader_compiler_options v3d_nir_options = {
1962 .lower_extract_byte = true,
1963 .lower_extract_word = true,
1964 .lower_bitfield_insert = true,
1965 .lower_bitfield_extract = true,
1966 .lower_ffma = true,
1967 .lower_flrp32 = true,
1968 .lower_fpow = true,
1969 .lower_fsat = true,
1970 .lower_fsqrt = true,
1971 .lower_negate = true,
1972 .native_integers = true,
1973 };
1974
1975
1976 #if 0
1977 static int
1978 count_nir_instrs(nir_shader *nir)
1979 {
1980 int count = 0;
1981 nir_foreach_function(function, nir) {
1982 if (!function->impl)
1983 continue;
1984 nir_foreach_block(block, function->impl) {
1985 nir_foreach_instr(instr, block)
1986 count++;
1987 }
1988 }
1989 return count;
1990 }
1991 #endif
1992
1993 void
1994 v3d_nir_to_vir(struct v3d_compile *c)
1995 {
1996 if (V3D_DEBUG & (V3D_DEBUG_NIR |
1997 v3d_debug_flag_for_shader_stage(c->s->stage))) {
1998 fprintf(stderr, "%s prog %d/%d NIR:\n",
1999 vir_get_stage_name(c),
2000 c->program_id, c->variant_id);
2001 nir_print_shader(c->s, stderr);
2002 }
2003
2004 nir_to_vir(c);
2005
2006 switch (c->s->stage) {
2007 case MESA_SHADER_FRAGMENT:
2008 emit_frag_end(c);
2009 break;
2010 case MESA_SHADER_VERTEX:
2011 emit_vert_end(c);
2012 break;
2013 default:
2014 unreachable("bad stage");
2015 }
2016
2017 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2018 v3d_debug_flag_for_shader_stage(c->s->stage))) {
2019 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
2020 vir_get_stage_name(c),
2021 c->program_id, c->variant_id);
2022 vir_dump(c);
2023 fprintf(stderr, "\n");
2024 }
2025
2026 vir_optimize(c);
2027 vir_lower_uniforms(c);
2028
2029 /* XXX: vir_schedule_instructions(c); */
2030
2031 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2032 v3d_debug_flag_for_shader_stage(c->s->stage))) {
2033 fprintf(stderr, "%s prog %d/%d VIR:\n",
2034 vir_get_stage_name(c),
2035 c->program_id, c->variant_id);
2036 vir_dump(c);
2037 fprintf(stderr, "\n");
2038 }
2039
2040 v3d_vir_to_qpu(c);
2041 }