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v3d: Implement ALPHA_TO_COVERAGE.
[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
34
35 static void
36 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
37
38 static void
39 resize_qreg_array(struct v3d_compile *c,
40 struct qreg **regs,
41 uint32_t *size,
42 uint32_t decl_size)
43 {
44 if (*size >= decl_size)
45 return;
46
47 uint32_t old_size = *size;
48 *size = MAX2(*size * 2, decl_size);
49 *regs = reralloc(c, *regs, struct qreg, *size);
50 if (!*regs) {
51 fprintf(stderr, "Malloc failure\n");
52 abort();
53 }
54
55 for (uint32_t i = old_size; i < *size; i++)
56 (*regs)[i] = c->undef;
57 }
58
59 void
60 vir_emit_thrsw(struct v3d_compile *c)
61 {
62 if (c->threads == 1)
63 return;
64
65 /* Always thread switch after each texture operation for now.
66 *
67 * We could do better by batching a bunch of texture fetches up and
68 * then doing one thread switch and collecting all their results
69 * afterward.
70 */
71 c->last_thrsw = vir_NOP(c);
72 c->last_thrsw->qpu.sig.thrsw = true;
73 c->last_thrsw_at_top_level = (c->execute.file == QFILE_NULL);
74 }
75
76 static struct qreg
77 vir_SFU(struct v3d_compile *c, int waddr, struct qreg src)
78 {
79 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, waddr), src);
80 return vir_FMOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4));
81 }
82
83 static struct qreg
84 indirect_uniform_load(struct v3d_compile *c, nir_intrinsic_instr *intr)
85 {
86 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
87 uint32_t offset = nir_intrinsic_base(intr);
88 struct v3d_ubo_range *range = NULL;
89 unsigned i;
90
91 for (i = 0; i < c->num_ubo_ranges; i++) {
92 range = &c->ubo_ranges[i];
93 if (offset >= range->src_offset &&
94 offset < range->src_offset + range->size) {
95 break;
96 }
97 }
98 /* The driver-location-based offset always has to be within a declared
99 * uniform range.
100 */
101 assert(i != c->num_ubo_ranges);
102 if (!c->ubo_range_used[i]) {
103 c->ubo_range_used[i] = true;
104 range->dst_offset = c->next_ubo_dst_offset;
105 c->next_ubo_dst_offset += range->size;
106 }
107
108 offset -= range->src_offset;
109
110 if (range->dst_offset + offset != 0) {
111 indirect_offset = vir_ADD(c, indirect_offset,
112 vir_uniform_ui(c, range->dst_offset +
113 offset));
114 }
115
116 /* Adjust for where we stored the TGSI register base. */
117 vir_ADD_dest(c,
118 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA),
119 vir_uniform(c, QUNIFORM_UBO_ADDR, 0),
120 indirect_offset);
121
122 vir_emit_thrsw(c);
123 return vir_LDTMU(c);
124 }
125
126 static struct qreg *
127 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
128 {
129 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
130 def->num_components);
131 _mesa_hash_table_insert(c->def_ht, def, qregs);
132 return qregs;
133 }
134
135 /**
136 * This function is responsible for getting VIR results into the associated
137 * storage for a NIR instruction.
138 *
139 * If it's a NIR SSA def, then we just set the associated hash table entry to
140 * the new result.
141 *
142 * If it's a NIR reg, then we need to update the existing qreg assigned to the
143 * NIR destination with the incoming value. To do that without introducing
144 * new MOVs, we require that the incoming qreg either be a uniform, or be
145 * SSA-defined by the previous VIR instruction in the block and rewritable by
146 * this function. That lets us sneak ahead and insert the SF flag beforehand
147 * (knowing that the previous instruction doesn't depend on flags) and rewrite
148 * its destination to be the NIR reg's destination
149 */
150 void
151 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
152 struct qreg result)
153 {
154 struct qinst *last_inst = NULL;
155 if (!list_empty(&c->cur_block->instructions))
156 last_inst = (struct qinst *)c->cur_block->instructions.prev;
157
158 assert(result.file == QFILE_UNIF ||
159 (result.file == QFILE_TEMP &&
160 last_inst && last_inst == c->defs[result.index]));
161
162 if (dest->is_ssa) {
163 assert(chan < dest->ssa.num_components);
164
165 struct qreg *qregs;
166 struct hash_entry *entry =
167 _mesa_hash_table_search(c->def_ht, &dest->ssa);
168
169 if (entry)
170 qregs = entry->data;
171 else
172 qregs = ntq_init_ssa_def(c, &dest->ssa);
173
174 qregs[chan] = result;
175 } else {
176 nir_register *reg = dest->reg.reg;
177 assert(dest->reg.base_offset == 0);
178 assert(reg->num_array_elems == 0);
179 struct hash_entry *entry =
180 _mesa_hash_table_search(c->def_ht, reg);
181 struct qreg *qregs = entry->data;
182
183 /* Insert a MOV if the source wasn't an SSA def in the
184 * previous instruction.
185 */
186 if (result.file == QFILE_UNIF) {
187 result = vir_MOV(c, result);
188 last_inst = c->defs[result.index];
189 }
190
191 /* We know they're both temps, so just rewrite index. */
192 c->defs[last_inst->dst.index] = NULL;
193 last_inst->dst.index = qregs[chan].index;
194
195 /* If we're in control flow, then make this update of the reg
196 * conditional on the execution mask.
197 */
198 if (c->execute.file != QFILE_NULL) {
199 last_inst->dst.index = qregs[chan].index;
200
201 /* Set the flags to the current exec mask.
202 */
203 c->cursor = vir_before_inst(last_inst);
204 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
205 c->cursor = vir_after_inst(last_inst);
206
207 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
208 last_inst->cond_is_exec_mask = true;
209 }
210 }
211 }
212
213 struct qreg
214 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
215 {
216 struct hash_entry *entry;
217 if (src.is_ssa) {
218 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
219 assert(i < src.ssa->num_components);
220 } else {
221 nir_register *reg = src.reg.reg;
222 entry = _mesa_hash_table_search(c->def_ht, reg);
223 assert(reg->num_array_elems == 0);
224 assert(src.reg.base_offset == 0);
225 assert(i < reg->num_components);
226 }
227
228 struct qreg *qregs = entry->data;
229 return qregs[i];
230 }
231
232 static struct qreg
233 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
234 unsigned src)
235 {
236 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
237 unsigned chan = ffs(instr->dest.write_mask) - 1;
238 struct qreg r = ntq_get_src(c, instr->src[src].src,
239 instr->src[src].swizzle[chan]);
240
241 assert(!instr->src[src].abs);
242 assert(!instr->src[src].negate);
243
244 return r;
245 };
246
247 static inline struct qreg
248 vir_SAT(struct v3d_compile *c, struct qreg val)
249 {
250 return vir_FMAX(c,
251 vir_FMIN(c, val, vir_uniform_f(c, 1.0)),
252 vir_uniform_f(c, 0.0));
253 }
254
255 static struct qreg
256 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
257 {
258 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
259 }
260
261 static void
262 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
263 {
264 unsigned unit = instr->texture_index;
265 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
266 int dest_size = nir_tex_instr_dest_size(instr);
267
268 struct qreg lod = c->undef;
269 if (lod_index != -1)
270 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
271
272 for (int i = 0; i < dest_size; i++) {
273 assert(i < 3);
274 enum quniform_contents contents;
275
276 if (instr->is_array && i == dest_size - 1)
277 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
278 else
279 contents = QUNIFORM_TEXTURE_WIDTH + i;
280
281 struct qreg size = vir_uniform(c, contents, unit);
282
283 switch (instr->sampler_dim) {
284 case GLSL_SAMPLER_DIM_1D:
285 case GLSL_SAMPLER_DIM_2D:
286 case GLSL_SAMPLER_DIM_3D:
287 case GLSL_SAMPLER_DIM_CUBE:
288 /* Don't minify the array size. */
289 if (!(instr->is_array && i == dest_size - 1)) {
290 size = ntq_minify(c, size, lod);
291 }
292 break;
293
294 case GLSL_SAMPLER_DIM_RECT:
295 /* There's no LOD field for rects */
296 break;
297
298 default:
299 unreachable("Bad sampler type");
300 }
301
302 ntq_store_dest(c, &instr->dest, i, size);
303 }
304 }
305
306 static void
307 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
308 {
309 unsigned unit = instr->texture_index;
310
311 /* Since each texture sampling op requires uploading uniforms to
312 * reference the texture, there's no HW support for texture size and
313 * you just upload uniforms containing the size.
314 */
315 switch (instr->op) {
316 case nir_texop_query_levels:
317 ntq_store_dest(c, &instr->dest, 0,
318 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
319 return;
320 case nir_texop_txs:
321 ntq_emit_txs(c, instr);
322 return;
323 default:
324 break;
325 }
326
327 if (c->devinfo->ver >= 40)
328 v3d40_vir_emit_tex(c, instr);
329 else
330 v3d33_vir_emit_tex(c, instr);
331 }
332
333 static struct qreg
334 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
335 {
336 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
337 if (is_cos)
338 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
339
340 struct qreg periods = vir_FROUND(c, input);
341 struct qreg sin_output = vir_SFU(c, V3D_QPU_WADDR_SIN,
342 vir_FSUB(c, input, periods));
343 return vir_XOR(c, sin_output, vir_SHL(c,
344 vir_FTOIN(c, periods),
345 vir_uniform_ui(c, -1)));
346 }
347
348 static struct qreg
349 ntq_fsign(struct v3d_compile *c, struct qreg src)
350 {
351 struct qreg t = vir_get_temp(c);
352
353 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
354 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHZ);
355 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
356 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHN);
357 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
358 return vir_MOV(c, t);
359 }
360
361 static struct qreg
362 ntq_isign(struct v3d_compile *c, struct qreg src)
363 {
364 struct qreg t = vir_get_temp(c);
365
366 vir_MOV_dest(c, t, vir_uniform_ui(c, 0));
367 vir_PF(c, vir_MOV(c, src), V3D_QPU_PF_PUSHZ);
368 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_ui(c, 1));
369 vir_PF(c, vir_MOV(c, src), V3D_QPU_PF_PUSHN);
370 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_ui(c, -1));
371 return vir_MOV(c, t);
372 }
373
374 static void
375 emit_fragcoord_input(struct v3d_compile *c, int attr)
376 {
377 c->inputs[attr * 4 + 0] = vir_FXCD(c);
378 c->inputs[attr * 4 + 1] = vir_FYCD(c);
379 c->inputs[attr * 4 + 2] = c->payload_z;
380 c->inputs[attr * 4 + 3] = vir_SFU(c, V3D_QPU_WADDR_RECIP,
381 c->payload_w);
382 }
383
384 static struct qreg
385 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
386 uint8_t swizzle)
387 {
388 struct qreg r3 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R3);
389 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
390
391 struct qreg vary;
392 if (c->devinfo->ver >= 41) {
393 struct qinst *ldvary = vir_add_inst(V3D_QPU_A_NOP, c->undef,
394 c->undef, c->undef);
395 ldvary->qpu.sig.ldvary = true;
396 vary = vir_emit_def(c, ldvary);
397 } else {
398 vir_NOP(c)->qpu.sig.ldvary = true;
399 vary = r3;
400 }
401
402 /* For gl_PointCoord input or distance along a line, we'll be called
403 * with no nir_variable, and we don't count toward VPM size so we
404 * don't track an input slot.
405 */
406 if (!var) {
407 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
408 }
409
410 int i = c->num_inputs++;
411 c->input_slots[i] = v3d_slot_from_slot_and_component(var->data.location,
412 swizzle);
413
414 switch (var->data.interpolation) {
415 case INTERP_MODE_NONE:
416 /* If a gl_FrontColor or gl_BackColor input has no interp
417 * qualifier, then if we're using glShadeModel(GL_FLAT) it
418 * needs to be flat shaded.
419 */
420 switch (var->data.location) {
421 case VARYING_SLOT_COL0:
422 case VARYING_SLOT_COL1:
423 case VARYING_SLOT_BFC0:
424 case VARYING_SLOT_BFC1:
425 if (c->fs_key->shade_model_flat) {
426 BITSET_SET(c->flat_shade_flags, i);
427 vir_MOV_dest(c, c->undef, vary);
428 return vir_MOV(c, r5);
429 } else {
430 return vir_FADD(c, vir_FMUL(c, vary,
431 c->payload_w), r5);
432 }
433 default:
434 break;
435 }
436 /* FALLTHROUGH */
437 case INTERP_MODE_SMOOTH:
438 if (var->data.centroid) {
439 BITSET_SET(c->centroid_flags, i);
440 return vir_FADD(c, vir_FMUL(c, vary,
441 c->payload_w_centroid), r5);
442 } else {
443 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
444 }
445 case INTERP_MODE_NOPERSPECTIVE:
446 /* C appears after the mov from the varying.
447 XXX: improve ldvary setup.
448 */
449 return vir_FADD(c, vir_MOV(c, vary), r5);
450 case INTERP_MODE_FLAT:
451 BITSET_SET(c->flat_shade_flags, i);
452 vir_MOV_dest(c, c->undef, vary);
453 return vir_MOV(c, r5);
454 default:
455 unreachable("Bad interp mode");
456 }
457 }
458
459 static void
460 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var)
461 {
462 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
463 int chan = var->data.location_frac + i;
464 c->inputs[attr * 4 + chan] =
465 emit_fragment_varying(c, var, chan);
466 }
467 }
468
469 static void
470 add_output(struct v3d_compile *c,
471 uint32_t decl_offset,
472 uint8_t slot,
473 uint8_t swizzle)
474 {
475 uint32_t old_array_size = c->outputs_array_size;
476 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
477 decl_offset + 1);
478
479 if (old_array_size != c->outputs_array_size) {
480 c->output_slots = reralloc(c,
481 c->output_slots,
482 struct v3d_varying_slot,
483 c->outputs_array_size);
484 }
485
486 c->output_slots[decl_offset] =
487 v3d_slot_from_slot_and_component(slot, swizzle);
488 }
489
490 static void
491 declare_uniform_range(struct v3d_compile *c, uint32_t start, uint32_t size)
492 {
493 unsigned array_id = c->num_ubo_ranges++;
494 if (array_id >= c->ubo_ranges_array_size) {
495 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
496 array_id + 1);
497 c->ubo_ranges = reralloc(c, c->ubo_ranges,
498 struct v3d_ubo_range,
499 c->ubo_ranges_array_size);
500 c->ubo_range_used = reralloc(c, c->ubo_range_used,
501 bool,
502 c->ubo_ranges_array_size);
503 }
504
505 c->ubo_ranges[array_id].dst_offset = 0;
506 c->ubo_ranges[array_id].src_offset = start;
507 c->ubo_ranges[array_id].size = size;
508 c->ubo_range_used[array_id] = false;
509 }
510
511 /**
512 * If compare_instr is a valid comparison instruction, emits the
513 * compare_instr's comparison and returns the sel_instr's return value based
514 * on the compare_instr's result.
515 */
516 static bool
517 ntq_emit_comparison(struct v3d_compile *c, struct qreg *dest,
518 nir_alu_instr *compare_instr,
519 nir_alu_instr *sel_instr)
520 {
521 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
522 struct qreg src1;
523 if (nir_op_infos[compare_instr->op].num_inputs > 1)
524 src1 = ntq_get_alu_src(c, compare_instr, 1);
525 bool cond_invert = false;
526
527 switch (compare_instr->op) {
528 case nir_op_feq:
529 case nir_op_seq:
530 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHZ);
531 break;
532 case nir_op_ieq:
533 vir_PF(c, vir_XOR(c, src0, src1), V3D_QPU_PF_PUSHZ);
534 break;
535
536 case nir_op_fne:
537 case nir_op_sne:
538 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHZ);
539 cond_invert = true;
540 break;
541 case nir_op_ine:
542 vir_PF(c, vir_XOR(c, src0, src1), V3D_QPU_PF_PUSHZ);
543 cond_invert = true;
544 break;
545
546 case nir_op_fge:
547 case nir_op_sge:
548 vir_PF(c, vir_FCMP(c, src1, src0), V3D_QPU_PF_PUSHC);
549 break;
550 case nir_op_ige:
551 vir_PF(c, vir_MIN(c, src1, src0), V3D_QPU_PF_PUSHC);
552 cond_invert = true;
553 break;
554 case nir_op_uge:
555 vir_PF(c, vir_SUB(c, src0, src1), V3D_QPU_PF_PUSHC);
556 cond_invert = true;
557 break;
558
559 case nir_op_slt:
560 case nir_op_flt:
561 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHN);
562 break;
563 case nir_op_ilt:
564 vir_PF(c, vir_MIN(c, src1, src0), V3D_QPU_PF_PUSHC);
565 break;
566 case nir_op_ult:
567 vir_PF(c, vir_SUB(c, src0, src1), V3D_QPU_PF_PUSHC);
568 break;
569
570 default:
571 return false;
572 }
573
574 enum v3d_qpu_cond cond = (cond_invert ?
575 V3D_QPU_COND_IFNA :
576 V3D_QPU_COND_IFA);
577
578 switch (sel_instr->op) {
579 case nir_op_seq:
580 case nir_op_sne:
581 case nir_op_sge:
582 case nir_op_slt:
583 *dest = vir_SEL(c, cond,
584 vir_uniform_f(c, 1.0), vir_uniform_f(c, 0.0));
585 break;
586
587 case nir_op_bcsel:
588 *dest = vir_SEL(c, cond,
589 ntq_get_alu_src(c, sel_instr, 1),
590 ntq_get_alu_src(c, sel_instr, 2));
591 break;
592
593 default:
594 *dest = vir_SEL(c, cond,
595 vir_uniform_ui(c, ~0), vir_uniform_ui(c, 0));
596 break;
597 }
598
599 /* Make the temporary for nir_store_dest(). */
600 *dest = vir_MOV(c, *dest);
601
602 return true;
603 }
604
605 /**
606 * Attempts to fold a comparison generating a boolean result into the
607 * condition code for selecting between two values, instead of comparing the
608 * boolean result against 0 to generate the condition code.
609 */
610 static struct qreg ntq_emit_bcsel(struct v3d_compile *c, nir_alu_instr *instr,
611 struct qreg *src)
612 {
613 if (!instr->src[0].src.is_ssa)
614 goto out;
615 if (instr->src[0].src.ssa->parent_instr->type != nir_instr_type_alu)
616 goto out;
617 nir_alu_instr *compare =
618 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
619 if (!compare)
620 goto out;
621
622 struct qreg dest;
623 if (ntq_emit_comparison(c, &dest, compare, instr))
624 return dest;
625
626 out:
627 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
628 return vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA, src[1], src[2]));
629 }
630
631
632 static void
633 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
634 {
635 /* This should always be lowered to ALU operations for V3D. */
636 assert(!instr->dest.saturate);
637
638 /* Vectors are special in that they have non-scalarized writemasks,
639 * and just take the first swizzle channel for each argument in order
640 * into each writemask channel.
641 */
642 if (instr->op == nir_op_vec2 ||
643 instr->op == nir_op_vec3 ||
644 instr->op == nir_op_vec4) {
645 struct qreg srcs[4];
646 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
647 srcs[i] = ntq_get_src(c, instr->src[i].src,
648 instr->src[i].swizzle[0]);
649 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
650 ntq_store_dest(c, &instr->dest.dest, i,
651 vir_MOV(c, srcs[i]));
652 return;
653 }
654
655 /* General case: We can just grab the one used channel per src. */
656 struct qreg src[nir_op_infos[instr->op].num_inputs];
657 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
658 src[i] = ntq_get_alu_src(c, instr, i);
659 }
660
661 struct qreg result;
662
663 switch (instr->op) {
664 case nir_op_fmov:
665 case nir_op_imov:
666 result = vir_MOV(c, src[0]);
667 break;
668
669 case nir_op_fneg:
670 result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
671 break;
672 case nir_op_ineg:
673 result = vir_NEG(c, src[0]);
674 break;
675
676 case nir_op_fmul:
677 result = vir_FMUL(c, src[0], src[1]);
678 break;
679 case nir_op_fadd:
680 result = vir_FADD(c, src[0], src[1]);
681 break;
682 case nir_op_fsub:
683 result = vir_FSUB(c, src[0], src[1]);
684 break;
685 case nir_op_fmin:
686 result = vir_FMIN(c, src[0], src[1]);
687 break;
688 case nir_op_fmax:
689 result = vir_FMAX(c, src[0], src[1]);
690 break;
691
692 case nir_op_f2i32:
693 result = vir_FTOIZ(c, src[0]);
694 break;
695 case nir_op_f2u32:
696 result = vir_FTOUZ(c, src[0]);
697 break;
698 case nir_op_i2f32:
699 result = vir_ITOF(c, src[0]);
700 break;
701 case nir_op_u2f32:
702 result = vir_UTOF(c, src[0]);
703 break;
704 case nir_op_b2f:
705 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
706 break;
707 case nir_op_b2i:
708 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
709 break;
710 case nir_op_i2b:
711 case nir_op_f2b:
712 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
713 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
714 vir_uniform_ui(c, ~0),
715 vir_uniform_ui(c, 0)));
716 break;
717
718 case nir_op_iadd:
719 result = vir_ADD(c, src[0], src[1]);
720 break;
721 case nir_op_ushr:
722 result = vir_SHR(c, src[0], src[1]);
723 break;
724 case nir_op_isub:
725 result = vir_SUB(c, src[0], src[1]);
726 break;
727 case nir_op_ishr:
728 result = vir_ASR(c, src[0], src[1]);
729 break;
730 case nir_op_ishl:
731 result = vir_SHL(c, src[0], src[1]);
732 break;
733 case nir_op_imin:
734 result = vir_MIN(c, src[0], src[1]);
735 break;
736 case nir_op_umin:
737 result = vir_UMIN(c, src[0], src[1]);
738 break;
739 case nir_op_imax:
740 result = vir_MAX(c, src[0], src[1]);
741 break;
742 case nir_op_umax:
743 result = vir_UMAX(c, src[0], src[1]);
744 break;
745 case nir_op_iand:
746 result = vir_AND(c, src[0], src[1]);
747 break;
748 case nir_op_ior:
749 result = vir_OR(c, src[0], src[1]);
750 break;
751 case nir_op_ixor:
752 result = vir_XOR(c, src[0], src[1]);
753 break;
754 case nir_op_inot:
755 result = vir_NOT(c, src[0]);
756 break;
757
758 case nir_op_ufind_msb:
759 result = vir_SUB(c, vir_uniform_ui(c, 31), vir_CLZ(c, src[0]));
760 break;
761
762 case nir_op_imul:
763 result = vir_UMUL(c, src[0], src[1]);
764 break;
765
766 case nir_op_seq:
767 case nir_op_sne:
768 case nir_op_sge:
769 case nir_op_slt:
770 case nir_op_feq:
771 case nir_op_fne:
772 case nir_op_fge:
773 case nir_op_flt:
774 case nir_op_ieq:
775 case nir_op_ine:
776 case nir_op_ige:
777 case nir_op_uge:
778 case nir_op_ilt:
779 case nir_op_ult:
780 if (!ntq_emit_comparison(c, &result, instr, instr)) {
781 fprintf(stderr, "Bad comparison instruction\n");
782 }
783 break;
784
785 case nir_op_bcsel:
786 result = ntq_emit_bcsel(c, instr, src);
787 break;
788 case nir_op_fcsel:
789 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
790 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
791 src[1], src[2]));
792 break;
793
794 case nir_op_frcp:
795 result = vir_SFU(c, V3D_QPU_WADDR_RECIP, src[0]);
796 break;
797 case nir_op_frsq:
798 result = vir_SFU(c, V3D_QPU_WADDR_RSQRT, src[0]);
799 break;
800 case nir_op_fexp2:
801 result = vir_SFU(c, V3D_QPU_WADDR_EXP, src[0]);
802 break;
803 case nir_op_flog2:
804 result = vir_SFU(c, V3D_QPU_WADDR_LOG, src[0]);
805 break;
806
807 case nir_op_fceil:
808 result = vir_FCEIL(c, src[0]);
809 break;
810 case nir_op_ffloor:
811 result = vir_FFLOOR(c, src[0]);
812 break;
813 case nir_op_fround_even:
814 result = vir_FROUND(c, src[0]);
815 break;
816 case nir_op_ftrunc:
817 result = vir_FTRUNC(c, src[0]);
818 break;
819 case nir_op_ffract:
820 result = vir_FSUB(c, src[0], vir_FFLOOR(c, src[0]));
821 break;
822
823 case nir_op_fsin:
824 result = ntq_fsincos(c, src[0], false);
825 break;
826 case nir_op_fcos:
827 result = ntq_fsincos(c, src[0], true);
828 break;
829
830 case nir_op_fsign:
831 result = ntq_fsign(c, src[0]);
832 break;
833 case nir_op_isign:
834 result = ntq_isign(c, src[0]);
835 break;
836
837 case nir_op_fabs: {
838 result = vir_FMOV(c, src[0]);
839 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
840 break;
841 }
842
843 case nir_op_iabs:
844 result = vir_MAX(c, src[0],
845 vir_SUB(c, vir_uniform_ui(c, 0), src[0]));
846 break;
847
848 case nir_op_fddx:
849 case nir_op_fddx_coarse:
850 case nir_op_fddx_fine:
851 result = vir_FDX(c, src[0]);
852 break;
853
854 case nir_op_fddy:
855 case nir_op_fddy_coarse:
856 case nir_op_fddy_fine:
857 result = vir_FDY(c, src[0]);
858 break;
859
860 case nir_op_uadd_carry:
861 vir_PF(c, vir_ADD(c, src[0], src[1]), V3D_QPU_PF_PUSHC);
862 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
863 vir_uniform_ui(c, ~0),
864 vir_uniform_ui(c, 0)));
865 break;
866
867 default:
868 fprintf(stderr, "unknown NIR ALU inst: ");
869 nir_print_instr(&instr->instr, stderr);
870 fprintf(stderr, "\n");
871 abort();
872 }
873
874 /* We have a scalar result, so the instruction should only have a
875 * single channel written to.
876 */
877 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
878 ntq_store_dest(c, &instr->dest.dest,
879 ffs(instr->dest.write_mask) - 1, result);
880 }
881
882 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
883 * specifier. They come from a register that's preloaded with 0xffffffff
884 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
885 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
886 */
887 #define TLB_TYPE_F16_COLOR (3 << 6)
888 #define TLB_TYPE_I32_COLOR (1 << 6)
889 #define TLB_TYPE_F32_COLOR (0 << 6)
890 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
891 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
892 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
893 #define TLB_F16_SWAP_HI_LO (1 << 1)
894 #define TLB_VEC_SIZE_4_F16 (1 << 0)
895 #define TLB_VEC_SIZE_2_F16 (0 << 0)
896 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
897
898 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
899 * flag is set.
900 */
901 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
902 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
903 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
904
905 /* Stencil is a single 32-bit write. */
906 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
907
908 static void
909 emit_frag_end(struct v3d_compile *c)
910 {
911 /* XXX
912 if (c->output_sample_mask_index != -1) {
913 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
914 }
915 */
916
917 bool has_any_tlb_color_write = false;
918 for (int rt = 0; rt < c->fs_key->nr_cbufs; rt++) {
919 if (c->output_color_var[rt])
920 has_any_tlb_color_write = true;
921 }
922
923 if (c->fs_key->sample_alpha_to_coverage && c->output_color_var[0]) {
924 struct nir_variable *var = c->output_color_var[0];
925 struct qreg *color = &c->outputs[var->data.driver_location * 4];
926
927 vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
928 vir_AND(c,
929 vir_MSF(c),
930 vir_FTOC(c, color[3])));
931 }
932
933 if (c->output_position_index != -1) {
934 struct qinst *inst = vir_MOV_dest(c,
935 vir_reg(QFILE_TLBU, 0),
936 c->outputs[c->output_position_index]);
937
938 inst->src[vir_get_implicit_uniform_src(inst)] =
939 vir_uniform_ui(c,
940 TLB_TYPE_DEPTH |
941 TLB_DEPTH_TYPE_PER_PIXEL |
942 0xffffff00);
943 } else if (c->s->info.fs.uses_discard ||
944 c->fs_key->sample_alpha_to_coverage ||
945 !has_any_tlb_color_write) {
946 /* Emit passthrough Z if it needed to be delayed until shader
947 * end due to potential discards.
948 *
949 * Since (single-threaded) fragment shaders always need a TLB
950 * write, emit passthrouh Z if we didn't have any color
951 * buffers and flag us as potentially discarding, so that we
952 * can use Z as the TLB write.
953 */
954 c->s->info.fs.uses_discard = true;
955
956 struct qinst *inst = vir_MOV_dest(c,
957 vir_reg(QFILE_TLBU, 0),
958 vir_reg(QFILE_NULL, 0));
959
960 inst->src[vir_get_implicit_uniform_src(inst)] =
961 vir_uniform_ui(c,
962 TLB_TYPE_DEPTH |
963 TLB_DEPTH_TYPE_INVARIANT |
964 0xffffff00);
965 }
966
967 /* XXX: Performance improvement: Merge Z write and color writes TLB
968 * uniform setup
969 */
970
971 for (int rt = 0; rt < c->fs_key->nr_cbufs; rt++) {
972 if (!c->output_color_var[rt])
973 continue;
974
975 nir_variable *var = c->output_color_var[rt];
976 struct qreg *color = &c->outputs[var->data.driver_location * 4];
977 int num_components = glsl_get_vector_elements(var->type);
978 uint32_t conf = 0xffffff00;
979 struct qinst *inst;
980
981 conf |= TLB_SAMPLE_MODE_PER_PIXEL;
982 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
983
984 if (c->fs_key->swap_color_rb & (1 << rt))
985 num_components = MAX2(num_components, 3);
986
987 assert(num_components != 0);
988 switch (glsl_get_base_type(var->type)) {
989 case GLSL_TYPE_UINT:
990 case GLSL_TYPE_INT:
991 /* The F32 vs I32 distinction was dropped in 4.2. */
992 if (c->devinfo->ver < 42)
993 conf |= TLB_TYPE_I32_COLOR;
994 else
995 conf |= TLB_TYPE_F32_COLOR;
996 conf |= ((num_components - 1) <<
997 TLB_VEC_SIZE_MINUS_1_SHIFT);
998
999 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
1000 inst->src[vir_get_implicit_uniform_src(inst)] =
1001 vir_uniform_ui(c, conf);
1002
1003 for (int i = 1; i < num_components; i++) {
1004 inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
1005 color[i]);
1006 }
1007 break;
1008
1009 default: {
1010 struct qreg r = color[0];
1011 struct qreg g = color[1];
1012 struct qreg b = color[2];
1013 struct qreg a = color[3];
1014
1015 if (c->fs_key->f32_color_rb & (1 << rt)) {
1016 conf |= TLB_TYPE_F32_COLOR;
1017 conf |= ((num_components - 1) <<
1018 TLB_VEC_SIZE_MINUS_1_SHIFT);
1019 } else {
1020 conf |= TLB_TYPE_F16_COLOR;
1021 conf |= TLB_F16_SWAP_HI_LO;
1022 if (num_components >= 3)
1023 conf |= TLB_VEC_SIZE_4_F16;
1024 else
1025 conf |= TLB_VEC_SIZE_2_F16;
1026 }
1027
1028 if (c->fs_key->swap_color_rb & (1 << rt)) {
1029 r = color[2];
1030 b = color[0];
1031 }
1032
1033 if (c->fs_key->f32_color_rb & (1 << rt)) {
1034 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
1035 inst->src[vir_get_implicit_uniform_src(inst)] =
1036 vir_uniform_ui(c, conf);
1037
1038 for (int i = 1; i < num_components; i++) {
1039 inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
1040 color[i]);
1041 }
1042 } else {
1043 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), r, g);
1044 if (conf != ~0) {
1045 inst->dst.file = QFILE_TLBU;
1046 inst->src[vir_get_implicit_uniform_src(inst)] =
1047 vir_uniform_ui(c, conf);
1048 }
1049
1050 if (num_components >= 3)
1051 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), b, a);
1052 }
1053 break;
1054 }
1055 }
1056 }
1057 }
1058
1059 static void
1060 vir_VPM_WRITE(struct v3d_compile *c, struct qreg val, uint32_t *vpm_index)
1061 {
1062 if (c->devinfo->ver >= 40) {
1063 vir_STVPMV(c, vir_uniform_ui(c, *vpm_index), val);
1064 *vpm_index = *vpm_index + 1;
1065 } else {
1066 vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM), val);
1067 }
1068
1069 c->num_vpm_writes++;
1070 }
1071
1072 static void
1073 emit_scaled_viewport_write(struct v3d_compile *c, struct qreg rcp_w,
1074 uint32_t *vpm_index)
1075 {
1076 for (int i = 0; i < 2; i++) {
1077 struct qreg coord = c->outputs[c->output_position_index + i];
1078 coord = vir_FMUL(c, coord,
1079 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i,
1080 0));
1081 coord = vir_FMUL(c, coord, rcp_w);
1082 vir_VPM_WRITE(c, vir_FTOIN(c, coord), vpm_index);
1083 }
1084
1085 }
1086
1087 static void
1088 emit_zs_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index)
1089 {
1090 struct qreg zscale = vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1091 struct qreg zoffset = vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1092
1093 struct qreg z = c->outputs[c->output_position_index + 2];
1094 z = vir_FMUL(c, z, zscale);
1095 z = vir_FMUL(c, z, rcp_w);
1096 z = vir_FADD(c, z, zoffset);
1097 vir_VPM_WRITE(c, z, vpm_index);
1098 }
1099
1100 static void
1101 emit_rcp_wc_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index)
1102 {
1103 vir_VPM_WRITE(c, rcp_w, vpm_index);
1104 }
1105
1106 static void
1107 emit_point_size_write(struct v3d_compile *c, uint32_t *vpm_index)
1108 {
1109 struct qreg point_size;
1110
1111 if (c->output_point_size_index != -1)
1112 point_size = c->outputs[c->output_point_size_index];
1113 else
1114 point_size = vir_uniform_f(c, 1.0);
1115
1116 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1117 * BCM21553).
1118 */
1119 point_size = vir_FMAX(c, point_size, vir_uniform_f(c, .125));
1120
1121 vir_VPM_WRITE(c, point_size, vpm_index);
1122 }
1123
1124 static void
1125 emit_vpm_write_setup(struct v3d_compile *c)
1126 {
1127 if (c->devinfo->ver >= 40)
1128 return;
1129
1130 v3d33_vir_vpm_write_setup(c);
1131 }
1132
1133 /**
1134 * Sets up c->outputs[c->output_position_index] for the vertex shader
1135 * epilogue, if an output vertex position wasn't specified in the user's
1136 * shader. This may be the case for transform feedback with rasterizer
1137 * discard enabled.
1138 */
1139 static void
1140 setup_default_position(struct v3d_compile *c)
1141 {
1142 if (c->output_position_index != -1)
1143 return;
1144
1145 c->output_position_index = c->outputs_array_size;
1146 for (int i = 0; i < 4; i++) {
1147 add_output(c,
1148 c->output_position_index + i,
1149 VARYING_SLOT_POS, i);
1150 }
1151 }
1152
1153 static void
1154 emit_vert_end(struct v3d_compile *c)
1155 {
1156 setup_default_position(c);
1157
1158 uint32_t vpm_index = 0;
1159 struct qreg rcp_w = vir_SFU(c, V3D_QPU_WADDR_RECIP,
1160 c->outputs[c->output_position_index + 3]);
1161
1162 emit_vpm_write_setup(c);
1163
1164 if (c->vs_key->is_coord) {
1165 for (int i = 0; i < 4; i++)
1166 vir_VPM_WRITE(c, c->outputs[c->output_position_index + i],
1167 &vpm_index);
1168 emit_scaled_viewport_write(c, rcp_w, &vpm_index);
1169 if (c->vs_key->per_vertex_point_size) {
1170 emit_point_size_write(c, &vpm_index);
1171 /* emit_rcp_wc_write(c, rcp_w); */
1172 }
1173 /* XXX: Z-only rendering */
1174 if (0)
1175 emit_zs_write(c, rcp_w, &vpm_index);
1176 } else {
1177 emit_scaled_viewport_write(c, rcp_w, &vpm_index);
1178 emit_zs_write(c, rcp_w, &vpm_index);
1179 emit_rcp_wc_write(c, rcp_w, &vpm_index);
1180 if (c->vs_key->per_vertex_point_size)
1181 emit_point_size_write(c, &vpm_index);
1182 }
1183
1184 for (int i = 0; i < c->vs_key->num_fs_inputs; i++) {
1185 struct v3d_varying_slot input = c->vs_key->fs_inputs[i];
1186 int j;
1187
1188 for (j = 0; j < c->num_outputs; j++) {
1189 struct v3d_varying_slot output = c->output_slots[j];
1190
1191 if (!memcmp(&input, &output, sizeof(input))) {
1192 vir_VPM_WRITE(c, c->outputs[j],
1193 &vpm_index);
1194 break;
1195 }
1196 }
1197 /* Emit padding if we didn't find a declared VS output for
1198 * this FS input.
1199 */
1200 if (j == c->num_outputs)
1201 vir_VPM_WRITE(c, vir_uniform_f(c, 0.0),
1202 &vpm_index);
1203 }
1204
1205 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1206 */
1207 if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
1208 vir_VPMWT(c);
1209 }
1210
1211 void
1212 v3d_optimize_nir(struct nir_shader *s)
1213 {
1214 bool progress;
1215
1216 do {
1217 progress = false;
1218
1219 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1220 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1221 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1222 NIR_PASS(progress, s, nir_copy_prop);
1223 NIR_PASS(progress, s, nir_opt_remove_phis);
1224 NIR_PASS(progress, s, nir_opt_dce);
1225 NIR_PASS(progress, s, nir_opt_dead_cf);
1226 NIR_PASS(progress, s, nir_opt_cse);
1227 NIR_PASS(progress, s, nir_opt_peephole_select, 8);
1228 NIR_PASS(progress, s, nir_opt_algebraic);
1229 NIR_PASS(progress, s, nir_opt_constant_folding);
1230 NIR_PASS(progress, s, nir_opt_undef);
1231 } while (progress);
1232
1233 NIR_PASS(progress, s, nir_opt_move_load_ubo);
1234 }
1235
1236 static int
1237 driver_location_compare(const void *in_a, const void *in_b)
1238 {
1239 const nir_variable *const *a = in_a;
1240 const nir_variable *const *b = in_b;
1241
1242 return (*a)->data.driver_location - (*b)->data.driver_location;
1243 }
1244
1245 static struct qreg
1246 ntq_emit_vpm_read(struct v3d_compile *c,
1247 uint32_t *num_components_queued,
1248 uint32_t *remaining,
1249 uint32_t vpm_index)
1250 {
1251 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1252
1253 if (c->devinfo->ver >= 40 ) {
1254 return vir_LDVPMV_IN(c,
1255 vir_uniform_ui(c,
1256 (*num_components_queued)++));
1257 }
1258
1259 if (*num_components_queued != 0) {
1260 (*num_components_queued)--;
1261 c->num_inputs++;
1262 return vir_MOV(c, vpm);
1263 }
1264
1265 uint32_t num_components = MIN2(*remaining, 32);
1266
1267 v3d33_vir_vpm_read_setup(c, num_components);
1268
1269 *num_components_queued = num_components - 1;
1270 *remaining -= num_components;
1271 c->num_inputs++;
1272
1273 return vir_MOV(c, vpm);
1274 }
1275
1276 static void
1277 ntq_setup_inputs(struct v3d_compile *c)
1278 {
1279 unsigned num_entries = 0;
1280 unsigned num_components = 0;
1281 nir_foreach_variable(var, &c->s->inputs) {
1282 num_entries++;
1283 num_components += glsl_get_components(var->type);
1284 }
1285
1286 nir_variable *vars[num_entries];
1287
1288 unsigned i = 0;
1289 nir_foreach_variable(var, &c->s->inputs)
1290 vars[i++] = var;
1291
1292 /* Sort the variables so that we emit the input setup in
1293 * driver_location order. This is required for VPM reads, whose data
1294 * is fetched into the VPM in driver_location (TGSI register index)
1295 * order.
1296 */
1297 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1298
1299 uint32_t vpm_components_queued = 0;
1300 if (c->s->info.stage == MESA_SHADER_VERTEX) {
1301 bool uses_iid = c->s->info.system_values_read &
1302 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1303 bool uses_vid = c->s->info.system_values_read &
1304 (1ull << SYSTEM_VALUE_VERTEX_ID);
1305
1306 num_components += uses_iid;
1307 num_components += uses_vid;
1308
1309 if (uses_iid) {
1310 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1311 &num_components, ~0);
1312 }
1313
1314 if (uses_vid) {
1315 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1316 &num_components, ~0);
1317 }
1318 }
1319
1320 for (unsigned i = 0; i < num_entries; i++) {
1321 nir_variable *var = vars[i];
1322 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1323 unsigned loc = var->data.driver_location;
1324
1325 assert(array_len == 1);
1326 (void)array_len;
1327 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1328 (loc + 1) * 4);
1329
1330 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1331 if (var->data.location == VARYING_SLOT_POS) {
1332 emit_fragcoord_input(c, loc);
1333 } else if (var->data.location == VARYING_SLOT_PNTC ||
1334 (var->data.location >= VARYING_SLOT_VAR0 &&
1335 (c->fs_key->point_sprite_mask &
1336 (1 << (var->data.location -
1337 VARYING_SLOT_VAR0))))) {
1338 c->inputs[loc * 4 + 0] = c->point_x;
1339 c->inputs[loc * 4 + 1] = c->point_y;
1340 } else {
1341 emit_fragment_input(c, loc, var);
1342 }
1343 } else {
1344 int var_components = glsl_get_components(var->type);
1345
1346 for (int i = 0; i < var_components; i++) {
1347 c->inputs[loc * 4 + i] =
1348 ntq_emit_vpm_read(c,
1349 &vpm_components_queued,
1350 &num_components,
1351 loc * 4 + i);
1352
1353 }
1354 c->vattr_sizes[loc] = var_components;
1355 }
1356 }
1357
1358 if (c->s->info.stage == MESA_SHADER_VERTEX) {
1359 if (c->devinfo->ver >= 40) {
1360 assert(vpm_components_queued == num_components);
1361 } else {
1362 assert(vpm_components_queued == 0);
1363 assert(num_components == 0);
1364 }
1365 }
1366 }
1367
1368 static void
1369 ntq_setup_outputs(struct v3d_compile *c)
1370 {
1371 nir_foreach_variable(var, &c->s->outputs) {
1372 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1373 unsigned loc = var->data.driver_location * 4;
1374
1375 assert(array_len == 1);
1376 (void)array_len;
1377
1378 for (int i = 0; i < 4; i++) {
1379 add_output(c, loc + var->data.location_frac + i,
1380 var->data.location,
1381 var->data.location_frac + i);
1382 }
1383
1384 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1385 switch (var->data.location) {
1386 case FRAG_RESULT_COLOR:
1387 c->output_color_var[0] = var;
1388 c->output_color_var[1] = var;
1389 c->output_color_var[2] = var;
1390 c->output_color_var[3] = var;
1391 break;
1392 case FRAG_RESULT_DATA0:
1393 case FRAG_RESULT_DATA1:
1394 case FRAG_RESULT_DATA2:
1395 case FRAG_RESULT_DATA3:
1396 c->output_color_var[var->data.location -
1397 FRAG_RESULT_DATA0] = var;
1398 break;
1399 case FRAG_RESULT_DEPTH:
1400 c->output_position_index = loc;
1401 break;
1402 case FRAG_RESULT_SAMPLE_MASK:
1403 c->output_sample_mask_index = loc;
1404 break;
1405 }
1406 } else {
1407 switch (var->data.location) {
1408 case VARYING_SLOT_POS:
1409 c->output_position_index = loc;
1410 break;
1411 case VARYING_SLOT_PSIZ:
1412 c->output_point_size_index = loc;
1413 break;
1414 }
1415 }
1416 }
1417 }
1418
1419 static void
1420 ntq_setup_uniforms(struct v3d_compile *c)
1421 {
1422 nir_foreach_variable(var, &c->s->uniforms) {
1423 uint32_t vec4_count = glsl_count_attribute_slots(var->type,
1424 false);
1425 unsigned vec4_size = 4 * sizeof(float);
1426
1427 declare_uniform_range(c, var->data.driver_location * vec4_size,
1428 vec4_count * vec4_size);
1429
1430 }
1431 }
1432
1433 /**
1434 * Sets up the mapping from nir_register to struct qreg *.
1435 *
1436 * Each nir_register gets a struct qreg per 32-bit component being stored.
1437 */
1438 static void
1439 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1440 {
1441 foreach_list_typed(nir_register, nir_reg, node, list) {
1442 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1443 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1444 array_len *
1445 nir_reg->num_components);
1446
1447 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1448
1449 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1450 qregs[i] = vir_get_temp(c);
1451 }
1452 }
1453
1454 static void
1455 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1456 {
1457 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1458 for (int i = 0; i < instr->def.num_components; i++)
1459 qregs[i] = vir_uniform_ui(c, instr->value.u32[i]);
1460
1461 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1462 }
1463
1464 static void
1465 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1466 {
1467 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1468
1469 /* VIR needs there to be *some* value, so pick 0 (same as for
1470 * ntq_setup_registers().
1471 */
1472 for (int i = 0; i < instr->def.num_components; i++)
1473 qregs[i] = vir_uniform_ui(c, 0);
1474 }
1475
1476 static void
1477 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
1478 {
1479 nir_const_value *const_offset;
1480 unsigned offset;
1481
1482 switch (instr->intrinsic) {
1483 case nir_intrinsic_load_uniform:
1484 assert(instr->num_components == 1);
1485 const_offset = nir_src_as_const_value(instr->src[0]);
1486 if (const_offset) {
1487 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1488 assert(offset % 4 == 0);
1489 /* We need dwords */
1490 offset = offset / 4;
1491 ntq_store_dest(c, &instr->dest, 0,
1492 vir_uniform(c, QUNIFORM_UNIFORM,
1493 offset));
1494 } else {
1495 ntq_store_dest(c, &instr->dest, 0,
1496 indirect_uniform_load(c, instr));
1497 }
1498 break;
1499
1500 case nir_intrinsic_load_ubo:
1501 for (int i = 0; i < instr->num_components; i++) {
1502 int ubo = nir_src_as_const_value(instr->src[0])->u32[0];
1503
1504 /* Adjust for where we stored the TGSI register base. */
1505 vir_ADD_dest(c,
1506 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA),
1507 vir_uniform(c, QUNIFORM_UBO_ADDR, 1 + ubo),
1508 vir_ADD(c,
1509 ntq_get_src(c, instr->src[1], 0),
1510 vir_uniform_ui(c, i * 4)));
1511
1512 vir_emit_thrsw(c);
1513
1514 ntq_store_dest(c, &instr->dest, i, vir_LDTMU(c));
1515 }
1516 break;
1517
1518 const_offset = nir_src_as_const_value(instr->src[0]);
1519 if (const_offset) {
1520 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1521 assert(offset % 4 == 0);
1522 /* We need dwords */
1523 offset = offset / 4;
1524 ntq_store_dest(c, &instr->dest, 0,
1525 vir_uniform(c, QUNIFORM_UNIFORM,
1526 offset));
1527 } else {
1528 ntq_store_dest(c, &instr->dest, 0,
1529 indirect_uniform_load(c, instr));
1530 }
1531 break;
1532
1533 case nir_intrinsic_load_user_clip_plane:
1534 for (int i = 0; i < instr->num_components; i++) {
1535 ntq_store_dest(c, &instr->dest, i,
1536 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1537 nir_intrinsic_ucp_id(instr) *
1538 4 + i));
1539 }
1540 break;
1541
1542 case nir_intrinsic_load_alpha_ref_float:
1543 ntq_store_dest(c, &instr->dest, 0,
1544 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1545 break;
1546
1547 case nir_intrinsic_load_sample_mask_in:
1548 ntq_store_dest(c, &instr->dest, 0,
1549 vir_uniform(c, QUNIFORM_SAMPLE_MASK, 0));
1550 break;
1551
1552 case nir_intrinsic_load_front_face:
1553 /* The register contains 0 (front) or 1 (back), and we need to
1554 * turn it into a NIR bool where true means front.
1555 */
1556 ntq_store_dest(c, &instr->dest, 0,
1557 vir_ADD(c,
1558 vir_uniform_ui(c, -1),
1559 vir_REVF(c)));
1560 break;
1561
1562 case nir_intrinsic_load_instance_id:
1563 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
1564 break;
1565
1566 case nir_intrinsic_load_vertex_id:
1567 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
1568 break;
1569
1570 case nir_intrinsic_load_input:
1571 const_offset = nir_src_as_const_value(instr->src[0]);
1572 assert(const_offset && "v3d doesn't support indirect inputs");
1573 for (int i = 0; i < instr->num_components; i++) {
1574 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1575 int comp = nir_intrinsic_component(instr) + i;
1576 ntq_store_dest(c, &instr->dest, i,
1577 vir_MOV(c, c->inputs[offset * 4 + comp]));
1578 }
1579 break;
1580
1581 case nir_intrinsic_store_output:
1582 const_offset = nir_src_as_const_value(instr->src[1]);
1583 assert(const_offset && "v3d doesn't support indirect outputs");
1584 offset = ((nir_intrinsic_base(instr) +
1585 const_offset->u32[0]) * 4 +
1586 nir_intrinsic_component(instr));
1587
1588 for (int i = 0; i < instr->num_components; i++) {
1589 c->outputs[offset + i] =
1590 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
1591 }
1592 c->num_outputs = MAX2(c->num_outputs,
1593 offset + instr->num_components);
1594 break;
1595
1596 case nir_intrinsic_discard:
1597 if (c->execute.file != QFILE_NULL) {
1598 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1599 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1600 vir_uniform_ui(c, 0)),
1601 V3D_QPU_COND_IFA);
1602 } else {
1603 vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1604 vir_uniform_ui(c, 0));
1605 }
1606 break;
1607
1608 case nir_intrinsic_discard_if: {
1609 /* true (~0) if we're discarding */
1610 struct qreg cond = ntq_get_src(c, instr->src[0], 0);
1611
1612 if (c->execute.file != QFILE_NULL) {
1613 /* execute == 0 means the channel is active. Invert
1614 * the condition so that we can use zero as "executing
1615 * and discarding."
1616 */
1617 vir_PF(c, vir_OR(c, c->execute, vir_NOT(c, cond)),
1618 V3D_QPU_PF_PUSHZ);
1619 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1620 vir_uniform_ui(c, 0)),
1621 V3D_QPU_COND_IFA);
1622 } else {
1623 vir_PF(c, cond, V3D_QPU_PF_PUSHZ);
1624 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1625 vir_uniform_ui(c, 0)),
1626 V3D_QPU_COND_IFNA);
1627 }
1628
1629 break;
1630 }
1631
1632 default:
1633 fprintf(stderr, "Unknown intrinsic: ");
1634 nir_print_instr(&instr->instr, stderr);
1635 fprintf(stderr, "\n");
1636 break;
1637 }
1638 }
1639
1640 /* Clears (activates) the execute flags for any channels whose jump target
1641 * matches this block.
1642 */
1643 static void
1644 ntq_activate_execute_for_block(struct v3d_compile *c)
1645 {
1646 vir_PF(c, vir_XOR(c, c->execute, vir_uniform_ui(c, c->cur_block->index)),
1647 V3D_QPU_PF_PUSHZ);
1648
1649 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
1650 }
1651
1652 static void
1653 ntq_emit_if(struct v3d_compile *c, nir_if *if_stmt)
1654 {
1655 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
1656 bool empty_else_block =
1657 (nir_else_block == nir_if_last_else_block(if_stmt) &&
1658 exec_list_is_empty(&nir_else_block->instr_list));
1659
1660 struct qblock *then_block = vir_new_block(c);
1661 struct qblock *after_block = vir_new_block(c);
1662 struct qblock *else_block;
1663 if (empty_else_block)
1664 else_block = after_block;
1665 else
1666 else_block = vir_new_block(c);
1667
1668 bool was_top_level = false;
1669 if (c->execute.file == QFILE_NULL) {
1670 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
1671 was_top_level = true;
1672 }
1673
1674 /* Set A for executing (execute == 0) and jumping (if->condition ==
1675 * 0) channels, and then update execute flags for those to point to
1676 * the ELSE block.
1677 */
1678 vir_PF(c, vir_OR(c,
1679 c->execute,
1680 ntq_get_src(c, if_stmt->condition, 0)),
1681 V3D_QPU_PF_PUSHZ);
1682 vir_MOV_cond(c, V3D_QPU_COND_IFA,
1683 c->execute,
1684 vir_uniform_ui(c, else_block->index));
1685
1686 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1687 * through.
1688 */
1689 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1690 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
1691 vir_link_blocks(c->cur_block, else_block);
1692 vir_link_blocks(c->cur_block, then_block);
1693
1694 /* Process the THEN block. */
1695 vir_set_emit_block(c, then_block);
1696 ntq_emit_cf_list(c, &if_stmt->then_list);
1697
1698 if (!empty_else_block) {
1699 /* Handle the end of the THEN block. First, all currently
1700 * active channels update their execute flags to point to
1701 * ENDIF
1702 */
1703 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1704 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1705 vir_uniform_ui(c, after_block->index));
1706
1707 /* If everything points at ENDIF, then jump there immediately. */
1708 vir_PF(c, vir_XOR(c, c->execute,
1709 vir_uniform_ui(c, after_block->index)),
1710 V3D_QPU_PF_PUSHZ);
1711 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
1712 vir_link_blocks(c->cur_block, after_block);
1713 vir_link_blocks(c->cur_block, else_block);
1714
1715 vir_set_emit_block(c, else_block);
1716 ntq_activate_execute_for_block(c);
1717 ntq_emit_cf_list(c, &if_stmt->else_list);
1718 }
1719
1720 vir_link_blocks(c->cur_block, after_block);
1721
1722 vir_set_emit_block(c, after_block);
1723 if (was_top_level)
1724 c->execute = c->undef;
1725 else
1726 ntq_activate_execute_for_block(c);
1727 }
1728
1729 static void
1730 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
1731 {
1732 switch (jump->type) {
1733 case nir_jump_break:
1734 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1735 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1736 vir_uniform_ui(c, c->loop_break_block->index));
1737 break;
1738
1739 case nir_jump_continue:
1740 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1741 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1742 vir_uniform_ui(c, c->loop_cont_block->index));
1743 break;
1744
1745 case nir_jump_return:
1746 unreachable("All returns shouold be lowered\n");
1747 }
1748 }
1749
1750 static void
1751 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
1752 {
1753 switch (instr->type) {
1754 case nir_instr_type_alu:
1755 ntq_emit_alu(c, nir_instr_as_alu(instr));
1756 break;
1757
1758 case nir_instr_type_intrinsic:
1759 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
1760 break;
1761
1762 case nir_instr_type_load_const:
1763 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
1764 break;
1765
1766 case nir_instr_type_ssa_undef:
1767 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
1768 break;
1769
1770 case nir_instr_type_tex:
1771 ntq_emit_tex(c, nir_instr_as_tex(instr));
1772 break;
1773
1774 case nir_instr_type_jump:
1775 ntq_emit_jump(c, nir_instr_as_jump(instr));
1776 break;
1777
1778 default:
1779 fprintf(stderr, "Unknown NIR instr type: ");
1780 nir_print_instr(instr, stderr);
1781 fprintf(stderr, "\n");
1782 abort();
1783 }
1784 }
1785
1786 static void
1787 ntq_emit_block(struct v3d_compile *c, nir_block *block)
1788 {
1789 nir_foreach_instr(instr, block) {
1790 ntq_emit_instr(c, instr);
1791 }
1792 }
1793
1794 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
1795
1796 static void
1797 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
1798 {
1799 bool was_top_level = false;
1800 if (c->execute.file == QFILE_NULL) {
1801 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
1802 was_top_level = true;
1803 }
1804
1805 struct qblock *save_loop_cont_block = c->loop_cont_block;
1806 struct qblock *save_loop_break_block = c->loop_break_block;
1807
1808 c->loop_cont_block = vir_new_block(c);
1809 c->loop_break_block = vir_new_block(c);
1810
1811 vir_link_blocks(c->cur_block, c->loop_cont_block);
1812 vir_set_emit_block(c, c->loop_cont_block);
1813 ntq_activate_execute_for_block(c);
1814
1815 ntq_emit_cf_list(c, &loop->body);
1816
1817 /* Re-enable any previous continues now, so our ANYA check below
1818 * works.
1819 *
1820 * XXX: Use the .ORZ flags update, instead.
1821 */
1822 vir_PF(c, vir_XOR(c,
1823 c->execute,
1824 vir_uniform_ui(c, c->loop_cont_block->index)),
1825 V3D_QPU_PF_PUSHZ);
1826 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
1827
1828 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1829
1830 struct qinst *branch = vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
1831 /* Pixels that were not dispatched or have been discarded should not
1832 * contribute to looping again.
1833 */
1834 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P;
1835 vir_link_blocks(c->cur_block, c->loop_cont_block);
1836 vir_link_blocks(c->cur_block, c->loop_break_block);
1837
1838 vir_set_emit_block(c, c->loop_break_block);
1839 if (was_top_level)
1840 c->execute = c->undef;
1841 else
1842 ntq_activate_execute_for_block(c);
1843
1844 c->loop_break_block = save_loop_break_block;
1845 c->loop_cont_block = save_loop_cont_block;
1846 }
1847
1848 static void
1849 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
1850 {
1851 fprintf(stderr, "FUNCTIONS not handled.\n");
1852 abort();
1853 }
1854
1855 static void
1856 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
1857 {
1858 foreach_list_typed(nir_cf_node, node, node, list) {
1859 switch (node->type) {
1860 case nir_cf_node_block:
1861 ntq_emit_block(c, nir_cf_node_as_block(node));
1862 break;
1863
1864 case nir_cf_node_if:
1865 ntq_emit_if(c, nir_cf_node_as_if(node));
1866 break;
1867
1868 case nir_cf_node_loop:
1869 ntq_emit_loop(c, nir_cf_node_as_loop(node));
1870 break;
1871
1872 case nir_cf_node_function:
1873 ntq_emit_function(c, nir_cf_node_as_function(node));
1874 break;
1875
1876 default:
1877 fprintf(stderr, "Unknown NIR node type\n");
1878 abort();
1879 }
1880 }
1881 }
1882
1883 static void
1884 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
1885 {
1886 ntq_setup_registers(c, &impl->registers);
1887 ntq_emit_cf_list(c, &impl->body);
1888 }
1889
1890 static void
1891 nir_to_vir(struct v3d_compile *c)
1892 {
1893 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1894 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
1895 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
1896 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
1897
1898 if (c->fs_key->is_points) {
1899 c->point_x = emit_fragment_varying(c, NULL, 0);
1900 c->point_y = emit_fragment_varying(c, NULL, 0);
1901 } else if (c->fs_key->is_lines) {
1902 c->line_x = emit_fragment_varying(c, NULL, 0);
1903 }
1904 }
1905
1906 ntq_setup_inputs(c);
1907 ntq_setup_outputs(c);
1908 ntq_setup_uniforms(c);
1909 ntq_setup_registers(c, &c->s->registers);
1910
1911 /* Find the main function and emit the body. */
1912 nir_foreach_function(function, c->s) {
1913 assert(strcmp(function->name, "main") == 0);
1914 assert(function->impl);
1915 ntq_emit_impl(c, function->impl);
1916 }
1917 }
1918
1919 const nir_shader_compiler_options v3d_nir_options = {
1920 .lower_all_io_to_temps = true,
1921 .lower_extract_byte = true,
1922 .lower_extract_word = true,
1923 .lower_bfm = true,
1924 .lower_bitfield_insert_to_shifts = true,
1925 .lower_bitfield_extract_to_shifts = true,
1926 .lower_bitfield_reverse = true,
1927 .lower_bit_count = true,
1928 .lower_pack_unorm_2x16 = true,
1929 .lower_pack_snorm_2x16 = true,
1930 .lower_pack_unorm_4x8 = true,
1931 .lower_pack_snorm_4x8 = true,
1932 .lower_unpack_unorm_4x8 = true,
1933 .lower_unpack_snorm_4x8 = true,
1934 .lower_fdiv = true,
1935 .lower_find_lsb = true,
1936 .lower_ffma = true,
1937 .lower_flrp32 = true,
1938 .lower_fpow = true,
1939 .lower_fsat = true,
1940 .lower_fsqrt = true,
1941 .lower_ifind_msb = true,
1942 .lower_ldexp = true,
1943 .lower_mul_high = true,
1944 .native_integers = true,
1945 };
1946
1947
1948 #if 0
1949 static int
1950 count_nir_instrs(nir_shader *nir)
1951 {
1952 int count = 0;
1953 nir_foreach_function(function, nir) {
1954 if (!function->impl)
1955 continue;
1956 nir_foreach_block(block, function->impl) {
1957 nir_foreach_instr(instr, block)
1958 count++;
1959 }
1960 }
1961 return count;
1962 }
1963 #endif
1964
1965 /**
1966 * When demoting a shader down to single-threaded, removes the THRSW
1967 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
1968 * program end).
1969 */
1970 static void
1971 vir_remove_thrsw(struct v3d_compile *c)
1972 {
1973 vir_for_each_block(block, c) {
1974 vir_for_each_inst_safe(inst, block) {
1975 if (inst->qpu.sig.thrsw)
1976 vir_remove_instruction(c, inst);
1977 }
1978 }
1979
1980 c->last_thrsw = NULL;
1981 }
1982
1983 void
1984 vir_emit_last_thrsw(struct v3d_compile *c)
1985 {
1986 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
1987 * switching, so disable threads if we didn't do any TMU ops (each of
1988 * which would have emitted a THRSW).
1989 */
1990 if (!c->last_thrsw_at_top_level && c->devinfo->ver < 41) {
1991 c->threads = 1;
1992 if (c->last_thrsw)
1993 vir_remove_thrsw(c);
1994 return;
1995 }
1996
1997 /* If we're threaded and the last THRSW was in conditional code, then
1998 * we need to emit another one so that we can flag it as the last
1999 * thrsw.
2000 */
2001 if (c->last_thrsw && !c->last_thrsw_at_top_level) {
2002 assert(c->devinfo->ver >= 41);
2003 vir_emit_thrsw(c);
2004 }
2005
2006 /* If we're threaded, then we need to mark the last THRSW instruction
2007 * so we can emit a pair of them at QPU emit time.
2008 *
2009 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2010 * post-last-THRSW state, so we can skip this.
2011 */
2012 if (!c->last_thrsw && c->s->info.stage == MESA_SHADER_FRAGMENT) {
2013 assert(c->devinfo->ver >= 41);
2014 vir_emit_thrsw(c);
2015 }
2016
2017 if (c->last_thrsw)
2018 c->last_thrsw->is_last_thrsw = true;
2019 }
2020
2021 /* There's a flag in the shader for "center W is needed for reasons other than
2022 * non-centroid varyings", so we just walk the program after VIR optimization
2023 * to see if it's used. It should be harmless to set even if we only use
2024 * center W for varyings.
2025 */
2026 static void
2027 vir_check_payload_w(struct v3d_compile *c)
2028 {
2029 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
2030 return;
2031
2032 vir_for_each_inst_inorder(inst, c) {
2033 for (int i = 0; i < vir_get_nsrc(inst); i++) {
2034 if (inst->src[i].file == QFILE_REG &&
2035 inst->src[i].index == 0) {
2036 c->uses_center_w = true;
2037 return;
2038 }
2039 }
2040 }
2041
2042 }
2043
2044 void
2045 v3d_nir_to_vir(struct v3d_compile *c)
2046 {
2047 if (V3D_DEBUG & (V3D_DEBUG_NIR |
2048 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2049 fprintf(stderr, "%s prog %d/%d NIR:\n",
2050 vir_get_stage_name(c),
2051 c->program_id, c->variant_id);
2052 nir_print_shader(c->s, stderr);
2053 }
2054
2055 nir_to_vir(c);
2056
2057 /* Emit the last THRSW before STVPM and TLB writes. */
2058 vir_emit_last_thrsw(c);
2059
2060 switch (c->s->info.stage) {
2061 case MESA_SHADER_FRAGMENT:
2062 emit_frag_end(c);
2063 break;
2064 case MESA_SHADER_VERTEX:
2065 emit_vert_end(c);
2066 break;
2067 default:
2068 unreachable("bad stage");
2069 }
2070
2071 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2072 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2073 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
2074 vir_get_stage_name(c),
2075 c->program_id, c->variant_id);
2076 vir_dump(c);
2077 fprintf(stderr, "\n");
2078 }
2079
2080 vir_optimize(c);
2081 vir_lower_uniforms(c);
2082
2083 vir_check_payload_w(c);
2084
2085 /* XXX: vir_schedule_instructions(c); */
2086
2087 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2088 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2089 fprintf(stderr, "%s prog %d/%d VIR:\n",
2090 vir_get_stage_name(c),
2091 c->program_id, c->variant_id);
2092 vir_dump(c);
2093 fprintf(stderr, "\n");
2094 }
2095
2096 /* Attempt to allocate registers for the temporaries. If we fail,
2097 * reduce thread count and try again.
2098 */
2099 int min_threads = (c->devinfo->ver >= 41) ? 2 : 1;
2100 struct qpu_reg *temp_registers;
2101 while (true) {
2102 bool spilled;
2103 temp_registers = v3d_register_allocate(c, &spilled);
2104 if (spilled)
2105 continue;
2106
2107 if (temp_registers)
2108 break;
2109
2110 if (c->threads == min_threads) {
2111 fprintf(stderr, "Failed to register allocate at %d threads:\n",
2112 c->threads);
2113 vir_dump(c);
2114 c->failed = true;
2115 return;
2116 }
2117
2118 c->threads /= 2;
2119
2120 if (c->threads == 1)
2121 vir_remove_thrsw(c);
2122 }
2123
2124 v3d_vir_to_qpu(c, temp_registers);
2125 }