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v3d: Add support for CS barrier() intrinsics.
[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
34
35 #define GENERAL_TMU_LOOKUP_PER_QUAD (0 << 7)
36 #define GENERAL_TMU_LOOKUP_PER_PIXEL (1 << 7)
37 #define GENERAL_TMU_READ_OP_PREFETCH (0 << 3)
38 #define GENERAL_TMU_READ_OP_CACHE_CLEAR (1 << 3)
39 #define GENERAL_TMU_READ_OP_CACHE_FLUSH (3 << 3)
40 #define GENERAL_TMU_READ_OP_CACHE_CLEAN (3 << 3)
41 #define GENERAL_TMU_READ_OP_CACHE_L1T_CLEAR (4 << 3)
42 #define GENERAL_TMU_READ_OP_CACHE_L1T_FLUSH_AGGREGATION (5 << 3)
43 #define GENERAL_TMU_READ_OP_ATOMIC_INC (8 << 3)
44 #define GENERAL_TMU_READ_OP_ATOMIC_DEC (9 << 3)
45 #define GENERAL_TMU_READ_OP_ATOMIC_NOT (10 << 3)
46 #define GENERAL_TMU_READ_OP_READ (15 << 3)
47 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_I (0 << 0)
48 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_I (1 << 0)
49 #define GENERAL_TMU_LOOKUP_TYPE_VEC2 (2 << 0)
50 #define GENERAL_TMU_LOOKUP_TYPE_VEC3 (3 << 0)
51 #define GENERAL_TMU_LOOKUP_TYPE_VEC4 (4 << 0)
52 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_UI (5 << 0)
53 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_UI (6 << 0)
54 #define GENERAL_TMU_LOOKUP_TYPE_32BIT_UI (7 << 0)
55
56 #define GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP (0 << 3)
57 #define GENERAL_TMU_WRITE_OP_ATOMIC_SUB_WRAP (1 << 3)
58 #define GENERAL_TMU_WRITE_OP_ATOMIC_XCHG (2 << 3)
59 #define GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG (3 << 3)
60 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMIN (4 << 3)
61 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMAX (5 << 3)
62 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMIN (6 << 3)
63 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMAX (7 << 3)
64 #define GENERAL_TMU_WRITE_OP_ATOMIC_AND (8 << 3)
65 #define GENERAL_TMU_WRITE_OP_ATOMIC_OR (9 << 3)
66 #define GENERAL_TMU_WRITE_OP_ATOMIC_XOR (10 << 3)
67 #define GENERAL_TMU_WRITE_OP_WRITE (15 << 3)
68
69 #define V3D_TSY_SET_QUORUM 0
70 #define V3D_TSY_INC_WAITERS 1
71 #define V3D_TSY_DEC_WAITERS 2
72 #define V3D_TSY_INC_QUORUM 3
73 #define V3D_TSY_DEC_QUORUM 4
74 #define V3D_TSY_FREE_ALL 5
75 #define V3D_TSY_RELEASE 6
76 #define V3D_TSY_ACQUIRE 7
77 #define V3D_TSY_WAIT 8
78 #define V3D_TSY_WAIT_INC 9
79 #define V3D_TSY_WAIT_CHECK 10
80 #define V3D_TSY_WAIT_INC_CHECK 11
81 #define V3D_TSY_WAIT_CV 12
82 #define V3D_TSY_INC_SEMAPHORE 13
83 #define V3D_TSY_DEC_SEMAPHORE 14
84 #define V3D_TSY_SET_QUORUM_FREE_ALL 15
85
86 static void
87 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
88
89 static void
90 resize_qreg_array(struct v3d_compile *c,
91 struct qreg **regs,
92 uint32_t *size,
93 uint32_t decl_size)
94 {
95 if (*size >= decl_size)
96 return;
97
98 uint32_t old_size = *size;
99 *size = MAX2(*size * 2, decl_size);
100 *regs = reralloc(c, *regs, struct qreg, *size);
101 if (!*regs) {
102 fprintf(stderr, "Malloc failure\n");
103 abort();
104 }
105
106 for (uint32_t i = old_size; i < *size; i++)
107 (*regs)[i] = c->undef;
108 }
109
110 void
111 vir_emit_thrsw(struct v3d_compile *c)
112 {
113 if (c->threads == 1)
114 return;
115
116 /* Always thread switch after each texture operation for now.
117 *
118 * We could do better by batching a bunch of texture fetches up and
119 * then doing one thread switch and collecting all their results
120 * afterward.
121 */
122 c->last_thrsw = vir_NOP(c);
123 c->last_thrsw->qpu.sig.thrsw = true;
124 c->last_thrsw_at_top_level = (c->execute.file == QFILE_NULL);
125 }
126
127 static uint32_t
128 v3d_general_tmu_op(nir_intrinsic_instr *instr)
129 {
130 switch (instr->intrinsic) {
131 case nir_intrinsic_load_ssbo:
132 case nir_intrinsic_load_ubo:
133 case nir_intrinsic_load_uniform:
134 case nir_intrinsic_load_shared:
135 return GENERAL_TMU_READ_OP_READ;
136 case nir_intrinsic_store_ssbo:
137 case nir_intrinsic_store_shared:
138 return GENERAL_TMU_WRITE_OP_WRITE;
139 case nir_intrinsic_ssbo_atomic_add:
140 case nir_intrinsic_shared_atomic_add:
141 return GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP;
142 case nir_intrinsic_ssbo_atomic_imin:
143 case nir_intrinsic_shared_atomic_imin:
144 return GENERAL_TMU_WRITE_OP_ATOMIC_SMIN;
145 case nir_intrinsic_ssbo_atomic_umin:
146 case nir_intrinsic_shared_atomic_umin:
147 return GENERAL_TMU_WRITE_OP_ATOMIC_UMIN;
148 case nir_intrinsic_ssbo_atomic_imax:
149 case nir_intrinsic_shared_atomic_imax:
150 return GENERAL_TMU_WRITE_OP_ATOMIC_SMAX;
151 case nir_intrinsic_ssbo_atomic_umax:
152 case nir_intrinsic_shared_atomic_umax:
153 return GENERAL_TMU_WRITE_OP_ATOMIC_UMAX;
154 case nir_intrinsic_ssbo_atomic_and:
155 case nir_intrinsic_shared_atomic_and:
156 return GENERAL_TMU_WRITE_OP_ATOMIC_AND;
157 case nir_intrinsic_ssbo_atomic_or:
158 case nir_intrinsic_shared_atomic_or:
159 return GENERAL_TMU_WRITE_OP_ATOMIC_OR;
160 case nir_intrinsic_ssbo_atomic_xor:
161 case nir_intrinsic_shared_atomic_xor:
162 return GENERAL_TMU_WRITE_OP_ATOMIC_XOR;
163 case nir_intrinsic_ssbo_atomic_exchange:
164 case nir_intrinsic_shared_atomic_exchange:
165 return GENERAL_TMU_WRITE_OP_ATOMIC_XCHG;
166 case nir_intrinsic_ssbo_atomic_comp_swap:
167 case nir_intrinsic_shared_atomic_comp_swap:
168 return GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG;
169 default:
170 unreachable("unknown intrinsic op");
171 }
172 }
173
174 /**
175 * Implements indirect uniform loads and SSBO accesses through the TMU general
176 * memory access interface.
177 */
178 static void
179 ntq_emit_tmu_general(struct v3d_compile *c, nir_intrinsic_instr *instr,
180 bool is_shared)
181 {
182 /* XXX perf: We should turn add/sub of 1 to inc/dec. Perhaps NIR
183 * wants to have support for inc/dec?
184 */
185
186 uint32_t tmu_op = v3d_general_tmu_op(instr);
187 bool is_store = (instr->intrinsic == nir_intrinsic_store_ssbo ||
188 instr->intrinsic == nir_intrinsic_store_shared);
189 bool has_index = !is_shared;
190
191 int offset_src;
192 int tmu_writes = 1; /* address */
193 if (instr->intrinsic == nir_intrinsic_load_uniform) {
194 offset_src = 0;
195 } else if (instr->intrinsic == nir_intrinsic_load_ssbo ||
196 instr->intrinsic == nir_intrinsic_load_ubo ||
197 instr->intrinsic == nir_intrinsic_load_shared) {
198 offset_src = 0 + has_index;
199 } else if (is_store) {
200 offset_src = 1 + has_index;
201 for (int i = 0; i < instr->num_components; i++) {
202 vir_MOV_dest(c,
203 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
204 ntq_get_src(c, instr->src[0], i));
205 tmu_writes++;
206 }
207 } else {
208 offset_src = 0 + has_index;
209 vir_MOV_dest(c,
210 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
211 ntq_get_src(c, instr->src[1 + has_index], 0));
212 tmu_writes++;
213 if (tmu_op == GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG) {
214 vir_MOV_dest(c,
215 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
216 ntq_get_src(c, instr->src[2 + has_index],
217 0));
218 tmu_writes++;
219 }
220 }
221
222 /* Make sure we won't exceed the 16-entry TMU fifo if each thread is
223 * storing at the same time.
224 */
225 while (tmu_writes > 16 / c->threads)
226 c->threads /= 2;
227
228 struct qreg offset;
229 if (instr->intrinsic == nir_intrinsic_load_uniform) {
230 offset = vir_uniform(c, QUNIFORM_UBO_ADDR, 0);
231
232 /* Find what variable in the default uniform block this
233 * uniform load is coming from.
234 */
235 uint32_t base = nir_intrinsic_base(instr);
236 int i;
237 struct v3d_ubo_range *range = NULL;
238 for (i = 0; i < c->num_ubo_ranges; i++) {
239 range = &c->ubo_ranges[i];
240 if (base >= range->src_offset &&
241 base < range->src_offset + range->size) {
242 break;
243 }
244 }
245 /* The driver-location-based offset always has to be within a
246 * declared uniform range.
247 */
248 assert(i != c->num_ubo_ranges);
249 if (!c->ubo_range_used[i]) {
250 c->ubo_range_used[i] = true;
251 range->dst_offset = c->next_ubo_dst_offset;
252 c->next_ubo_dst_offset += range->size;
253 }
254
255 base = base - range->src_offset + range->dst_offset;
256
257 if (base != 0)
258 offset = vir_ADD(c, offset, vir_uniform_ui(c, base));
259 } else if (instr->intrinsic == nir_intrinsic_load_ubo) {
260 /* Note that QUNIFORM_UBO_ADDR takes a UBO index shifted up by
261 * 1 (0 is gallium's constant buffer 0).
262 */
263 offset = vir_uniform(c, QUNIFORM_UBO_ADDR,
264 nir_src_as_uint(instr->src[0]) + 1);
265 } else if (is_shared) {
266 /* Shared variables have no buffer index, and all start from a
267 * common base that we set up at the start of dispatch
268 */
269 offset = c->cs_shared_offset;
270 } else {
271 offset = vir_uniform(c, QUNIFORM_SSBO_OFFSET,
272 nir_src_as_uint(instr->src[is_store ?
273 1 : 0]));
274 }
275
276 uint32_t config = (0xffffff00 |
277 tmu_op |
278 GENERAL_TMU_LOOKUP_PER_PIXEL);
279 if (instr->num_components == 1) {
280 config |= GENERAL_TMU_LOOKUP_TYPE_32BIT_UI;
281 } else {
282 config |= (GENERAL_TMU_LOOKUP_TYPE_VEC2 +
283 instr->num_components - 2);
284 }
285
286 if (c->execute.file != QFILE_NULL)
287 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
288
289 struct qreg dest;
290 if (config == ~0)
291 dest = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA);
292 else
293 dest = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUAU);
294
295 struct qinst *tmu;
296 if (nir_src_is_const(instr->src[offset_src]) &&
297 nir_src_as_uint(instr->src[offset_src]) == 0) {
298 tmu = vir_MOV_dest(c, dest, offset);
299 } else {
300 tmu = vir_ADD_dest(c, dest,
301 offset,
302 ntq_get_src(c, instr->src[offset_src], 0));
303 }
304
305 if (config != ~0) {
306 tmu->src[vir_get_implicit_uniform_src(tmu)] =
307 vir_uniform_ui(c, config);
308 }
309
310 if (c->execute.file != QFILE_NULL)
311 vir_set_cond(tmu, V3D_QPU_COND_IFA);
312
313 vir_emit_thrsw(c);
314
315 /* Read the result, or wait for the TMU op to complete. */
316 for (int i = 0; i < nir_intrinsic_dest_components(instr); i++)
317 ntq_store_dest(c, &instr->dest, i, vir_MOV(c, vir_LDTMU(c)));
318
319 if (nir_intrinsic_dest_components(instr) == 0)
320 vir_TMUWT(c);
321 }
322
323 static struct qreg *
324 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
325 {
326 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
327 def->num_components);
328 _mesa_hash_table_insert(c->def_ht, def, qregs);
329 return qregs;
330 }
331
332 /**
333 * This function is responsible for getting VIR results into the associated
334 * storage for a NIR instruction.
335 *
336 * If it's a NIR SSA def, then we just set the associated hash table entry to
337 * the new result.
338 *
339 * If it's a NIR reg, then we need to update the existing qreg assigned to the
340 * NIR destination with the incoming value. To do that without introducing
341 * new MOVs, we require that the incoming qreg either be a uniform, or be
342 * SSA-defined by the previous VIR instruction in the block and rewritable by
343 * this function. That lets us sneak ahead and insert the SF flag beforehand
344 * (knowing that the previous instruction doesn't depend on flags) and rewrite
345 * its destination to be the NIR reg's destination
346 */
347 void
348 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
349 struct qreg result)
350 {
351 struct qinst *last_inst = NULL;
352 if (!list_empty(&c->cur_block->instructions))
353 last_inst = (struct qinst *)c->cur_block->instructions.prev;
354
355 assert(result.file == QFILE_UNIF ||
356 (result.file == QFILE_TEMP &&
357 last_inst && last_inst == c->defs[result.index]));
358
359 if (dest->is_ssa) {
360 assert(chan < dest->ssa.num_components);
361
362 struct qreg *qregs;
363 struct hash_entry *entry =
364 _mesa_hash_table_search(c->def_ht, &dest->ssa);
365
366 if (entry)
367 qregs = entry->data;
368 else
369 qregs = ntq_init_ssa_def(c, &dest->ssa);
370
371 qregs[chan] = result;
372 } else {
373 nir_register *reg = dest->reg.reg;
374 assert(dest->reg.base_offset == 0);
375 assert(reg->num_array_elems == 0);
376 struct hash_entry *entry =
377 _mesa_hash_table_search(c->def_ht, reg);
378 struct qreg *qregs = entry->data;
379
380 /* Insert a MOV if the source wasn't an SSA def in the
381 * previous instruction.
382 */
383 if (result.file == QFILE_UNIF) {
384 result = vir_MOV(c, result);
385 last_inst = c->defs[result.index];
386 }
387
388 /* We know they're both temps, so just rewrite index. */
389 c->defs[last_inst->dst.index] = NULL;
390 last_inst->dst.index = qregs[chan].index;
391
392 /* If we're in control flow, then make this update of the reg
393 * conditional on the execution mask.
394 */
395 if (c->execute.file != QFILE_NULL) {
396 last_inst->dst.index = qregs[chan].index;
397
398 /* Set the flags to the current exec mask.
399 */
400 c->cursor = vir_before_inst(last_inst);
401 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
402 c->cursor = vir_after_inst(last_inst);
403
404 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
405 last_inst->cond_is_exec_mask = true;
406 }
407 }
408 }
409
410 struct qreg
411 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
412 {
413 struct hash_entry *entry;
414 if (src.is_ssa) {
415 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
416 assert(i < src.ssa->num_components);
417 } else {
418 nir_register *reg = src.reg.reg;
419 entry = _mesa_hash_table_search(c->def_ht, reg);
420 assert(reg->num_array_elems == 0);
421 assert(src.reg.base_offset == 0);
422 assert(i < reg->num_components);
423 }
424
425 struct qreg *qregs = entry->data;
426 return qregs[i];
427 }
428
429 static struct qreg
430 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
431 unsigned src)
432 {
433 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
434 unsigned chan = ffs(instr->dest.write_mask) - 1;
435 struct qreg r = ntq_get_src(c, instr->src[src].src,
436 instr->src[src].swizzle[chan]);
437
438 assert(!instr->src[src].abs);
439 assert(!instr->src[src].negate);
440
441 return r;
442 };
443
444 static struct qreg
445 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
446 {
447 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
448 }
449
450 static void
451 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
452 {
453 unsigned unit = instr->texture_index;
454 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
455 int dest_size = nir_tex_instr_dest_size(instr);
456
457 struct qreg lod = c->undef;
458 if (lod_index != -1)
459 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
460
461 for (int i = 0; i < dest_size; i++) {
462 assert(i < 3);
463 enum quniform_contents contents;
464
465 if (instr->is_array && i == dest_size - 1)
466 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
467 else
468 contents = QUNIFORM_TEXTURE_WIDTH + i;
469
470 struct qreg size = vir_uniform(c, contents, unit);
471
472 switch (instr->sampler_dim) {
473 case GLSL_SAMPLER_DIM_1D:
474 case GLSL_SAMPLER_DIM_2D:
475 case GLSL_SAMPLER_DIM_MS:
476 case GLSL_SAMPLER_DIM_3D:
477 case GLSL_SAMPLER_DIM_CUBE:
478 /* Don't minify the array size. */
479 if (!(instr->is_array && i == dest_size - 1)) {
480 size = ntq_minify(c, size, lod);
481 }
482 break;
483
484 case GLSL_SAMPLER_DIM_RECT:
485 /* There's no LOD field for rects */
486 break;
487
488 default:
489 unreachable("Bad sampler type");
490 }
491
492 ntq_store_dest(c, &instr->dest, i, size);
493 }
494 }
495
496 static void
497 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
498 {
499 unsigned unit = instr->texture_index;
500
501 /* Since each texture sampling op requires uploading uniforms to
502 * reference the texture, there's no HW support for texture size and
503 * you just upload uniforms containing the size.
504 */
505 switch (instr->op) {
506 case nir_texop_query_levels:
507 ntq_store_dest(c, &instr->dest, 0,
508 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
509 return;
510 case nir_texop_txs:
511 ntq_emit_txs(c, instr);
512 return;
513 default:
514 break;
515 }
516
517 if (c->devinfo->ver >= 40)
518 v3d40_vir_emit_tex(c, instr);
519 else
520 v3d33_vir_emit_tex(c, instr);
521 }
522
523 static struct qreg
524 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
525 {
526 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
527 if (is_cos)
528 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
529
530 struct qreg periods = vir_FROUND(c, input);
531 struct qreg sin_output = vir_SIN(c, vir_FSUB(c, input, periods));
532 return vir_XOR(c, sin_output, vir_SHL(c,
533 vir_FTOIN(c, periods),
534 vir_uniform_ui(c, -1)));
535 }
536
537 static struct qreg
538 ntq_fsign(struct v3d_compile *c, struct qreg src)
539 {
540 struct qreg t = vir_get_temp(c);
541
542 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
543 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHZ);
544 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
545 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHN);
546 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
547 return vir_MOV(c, t);
548 }
549
550 static struct qreg
551 ntq_isign(struct v3d_compile *c, struct qreg src)
552 {
553 struct qreg t = vir_get_temp(c);
554
555 vir_MOV_dest(c, t, vir_uniform_ui(c, 0));
556 vir_PF(c, vir_MOV(c, src), V3D_QPU_PF_PUSHZ);
557 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_ui(c, 1));
558 vir_PF(c, vir_MOV(c, src), V3D_QPU_PF_PUSHN);
559 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_ui(c, -1));
560 return vir_MOV(c, t);
561 }
562
563 static void
564 emit_fragcoord_input(struct v3d_compile *c, int attr)
565 {
566 c->inputs[attr * 4 + 0] = vir_FXCD(c);
567 c->inputs[attr * 4 + 1] = vir_FYCD(c);
568 c->inputs[attr * 4 + 2] = c->payload_z;
569 c->inputs[attr * 4 + 3] = vir_RECIP(c, c->payload_w);
570 }
571
572 static struct qreg
573 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
574 uint8_t swizzle, int array_index)
575 {
576 struct qreg r3 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R3);
577 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
578
579 struct qreg vary;
580 if (c->devinfo->ver >= 41) {
581 struct qinst *ldvary = vir_add_inst(V3D_QPU_A_NOP, c->undef,
582 c->undef, c->undef);
583 ldvary->qpu.sig.ldvary = true;
584 vary = vir_emit_def(c, ldvary);
585 } else {
586 vir_NOP(c)->qpu.sig.ldvary = true;
587 vary = r3;
588 }
589
590 /* For gl_PointCoord input or distance along a line, we'll be called
591 * with no nir_variable, and we don't count toward VPM size so we
592 * don't track an input slot.
593 */
594 if (!var) {
595 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
596 }
597
598 int i = c->num_inputs++;
599 c->input_slots[i] =
600 v3d_slot_from_slot_and_component(var->data.location +
601 array_index, swizzle);
602
603 switch (var->data.interpolation) {
604 case INTERP_MODE_NONE:
605 /* If a gl_FrontColor or gl_BackColor input has no interp
606 * qualifier, then if we're using glShadeModel(GL_FLAT) it
607 * needs to be flat shaded.
608 */
609 switch (var->data.location + array_index) {
610 case VARYING_SLOT_COL0:
611 case VARYING_SLOT_COL1:
612 case VARYING_SLOT_BFC0:
613 case VARYING_SLOT_BFC1:
614 if (c->fs_key->shade_model_flat) {
615 BITSET_SET(c->flat_shade_flags, i);
616 vir_MOV_dest(c, c->undef, vary);
617 return vir_MOV(c, r5);
618 } else {
619 return vir_FADD(c, vir_FMUL(c, vary,
620 c->payload_w), r5);
621 }
622 default:
623 break;
624 }
625 /* FALLTHROUGH */
626 case INTERP_MODE_SMOOTH:
627 if (var->data.centroid) {
628 BITSET_SET(c->centroid_flags, i);
629 return vir_FADD(c, vir_FMUL(c, vary,
630 c->payload_w_centroid), r5);
631 } else {
632 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
633 }
634 case INTERP_MODE_NOPERSPECTIVE:
635 BITSET_SET(c->noperspective_flags, i);
636 return vir_FADD(c, vir_MOV(c, vary), r5);
637 case INTERP_MODE_FLAT:
638 BITSET_SET(c->flat_shade_flags, i);
639 vir_MOV_dest(c, c->undef, vary);
640 return vir_MOV(c, r5);
641 default:
642 unreachable("Bad interp mode");
643 }
644 }
645
646 static void
647 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var,
648 int array_index)
649 {
650 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
651 int chan = var->data.location_frac + i;
652 c->inputs[attr * 4 + chan] =
653 emit_fragment_varying(c, var, chan, array_index);
654 }
655 }
656
657 static void
658 add_output(struct v3d_compile *c,
659 uint32_t decl_offset,
660 uint8_t slot,
661 uint8_t swizzle)
662 {
663 uint32_t old_array_size = c->outputs_array_size;
664 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
665 decl_offset + 1);
666
667 if (old_array_size != c->outputs_array_size) {
668 c->output_slots = reralloc(c,
669 c->output_slots,
670 struct v3d_varying_slot,
671 c->outputs_array_size);
672 }
673
674 c->output_slots[decl_offset] =
675 v3d_slot_from_slot_and_component(slot, swizzle);
676 }
677
678 static void
679 declare_uniform_range(struct v3d_compile *c, uint32_t start, uint32_t size)
680 {
681 unsigned array_id = c->num_ubo_ranges++;
682 if (array_id >= c->ubo_ranges_array_size) {
683 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
684 array_id + 1);
685 c->ubo_ranges = reralloc(c, c->ubo_ranges,
686 struct v3d_ubo_range,
687 c->ubo_ranges_array_size);
688 c->ubo_range_used = reralloc(c, c->ubo_range_used,
689 bool,
690 c->ubo_ranges_array_size);
691 }
692
693 c->ubo_ranges[array_id].dst_offset = 0;
694 c->ubo_ranges[array_id].src_offset = start;
695 c->ubo_ranges[array_id].size = size;
696 c->ubo_range_used[array_id] = false;
697 }
698
699 /**
700 * If compare_instr is a valid comparison instruction, emits the
701 * compare_instr's comparison and returns the sel_instr's return value based
702 * on the compare_instr's result.
703 */
704 static bool
705 ntq_emit_comparison(struct v3d_compile *c,
706 nir_alu_instr *compare_instr,
707 enum v3d_qpu_cond *out_cond)
708 {
709 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
710 struct qreg src1;
711 if (nir_op_infos[compare_instr->op].num_inputs > 1)
712 src1 = ntq_get_alu_src(c, compare_instr, 1);
713 bool cond_invert = false;
714 struct qreg nop = vir_reg(QFILE_NULL, 0);
715
716 switch (compare_instr->op) {
717 case nir_op_feq32:
718 case nir_op_seq:
719 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
720 break;
721 case nir_op_ieq32:
722 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
723 break;
724
725 case nir_op_fne32:
726 case nir_op_sne:
727 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
728 cond_invert = true;
729 break;
730 case nir_op_ine32:
731 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
732 cond_invert = true;
733 break;
734
735 case nir_op_fge32:
736 case nir_op_sge:
737 vir_set_pf(vir_FCMP_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
738 break;
739 case nir_op_ige32:
740 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
741 cond_invert = true;
742 break;
743 case nir_op_uge32:
744 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
745 cond_invert = true;
746 break;
747
748 case nir_op_slt:
749 case nir_op_flt32:
750 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHN);
751 break;
752 case nir_op_ilt32:
753 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
754 break;
755 case nir_op_ult32:
756 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
757 break;
758
759 default:
760 return false;
761 }
762
763 *out_cond = cond_invert ? V3D_QPU_COND_IFNA : V3D_QPU_COND_IFA;
764
765 return true;
766 }
767
768 /* Finds an ALU instruction that generates our src value that could
769 * (potentially) be greedily emitted in the consuming instruction.
770 */
771 static struct nir_alu_instr *
772 ntq_get_alu_parent(nir_src src)
773 {
774 if (!src.is_ssa || src.ssa->parent_instr->type != nir_instr_type_alu)
775 return NULL;
776 nir_alu_instr *instr = nir_instr_as_alu(src.ssa->parent_instr);
777 if (!instr)
778 return NULL;
779
780 /* If the ALU instr's srcs are non-SSA, then we would have to avoid
781 * moving emission of the ALU instr down past another write of the
782 * src.
783 */
784 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
785 if (!instr->src[i].src.is_ssa)
786 return NULL;
787 }
788
789 return instr;
790 }
791
792 /**
793 * Attempts to fold a comparison generating a boolean result into the
794 * condition code for selecting between two values, instead of comparing the
795 * boolean result against 0 to generate the condition code.
796 */
797 static struct qreg ntq_emit_bcsel(struct v3d_compile *c, nir_alu_instr *instr,
798 struct qreg *src)
799 {
800 nir_alu_instr *compare = ntq_get_alu_parent(instr->src[0].src);
801 if (!compare)
802 goto out;
803
804 enum v3d_qpu_cond cond;
805 if (ntq_emit_comparison(c, compare, &cond))
806 return vir_MOV(c, vir_SEL(c, cond, src[1], src[2]));
807
808 out:
809 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
810 return vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA, src[1], src[2]));
811 }
812
813
814 static void
815 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
816 {
817 /* This should always be lowered to ALU operations for V3D. */
818 assert(!instr->dest.saturate);
819
820 /* Vectors are special in that they have non-scalarized writemasks,
821 * and just take the first swizzle channel for each argument in order
822 * into each writemask channel.
823 */
824 if (instr->op == nir_op_vec2 ||
825 instr->op == nir_op_vec3 ||
826 instr->op == nir_op_vec4) {
827 struct qreg srcs[4];
828 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
829 srcs[i] = ntq_get_src(c, instr->src[i].src,
830 instr->src[i].swizzle[0]);
831 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
832 ntq_store_dest(c, &instr->dest.dest, i,
833 vir_MOV(c, srcs[i]));
834 return;
835 }
836
837 /* General case: We can just grab the one used channel per src. */
838 struct qreg src[nir_op_infos[instr->op].num_inputs];
839 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
840 src[i] = ntq_get_alu_src(c, instr, i);
841 }
842
843 struct qreg result;
844
845 switch (instr->op) {
846 case nir_op_fmov:
847 case nir_op_imov:
848 result = vir_MOV(c, src[0]);
849 break;
850
851 case nir_op_fneg:
852 result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
853 break;
854 case nir_op_ineg:
855 result = vir_NEG(c, src[0]);
856 break;
857
858 case nir_op_fmul:
859 result = vir_FMUL(c, src[0], src[1]);
860 break;
861 case nir_op_fadd:
862 result = vir_FADD(c, src[0], src[1]);
863 break;
864 case nir_op_fsub:
865 result = vir_FSUB(c, src[0], src[1]);
866 break;
867 case nir_op_fmin:
868 result = vir_FMIN(c, src[0], src[1]);
869 break;
870 case nir_op_fmax:
871 result = vir_FMAX(c, src[0], src[1]);
872 break;
873
874 case nir_op_f2i32:
875 result = vir_FTOIZ(c, src[0]);
876 break;
877 case nir_op_f2u32:
878 result = vir_FTOUZ(c, src[0]);
879 break;
880 case nir_op_i2f32:
881 result = vir_ITOF(c, src[0]);
882 break;
883 case nir_op_u2f32:
884 result = vir_UTOF(c, src[0]);
885 break;
886 case nir_op_b2f32:
887 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
888 break;
889 case nir_op_b2i32:
890 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
891 break;
892 case nir_op_i2b32:
893 case nir_op_f2b32:
894 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
895 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
896 vir_uniform_ui(c, ~0),
897 vir_uniform_ui(c, 0)));
898 break;
899
900 case nir_op_iadd:
901 result = vir_ADD(c, src[0], src[1]);
902 break;
903 case nir_op_ushr:
904 result = vir_SHR(c, src[0], src[1]);
905 break;
906 case nir_op_isub:
907 result = vir_SUB(c, src[0], src[1]);
908 break;
909 case nir_op_ishr:
910 result = vir_ASR(c, src[0], src[1]);
911 break;
912 case nir_op_ishl:
913 result = vir_SHL(c, src[0], src[1]);
914 break;
915 case nir_op_imin:
916 result = vir_MIN(c, src[0], src[1]);
917 break;
918 case nir_op_umin:
919 result = vir_UMIN(c, src[0], src[1]);
920 break;
921 case nir_op_imax:
922 result = vir_MAX(c, src[0], src[1]);
923 break;
924 case nir_op_umax:
925 result = vir_UMAX(c, src[0], src[1]);
926 break;
927 case nir_op_iand:
928 result = vir_AND(c, src[0], src[1]);
929 break;
930 case nir_op_ior:
931 result = vir_OR(c, src[0], src[1]);
932 break;
933 case nir_op_ixor:
934 result = vir_XOR(c, src[0], src[1]);
935 break;
936 case nir_op_inot:
937 result = vir_NOT(c, src[0]);
938 break;
939
940 case nir_op_ufind_msb:
941 result = vir_SUB(c, vir_uniform_ui(c, 31), vir_CLZ(c, src[0]));
942 break;
943
944 case nir_op_imul:
945 result = vir_UMUL(c, src[0], src[1]);
946 break;
947
948 case nir_op_seq:
949 case nir_op_sne:
950 case nir_op_sge:
951 case nir_op_slt: {
952 enum v3d_qpu_cond cond;
953 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
954 assert(ok);
955 result = vir_MOV(c, vir_SEL(c, cond,
956 vir_uniform_f(c, 1.0),
957 vir_uniform_f(c, 0.0)));
958 break;
959 }
960
961 case nir_op_feq32:
962 case nir_op_fne32:
963 case nir_op_fge32:
964 case nir_op_flt32:
965 case nir_op_ieq32:
966 case nir_op_ine32:
967 case nir_op_ige32:
968 case nir_op_uge32:
969 case nir_op_ilt32:
970 case nir_op_ult32: {
971 enum v3d_qpu_cond cond;
972 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
973 assert(ok);
974 result = vir_MOV(c, vir_SEL(c, cond,
975 vir_uniform_ui(c, ~0),
976 vir_uniform_ui(c, 0)));
977 break;
978 }
979
980 case nir_op_b32csel:
981 result = ntq_emit_bcsel(c, instr, src);
982 break;
983 case nir_op_fcsel:
984 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
985 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
986 src[1], src[2]));
987 break;
988
989 case nir_op_frcp:
990 result = vir_RECIP(c, src[0]);
991 break;
992 case nir_op_frsq:
993 result = vir_RSQRT(c, src[0]);
994 break;
995 case nir_op_fexp2:
996 result = vir_EXP(c, src[0]);
997 break;
998 case nir_op_flog2:
999 result = vir_LOG(c, src[0]);
1000 break;
1001
1002 case nir_op_fceil:
1003 result = vir_FCEIL(c, src[0]);
1004 break;
1005 case nir_op_ffloor:
1006 result = vir_FFLOOR(c, src[0]);
1007 break;
1008 case nir_op_fround_even:
1009 result = vir_FROUND(c, src[0]);
1010 break;
1011 case nir_op_ftrunc:
1012 result = vir_FTRUNC(c, src[0]);
1013 break;
1014 case nir_op_ffract:
1015 result = vir_FSUB(c, src[0], vir_FFLOOR(c, src[0]));
1016 break;
1017
1018 case nir_op_fsin:
1019 result = ntq_fsincos(c, src[0], false);
1020 break;
1021 case nir_op_fcos:
1022 result = ntq_fsincos(c, src[0], true);
1023 break;
1024
1025 case nir_op_fsign:
1026 result = ntq_fsign(c, src[0]);
1027 break;
1028 case nir_op_isign:
1029 result = ntq_isign(c, src[0]);
1030 break;
1031
1032 case nir_op_fabs: {
1033 result = vir_FMOV(c, src[0]);
1034 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
1035 break;
1036 }
1037
1038 case nir_op_iabs:
1039 result = vir_MAX(c, src[0],
1040 vir_SUB(c, vir_uniform_ui(c, 0), src[0]));
1041 break;
1042
1043 case nir_op_fddx:
1044 case nir_op_fddx_coarse:
1045 case nir_op_fddx_fine:
1046 result = vir_FDX(c, src[0]);
1047 break;
1048
1049 case nir_op_fddy:
1050 case nir_op_fddy_coarse:
1051 case nir_op_fddy_fine:
1052 result = vir_FDY(c, src[0]);
1053 break;
1054
1055 case nir_op_uadd_carry:
1056 vir_PF(c, vir_ADD(c, src[0], src[1]), V3D_QPU_PF_PUSHC);
1057 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1058 vir_uniform_ui(c, ~0),
1059 vir_uniform_ui(c, 0)));
1060 break;
1061
1062 case nir_op_pack_half_2x16_split:
1063 result = vir_VFPACK(c, src[0], src[1]);
1064 break;
1065
1066 case nir_op_unpack_half_2x16_split_x:
1067 /* XXX perf: It would be good to be able to merge this unpack
1068 * with whatever uses our result.
1069 */
1070 result = vir_FMOV(c, src[0]);
1071 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_L);
1072 break;
1073
1074 case nir_op_unpack_half_2x16_split_y:
1075 result = vir_FMOV(c, src[0]);
1076 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_H);
1077 break;
1078
1079 default:
1080 fprintf(stderr, "unknown NIR ALU inst: ");
1081 nir_print_instr(&instr->instr, stderr);
1082 fprintf(stderr, "\n");
1083 abort();
1084 }
1085
1086 /* We have a scalar result, so the instruction should only have a
1087 * single channel written to.
1088 */
1089 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
1090 ntq_store_dest(c, &instr->dest.dest,
1091 ffs(instr->dest.write_mask) - 1, result);
1092 }
1093
1094 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
1095 * specifier. They come from a register that's preloaded with 0xffffffff
1096 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
1097 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
1098 */
1099 #define TLB_TYPE_F16_COLOR (3 << 6)
1100 #define TLB_TYPE_I32_COLOR (1 << 6)
1101 #define TLB_TYPE_F32_COLOR (0 << 6)
1102 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
1103 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
1104 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
1105 #define TLB_F16_SWAP_HI_LO (1 << 1)
1106 #define TLB_VEC_SIZE_4_F16 (1 << 0)
1107 #define TLB_VEC_SIZE_2_F16 (0 << 0)
1108 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
1109
1110 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
1111 * flag is set.
1112 */
1113 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
1114 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
1115 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
1116 #define TLB_V42_DEPTH_TYPE_INVARIANT (0 << 3) /* Unmodified sideband input used */
1117 #define TLB_V42_DEPTH_TYPE_PER_PIXEL (1 << 3) /* QPU result used */
1118
1119 /* Stencil is a single 32-bit write. */
1120 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1121
1122 static void
1123 emit_frag_end(struct v3d_compile *c)
1124 {
1125 /* XXX
1126 if (c->output_sample_mask_index != -1) {
1127 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1128 }
1129 */
1130
1131 bool has_any_tlb_color_write = false;
1132 for (int rt = 0; rt < c->fs_key->nr_cbufs; rt++) {
1133 if (c->output_color_var[rt])
1134 has_any_tlb_color_write = true;
1135 }
1136
1137 if (c->fs_key->sample_alpha_to_coverage && c->output_color_var[0]) {
1138 struct nir_variable *var = c->output_color_var[0];
1139 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1140
1141 vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1142 vir_AND(c,
1143 vir_MSF(c),
1144 vir_FTOC(c, color[3])));
1145 }
1146
1147 if (c->output_position_index != -1) {
1148 struct qinst *inst = vir_MOV_dest(c,
1149 vir_reg(QFILE_TLBU, 0),
1150 c->outputs[c->output_position_index]);
1151 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1152
1153 if (c->devinfo->ver >= 42) {
1154 tlb_specifier |= (TLB_V42_DEPTH_TYPE_PER_PIXEL |
1155 TLB_SAMPLE_MODE_PER_PIXEL);
1156 } else
1157 tlb_specifier |= TLB_DEPTH_TYPE_PER_PIXEL;
1158
1159 inst->src[vir_get_implicit_uniform_src(inst)] =
1160 vir_uniform_ui(c, tlb_specifier | 0xffffff00);
1161 } else if (c->s->info.fs.uses_discard ||
1162 c->fs_key->sample_alpha_to_coverage ||
1163 !has_any_tlb_color_write) {
1164 /* Emit passthrough Z if it needed to be delayed until shader
1165 * end due to potential discards.
1166 *
1167 * Since (single-threaded) fragment shaders always need a TLB
1168 * write, emit passthrouh Z if we didn't have any color
1169 * buffers and flag us as potentially discarding, so that we
1170 * can use Z as the TLB write.
1171 */
1172 c->s->info.fs.uses_discard = true;
1173
1174 struct qinst *inst = vir_MOV_dest(c,
1175 vir_reg(QFILE_TLBU, 0),
1176 vir_reg(QFILE_NULL, 0));
1177 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1178
1179 if (c->devinfo->ver >= 42) {
1180 /* The spec says the PER_PIXEL flag is ignored for
1181 * invariant writes, but the simulator demands it.
1182 */
1183 tlb_specifier |= (TLB_V42_DEPTH_TYPE_INVARIANT |
1184 TLB_SAMPLE_MODE_PER_PIXEL);
1185 } else {
1186 tlb_specifier |= TLB_DEPTH_TYPE_INVARIANT;
1187 }
1188
1189 inst->src[vir_get_implicit_uniform_src(inst)] =
1190 vir_uniform_ui(c, tlb_specifier | 0xffffff00);
1191 }
1192
1193 /* XXX: Performance improvement: Merge Z write and color writes TLB
1194 * uniform setup
1195 */
1196
1197 for (int rt = 0; rt < c->fs_key->nr_cbufs; rt++) {
1198 if (!c->output_color_var[rt])
1199 continue;
1200
1201 nir_variable *var = c->output_color_var[rt];
1202 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1203 int num_components = glsl_get_vector_elements(var->type);
1204 uint32_t conf = 0xffffff00;
1205 struct qinst *inst;
1206
1207 conf |= TLB_SAMPLE_MODE_PER_PIXEL;
1208 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1209
1210 if (c->fs_key->swap_color_rb & (1 << rt))
1211 num_components = MAX2(num_components, 3);
1212
1213 assert(num_components != 0);
1214 switch (glsl_get_base_type(var->type)) {
1215 case GLSL_TYPE_UINT:
1216 case GLSL_TYPE_INT:
1217 /* The F32 vs I32 distinction was dropped in 4.2. */
1218 if (c->devinfo->ver < 42)
1219 conf |= TLB_TYPE_I32_COLOR;
1220 else
1221 conf |= TLB_TYPE_F32_COLOR;
1222 conf |= ((num_components - 1) <<
1223 TLB_VEC_SIZE_MINUS_1_SHIFT);
1224
1225 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
1226 inst->src[vir_get_implicit_uniform_src(inst)] =
1227 vir_uniform_ui(c, conf);
1228
1229 for (int i = 1; i < num_components; i++) {
1230 inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
1231 color[i]);
1232 }
1233 break;
1234
1235 default: {
1236 struct qreg r = color[0];
1237 struct qreg g = color[1];
1238 struct qreg b = color[2];
1239 struct qreg a = color[3];
1240
1241 if (c->fs_key->f32_color_rb & (1 << rt)) {
1242 conf |= TLB_TYPE_F32_COLOR;
1243 conf |= ((num_components - 1) <<
1244 TLB_VEC_SIZE_MINUS_1_SHIFT);
1245 } else {
1246 conf |= TLB_TYPE_F16_COLOR;
1247 conf |= TLB_F16_SWAP_HI_LO;
1248 if (num_components >= 3)
1249 conf |= TLB_VEC_SIZE_4_F16;
1250 else
1251 conf |= TLB_VEC_SIZE_2_F16;
1252 }
1253
1254 if (c->fs_key->swap_color_rb & (1 << rt)) {
1255 r = color[2];
1256 b = color[0];
1257 }
1258
1259 if (c->fs_key->sample_alpha_to_one)
1260 a = vir_uniform_f(c, 1.0);
1261
1262 if (c->fs_key->f32_color_rb & (1 << rt)) {
1263 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), r);
1264 inst->src[vir_get_implicit_uniform_src(inst)] =
1265 vir_uniform_ui(c, conf);
1266
1267 if (num_components >= 2)
1268 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), g);
1269 if (num_components >= 3)
1270 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), b);
1271 if (num_components >= 4)
1272 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), a);
1273 } else {
1274 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), r, g);
1275 if (conf != ~0) {
1276 inst->dst.file = QFILE_TLBU;
1277 inst->src[vir_get_implicit_uniform_src(inst)] =
1278 vir_uniform_ui(c, conf);
1279 }
1280
1281 if (num_components >= 3)
1282 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), b, a);
1283 }
1284 break;
1285 }
1286 }
1287 }
1288 }
1289
1290 static void
1291 vir_VPM_WRITE(struct v3d_compile *c, struct qreg val, uint32_t *vpm_index)
1292 {
1293 if (c->devinfo->ver >= 40) {
1294 vir_STVPMV(c, vir_uniform_ui(c, *vpm_index), val);
1295 *vpm_index = *vpm_index + 1;
1296 } else {
1297 vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM), val);
1298 }
1299
1300 c->num_vpm_writes++;
1301 }
1302
1303 static void
1304 emit_scaled_viewport_write(struct v3d_compile *c, struct qreg rcp_w,
1305 uint32_t *vpm_index)
1306 {
1307 for (int i = 0; i < 2; i++) {
1308 struct qreg coord = c->outputs[c->output_position_index + i];
1309 coord = vir_FMUL(c, coord,
1310 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i,
1311 0));
1312 coord = vir_FMUL(c, coord, rcp_w);
1313 vir_VPM_WRITE(c, vir_FTOIN(c, coord), vpm_index);
1314 }
1315
1316 }
1317
1318 static void
1319 emit_zs_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index)
1320 {
1321 struct qreg zscale = vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1322 struct qreg zoffset = vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1323
1324 struct qreg z = c->outputs[c->output_position_index + 2];
1325 z = vir_FMUL(c, z, zscale);
1326 z = vir_FMUL(c, z, rcp_w);
1327 z = vir_FADD(c, z, zoffset);
1328 vir_VPM_WRITE(c, z, vpm_index);
1329 }
1330
1331 static void
1332 emit_rcp_wc_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index)
1333 {
1334 vir_VPM_WRITE(c, rcp_w, vpm_index);
1335 }
1336
1337 static void
1338 emit_point_size_write(struct v3d_compile *c, uint32_t *vpm_index)
1339 {
1340 struct qreg point_size;
1341
1342 if (c->output_point_size_index != -1)
1343 point_size = c->outputs[c->output_point_size_index];
1344 else
1345 point_size = vir_uniform_f(c, 1.0);
1346
1347 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1348 * BCM21553).
1349 */
1350 point_size = vir_FMAX(c, point_size, vir_uniform_f(c, .125));
1351
1352 vir_VPM_WRITE(c, point_size, vpm_index);
1353 }
1354
1355 static void
1356 emit_vpm_write_setup(struct v3d_compile *c)
1357 {
1358 if (c->devinfo->ver >= 40)
1359 return;
1360
1361 v3d33_vir_vpm_write_setup(c);
1362 }
1363
1364 /**
1365 * Sets up c->outputs[c->output_position_index] for the vertex shader
1366 * epilogue, if an output vertex position wasn't specified in the user's
1367 * shader. This may be the case for transform feedback with rasterizer
1368 * discard enabled.
1369 */
1370 static void
1371 setup_default_position(struct v3d_compile *c)
1372 {
1373 if (c->output_position_index != -1)
1374 return;
1375
1376 c->output_position_index = c->outputs_array_size;
1377 for (int i = 0; i < 4; i++) {
1378 add_output(c,
1379 c->output_position_index + i,
1380 VARYING_SLOT_POS, i);
1381 }
1382 }
1383
1384 static void
1385 emit_vert_end(struct v3d_compile *c)
1386 {
1387 setup_default_position(c);
1388
1389 uint32_t vpm_index = 0;
1390 struct qreg rcp_w = vir_RECIP(c,
1391 c->outputs[c->output_position_index + 3]);
1392
1393 emit_vpm_write_setup(c);
1394
1395 if (c->vs_key->is_coord) {
1396 for (int i = 0; i < 4; i++)
1397 vir_VPM_WRITE(c, c->outputs[c->output_position_index + i],
1398 &vpm_index);
1399 emit_scaled_viewport_write(c, rcp_w, &vpm_index);
1400 if (c->vs_key->per_vertex_point_size) {
1401 emit_point_size_write(c, &vpm_index);
1402 /* emit_rcp_wc_write(c, rcp_w); */
1403 }
1404 /* XXX: Z-only rendering */
1405 if (0)
1406 emit_zs_write(c, rcp_w, &vpm_index);
1407 } else {
1408 emit_scaled_viewport_write(c, rcp_w, &vpm_index);
1409 emit_zs_write(c, rcp_w, &vpm_index);
1410 emit_rcp_wc_write(c, rcp_w, &vpm_index);
1411 if (c->vs_key->per_vertex_point_size)
1412 emit_point_size_write(c, &vpm_index);
1413 }
1414
1415 for (int i = 0; i < c->vs_key->num_fs_inputs; i++) {
1416 struct v3d_varying_slot input = c->vs_key->fs_inputs[i];
1417 int j;
1418
1419 for (j = 0; j < c->num_outputs; j++) {
1420 struct v3d_varying_slot output = c->output_slots[j];
1421
1422 if (!memcmp(&input, &output, sizeof(input))) {
1423 vir_VPM_WRITE(c, c->outputs[j],
1424 &vpm_index);
1425 break;
1426 }
1427 }
1428 /* Emit padding if we didn't find a declared VS output for
1429 * this FS input.
1430 */
1431 if (j == c->num_outputs)
1432 vir_VPM_WRITE(c, vir_uniform_f(c, 0.0),
1433 &vpm_index);
1434 }
1435
1436 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1437 */
1438 if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
1439 vir_VPMWT(c);
1440 }
1441
1442 void
1443 v3d_optimize_nir(struct nir_shader *s)
1444 {
1445 bool progress;
1446
1447 do {
1448 progress = false;
1449
1450 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1451 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1452 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1453 NIR_PASS(progress, s, nir_copy_prop);
1454 NIR_PASS(progress, s, nir_opt_remove_phis);
1455 NIR_PASS(progress, s, nir_opt_dce);
1456 NIR_PASS(progress, s, nir_opt_dead_cf);
1457 NIR_PASS(progress, s, nir_opt_cse);
1458 NIR_PASS(progress, s, nir_opt_peephole_select, 8, true, true);
1459 NIR_PASS(progress, s, nir_opt_algebraic);
1460 NIR_PASS(progress, s, nir_opt_constant_folding);
1461 NIR_PASS(progress, s, nir_opt_undef);
1462 } while (progress);
1463
1464 NIR_PASS(progress, s, nir_opt_move_load_ubo);
1465 }
1466
1467 static int
1468 driver_location_compare(const void *in_a, const void *in_b)
1469 {
1470 const nir_variable *const *a = in_a;
1471 const nir_variable *const *b = in_b;
1472
1473 return (*a)->data.driver_location - (*b)->data.driver_location;
1474 }
1475
1476 static struct qreg
1477 ntq_emit_vpm_read(struct v3d_compile *c,
1478 uint32_t *num_components_queued,
1479 uint32_t *remaining,
1480 uint32_t vpm_index)
1481 {
1482 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1483
1484 if (c->devinfo->ver >= 40 ) {
1485 return vir_LDVPMV_IN(c,
1486 vir_uniform_ui(c,
1487 (*num_components_queued)++));
1488 }
1489
1490 if (*num_components_queued != 0) {
1491 (*num_components_queued)--;
1492 c->num_inputs++;
1493 return vir_MOV(c, vpm);
1494 }
1495
1496 uint32_t num_components = MIN2(*remaining, 32);
1497
1498 v3d33_vir_vpm_read_setup(c, num_components);
1499
1500 *num_components_queued = num_components - 1;
1501 *remaining -= num_components;
1502 c->num_inputs++;
1503
1504 return vir_MOV(c, vpm);
1505 }
1506
1507 static void
1508 ntq_setup_vpm_inputs(struct v3d_compile *c)
1509 {
1510 /* Figure out how many components of each vertex attribute the shader
1511 * uses. Each variable should have been split to individual
1512 * components and unused ones DCEed. The vertex fetcher will load
1513 * from the start of the attribute to the number of components we
1514 * declare we need in c->vattr_sizes[].
1515 */
1516 nir_foreach_variable(var, &c->s->inputs) {
1517 /* No VS attribute array support. */
1518 assert(MAX2(glsl_get_length(var->type), 1) == 1);
1519
1520 unsigned loc = var->data.driver_location;
1521 int start_component = var->data.location_frac;
1522 int num_components = glsl_get_components(var->type);
1523
1524 c->vattr_sizes[loc] = MAX2(c->vattr_sizes[loc],
1525 start_component + num_components);
1526 }
1527
1528 unsigned num_components = 0;
1529 uint32_t vpm_components_queued = 0;
1530 bool uses_iid = c->s->info.system_values_read &
1531 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1532 bool uses_vid = c->s->info.system_values_read &
1533 (1ull << SYSTEM_VALUE_VERTEX_ID);
1534 num_components += uses_iid;
1535 num_components += uses_vid;
1536
1537 for (int i = 0; i < ARRAY_SIZE(c->vattr_sizes); i++)
1538 num_components += c->vattr_sizes[i];
1539
1540 if (uses_iid) {
1541 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1542 &num_components, ~0);
1543 }
1544
1545 if (uses_vid) {
1546 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1547 &num_components, ~0);
1548 }
1549
1550 for (int loc = 0; loc < ARRAY_SIZE(c->vattr_sizes); loc++) {
1551 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1552 (loc + 1) * 4);
1553
1554 for (int i = 0; i < c->vattr_sizes[loc]; i++) {
1555 c->inputs[loc * 4 + i] =
1556 ntq_emit_vpm_read(c,
1557 &vpm_components_queued,
1558 &num_components,
1559 loc * 4 + i);
1560
1561 }
1562 }
1563
1564 if (c->devinfo->ver >= 40) {
1565 assert(vpm_components_queued == num_components);
1566 } else {
1567 assert(vpm_components_queued == 0);
1568 assert(num_components == 0);
1569 }
1570 }
1571
1572 static void
1573 ntq_setup_fs_inputs(struct v3d_compile *c)
1574 {
1575 unsigned num_entries = 0;
1576 unsigned num_components = 0;
1577 nir_foreach_variable(var, &c->s->inputs) {
1578 num_entries++;
1579 num_components += glsl_get_components(var->type);
1580 }
1581
1582 nir_variable *vars[num_entries];
1583
1584 unsigned i = 0;
1585 nir_foreach_variable(var, &c->s->inputs)
1586 vars[i++] = var;
1587
1588 /* Sort the variables so that we emit the input setup in
1589 * driver_location order. This is required for VPM reads, whose data
1590 * is fetched into the VPM in driver_location (TGSI register index)
1591 * order.
1592 */
1593 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1594
1595 for (unsigned i = 0; i < num_entries; i++) {
1596 nir_variable *var = vars[i];
1597 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1598 unsigned loc = var->data.driver_location;
1599
1600 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1601 (loc + array_len) * 4);
1602
1603 if (var->data.location == VARYING_SLOT_POS) {
1604 emit_fragcoord_input(c, loc);
1605 } else if (var->data.location == VARYING_SLOT_PNTC ||
1606 (var->data.location >= VARYING_SLOT_VAR0 &&
1607 (c->fs_key->point_sprite_mask &
1608 (1 << (var->data.location -
1609 VARYING_SLOT_VAR0))))) {
1610 c->inputs[loc * 4 + 0] = c->point_x;
1611 c->inputs[loc * 4 + 1] = c->point_y;
1612 } else {
1613 for (int j = 0; j < array_len; j++)
1614 emit_fragment_input(c, loc + j, var, j);
1615 }
1616 }
1617 }
1618
1619 static void
1620 ntq_setup_outputs(struct v3d_compile *c)
1621 {
1622 nir_foreach_variable(var, &c->s->outputs) {
1623 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1624 unsigned loc = var->data.driver_location * 4;
1625
1626 assert(array_len == 1);
1627 (void)array_len;
1628
1629 for (int i = 0; i < 4 - var->data.location_frac; i++) {
1630 add_output(c, loc + var->data.location_frac + i,
1631 var->data.location,
1632 var->data.location_frac + i);
1633 }
1634
1635 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1636 switch (var->data.location) {
1637 case FRAG_RESULT_COLOR:
1638 c->output_color_var[0] = var;
1639 c->output_color_var[1] = var;
1640 c->output_color_var[2] = var;
1641 c->output_color_var[3] = var;
1642 break;
1643 case FRAG_RESULT_DATA0:
1644 case FRAG_RESULT_DATA1:
1645 case FRAG_RESULT_DATA2:
1646 case FRAG_RESULT_DATA3:
1647 c->output_color_var[var->data.location -
1648 FRAG_RESULT_DATA0] = var;
1649 break;
1650 case FRAG_RESULT_DEPTH:
1651 c->output_position_index = loc;
1652 break;
1653 case FRAG_RESULT_SAMPLE_MASK:
1654 c->output_sample_mask_index = loc;
1655 break;
1656 }
1657 } else {
1658 switch (var->data.location) {
1659 case VARYING_SLOT_POS:
1660 c->output_position_index = loc;
1661 break;
1662 case VARYING_SLOT_PSIZ:
1663 c->output_point_size_index = loc;
1664 break;
1665 }
1666 }
1667 }
1668 }
1669
1670 static void
1671 ntq_setup_uniforms(struct v3d_compile *c)
1672 {
1673 nir_foreach_variable(var, &c->s->uniforms) {
1674 uint32_t vec4_count = glsl_count_attribute_slots(var->type,
1675 false);
1676 unsigned vec4_size = 4 * sizeof(float);
1677
1678 if (var->data.mode != nir_var_uniform)
1679 continue;
1680
1681 declare_uniform_range(c, var->data.driver_location * vec4_size,
1682 vec4_count * vec4_size);
1683
1684 }
1685 }
1686
1687 /**
1688 * Sets up the mapping from nir_register to struct qreg *.
1689 *
1690 * Each nir_register gets a struct qreg per 32-bit component being stored.
1691 */
1692 static void
1693 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1694 {
1695 foreach_list_typed(nir_register, nir_reg, node, list) {
1696 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1697 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1698 array_len *
1699 nir_reg->num_components);
1700
1701 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1702
1703 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1704 qregs[i] = vir_get_temp(c);
1705 }
1706 }
1707
1708 static void
1709 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1710 {
1711 /* XXX perf: Experiment with using immediate loads to avoid having
1712 * these end up in the uniform stream. Watch out for breaking the
1713 * small immediates optimization in the process!
1714 */
1715 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1716 for (int i = 0; i < instr->def.num_components; i++)
1717 qregs[i] = vir_uniform_ui(c, instr->value.u32[i]);
1718
1719 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1720 }
1721
1722 static void
1723 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1724 {
1725 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1726
1727 /* VIR needs there to be *some* value, so pick 0 (same as for
1728 * ntq_setup_registers().
1729 */
1730 for (int i = 0; i < instr->def.num_components; i++)
1731 qregs[i] = vir_uniform_ui(c, 0);
1732 }
1733
1734 static void
1735 ntq_emit_image_size(struct v3d_compile *c, nir_intrinsic_instr *instr)
1736 {
1737 assert(instr->intrinsic == nir_intrinsic_image_deref_size);
1738 nir_variable *var = nir_intrinsic_get_var(instr, 0);
1739 unsigned image_index = var->data.driver_location;
1740 const struct glsl_type *sampler_type = glsl_without_array(var->type);
1741 bool is_array = glsl_sampler_type_is_array(sampler_type);
1742
1743 ntq_store_dest(c, &instr->dest, 0,
1744 vir_uniform(c, QUNIFORM_IMAGE_WIDTH, image_index));
1745 if (instr->num_components > 1) {
1746 ntq_store_dest(c, &instr->dest, 1,
1747 vir_uniform(c, QUNIFORM_IMAGE_HEIGHT,
1748 image_index));
1749 }
1750 if (instr->num_components > 2) {
1751 ntq_store_dest(c, &instr->dest, 2,
1752 vir_uniform(c,
1753 is_array ?
1754 QUNIFORM_IMAGE_ARRAY_SIZE :
1755 QUNIFORM_IMAGE_DEPTH,
1756 image_index));
1757 }
1758 }
1759
1760 static void
1761 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
1762 {
1763 unsigned offset;
1764
1765 switch (instr->intrinsic) {
1766 case nir_intrinsic_load_uniform:
1767 if (nir_src_is_const(instr->src[0])) {
1768 int offset = (nir_intrinsic_base(instr) +
1769 nir_src_as_uint(instr->src[0]));
1770 assert(offset % 4 == 0);
1771 /* We need dwords */
1772 offset = offset / 4;
1773 for (int i = 0; i < instr->num_components; i++) {
1774 ntq_store_dest(c, &instr->dest, i,
1775 vir_uniform(c, QUNIFORM_UNIFORM,
1776 offset + i));
1777 }
1778 } else {
1779 ntq_emit_tmu_general(c, instr, false);
1780 }
1781 break;
1782
1783 case nir_intrinsic_load_ubo:
1784 ntq_emit_tmu_general(c, instr, false);
1785 break;
1786
1787 case nir_intrinsic_ssbo_atomic_add:
1788 case nir_intrinsic_ssbo_atomic_imin:
1789 case nir_intrinsic_ssbo_atomic_umin:
1790 case nir_intrinsic_ssbo_atomic_imax:
1791 case nir_intrinsic_ssbo_atomic_umax:
1792 case nir_intrinsic_ssbo_atomic_and:
1793 case nir_intrinsic_ssbo_atomic_or:
1794 case nir_intrinsic_ssbo_atomic_xor:
1795 case nir_intrinsic_ssbo_atomic_exchange:
1796 case nir_intrinsic_ssbo_atomic_comp_swap:
1797 case nir_intrinsic_load_ssbo:
1798 case nir_intrinsic_store_ssbo:
1799 ntq_emit_tmu_general(c, instr, false);
1800 break;
1801
1802 case nir_intrinsic_shared_atomic_add:
1803 case nir_intrinsic_shared_atomic_imin:
1804 case nir_intrinsic_shared_atomic_umin:
1805 case nir_intrinsic_shared_atomic_imax:
1806 case nir_intrinsic_shared_atomic_umax:
1807 case nir_intrinsic_shared_atomic_and:
1808 case nir_intrinsic_shared_atomic_or:
1809 case nir_intrinsic_shared_atomic_xor:
1810 case nir_intrinsic_shared_atomic_exchange:
1811 case nir_intrinsic_shared_atomic_comp_swap:
1812 case nir_intrinsic_load_shared:
1813 case nir_intrinsic_store_shared:
1814 ntq_emit_tmu_general(c, instr, true);
1815 break;
1816
1817 case nir_intrinsic_image_deref_load:
1818 case nir_intrinsic_image_deref_store:
1819 case nir_intrinsic_image_deref_atomic_add:
1820 case nir_intrinsic_image_deref_atomic_min:
1821 case nir_intrinsic_image_deref_atomic_max:
1822 case nir_intrinsic_image_deref_atomic_and:
1823 case nir_intrinsic_image_deref_atomic_or:
1824 case nir_intrinsic_image_deref_atomic_xor:
1825 case nir_intrinsic_image_deref_atomic_exchange:
1826 case nir_intrinsic_image_deref_atomic_comp_swap:
1827 v3d40_vir_emit_image_load_store(c, instr);
1828 break;
1829
1830 case nir_intrinsic_get_buffer_size:
1831 ntq_store_dest(c, &instr->dest, 0,
1832 vir_uniform(c, QUNIFORM_GET_BUFFER_SIZE,
1833 nir_src_as_uint(instr->src[0])));
1834 break;
1835
1836 case nir_intrinsic_load_user_clip_plane:
1837 for (int i = 0; i < instr->num_components; i++) {
1838 ntq_store_dest(c, &instr->dest, i,
1839 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1840 nir_intrinsic_ucp_id(instr) *
1841 4 + i));
1842 }
1843 break;
1844
1845 case nir_intrinsic_load_alpha_ref_float:
1846 ntq_store_dest(c, &instr->dest, 0,
1847 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1848 break;
1849
1850 case nir_intrinsic_load_sample_mask_in:
1851 ntq_store_dest(c, &instr->dest, 0, vir_MSF(c));
1852 break;
1853
1854 case nir_intrinsic_load_helper_invocation:
1855 vir_PF(c, vir_MSF(c), V3D_QPU_PF_PUSHZ);
1856 ntq_store_dest(c, &instr->dest, 0,
1857 vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1858 vir_uniform_ui(c, ~0),
1859 vir_uniform_ui(c, 0))));
1860 break;
1861
1862 case nir_intrinsic_load_front_face:
1863 /* The register contains 0 (front) or 1 (back), and we need to
1864 * turn it into a NIR bool where true means front.
1865 */
1866 ntq_store_dest(c, &instr->dest, 0,
1867 vir_ADD(c,
1868 vir_uniform_ui(c, -1),
1869 vir_REVF(c)));
1870 break;
1871
1872 case nir_intrinsic_load_instance_id:
1873 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
1874 break;
1875
1876 case nir_intrinsic_load_vertex_id:
1877 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
1878 break;
1879
1880 case nir_intrinsic_load_input:
1881 for (int i = 0; i < instr->num_components; i++) {
1882 offset = (nir_intrinsic_base(instr) +
1883 nir_src_as_uint(instr->src[0]));
1884 int comp = nir_intrinsic_component(instr) + i;
1885 ntq_store_dest(c, &instr->dest, i,
1886 vir_MOV(c, c->inputs[offset * 4 + comp]));
1887 }
1888 break;
1889
1890 case nir_intrinsic_store_output:
1891 offset = ((nir_intrinsic_base(instr) +
1892 nir_src_as_uint(instr->src[1])) * 4 +
1893 nir_intrinsic_component(instr));
1894
1895 for (int i = 0; i < instr->num_components; i++) {
1896 c->outputs[offset + i] =
1897 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
1898 }
1899 c->num_outputs = MAX2(c->num_outputs,
1900 offset + instr->num_components);
1901 break;
1902
1903 case nir_intrinsic_image_deref_size:
1904 ntq_emit_image_size(c, instr);
1905 break;
1906
1907 case nir_intrinsic_discard:
1908 if (c->execute.file != QFILE_NULL) {
1909 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1910 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1911 vir_uniform_ui(c, 0)),
1912 V3D_QPU_COND_IFA);
1913 } else {
1914 vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1915 vir_uniform_ui(c, 0));
1916 }
1917 break;
1918
1919 case nir_intrinsic_discard_if: {
1920 /* true (~0) if we're discarding */
1921 struct qreg cond = ntq_get_src(c, instr->src[0], 0);
1922
1923 if (c->execute.file != QFILE_NULL) {
1924 /* execute == 0 means the channel is active. Invert
1925 * the condition so that we can use zero as "executing
1926 * and discarding."
1927 */
1928 vir_PF(c, vir_OR(c, c->execute, vir_NOT(c, cond)),
1929 V3D_QPU_PF_PUSHZ);
1930 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1931 vir_uniform_ui(c, 0)),
1932 V3D_QPU_COND_IFA);
1933 } else {
1934 vir_PF(c, cond, V3D_QPU_PF_PUSHZ);
1935 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1936 vir_uniform_ui(c, 0)),
1937 V3D_QPU_COND_IFNA);
1938 }
1939
1940 break;
1941 }
1942
1943 case nir_intrinsic_memory_barrier:
1944 case nir_intrinsic_memory_barrier_atomic_counter:
1945 case nir_intrinsic_memory_barrier_buffer:
1946 case nir_intrinsic_memory_barrier_image:
1947 case nir_intrinsic_memory_barrier_shared:
1948 /* We don't do any instruction scheduling of these NIR
1949 * instructions between each other, so we just need to make
1950 * sure that the TMU operations before the barrier are flushed
1951 * before the ones after the barrier. That is currently
1952 * handled by having a THRSW in each of them and a LDTMU
1953 * series or a TMUWT after.
1954 */
1955 break;
1956
1957 case nir_intrinsic_barrier:
1958 /* Emit a TSY op to get all invocations in the workgroup
1959 * (actually supergroup) to block until the last invocation
1960 * reaches the TSY op.
1961 */
1962 if (c->devinfo->ver >= 42) {
1963 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
1964 V3D_QPU_WADDR_SYNCB));
1965 } else {
1966 struct qinst *sync =
1967 vir_BARRIERID_dest(c,
1968 vir_reg(QFILE_MAGIC,
1969 V3D_QPU_WADDR_SYNCU));
1970 sync->src[vir_get_implicit_uniform_src(sync)] =
1971 vir_uniform_ui(c,
1972 0xffffff00 |
1973 V3D_TSY_WAIT_INC_CHECK);
1974
1975 }
1976
1977 /* The blocking of a TSY op only happens at the next thread
1978 * switch. No texturing may be outstanding at the time of a
1979 * TSY blocking operation.
1980 */
1981 vir_emit_thrsw(c);
1982 break;
1983
1984 case nir_intrinsic_load_num_work_groups:
1985 for (int i = 0; i < 3; i++) {
1986 ntq_store_dest(c, &instr->dest, i,
1987 vir_uniform(c, QUNIFORM_NUM_WORK_GROUPS,
1988 i));
1989 }
1990 break;
1991
1992 case nir_intrinsic_load_local_invocation_index:
1993 ntq_store_dest(c, &instr->dest, 0,
1994 vir_SHR(c, c->cs_payload[1],
1995 vir_uniform_ui(c, 32 - c->local_invocation_index_bits)));
1996 break;
1997
1998 case nir_intrinsic_load_work_group_id:
1999 ntq_store_dest(c, &instr->dest, 0,
2000 vir_AND(c, c->cs_payload[0],
2001 vir_uniform_ui(c, 0xffff)));
2002 ntq_store_dest(c, &instr->dest, 1,
2003 vir_SHR(c, c->cs_payload[0],
2004 vir_uniform_ui(c, 16)));
2005 ntq_store_dest(c, &instr->dest, 2,
2006 vir_AND(c, c->cs_payload[1],
2007 vir_uniform_ui(c, 0xffff)));
2008 break;
2009
2010 default:
2011 fprintf(stderr, "Unknown intrinsic: ");
2012 nir_print_instr(&instr->instr, stderr);
2013 fprintf(stderr, "\n");
2014 break;
2015 }
2016 }
2017
2018 /* Clears (activates) the execute flags for any channels whose jump target
2019 * matches this block.
2020 *
2021 * XXX perf: Could we be using flpush/flpop somehow for our execution channel
2022 * enabling?
2023 *
2024 * XXX perf: For uniform control flow, we should be able to skip c->execute
2025 * handling entirely.
2026 */
2027 static void
2028 ntq_activate_execute_for_block(struct v3d_compile *c)
2029 {
2030 vir_set_pf(vir_XOR_dest(c, vir_reg(QFILE_NULL, 0),
2031 c->execute, vir_uniform_ui(c, c->cur_block->index)),
2032 V3D_QPU_PF_PUSHZ);
2033
2034 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2035 }
2036
2037 static void
2038 ntq_emit_uniform_if(struct v3d_compile *c, nir_if *if_stmt)
2039 {
2040 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2041 bool empty_else_block =
2042 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2043 exec_list_is_empty(&nir_else_block->instr_list));
2044
2045 struct qblock *then_block = vir_new_block(c);
2046 struct qblock *after_block = vir_new_block(c);
2047 struct qblock *else_block;
2048 if (empty_else_block)
2049 else_block = after_block;
2050 else
2051 else_block = vir_new_block(c);
2052
2053 /* Set up the flags for the IF condition (taking the THEN branch). */
2054 nir_alu_instr *if_condition_alu = ntq_get_alu_parent(if_stmt->condition);
2055 enum v3d_qpu_cond cond;
2056 if (!if_condition_alu ||
2057 !ntq_emit_comparison(c, if_condition_alu, &cond)) {
2058 vir_PF(c, ntq_get_src(c, if_stmt->condition, 0),
2059 V3D_QPU_PF_PUSHZ);
2060 cond = V3D_QPU_COND_IFNA;
2061 }
2062
2063 /* Jump to ELSE. */
2064 vir_BRANCH(c, cond == V3D_QPU_COND_IFA ?
2065 V3D_QPU_BRANCH_COND_ALLNA :
2066 V3D_QPU_BRANCH_COND_ALLA);
2067 vir_link_blocks(c->cur_block, else_block);
2068 vir_link_blocks(c->cur_block, then_block);
2069
2070 /* Process the THEN block. */
2071 vir_set_emit_block(c, then_block);
2072 ntq_emit_cf_list(c, &if_stmt->then_list);
2073
2074 if (!empty_else_block) {
2075 /* At the end of the THEN block, jump to ENDIF */
2076 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALWAYS);
2077 vir_link_blocks(c->cur_block, after_block);
2078
2079 /* Emit the else block. */
2080 vir_set_emit_block(c, else_block);
2081 ntq_activate_execute_for_block(c);
2082 ntq_emit_cf_list(c, &if_stmt->else_list);
2083 }
2084
2085 vir_link_blocks(c->cur_block, after_block);
2086
2087 vir_set_emit_block(c, after_block);
2088 }
2089
2090 static void
2091 ntq_emit_nonuniform_if(struct v3d_compile *c, nir_if *if_stmt)
2092 {
2093 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2094 bool empty_else_block =
2095 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2096 exec_list_is_empty(&nir_else_block->instr_list));
2097
2098 struct qblock *then_block = vir_new_block(c);
2099 struct qblock *after_block = vir_new_block(c);
2100 struct qblock *else_block;
2101 if (empty_else_block)
2102 else_block = after_block;
2103 else
2104 else_block = vir_new_block(c);
2105
2106 bool was_top_level = false;
2107 if (c->execute.file == QFILE_NULL) {
2108 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2109 was_top_level = true;
2110 }
2111
2112 /* Set up the flags for the IF condition (taking the THEN branch). */
2113 nir_alu_instr *if_condition_alu = ntq_get_alu_parent(if_stmt->condition);
2114 enum v3d_qpu_cond cond;
2115 if (!if_condition_alu ||
2116 !ntq_emit_comparison(c, if_condition_alu, &cond)) {
2117 vir_PF(c, ntq_get_src(c, if_stmt->condition, 0),
2118 V3D_QPU_PF_PUSHZ);
2119 cond = V3D_QPU_COND_IFNA;
2120 }
2121
2122 /* Update the flags+cond to mean "Taking the ELSE branch (!cond) and
2123 * was previously active (execute Z) for updating the exec flags.
2124 */
2125 if (was_top_level) {
2126 cond = v3d_qpu_cond_invert(cond);
2127 } else {
2128 struct qinst *inst = vir_MOV_dest(c, vir_reg(QFILE_NULL, 0),
2129 c->execute);
2130 if (cond == V3D_QPU_COND_IFA) {
2131 vir_set_uf(inst, V3D_QPU_UF_NORNZ);
2132 } else {
2133 vir_set_uf(inst, V3D_QPU_UF_ANDZ);
2134 cond = V3D_QPU_COND_IFA;
2135 }
2136 }
2137
2138 vir_MOV_cond(c, cond,
2139 c->execute,
2140 vir_uniform_ui(c, else_block->index));
2141
2142 /* Jump to ELSE if nothing is active for THEN, otherwise fall
2143 * through.
2144 */
2145 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
2146 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
2147 vir_link_blocks(c->cur_block, else_block);
2148 vir_link_blocks(c->cur_block, then_block);
2149
2150 /* Process the THEN block. */
2151 vir_set_emit_block(c, then_block);
2152 ntq_emit_cf_list(c, &if_stmt->then_list);
2153
2154 if (!empty_else_block) {
2155 /* Handle the end of the THEN block. First, all currently
2156 * active channels update their execute flags to point to
2157 * ENDIF
2158 */
2159 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
2160 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2161 vir_uniform_ui(c, after_block->index));
2162
2163 /* If everything points at ENDIF, then jump there immediately. */
2164 vir_PF(c, vir_XOR(c, c->execute,
2165 vir_uniform_ui(c, after_block->index)),
2166 V3D_QPU_PF_PUSHZ);
2167 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
2168 vir_link_blocks(c->cur_block, after_block);
2169 vir_link_blocks(c->cur_block, else_block);
2170
2171 vir_set_emit_block(c, else_block);
2172 ntq_activate_execute_for_block(c);
2173 ntq_emit_cf_list(c, &if_stmt->else_list);
2174 }
2175
2176 vir_link_blocks(c->cur_block, after_block);
2177
2178 vir_set_emit_block(c, after_block);
2179 if (was_top_level)
2180 c->execute = c->undef;
2181 else
2182 ntq_activate_execute_for_block(c);
2183 }
2184
2185 static void
2186 ntq_emit_if(struct v3d_compile *c, nir_if *nif)
2187 {
2188 if (c->execute.file == QFILE_NULL &&
2189 nir_src_is_dynamically_uniform(nif->condition)) {
2190 ntq_emit_uniform_if(c, nif);
2191 } else {
2192 ntq_emit_nonuniform_if(c, nif);
2193 }
2194 }
2195
2196 static void
2197 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
2198 {
2199 switch (jump->type) {
2200 case nir_jump_break:
2201 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
2202 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2203 vir_uniform_ui(c, c->loop_break_block->index));
2204 break;
2205
2206 case nir_jump_continue:
2207 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
2208 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2209 vir_uniform_ui(c, c->loop_cont_block->index));
2210 break;
2211
2212 case nir_jump_return:
2213 unreachable("All returns shouold be lowered\n");
2214 }
2215 }
2216
2217 static void
2218 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
2219 {
2220 switch (instr->type) {
2221 case nir_instr_type_deref:
2222 /* ignored, will be walked by the intrinsic using it. */
2223 break;
2224
2225 case nir_instr_type_alu:
2226 ntq_emit_alu(c, nir_instr_as_alu(instr));
2227 break;
2228
2229 case nir_instr_type_intrinsic:
2230 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
2231 break;
2232
2233 case nir_instr_type_load_const:
2234 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
2235 break;
2236
2237 case nir_instr_type_ssa_undef:
2238 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
2239 break;
2240
2241 case nir_instr_type_tex:
2242 ntq_emit_tex(c, nir_instr_as_tex(instr));
2243 break;
2244
2245 case nir_instr_type_jump:
2246 ntq_emit_jump(c, nir_instr_as_jump(instr));
2247 break;
2248
2249 default:
2250 fprintf(stderr, "Unknown NIR instr type: ");
2251 nir_print_instr(instr, stderr);
2252 fprintf(stderr, "\n");
2253 abort();
2254 }
2255 }
2256
2257 static void
2258 ntq_emit_block(struct v3d_compile *c, nir_block *block)
2259 {
2260 nir_foreach_instr(instr, block) {
2261 ntq_emit_instr(c, instr);
2262 }
2263 }
2264
2265 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
2266
2267 static void
2268 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
2269 {
2270 bool was_top_level = false;
2271 if (c->execute.file == QFILE_NULL) {
2272 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2273 was_top_level = true;
2274 }
2275
2276 struct qblock *save_loop_cont_block = c->loop_cont_block;
2277 struct qblock *save_loop_break_block = c->loop_break_block;
2278
2279 c->loop_cont_block = vir_new_block(c);
2280 c->loop_break_block = vir_new_block(c);
2281
2282 vir_link_blocks(c->cur_block, c->loop_cont_block);
2283 vir_set_emit_block(c, c->loop_cont_block);
2284 ntq_activate_execute_for_block(c);
2285
2286 ntq_emit_cf_list(c, &loop->body);
2287
2288 /* Re-enable any previous continues now, so our ANYA check below
2289 * works.
2290 *
2291 * XXX: Use the .ORZ flags update, instead.
2292 */
2293 vir_PF(c, vir_XOR(c,
2294 c->execute,
2295 vir_uniform_ui(c, c->loop_cont_block->index)),
2296 V3D_QPU_PF_PUSHZ);
2297 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2298
2299 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
2300
2301 struct qinst *branch = vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
2302 /* Pixels that were not dispatched or have been discarded should not
2303 * contribute to looping again.
2304 */
2305 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P;
2306 vir_link_blocks(c->cur_block, c->loop_cont_block);
2307 vir_link_blocks(c->cur_block, c->loop_break_block);
2308
2309 vir_set_emit_block(c, c->loop_break_block);
2310 if (was_top_level)
2311 c->execute = c->undef;
2312 else
2313 ntq_activate_execute_for_block(c);
2314
2315 c->loop_break_block = save_loop_break_block;
2316 c->loop_cont_block = save_loop_cont_block;
2317
2318 c->loops++;
2319 }
2320
2321 static void
2322 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
2323 {
2324 fprintf(stderr, "FUNCTIONS not handled.\n");
2325 abort();
2326 }
2327
2328 static void
2329 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
2330 {
2331 foreach_list_typed(nir_cf_node, node, node, list) {
2332 switch (node->type) {
2333 case nir_cf_node_block:
2334 ntq_emit_block(c, nir_cf_node_as_block(node));
2335 break;
2336
2337 case nir_cf_node_if:
2338 ntq_emit_if(c, nir_cf_node_as_if(node));
2339 break;
2340
2341 case nir_cf_node_loop:
2342 ntq_emit_loop(c, nir_cf_node_as_loop(node));
2343 break;
2344
2345 case nir_cf_node_function:
2346 ntq_emit_function(c, nir_cf_node_as_function(node));
2347 break;
2348
2349 default:
2350 fprintf(stderr, "Unknown NIR node type\n");
2351 abort();
2352 }
2353 }
2354 }
2355
2356 static void
2357 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
2358 {
2359 ntq_setup_registers(c, &impl->registers);
2360 ntq_emit_cf_list(c, &impl->body);
2361 }
2362
2363 static void
2364 nir_to_vir(struct v3d_compile *c)
2365 {
2366 switch (c->s->info.stage) {
2367 case MESA_SHADER_FRAGMENT:
2368 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
2369 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
2370 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
2371
2372 /* XXX perf: We could set the "disable implicit point/line
2373 * varyings" field in the shader record and not emit these, if
2374 * they're not going to be used.
2375 */
2376 if (c->fs_key->is_points) {
2377 c->point_x = emit_fragment_varying(c, NULL, 0, 0);
2378 c->point_y = emit_fragment_varying(c, NULL, 0, 0);
2379 } else if (c->fs_key->is_lines) {
2380 c->line_x = emit_fragment_varying(c, NULL, 0, 0);
2381 }
2382 break;
2383 case MESA_SHADER_COMPUTE:
2384 /* Set up the TSO for barriers, assuming we do some. */
2385 if (c->devinfo->ver < 42) {
2386 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
2387 V3D_QPU_WADDR_SYNC));
2388 }
2389
2390 if (c->s->info.system_values_read &
2391 ((1ull << SYSTEM_VALUE_LOCAL_INVOCATION_INDEX) |
2392 (1ull << SYSTEM_VALUE_WORK_GROUP_ID))) {
2393 c->cs_payload[0] = vir_MOV(c, vir_reg(QFILE_REG, 0));
2394 }
2395 if ((c->s->info.system_values_read &
2396 ((1ull << SYSTEM_VALUE_WORK_GROUP_ID))) ||
2397 c->s->info.cs.shared_size) {
2398 c->cs_payload[1] = vir_MOV(c, vir_reg(QFILE_REG, 2));
2399 }
2400
2401 /* Set up the division between gl_LocalInvocationIndex and
2402 * wg_in_mem in the payload reg.
2403 */
2404 int wg_size = (c->s->info.cs.local_size[0] *
2405 c->s->info.cs.local_size[1] *
2406 c->s->info.cs.local_size[2]);
2407 c->local_invocation_index_bits =
2408 ffs(util_next_power_of_two(MAX2(wg_size, 64))) - 1;
2409 assert(c->local_invocation_index_bits <= 8);
2410
2411 if (c->s->info.cs.shared_size) {
2412 struct qreg wg_in_mem = vir_SHR(c, c->cs_payload[1],
2413 vir_uniform_ui(c, 16));
2414 if (c->s->info.cs.local_size[0] != 1 ||
2415 c->s->info.cs.local_size[1] != 1 ||
2416 c->s->info.cs.local_size[2] != 1) {
2417 int wg_bits = (16 -
2418 c->local_invocation_index_bits);
2419 int wg_mask = (1 << wg_bits) - 1;
2420 wg_in_mem = vir_AND(c, wg_in_mem,
2421 vir_uniform_ui(c, wg_mask));
2422 }
2423 struct qreg shared_per_wg =
2424 vir_uniform_ui(c, c->s->info.cs.shared_size);
2425
2426 c->cs_shared_offset =
2427 vir_ADD(c,
2428 vir_uniform(c, QUNIFORM_SHARED_OFFSET,0),
2429 vir_UMUL(c, wg_in_mem, shared_per_wg));
2430 }
2431 break;
2432 default:
2433 break;
2434 }
2435
2436 if (c->s->info.stage == MESA_SHADER_FRAGMENT)
2437 ntq_setup_fs_inputs(c);
2438 else
2439 ntq_setup_vpm_inputs(c);
2440
2441 ntq_setup_outputs(c);
2442 ntq_setup_uniforms(c);
2443 ntq_setup_registers(c, &c->s->registers);
2444
2445 /* Find the main function and emit the body. */
2446 nir_foreach_function(function, c->s) {
2447 assert(strcmp(function->name, "main") == 0);
2448 assert(function->impl);
2449 ntq_emit_impl(c, function->impl);
2450 }
2451 }
2452
2453 const nir_shader_compiler_options v3d_nir_options = {
2454 .lower_all_io_to_temps = true,
2455 .lower_extract_byte = true,
2456 .lower_extract_word = true,
2457 .lower_bfm = true,
2458 .lower_bitfield_insert_to_shifts = true,
2459 .lower_bitfield_extract_to_shifts = true,
2460 .lower_bitfield_reverse = true,
2461 .lower_bit_count = true,
2462 .lower_cs_local_id_from_index = true,
2463 .lower_pack_unorm_2x16 = true,
2464 .lower_pack_snorm_2x16 = true,
2465 .lower_pack_unorm_4x8 = true,
2466 .lower_pack_snorm_4x8 = true,
2467 .lower_unpack_unorm_4x8 = true,
2468 .lower_unpack_snorm_4x8 = true,
2469 .lower_pack_half_2x16 = true,
2470 .lower_unpack_half_2x16 = true,
2471 .lower_fdiv = true,
2472 .lower_find_lsb = true,
2473 .lower_ffma = true,
2474 .lower_flrp32 = true,
2475 .lower_fpow = true,
2476 .lower_fsat = true,
2477 .lower_fsqrt = true,
2478 .lower_ifind_msb = true,
2479 .lower_ldexp = true,
2480 .lower_mul_high = true,
2481 .lower_wpos_pntc = true,
2482 .native_integers = true,
2483 };
2484
2485 /**
2486 * When demoting a shader down to single-threaded, removes the THRSW
2487 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
2488 * program end).
2489 */
2490 static void
2491 vir_remove_thrsw(struct v3d_compile *c)
2492 {
2493 vir_for_each_block(block, c) {
2494 vir_for_each_inst_safe(inst, block) {
2495 if (inst->qpu.sig.thrsw)
2496 vir_remove_instruction(c, inst);
2497 }
2498 }
2499
2500 c->last_thrsw = NULL;
2501 }
2502
2503 void
2504 vir_emit_last_thrsw(struct v3d_compile *c)
2505 {
2506 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
2507 * switching, so disable threads if we didn't do any TMU ops (each of
2508 * which would have emitted a THRSW).
2509 */
2510 if (!c->last_thrsw_at_top_level && c->devinfo->ver < 41) {
2511 c->threads = 1;
2512 if (c->last_thrsw)
2513 vir_remove_thrsw(c);
2514 return;
2515 }
2516
2517 /* If we're threaded and the last THRSW was in conditional code, then
2518 * we need to emit another one so that we can flag it as the last
2519 * thrsw.
2520 */
2521 if (c->last_thrsw && !c->last_thrsw_at_top_level) {
2522 assert(c->devinfo->ver >= 41);
2523 vir_emit_thrsw(c);
2524 }
2525
2526 /* If we're threaded, then we need to mark the last THRSW instruction
2527 * so we can emit a pair of them at QPU emit time.
2528 *
2529 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2530 * post-last-THRSW state, so we can skip this.
2531 */
2532 if (!c->last_thrsw && c->s->info.stage == MESA_SHADER_FRAGMENT) {
2533 assert(c->devinfo->ver >= 41);
2534 vir_emit_thrsw(c);
2535 }
2536
2537 if (c->last_thrsw)
2538 c->last_thrsw->is_last_thrsw = true;
2539 }
2540
2541 /* There's a flag in the shader for "center W is needed for reasons other than
2542 * non-centroid varyings", so we just walk the program after VIR optimization
2543 * to see if it's used. It should be harmless to set even if we only use
2544 * center W for varyings.
2545 */
2546 static void
2547 vir_check_payload_w(struct v3d_compile *c)
2548 {
2549 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
2550 return;
2551
2552 vir_for_each_inst_inorder(inst, c) {
2553 for (int i = 0; i < vir_get_nsrc(inst); i++) {
2554 if (inst->src[i].file == QFILE_REG &&
2555 inst->src[i].index == 0) {
2556 c->uses_center_w = true;
2557 return;
2558 }
2559 }
2560 }
2561
2562 }
2563
2564 void
2565 v3d_nir_to_vir(struct v3d_compile *c)
2566 {
2567 if (V3D_DEBUG & (V3D_DEBUG_NIR |
2568 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2569 fprintf(stderr, "%s prog %d/%d NIR:\n",
2570 vir_get_stage_name(c),
2571 c->program_id, c->variant_id);
2572 nir_print_shader(c->s, stderr);
2573 }
2574
2575 nir_to_vir(c);
2576
2577 /* Emit the last THRSW before STVPM and TLB writes. */
2578 vir_emit_last_thrsw(c);
2579
2580 switch (c->s->info.stage) {
2581 case MESA_SHADER_FRAGMENT:
2582 emit_frag_end(c);
2583 break;
2584 case MESA_SHADER_VERTEX:
2585 emit_vert_end(c);
2586 break;
2587 default:
2588 unreachable("bad stage");
2589 }
2590
2591 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2592 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2593 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
2594 vir_get_stage_name(c),
2595 c->program_id, c->variant_id);
2596 vir_dump(c);
2597 fprintf(stderr, "\n");
2598 }
2599
2600 vir_optimize(c);
2601 vir_lower_uniforms(c);
2602
2603 vir_check_payload_w(c);
2604
2605 /* XXX perf: On VC4, we do a VIR-level instruction scheduling here.
2606 * We used that on that platform to pipeline TMU writes and reduce the
2607 * number of thread switches, as well as try (mostly successfully) to
2608 * reduce maximum register pressure to allow more threads. We should
2609 * do something of that sort for V3D -- either instruction scheduling
2610 * here, or delay the the THRSW and LDTMUs from our texture
2611 * instructions until the results are needed.
2612 */
2613
2614 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2615 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2616 fprintf(stderr, "%s prog %d/%d VIR:\n",
2617 vir_get_stage_name(c),
2618 c->program_id, c->variant_id);
2619 vir_dump(c);
2620 fprintf(stderr, "\n");
2621 }
2622
2623 /* Attempt to allocate registers for the temporaries. If we fail,
2624 * reduce thread count and try again.
2625 */
2626 int min_threads = (c->devinfo->ver >= 41) ? 2 : 1;
2627 struct qpu_reg *temp_registers;
2628 while (true) {
2629 bool spilled;
2630 temp_registers = v3d_register_allocate(c, &spilled);
2631 if (spilled)
2632 continue;
2633
2634 if (temp_registers)
2635 break;
2636
2637 if (c->threads == min_threads) {
2638 fprintf(stderr, "Failed to register allocate at %d threads:\n",
2639 c->threads);
2640 vir_dump(c);
2641 c->failed = true;
2642 return;
2643 }
2644
2645 c->threads /= 2;
2646
2647 if (c->threads == 1)
2648 vir_remove_thrsw(c);
2649 }
2650
2651 v3d_vir_to_qpu(c, temp_registers);
2652 }