2 * Copyright © 2016 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
35 #define GENERAL_TMU_LOOKUP_PER_QUAD (0 << 7)
36 #define GENERAL_TMU_LOOKUP_PER_PIXEL (1 << 7)
37 #define GENERAL_TMU_READ_OP_PREFETCH (0 << 3)
38 #define GENERAL_TMU_READ_OP_CACHE_CLEAR (1 << 3)
39 #define GENERAL_TMU_READ_OP_CACHE_FLUSH (3 << 3)
40 #define GENERAL_TMU_READ_OP_CACHE_CLEAN (3 << 3)
41 #define GENERAL_TMU_READ_OP_CACHE_L1T_CLEAR (4 << 3)
42 #define GENERAL_TMU_READ_OP_CACHE_L1T_FLUSH_AGGREGATION (5 << 3)
43 #define GENERAL_TMU_READ_OP_ATOMIC_INC (8 << 3)
44 #define GENERAL_TMU_READ_OP_ATOMIC_DEC (9 << 3)
45 #define GENERAL_TMU_READ_OP_ATOMIC_NOT (10 << 3)
46 #define GENERAL_TMU_READ_OP_READ (15 << 3)
47 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_I (0 << 0)
48 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_I (1 << 0)
49 #define GENERAL_TMU_LOOKUP_TYPE_VEC2 (2 << 0)
50 #define GENERAL_TMU_LOOKUP_TYPE_VEC3 (3 << 0)
51 #define GENERAL_TMU_LOOKUP_TYPE_VEC4 (4 << 0)
52 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_UI (5 << 0)
53 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_UI (6 << 0)
54 #define GENERAL_TMU_LOOKUP_TYPE_32BIT_UI (7 << 0)
56 #define GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP (0 << 3)
57 #define GENERAL_TMU_WRITE_OP_ATOMIC_SUB_WRAP (1 << 3)
58 #define GENERAL_TMU_WRITE_OP_ATOMIC_XCHG (2 << 3)
59 #define GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG (3 << 3)
60 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMIN (4 << 3)
61 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMAX (5 << 3)
62 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMIN (6 << 3)
63 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMAX (7 << 3)
64 #define GENERAL_TMU_WRITE_OP_ATOMIC_AND (8 << 3)
65 #define GENERAL_TMU_WRITE_OP_ATOMIC_OR (9 << 3)
66 #define GENERAL_TMU_WRITE_OP_ATOMIC_XOR (10 << 3)
67 #define GENERAL_TMU_WRITE_OP_WRITE (15 << 3)
70 ntq_emit_cf_list(struct v3d_compile
*c
, struct exec_list
*list
);
73 resize_qreg_array(struct v3d_compile
*c
,
78 if (*size
>= decl_size
)
81 uint32_t old_size
= *size
;
82 *size
= MAX2(*size
* 2, decl_size
);
83 *regs
= reralloc(c
, *regs
, struct qreg
, *size
);
85 fprintf(stderr
, "Malloc failure\n");
89 for (uint32_t i
= old_size
; i
< *size
; i
++)
90 (*regs
)[i
] = c
->undef
;
94 vir_emit_thrsw(struct v3d_compile
*c
)
99 /* Always thread switch after each texture operation for now.
101 * We could do better by batching a bunch of texture fetches up and
102 * then doing one thread switch and collecting all their results
105 c
->last_thrsw
= vir_NOP(c
);
106 c
->last_thrsw
->qpu
.sig
.thrsw
= true;
107 c
->last_thrsw_at_top_level
= (c
->execute
.file
== QFILE_NULL
);
111 * Implements indirect uniform loads through the TMU general memory access
115 ntq_emit_tmu_general(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
)
117 uint32_t tmu_op
= GENERAL_TMU_READ_OP_READ
;
118 bool has_index
= instr
->intrinsic
== nir_intrinsic_load_ubo
;
119 int offset_src
= 0 + has_index
;
121 /* Note that QUNIFORM_UBO_ADDR takes a UBO index shifted up by
122 * 1 (0 is gallium's constant buffer 0).
124 struct qreg offset
= vir_uniform(c
, QUNIFORM_UBO_ADDR
,
125 nir_src_as_uint(instr
->src
[0]) + 1);
127 uint32_t config
= (0xffffff00 |
129 GENERAL_TMU_LOOKUP_PER_PIXEL
);
130 if (instr
->num_components
== 1) {
131 config
|= GENERAL_TMU_LOOKUP_TYPE_32BIT_UI
;
133 config
|= (GENERAL_TMU_LOOKUP_TYPE_VEC2
+
134 instr
->num_components
- 2);
139 dest
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_TMUA
);
141 dest
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_TMUAU
);
144 if (nir_src_is_const(instr
->src
[offset_src
]) &&
145 nir_src_as_uint(instr
->src
[offset_src
]) == 0) {
146 tmu
= vir_MOV_dest(c
, dest
, offset
);
148 tmu
= vir_ADD_dest(c
, dest
,
150 ntq_get_src(c
, instr
->src
[offset_src
], 0));
154 tmu
->src
[vir_get_implicit_uniform_src(tmu
)] =
155 vir_uniform_ui(c
, config
);
160 for (int i
= 0; i
< nir_intrinsic_dest_components(instr
); i
++)
161 ntq_store_dest(c
, &instr
->dest
, i
, vir_MOV(c
, vir_LDTMU(c
)));
165 indirect_uniform_load(struct v3d_compile
*c
, nir_intrinsic_instr
*intr
)
167 struct qreg indirect_offset
= ntq_get_src(c
, intr
->src
[0], 0);
168 uint32_t offset
= nir_intrinsic_base(intr
);
169 struct v3d_ubo_range
*range
= NULL
;
172 for (i
= 0; i
< c
->num_ubo_ranges
; i
++) {
173 range
= &c
->ubo_ranges
[i
];
174 if (offset
>= range
->src_offset
&&
175 offset
< range
->src_offset
+ range
->size
) {
179 /* The driver-location-based offset always has to be within a declared
182 assert(i
!= c
->num_ubo_ranges
);
183 if (!c
->ubo_range_used
[i
]) {
184 c
->ubo_range_used
[i
] = true;
185 range
->dst_offset
= c
->next_ubo_dst_offset
;
186 c
->next_ubo_dst_offset
+= range
->size
;
189 offset
-= range
->src_offset
;
191 if (range
->dst_offset
+ offset
!= 0) {
192 indirect_offset
= vir_ADD(c
, indirect_offset
,
193 vir_uniform_ui(c
, range
->dst_offset
+
197 /* Adjust for where we stored the TGSI register base. */
199 vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_TMUA
),
200 vir_uniform(c
, QUNIFORM_UBO_ADDR
, 0),
208 ntq_init_ssa_def(struct v3d_compile
*c
, nir_ssa_def
*def
)
210 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
211 def
->num_components
);
212 _mesa_hash_table_insert(c
->def_ht
, def
, qregs
);
217 * This function is responsible for getting VIR results into the associated
218 * storage for a NIR instruction.
220 * If it's a NIR SSA def, then we just set the associated hash table entry to
223 * If it's a NIR reg, then we need to update the existing qreg assigned to the
224 * NIR destination with the incoming value. To do that without introducing
225 * new MOVs, we require that the incoming qreg either be a uniform, or be
226 * SSA-defined by the previous VIR instruction in the block and rewritable by
227 * this function. That lets us sneak ahead and insert the SF flag beforehand
228 * (knowing that the previous instruction doesn't depend on flags) and rewrite
229 * its destination to be the NIR reg's destination
232 ntq_store_dest(struct v3d_compile
*c
, nir_dest
*dest
, int chan
,
235 struct qinst
*last_inst
= NULL
;
236 if (!list_empty(&c
->cur_block
->instructions
))
237 last_inst
= (struct qinst
*)c
->cur_block
->instructions
.prev
;
239 assert(result
.file
== QFILE_UNIF
||
240 (result
.file
== QFILE_TEMP
&&
241 last_inst
&& last_inst
== c
->defs
[result
.index
]));
244 assert(chan
< dest
->ssa
.num_components
);
247 struct hash_entry
*entry
=
248 _mesa_hash_table_search(c
->def_ht
, &dest
->ssa
);
253 qregs
= ntq_init_ssa_def(c
, &dest
->ssa
);
255 qregs
[chan
] = result
;
257 nir_register
*reg
= dest
->reg
.reg
;
258 assert(dest
->reg
.base_offset
== 0);
259 assert(reg
->num_array_elems
== 0);
260 struct hash_entry
*entry
=
261 _mesa_hash_table_search(c
->def_ht
, reg
);
262 struct qreg
*qregs
= entry
->data
;
264 /* Insert a MOV if the source wasn't an SSA def in the
265 * previous instruction.
267 if (result
.file
== QFILE_UNIF
) {
268 result
= vir_MOV(c
, result
);
269 last_inst
= c
->defs
[result
.index
];
272 /* We know they're both temps, so just rewrite index. */
273 c
->defs
[last_inst
->dst
.index
] = NULL
;
274 last_inst
->dst
.index
= qregs
[chan
].index
;
276 /* If we're in control flow, then make this update of the reg
277 * conditional on the execution mask.
279 if (c
->execute
.file
!= QFILE_NULL
) {
280 last_inst
->dst
.index
= qregs
[chan
].index
;
282 /* Set the flags to the current exec mask.
284 c
->cursor
= vir_before_inst(last_inst
);
285 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
286 c
->cursor
= vir_after_inst(last_inst
);
288 vir_set_cond(last_inst
, V3D_QPU_COND_IFA
);
289 last_inst
->cond_is_exec_mask
= true;
295 ntq_get_src(struct v3d_compile
*c
, nir_src src
, int i
)
297 struct hash_entry
*entry
;
299 entry
= _mesa_hash_table_search(c
->def_ht
, src
.ssa
);
300 assert(i
< src
.ssa
->num_components
);
302 nir_register
*reg
= src
.reg
.reg
;
303 entry
= _mesa_hash_table_search(c
->def_ht
, reg
);
304 assert(reg
->num_array_elems
== 0);
305 assert(src
.reg
.base_offset
== 0);
306 assert(i
< reg
->num_components
);
309 struct qreg
*qregs
= entry
->data
;
314 ntq_get_alu_src(struct v3d_compile
*c
, nir_alu_instr
*instr
,
317 assert(util_is_power_of_two_or_zero(instr
->dest
.write_mask
));
318 unsigned chan
= ffs(instr
->dest
.write_mask
) - 1;
319 struct qreg r
= ntq_get_src(c
, instr
->src
[src
].src
,
320 instr
->src
[src
].swizzle
[chan
]);
322 assert(!instr
->src
[src
].abs
);
323 assert(!instr
->src
[src
].negate
);
329 ntq_minify(struct v3d_compile
*c
, struct qreg size
, struct qreg level
)
331 return vir_MAX(c
, vir_SHR(c
, size
, level
), vir_uniform_ui(c
, 1));
335 ntq_emit_txs(struct v3d_compile
*c
, nir_tex_instr
*instr
)
337 unsigned unit
= instr
->texture_index
;
338 int lod_index
= nir_tex_instr_src_index(instr
, nir_tex_src_lod
);
339 int dest_size
= nir_tex_instr_dest_size(instr
);
341 struct qreg lod
= c
->undef
;
343 lod
= ntq_get_src(c
, instr
->src
[lod_index
].src
, 0);
345 for (int i
= 0; i
< dest_size
; i
++) {
347 enum quniform_contents contents
;
349 if (instr
->is_array
&& i
== dest_size
- 1)
350 contents
= QUNIFORM_TEXTURE_ARRAY_SIZE
;
352 contents
= QUNIFORM_TEXTURE_WIDTH
+ i
;
354 struct qreg size
= vir_uniform(c
, contents
, unit
);
356 switch (instr
->sampler_dim
) {
357 case GLSL_SAMPLER_DIM_1D
:
358 case GLSL_SAMPLER_DIM_2D
:
359 case GLSL_SAMPLER_DIM_MS
:
360 case GLSL_SAMPLER_DIM_3D
:
361 case GLSL_SAMPLER_DIM_CUBE
:
362 /* Don't minify the array size. */
363 if (!(instr
->is_array
&& i
== dest_size
- 1)) {
364 size
= ntq_minify(c
, size
, lod
);
368 case GLSL_SAMPLER_DIM_RECT
:
369 /* There's no LOD field for rects */
373 unreachable("Bad sampler type");
376 ntq_store_dest(c
, &instr
->dest
, i
, size
);
381 ntq_emit_tex(struct v3d_compile
*c
, nir_tex_instr
*instr
)
383 unsigned unit
= instr
->texture_index
;
385 /* Since each texture sampling op requires uploading uniforms to
386 * reference the texture, there's no HW support for texture size and
387 * you just upload uniforms containing the size.
390 case nir_texop_query_levels
:
391 ntq_store_dest(c
, &instr
->dest
, 0,
392 vir_uniform(c
, QUNIFORM_TEXTURE_LEVELS
, unit
));
395 ntq_emit_txs(c
, instr
);
401 if (c
->devinfo
->ver
>= 40)
402 v3d40_vir_emit_tex(c
, instr
);
404 v3d33_vir_emit_tex(c
, instr
);
408 ntq_fsincos(struct v3d_compile
*c
, struct qreg src
, bool is_cos
)
410 struct qreg input
= vir_FMUL(c
, src
, vir_uniform_f(c
, 1.0f
/ M_PI
));
412 input
= vir_FADD(c
, input
, vir_uniform_f(c
, 0.5));
414 struct qreg periods
= vir_FROUND(c
, input
);
415 struct qreg sin_output
= vir_SIN(c
, vir_FSUB(c
, input
, periods
));
416 return vir_XOR(c
, sin_output
, vir_SHL(c
,
417 vir_FTOIN(c
, periods
),
418 vir_uniform_ui(c
, -1)));
422 ntq_fsign(struct v3d_compile
*c
, struct qreg src
)
424 struct qreg t
= vir_get_temp(c
);
426 vir_MOV_dest(c
, t
, vir_uniform_f(c
, 0.0));
427 vir_PF(c
, vir_FMOV(c
, src
), V3D_QPU_PF_PUSHZ
);
428 vir_MOV_cond(c
, V3D_QPU_COND_IFNA
, t
, vir_uniform_f(c
, 1.0));
429 vir_PF(c
, vir_FMOV(c
, src
), V3D_QPU_PF_PUSHN
);
430 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, t
, vir_uniform_f(c
, -1.0));
431 return vir_MOV(c
, t
);
435 ntq_isign(struct v3d_compile
*c
, struct qreg src
)
437 struct qreg t
= vir_get_temp(c
);
439 vir_MOV_dest(c
, t
, vir_uniform_ui(c
, 0));
440 vir_PF(c
, vir_MOV(c
, src
), V3D_QPU_PF_PUSHZ
);
441 vir_MOV_cond(c
, V3D_QPU_COND_IFNA
, t
, vir_uniform_ui(c
, 1));
442 vir_PF(c
, vir_MOV(c
, src
), V3D_QPU_PF_PUSHN
);
443 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, t
, vir_uniform_ui(c
, -1));
444 return vir_MOV(c
, t
);
448 emit_fragcoord_input(struct v3d_compile
*c
, int attr
)
450 c
->inputs
[attr
* 4 + 0] = vir_FXCD(c
);
451 c
->inputs
[attr
* 4 + 1] = vir_FYCD(c
);
452 c
->inputs
[attr
* 4 + 2] = c
->payload_z
;
453 c
->inputs
[attr
* 4 + 3] = vir_RECIP(c
, c
->payload_w
);
457 emit_fragment_varying(struct v3d_compile
*c
, nir_variable
*var
,
460 struct qreg r3
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_R3
);
461 struct qreg r5
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_R5
);
464 if (c
->devinfo
->ver
>= 41) {
465 struct qinst
*ldvary
= vir_add_inst(V3D_QPU_A_NOP
, c
->undef
,
467 ldvary
->qpu
.sig
.ldvary
= true;
468 vary
= vir_emit_def(c
, ldvary
);
470 vir_NOP(c
)->qpu
.sig
.ldvary
= true;
474 /* For gl_PointCoord input or distance along a line, we'll be called
475 * with no nir_variable, and we don't count toward VPM size so we
476 * don't track an input slot.
479 return vir_FADD(c
, vir_FMUL(c
, vary
, c
->payload_w
), r5
);
482 int i
= c
->num_inputs
++;
483 c
->input_slots
[i
] = v3d_slot_from_slot_and_component(var
->data
.location
,
486 switch (var
->data
.interpolation
) {
487 case INTERP_MODE_NONE
:
488 /* If a gl_FrontColor or gl_BackColor input has no interp
489 * qualifier, then if we're using glShadeModel(GL_FLAT) it
490 * needs to be flat shaded.
492 switch (var
->data
.location
) {
493 case VARYING_SLOT_COL0
:
494 case VARYING_SLOT_COL1
:
495 case VARYING_SLOT_BFC0
:
496 case VARYING_SLOT_BFC1
:
497 if (c
->fs_key
->shade_model_flat
) {
498 BITSET_SET(c
->flat_shade_flags
, i
);
499 vir_MOV_dest(c
, c
->undef
, vary
);
500 return vir_MOV(c
, r5
);
502 return vir_FADD(c
, vir_FMUL(c
, vary
,
509 case INTERP_MODE_SMOOTH
:
510 if (var
->data
.centroid
) {
511 BITSET_SET(c
->centroid_flags
, i
);
512 return vir_FADD(c
, vir_FMUL(c
, vary
,
513 c
->payload_w_centroid
), r5
);
515 return vir_FADD(c
, vir_FMUL(c
, vary
, c
->payload_w
), r5
);
517 case INTERP_MODE_NOPERSPECTIVE
:
518 BITSET_SET(c
->noperspective_flags
, i
);
519 return vir_FADD(c
, vir_MOV(c
, vary
), r5
);
520 case INTERP_MODE_FLAT
:
521 BITSET_SET(c
->flat_shade_flags
, i
);
522 vir_MOV_dest(c
, c
->undef
, vary
);
523 return vir_MOV(c
, r5
);
525 unreachable("Bad interp mode");
530 emit_fragment_input(struct v3d_compile
*c
, int attr
, nir_variable
*var
)
532 for (int i
= 0; i
< glsl_get_vector_elements(var
->type
); i
++) {
533 int chan
= var
->data
.location_frac
+ i
;
534 c
->inputs
[attr
* 4 + chan
] =
535 emit_fragment_varying(c
, var
, chan
);
540 add_output(struct v3d_compile
*c
,
541 uint32_t decl_offset
,
545 uint32_t old_array_size
= c
->outputs_array_size
;
546 resize_qreg_array(c
, &c
->outputs
, &c
->outputs_array_size
,
549 if (old_array_size
!= c
->outputs_array_size
) {
550 c
->output_slots
= reralloc(c
,
552 struct v3d_varying_slot
,
553 c
->outputs_array_size
);
556 c
->output_slots
[decl_offset
] =
557 v3d_slot_from_slot_and_component(slot
, swizzle
);
561 declare_uniform_range(struct v3d_compile
*c
, uint32_t start
, uint32_t size
)
563 unsigned array_id
= c
->num_ubo_ranges
++;
564 if (array_id
>= c
->ubo_ranges_array_size
) {
565 c
->ubo_ranges_array_size
= MAX2(c
->ubo_ranges_array_size
* 2,
567 c
->ubo_ranges
= reralloc(c
, c
->ubo_ranges
,
568 struct v3d_ubo_range
,
569 c
->ubo_ranges_array_size
);
570 c
->ubo_range_used
= reralloc(c
, c
->ubo_range_used
,
572 c
->ubo_ranges_array_size
);
575 c
->ubo_ranges
[array_id
].dst_offset
= 0;
576 c
->ubo_ranges
[array_id
].src_offset
= start
;
577 c
->ubo_ranges
[array_id
].size
= size
;
578 c
->ubo_range_used
[array_id
] = false;
582 * If compare_instr is a valid comparison instruction, emits the
583 * compare_instr's comparison and returns the sel_instr's return value based
584 * on the compare_instr's result.
587 ntq_emit_comparison(struct v3d_compile
*c
,
588 nir_alu_instr
*compare_instr
,
589 enum v3d_qpu_cond
*out_cond
)
591 struct qreg src0
= ntq_get_alu_src(c
, compare_instr
, 0);
593 if (nir_op_infos
[compare_instr
->op
].num_inputs
> 1)
594 src1
= ntq_get_alu_src(c
, compare_instr
, 1);
595 bool cond_invert
= false;
596 struct qreg nop
= vir_reg(QFILE_NULL
, 0);
598 switch (compare_instr
->op
) {
601 vir_set_pf(vir_FCMP_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
604 vir_set_pf(vir_XOR_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
609 vir_set_pf(vir_FCMP_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
613 vir_set_pf(vir_XOR_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
619 vir_set_pf(vir_FCMP_dest(c
, nop
, src1
, src0
), V3D_QPU_PF_PUSHC
);
622 vir_set_pf(vir_MIN_dest(c
, nop
, src1
, src0
), V3D_QPU_PF_PUSHC
);
626 vir_set_pf(vir_SUB_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHC
);
632 vir_set_pf(vir_FCMP_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHN
);
635 vir_set_pf(vir_MIN_dest(c
, nop
, src1
, src0
), V3D_QPU_PF_PUSHC
);
638 vir_set_pf(vir_SUB_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHC
);
645 *out_cond
= cond_invert
? V3D_QPU_COND_IFNA
: V3D_QPU_COND_IFA
;
650 /* Finds an ALU instruction that generates our src value that could
651 * (potentially) be greedily emitted in the consuming instruction.
653 static struct nir_alu_instr
*
654 ntq_get_alu_parent(nir_src src
)
656 if (!src
.is_ssa
|| src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
658 nir_alu_instr
*instr
= nir_instr_as_alu(src
.ssa
->parent_instr
);
662 /* If the ALU instr's srcs are non-SSA, then we would have to avoid
663 * moving emission of the ALU instr down past another write of the
666 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
667 if (!instr
->src
[i
].src
.is_ssa
)
675 * Attempts to fold a comparison generating a boolean result into the
676 * condition code for selecting between two values, instead of comparing the
677 * boolean result against 0 to generate the condition code.
679 static struct qreg
ntq_emit_bcsel(struct v3d_compile
*c
, nir_alu_instr
*instr
,
682 nir_alu_instr
*compare
= ntq_get_alu_parent(instr
->src
[0].src
);
686 enum v3d_qpu_cond cond
;
687 if (ntq_emit_comparison(c
, compare
, &cond
))
688 return vir_MOV(c
, vir_SEL(c
, cond
, src
[1], src
[2]));
691 vir_PF(c
, src
[0], V3D_QPU_PF_PUSHZ
);
692 return vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFNA
, src
[1], src
[2]));
697 ntq_emit_alu(struct v3d_compile
*c
, nir_alu_instr
*instr
)
699 /* This should always be lowered to ALU operations for V3D. */
700 assert(!instr
->dest
.saturate
);
702 /* Vectors are special in that they have non-scalarized writemasks,
703 * and just take the first swizzle channel for each argument in order
704 * into each writemask channel.
706 if (instr
->op
== nir_op_vec2
||
707 instr
->op
== nir_op_vec3
||
708 instr
->op
== nir_op_vec4
) {
710 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
711 srcs
[i
] = ntq_get_src(c
, instr
->src
[i
].src
,
712 instr
->src
[i
].swizzle
[0]);
713 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
714 ntq_store_dest(c
, &instr
->dest
.dest
, i
,
715 vir_MOV(c
, srcs
[i
]));
719 /* General case: We can just grab the one used channel per src. */
720 struct qreg src
[nir_op_infos
[instr
->op
].num_inputs
];
721 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
722 src
[i
] = ntq_get_alu_src(c
, instr
, i
);
730 result
= vir_MOV(c
, src
[0]);
734 result
= vir_XOR(c
, src
[0], vir_uniform_ui(c
, 1 << 31));
737 result
= vir_NEG(c
, src
[0]);
741 result
= vir_FMUL(c
, src
[0], src
[1]);
744 result
= vir_FADD(c
, src
[0], src
[1]);
747 result
= vir_FSUB(c
, src
[0], src
[1]);
750 result
= vir_FMIN(c
, src
[0], src
[1]);
753 result
= vir_FMAX(c
, src
[0], src
[1]);
757 result
= vir_FTOIZ(c
, src
[0]);
760 result
= vir_FTOUZ(c
, src
[0]);
763 result
= vir_ITOF(c
, src
[0]);
766 result
= vir_UTOF(c
, src
[0]);
769 result
= vir_AND(c
, src
[0], vir_uniform_f(c
, 1.0));
772 result
= vir_AND(c
, src
[0], vir_uniform_ui(c
, 1));
776 vir_PF(c
, src
[0], V3D_QPU_PF_PUSHZ
);
777 result
= vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFNA
,
778 vir_uniform_ui(c
, ~0),
779 vir_uniform_ui(c
, 0)));
783 result
= vir_ADD(c
, src
[0], src
[1]);
786 result
= vir_SHR(c
, src
[0], src
[1]);
789 result
= vir_SUB(c
, src
[0], src
[1]);
792 result
= vir_ASR(c
, src
[0], src
[1]);
795 result
= vir_SHL(c
, src
[0], src
[1]);
798 result
= vir_MIN(c
, src
[0], src
[1]);
801 result
= vir_UMIN(c
, src
[0], src
[1]);
804 result
= vir_MAX(c
, src
[0], src
[1]);
807 result
= vir_UMAX(c
, src
[0], src
[1]);
810 result
= vir_AND(c
, src
[0], src
[1]);
813 result
= vir_OR(c
, src
[0], src
[1]);
816 result
= vir_XOR(c
, src
[0], src
[1]);
819 result
= vir_NOT(c
, src
[0]);
822 case nir_op_ufind_msb
:
823 result
= vir_SUB(c
, vir_uniform_ui(c
, 31), vir_CLZ(c
, src
[0]));
827 result
= vir_UMUL(c
, src
[0], src
[1]);
834 enum v3d_qpu_cond cond
;
835 MAYBE_UNUSED
bool ok
= ntq_emit_comparison(c
, instr
, &cond
);
837 result
= vir_MOV(c
, vir_SEL(c
, cond
,
838 vir_uniform_f(c
, 1.0),
839 vir_uniform_f(c
, 0.0)));
853 enum v3d_qpu_cond cond
;
854 MAYBE_UNUSED
bool ok
= ntq_emit_comparison(c
, instr
, &cond
);
856 result
= vir_MOV(c
, vir_SEL(c
, cond
,
857 vir_uniform_ui(c
, ~0),
858 vir_uniform_ui(c
, 0)));
863 result
= ntq_emit_bcsel(c
, instr
, src
);
866 vir_PF(c
, src
[0], V3D_QPU_PF_PUSHZ
);
867 result
= vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFNA
,
872 result
= vir_RECIP(c
, src
[0]);
875 result
= vir_RSQRT(c
, src
[0]);
878 result
= vir_EXP(c
, src
[0]);
881 result
= vir_LOG(c
, src
[0]);
885 result
= vir_FCEIL(c
, src
[0]);
888 result
= vir_FFLOOR(c
, src
[0]);
890 case nir_op_fround_even
:
891 result
= vir_FROUND(c
, src
[0]);
894 result
= vir_FTRUNC(c
, src
[0]);
897 result
= vir_FSUB(c
, src
[0], vir_FFLOOR(c
, src
[0]));
901 result
= ntq_fsincos(c
, src
[0], false);
904 result
= ntq_fsincos(c
, src
[0], true);
908 result
= ntq_fsign(c
, src
[0]);
911 result
= ntq_isign(c
, src
[0]);
915 result
= vir_FMOV(c
, src
[0]);
916 vir_set_unpack(c
->defs
[result
.index
], 0, V3D_QPU_UNPACK_ABS
);
921 result
= vir_MAX(c
, src
[0],
922 vir_SUB(c
, vir_uniform_ui(c
, 0), src
[0]));
926 case nir_op_fddx_coarse
:
927 case nir_op_fddx_fine
:
928 result
= vir_FDX(c
, src
[0]);
932 case nir_op_fddy_coarse
:
933 case nir_op_fddy_fine
:
934 result
= vir_FDY(c
, src
[0]);
937 case nir_op_uadd_carry
:
938 vir_PF(c
, vir_ADD(c
, src
[0], src
[1]), V3D_QPU_PF_PUSHC
);
939 result
= vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFA
,
940 vir_uniform_ui(c
, ~0),
941 vir_uniform_ui(c
, 0)));
944 case nir_op_pack_half_2x16_split
:
945 result
= vir_VFPACK(c
, src
[0], src
[1]);
948 case nir_op_unpack_half_2x16_split_x
:
949 /* XXX perf: It would be good to be able to merge this unpack
950 * with whatever uses our result.
952 result
= vir_FMOV(c
, src
[0]);
953 vir_set_unpack(c
->defs
[result
.index
], 0, V3D_QPU_UNPACK_L
);
956 case nir_op_unpack_half_2x16_split_y
:
957 result
= vir_FMOV(c
, src
[0]);
958 vir_set_unpack(c
->defs
[result
.index
], 0, V3D_QPU_UNPACK_H
);
962 fprintf(stderr
, "unknown NIR ALU inst: ");
963 nir_print_instr(&instr
->instr
, stderr
);
964 fprintf(stderr
, "\n");
968 /* We have a scalar result, so the instruction should only have a
969 * single channel written to.
971 assert(util_is_power_of_two_or_zero(instr
->dest
.write_mask
));
972 ntq_store_dest(c
, &instr
->dest
.dest
,
973 ffs(instr
->dest
.write_mask
) - 1, result
);
976 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
977 * specifier. They come from a register that's preloaded with 0xffffffff
978 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
979 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
981 #define TLB_TYPE_F16_COLOR (3 << 6)
982 #define TLB_TYPE_I32_COLOR (1 << 6)
983 #define TLB_TYPE_F32_COLOR (0 << 6)
984 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
985 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
986 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
987 #define TLB_F16_SWAP_HI_LO (1 << 1)
988 #define TLB_VEC_SIZE_4_F16 (1 << 0)
989 #define TLB_VEC_SIZE_2_F16 (0 << 0)
990 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
992 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
995 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
996 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
997 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
998 #define TLB_V42_DEPTH_TYPE_INVARIANT (0 << 3) /* Unmodified sideband input used */
999 #define TLB_V42_DEPTH_TYPE_PER_PIXEL (1 << 3) /* QPU result used */
1001 /* Stencil is a single 32-bit write. */
1002 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1005 emit_frag_end(struct v3d_compile
*c
)
1008 if (c->output_sample_mask_index != -1) {
1009 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1013 bool has_any_tlb_color_write
= false;
1014 for (int rt
= 0; rt
< c
->fs_key
->nr_cbufs
; rt
++) {
1015 if (c
->output_color_var
[rt
])
1016 has_any_tlb_color_write
= true;
1019 if (c
->fs_key
->sample_alpha_to_coverage
&& c
->output_color_var
[0]) {
1020 struct nir_variable
*var
= c
->output_color_var
[0];
1021 struct qreg
*color
= &c
->outputs
[var
->data
.driver_location
* 4];
1023 vir_SETMSF_dest(c
, vir_reg(QFILE_NULL
, 0),
1026 vir_FTOC(c
, color
[3])));
1029 if (c
->output_position_index
!= -1) {
1030 struct qinst
*inst
= vir_MOV_dest(c
,
1031 vir_reg(QFILE_TLBU
, 0),
1032 c
->outputs
[c
->output_position_index
]);
1033 uint8_t tlb_specifier
= TLB_TYPE_DEPTH
;
1035 if (c
->devinfo
->ver
>= 42) {
1036 tlb_specifier
|= (TLB_V42_DEPTH_TYPE_PER_PIXEL
|
1037 TLB_SAMPLE_MODE_PER_PIXEL
);
1039 tlb_specifier
|= TLB_DEPTH_TYPE_PER_PIXEL
;
1041 inst
->src
[vir_get_implicit_uniform_src(inst
)] =
1042 vir_uniform_ui(c
, tlb_specifier
| 0xffffff00);
1043 } else if (c
->s
->info
.fs
.uses_discard
||
1044 c
->fs_key
->sample_alpha_to_coverage
||
1045 !has_any_tlb_color_write
) {
1046 /* Emit passthrough Z if it needed to be delayed until shader
1047 * end due to potential discards.
1049 * Since (single-threaded) fragment shaders always need a TLB
1050 * write, emit passthrouh Z if we didn't have any color
1051 * buffers and flag us as potentially discarding, so that we
1052 * can use Z as the TLB write.
1054 c
->s
->info
.fs
.uses_discard
= true;
1056 struct qinst
*inst
= vir_MOV_dest(c
,
1057 vir_reg(QFILE_TLBU
, 0),
1058 vir_reg(QFILE_NULL
, 0));
1059 uint8_t tlb_specifier
= TLB_TYPE_DEPTH
;
1061 if (c
->devinfo
->ver
>= 42) {
1062 /* The spec says the PER_PIXEL flag is ignored for
1063 * invariant writes, but the simulator demands it.
1065 tlb_specifier
|= (TLB_V42_DEPTH_TYPE_INVARIANT
|
1066 TLB_SAMPLE_MODE_PER_PIXEL
);
1068 tlb_specifier
|= TLB_DEPTH_TYPE_INVARIANT
;
1071 inst
->src
[vir_get_implicit_uniform_src(inst
)] =
1072 vir_uniform_ui(c
, tlb_specifier
| 0xffffff00);
1075 /* XXX: Performance improvement: Merge Z write and color writes TLB
1079 for (int rt
= 0; rt
< c
->fs_key
->nr_cbufs
; rt
++) {
1080 if (!c
->output_color_var
[rt
])
1083 nir_variable
*var
= c
->output_color_var
[rt
];
1084 struct qreg
*color
= &c
->outputs
[var
->data
.driver_location
* 4];
1085 int num_components
= glsl_get_vector_elements(var
->type
);
1086 uint32_t conf
= 0xffffff00;
1089 conf
|= TLB_SAMPLE_MODE_PER_PIXEL
;
1090 conf
|= (7 - rt
) << TLB_RENDER_TARGET_SHIFT
;
1092 if (c
->fs_key
->swap_color_rb
& (1 << rt
))
1093 num_components
= MAX2(num_components
, 3);
1095 assert(num_components
!= 0);
1096 switch (glsl_get_base_type(var
->type
)) {
1097 case GLSL_TYPE_UINT
:
1099 /* The F32 vs I32 distinction was dropped in 4.2. */
1100 if (c
->devinfo
->ver
< 42)
1101 conf
|= TLB_TYPE_I32_COLOR
;
1103 conf
|= TLB_TYPE_F32_COLOR
;
1104 conf
|= ((num_components
- 1) <<
1105 TLB_VEC_SIZE_MINUS_1_SHIFT
);
1107 inst
= vir_MOV_dest(c
, vir_reg(QFILE_TLBU
, 0), color
[0]);
1108 inst
->src
[vir_get_implicit_uniform_src(inst
)] =
1109 vir_uniform_ui(c
, conf
);
1111 for (int i
= 1; i
< num_components
; i
++) {
1112 inst
= vir_MOV_dest(c
, vir_reg(QFILE_TLB
, 0),
1118 struct qreg r
= color
[0];
1119 struct qreg g
= color
[1];
1120 struct qreg b
= color
[2];
1121 struct qreg a
= color
[3];
1123 if (c
->fs_key
->f32_color_rb
& (1 << rt
)) {
1124 conf
|= TLB_TYPE_F32_COLOR
;
1125 conf
|= ((num_components
- 1) <<
1126 TLB_VEC_SIZE_MINUS_1_SHIFT
);
1128 conf
|= TLB_TYPE_F16_COLOR
;
1129 conf
|= TLB_F16_SWAP_HI_LO
;
1130 if (num_components
>= 3)
1131 conf
|= TLB_VEC_SIZE_4_F16
;
1133 conf
|= TLB_VEC_SIZE_2_F16
;
1136 if (c
->fs_key
->swap_color_rb
& (1 << rt
)) {
1141 if (c
->fs_key
->sample_alpha_to_one
)
1142 a
= vir_uniform_f(c
, 1.0);
1144 if (c
->fs_key
->f32_color_rb
& (1 << rt
)) {
1145 inst
= vir_MOV_dest(c
, vir_reg(QFILE_TLBU
, 0), r
);
1146 inst
->src
[vir_get_implicit_uniform_src(inst
)] =
1147 vir_uniform_ui(c
, conf
);
1149 if (num_components
>= 2)
1150 vir_MOV_dest(c
, vir_reg(QFILE_TLB
, 0), g
);
1151 if (num_components
>= 3)
1152 vir_MOV_dest(c
, vir_reg(QFILE_TLB
, 0), b
);
1153 if (num_components
>= 4)
1154 vir_MOV_dest(c
, vir_reg(QFILE_TLB
, 0), a
);
1156 inst
= vir_VFPACK_dest(c
, vir_reg(QFILE_TLB
, 0), r
, g
);
1158 inst
->dst
.file
= QFILE_TLBU
;
1159 inst
->src
[vir_get_implicit_uniform_src(inst
)] =
1160 vir_uniform_ui(c
, conf
);
1163 if (num_components
>= 3)
1164 inst
= vir_VFPACK_dest(c
, vir_reg(QFILE_TLB
, 0), b
, a
);
1173 vir_VPM_WRITE(struct v3d_compile
*c
, struct qreg val
, uint32_t *vpm_index
)
1175 if (c
->devinfo
->ver
>= 40) {
1176 vir_STVPMV(c
, vir_uniform_ui(c
, *vpm_index
), val
);
1177 *vpm_index
= *vpm_index
+ 1;
1179 vir_MOV_dest(c
, vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_VPM
), val
);
1182 c
->num_vpm_writes
++;
1186 emit_scaled_viewport_write(struct v3d_compile
*c
, struct qreg rcp_w
,
1187 uint32_t *vpm_index
)
1189 for (int i
= 0; i
< 2; i
++) {
1190 struct qreg coord
= c
->outputs
[c
->output_position_index
+ i
];
1191 coord
= vir_FMUL(c
, coord
,
1192 vir_uniform(c
, QUNIFORM_VIEWPORT_X_SCALE
+ i
,
1194 coord
= vir_FMUL(c
, coord
, rcp_w
);
1195 vir_VPM_WRITE(c
, vir_FTOIN(c
, coord
), vpm_index
);
1201 emit_zs_write(struct v3d_compile
*c
, struct qreg rcp_w
, uint32_t *vpm_index
)
1203 struct qreg zscale
= vir_uniform(c
, QUNIFORM_VIEWPORT_Z_SCALE
, 0);
1204 struct qreg zoffset
= vir_uniform(c
, QUNIFORM_VIEWPORT_Z_OFFSET
, 0);
1206 struct qreg z
= c
->outputs
[c
->output_position_index
+ 2];
1207 z
= vir_FMUL(c
, z
, zscale
);
1208 z
= vir_FMUL(c
, z
, rcp_w
);
1209 z
= vir_FADD(c
, z
, zoffset
);
1210 vir_VPM_WRITE(c
, z
, vpm_index
);
1214 emit_rcp_wc_write(struct v3d_compile
*c
, struct qreg rcp_w
, uint32_t *vpm_index
)
1216 vir_VPM_WRITE(c
, rcp_w
, vpm_index
);
1220 emit_point_size_write(struct v3d_compile
*c
, uint32_t *vpm_index
)
1222 struct qreg point_size
;
1224 if (c
->output_point_size_index
!= -1)
1225 point_size
= c
->outputs
[c
->output_point_size_index
];
1227 point_size
= vir_uniform_f(c
, 1.0);
1229 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1232 point_size
= vir_FMAX(c
, point_size
, vir_uniform_f(c
, .125));
1234 vir_VPM_WRITE(c
, point_size
, vpm_index
);
1238 emit_vpm_write_setup(struct v3d_compile
*c
)
1240 if (c
->devinfo
->ver
>= 40)
1243 v3d33_vir_vpm_write_setup(c
);
1247 * Sets up c->outputs[c->output_position_index] for the vertex shader
1248 * epilogue, if an output vertex position wasn't specified in the user's
1249 * shader. This may be the case for transform feedback with rasterizer
1253 setup_default_position(struct v3d_compile
*c
)
1255 if (c
->output_position_index
!= -1)
1258 c
->output_position_index
= c
->outputs_array_size
;
1259 for (int i
= 0; i
< 4; i
++) {
1261 c
->output_position_index
+ i
,
1262 VARYING_SLOT_POS
, i
);
1267 emit_vert_end(struct v3d_compile
*c
)
1269 setup_default_position(c
);
1271 uint32_t vpm_index
= 0;
1272 struct qreg rcp_w
= vir_RECIP(c
,
1273 c
->outputs
[c
->output_position_index
+ 3]);
1275 emit_vpm_write_setup(c
);
1277 if (c
->vs_key
->is_coord
) {
1278 for (int i
= 0; i
< 4; i
++)
1279 vir_VPM_WRITE(c
, c
->outputs
[c
->output_position_index
+ i
],
1281 emit_scaled_viewport_write(c
, rcp_w
, &vpm_index
);
1282 if (c
->vs_key
->per_vertex_point_size
) {
1283 emit_point_size_write(c
, &vpm_index
);
1284 /* emit_rcp_wc_write(c, rcp_w); */
1286 /* XXX: Z-only rendering */
1288 emit_zs_write(c
, rcp_w
, &vpm_index
);
1290 emit_scaled_viewport_write(c
, rcp_w
, &vpm_index
);
1291 emit_zs_write(c
, rcp_w
, &vpm_index
);
1292 emit_rcp_wc_write(c
, rcp_w
, &vpm_index
);
1293 if (c
->vs_key
->per_vertex_point_size
)
1294 emit_point_size_write(c
, &vpm_index
);
1297 for (int i
= 0; i
< c
->vs_key
->num_fs_inputs
; i
++) {
1298 struct v3d_varying_slot input
= c
->vs_key
->fs_inputs
[i
];
1301 for (j
= 0; j
< c
->num_outputs
; j
++) {
1302 struct v3d_varying_slot output
= c
->output_slots
[j
];
1304 if (!memcmp(&input
, &output
, sizeof(input
))) {
1305 vir_VPM_WRITE(c
, c
->outputs
[j
],
1310 /* Emit padding if we didn't find a declared VS output for
1313 if (j
== c
->num_outputs
)
1314 vir_VPM_WRITE(c
, vir_uniform_f(c
, 0.0),
1318 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1320 if (c
->devinfo
->ver
>= 40 && c
->devinfo
->ver
<= 42)
1325 v3d_optimize_nir(struct nir_shader
*s
)
1332 NIR_PASS_V(s
, nir_lower_vars_to_ssa
);
1333 NIR_PASS(progress
, s
, nir_lower_alu_to_scalar
);
1334 NIR_PASS(progress
, s
, nir_lower_phis_to_scalar
);
1335 NIR_PASS(progress
, s
, nir_copy_prop
);
1336 NIR_PASS(progress
, s
, nir_opt_remove_phis
);
1337 NIR_PASS(progress
, s
, nir_opt_dce
);
1338 NIR_PASS(progress
, s
, nir_opt_dead_cf
);
1339 NIR_PASS(progress
, s
, nir_opt_cse
);
1340 NIR_PASS(progress
, s
, nir_opt_peephole_select
, 8, true, true);
1341 NIR_PASS(progress
, s
, nir_opt_algebraic
);
1342 NIR_PASS(progress
, s
, nir_opt_constant_folding
);
1343 NIR_PASS(progress
, s
, nir_opt_undef
);
1346 NIR_PASS(progress
, s
, nir_opt_move_load_ubo
);
1350 driver_location_compare(const void *in_a
, const void *in_b
)
1352 const nir_variable
*const *a
= in_a
;
1353 const nir_variable
*const *b
= in_b
;
1355 return (*a
)->data
.driver_location
- (*b
)->data
.driver_location
;
1359 ntq_emit_vpm_read(struct v3d_compile
*c
,
1360 uint32_t *num_components_queued
,
1361 uint32_t *remaining
,
1364 struct qreg vpm
= vir_reg(QFILE_VPM
, vpm_index
);
1366 if (c
->devinfo
->ver
>= 40 ) {
1367 return vir_LDVPMV_IN(c
,
1369 (*num_components_queued
)++));
1372 if (*num_components_queued
!= 0) {
1373 (*num_components_queued
)--;
1375 return vir_MOV(c
, vpm
);
1378 uint32_t num_components
= MIN2(*remaining
, 32);
1380 v3d33_vir_vpm_read_setup(c
, num_components
);
1382 *num_components_queued
= num_components
- 1;
1383 *remaining
-= num_components
;
1386 return vir_MOV(c
, vpm
);
1390 ntq_setup_vpm_inputs(struct v3d_compile
*c
)
1392 /* Figure out how many components of each vertex attribute the shader
1393 * uses. Each variable should have been split to individual
1394 * components and unused ones DCEed. The vertex fetcher will load
1395 * from the start of the attribute to the number of components we
1396 * declare we need in c->vattr_sizes[].
1398 nir_foreach_variable(var
, &c
->s
->inputs
) {
1399 /* No VS attribute array support. */
1400 assert(MAX2(glsl_get_length(var
->type
), 1) == 1);
1402 unsigned loc
= var
->data
.driver_location
;
1403 int start_component
= var
->data
.location_frac
;
1404 int num_components
= glsl_get_components(var
->type
);
1406 c
->vattr_sizes
[loc
] = MAX2(c
->vattr_sizes
[loc
],
1407 start_component
+ num_components
);
1410 unsigned num_components
= 0;
1411 uint32_t vpm_components_queued
= 0;
1412 bool uses_iid
= c
->s
->info
.system_values_read
&
1413 (1ull << SYSTEM_VALUE_INSTANCE_ID
);
1414 bool uses_vid
= c
->s
->info
.system_values_read
&
1415 (1ull << SYSTEM_VALUE_VERTEX_ID
);
1416 num_components
+= uses_iid
;
1417 num_components
+= uses_vid
;
1419 for (int i
= 0; i
< ARRAY_SIZE(c
->vattr_sizes
); i
++)
1420 num_components
+= c
->vattr_sizes
[i
];
1423 c
->iid
= ntq_emit_vpm_read(c
, &vpm_components_queued
,
1424 &num_components
, ~0);
1428 c
->vid
= ntq_emit_vpm_read(c
, &vpm_components_queued
,
1429 &num_components
, ~0);
1432 for (int loc
= 0; loc
< ARRAY_SIZE(c
->vattr_sizes
); loc
++) {
1433 resize_qreg_array(c
, &c
->inputs
, &c
->inputs_array_size
,
1436 for (int i
= 0; i
< c
->vattr_sizes
[loc
]; i
++) {
1437 c
->inputs
[loc
* 4 + i
] =
1438 ntq_emit_vpm_read(c
,
1439 &vpm_components_queued
,
1446 if (c
->devinfo
->ver
>= 40) {
1447 assert(vpm_components_queued
== num_components
);
1449 assert(vpm_components_queued
== 0);
1450 assert(num_components
== 0);
1455 ntq_setup_fs_inputs(struct v3d_compile
*c
)
1457 unsigned num_entries
= 0;
1458 unsigned num_components
= 0;
1459 nir_foreach_variable(var
, &c
->s
->inputs
) {
1461 num_components
+= glsl_get_components(var
->type
);
1464 nir_variable
*vars
[num_entries
];
1467 nir_foreach_variable(var
, &c
->s
->inputs
)
1470 /* Sort the variables so that we emit the input setup in
1471 * driver_location order. This is required for VPM reads, whose data
1472 * is fetched into the VPM in driver_location (TGSI register index)
1475 qsort(&vars
, num_entries
, sizeof(*vars
), driver_location_compare
);
1477 for (unsigned i
= 0; i
< num_entries
; i
++) {
1478 nir_variable
*var
= vars
[i
];
1479 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1480 unsigned loc
= var
->data
.driver_location
;
1482 assert(array_len
== 1);
1484 resize_qreg_array(c
, &c
->inputs
, &c
->inputs_array_size
,
1487 if (var
->data
.location
== VARYING_SLOT_POS
) {
1488 emit_fragcoord_input(c
, loc
);
1489 } else if (var
->data
.location
== VARYING_SLOT_PNTC
||
1490 (var
->data
.location
>= VARYING_SLOT_VAR0
&&
1491 (c
->fs_key
->point_sprite_mask
&
1492 (1 << (var
->data
.location
-
1493 VARYING_SLOT_VAR0
))))) {
1494 c
->inputs
[loc
* 4 + 0] = c
->point_x
;
1495 c
->inputs
[loc
* 4 + 1] = c
->point_y
;
1497 emit_fragment_input(c
, loc
, var
);
1503 ntq_setup_outputs(struct v3d_compile
*c
)
1505 nir_foreach_variable(var
, &c
->s
->outputs
) {
1506 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1507 unsigned loc
= var
->data
.driver_location
* 4;
1509 assert(array_len
== 1);
1512 for (int i
= 0; i
< 4 - var
->data
.location_frac
; i
++) {
1513 add_output(c
, loc
+ var
->data
.location_frac
+ i
,
1515 var
->data
.location_frac
+ i
);
1518 if (c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
) {
1519 switch (var
->data
.location
) {
1520 case FRAG_RESULT_COLOR
:
1521 c
->output_color_var
[0] = var
;
1522 c
->output_color_var
[1] = var
;
1523 c
->output_color_var
[2] = var
;
1524 c
->output_color_var
[3] = var
;
1526 case FRAG_RESULT_DATA0
:
1527 case FRAG_RESULT_DATA1
:
1528 case FRAG_RESULT_DATA2
:
1529 case FRAG_RESULT_DATA3
:
1530 c
->output_color_var
[var
->data
.location
-
1531 FRAG_RESULT_DATA0
] = var
;
1533 case FRAG_RESULT_DEPTH
:
1534 c
->output_position_index
= loc
;
1536 case FRAG_RESULT_SAMPLE_MASK
:
1537 c
->output_sample_mask_index
= loc
;
1541 switch (var
->data
.location
) {
1542 case VARYING_SLOT_POS
:
1543 c
->output_position_index
= loc
;
1545 case VARYING_SLOT_PSIZ
:
1546 c
->output_point_size_index
= loc
;
1554 ntq_setup_uniforms(struct v3d_compile
*c
)
1556 nir_foreach_variable(var
, &c
->s
->uniforms
) {
1557 uint32_t vec4_count
= glsl_count_attribute_slots(var
->type
,
1559 unsigned vec4_size
= 4 * sizeof(float);
1561 declare_uniform_range(c
, var
->data
.driver_location
* vec4_size
,
1562 vec4_count
* vec4_size
);
1568 * Sets up the mapping from nir_register to struct qreg *.
1570 * Each nir_register gets a struct qreg per 32-bit component being stored.
1573 ntq_setup_registers(struct v3d_compile
*c
, struct exec_list
*list
)
1575 foreach_list_typed(nir_register
, nir_reg
, node
, list
) {
1576 unsigned array_len
= MAX2(nir_reg
->num_array_elems
, 1);
1577 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
1579 nir_reg
->num_components
);
1581 _mesa_hash_table_insert(c
->def_ht
, nir_reg
, qregs
);
1583 for (int i
= 0; i
< array_len
* nir_reg
->num_components
; i
++)
1584 qregs
[i
] = vir_get_temp(c
);
1589 ntq_emit_load_const(struct v3d_compile
*c
, nir_load_const_instr
*instr
)
1591 /* XXX perf: Experiment with using immediate loads to avoid having
1592 * these end up in the uniform stream. Watch out for breaking the
1593 * small immediates optimization in the process!
1595 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1596 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1597 qregs
[i
] = vir_uniform_ui(c
, instr
->value
.u32
[i
]);
1599 _mesa_hash_table_insert(c
->def_ht
, &instr
->def
, qregs
);
1603 ntq_emit_ssa_undef(struct v3d_compile
*c
, nir_ssa_undef_instr
*instr
)
1605 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1607 /* VIR needs there to be *some* value, so pick 0 (same as for
1608 * ntq_setup_registers().
1610 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1611 qregs
[i
] = vir_uniform_ui(c
, 0);
1615 ntq_emit_intrinsic(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
)
1619 switch (instr
->intrinsic
) {
1620 case nir_intrinsic_load_uniform
:
1621 assert(instr
->num_components
== 1);
1622 if (nir_src_is_const(instr
->src
[0])) {
1623 offset
= (nir_intrinsic_base(instr
) +
1624 nir_src_as_uint(instr
->src
[0]));
1625 assert(offset
% 4 == 0);
1626 /* We need dwords */
1627 offset
= offset
/ 4;
1628 ntq_store_dest(c
, &instr
->dest
, 0,
1629 vir_uniform(c
, QUNIFORM_UNIFORM
,
1632 ntq_store_dest(c
, &instr
->dest
, 0,
1633 indirect_uniform_load(c
, instr
));
1637 case nir_intrinsic_load_ubo
:
1638 ntq_emit_tmu_general(c
, instr
);
1641 case nir_intrinsic_load_user_clip_plane
:
1642 for (int i
= 0; i
< instr
->num_components
; i
++) {
1643 ntq_store_dest(c
, &instr
->dest
, i
,
1644 vir_uniform(c
, QUNIFORM_USER_CLIP_PLANE
,
1645 nir_intrinsic_ucp_id(instr
) *
1650 case nir_intrinsic_load_alpha_ref_float
:
1651 ntq_store_dest(c
, &instr
->dest
, 0,
1652 vir_uniform(c
, QUNIFORM_ALPHA_REF
, 0));
1655 case nir_intrinsic_load_sample_mask_in
:
1656 ntq_store_dest(c
, &instr
->dest
, 0, vir_MSF(c
));
1659 case nir_intrinsic_load_helper_invocation
:
1660 vir_PF(c
, vir_MSF(c
), V3D_QPU_PF_PUSHZ
);
1661 ntq_store_dest(c
, &instr
->dest
, 0,
1662 vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFA
,
1663 vir_uniform_ui(c
, ~0),
1664 vir_uniform_ui(c
, 0))));
1667 case nir_intrinsic_load_front_face
:
1668 /* The register contains 0 (front) or 1 (back), and we need to
1669 * turn it into a NIR bool where true means front.
1671 ntq_store_dest(c
, &instr
->dest
, 0,
1673 vir_uniform_ui(c
, -1),
1677 case nir_intrinsic_load_instance_id
:
1678 ntq_store_dest(c
, &instr
->dest
, 0, vir_MOV(c
, c
->iid
));
1681 case nir_intrinsic_load_vertex_id
:
1682 ntq_store_dest(c
, &instr
->dest
, 0, vir_MOV(c
, c
->vid
));
1685 case nir_intrinsic_load_input
:
1686 for (int i
= 0; i
< instr
->num_components
; i
++) {
1687 offset
= (nir_intrinsic_base(instr
) +
1688 nir_src_as_uint(instr
->src
[0]));
1689 int comp
= nir_intrinsic_component(instr
) + i
;
1690 ntq_store_dest(c
, &instr
->dest
, i
,
1691 vir_MOV(c
, c
->inputs
[offset
* 4 + comp
]));
1695 case nir_intrinsic_store_output
:
1696 offset
= ((nir_intrinsic_base(instr
) +
1697 nir_src_as_uint(instr
->src
[1])) * 4 +
1698 nir_intrinsic_component(instr
));
1700 for (int i
= 0; i
< instr
->num_components
; i
++) {
1701 c
->outputs
[offset
+ i
] =
1702 vir_MOV(c
, ntq_get_src(c
, instr
->src
[0], i
));
1704 c
->num_outputs
= MAX2(c
->num_outputs
,
1705 offset
+ instr
->num_components
);
1708 case nir_intrinsic_discard
:
1709 if (c
->execute
.file
!= QFILE_NULL
) {
1710 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
1711 vir_set_cond(vir_SETMSF_dest(c
, vir_reg(QFILE_NULL
, 0),
1712 vir_uniform_ui(c
, 0)),
1715 vir_SETMSF_dest(c
, vir_reg(QFILE_NULL
, 0),
1716 vir_uniform_ui(c
, 0));
1720 case nir_intrinsic_discard_if
: {
1721 /* true (~0) if we're discarding */
1722 struct qreg cond
= ntq_get_src(c
, instr
->src
[0], 0);
1724 if (c
->execute
.file
!= QFILE_NULL
) {
1725 /* execute == 0 means the channel is active. Invert
1726 * the condition so that we can use zero as "executing
1729 vir_PF(c
, vir_OR(c
, c
->execute
, vir_NOT(c
, cond
)),
1731 vir_set_cond(vir_SETMSF_dest(c
, vir_reg(QFILE_NULL
, 0),
1732 vir_uniform_ui(c
, 0)),
1735 vir_PF(c
, cond
, V3D_QPU_PF_PUSHZ
);
1736 vir_set_cond(vir_SETMSF_dest(c
, vir_reg(QFILE_NULL
, 0),
1737 vir_uniform_ui(c
, 0)),
1745 fprintf(stderr
, "Unknown intrinsic: ");
1746 nir_print_instr(&instr
->instr
, stderr
);
1747 fprintf(stderr
, "\n");
1752 /* Clears (activates) the execute flags for any channels whose jump target
1753 * matches this block.
1755 * XXX perf: Could we be using flpush/flpop somehow for our execution channel
1758 * XXX perf: For uniform control flow, we should be able to skip c->execute
1759 * handling entirely.
1762 ntq_activate_execute_for_block(struct v3d_compile
*c
)
1764 vir_set_pf(vir_XOR_dest(c
, vir_reg(QFILE_NULL
, 0),
1765 c
->execute
, vir_uniform_ui(c
, c
->cur_block
->index
)),
1768 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
, vir_uniform_ui(c
, 0));
1772 ntq_emit_uniform_if(struct v3d_compile
*c
, nir_if
*if_stmt
)
1774 nir_block
*nir_else_block
= nir_if_first_else_block(if_stmt
);
1775 bool empty_else_block
=
1776 (nir_else_block
== nir_if_last_else_block(if_stmt
) &&
1777 exec_list_is_empty(&nir_else_block
->instr_list
));
1779 struct qblock
*then_block
= vir_new_block(c
);
1780 struct qblock
*after_block
= vir_new_block(c
);
1781 struct qblock
*else_block
;
1782 if (empty_else_block
)
1783 else_block
= after_block
;
1785 else_block
= vir_new_block(c
);
1787 /* Set up the flags for the IF condition (taking the THEN branch). */
1788 nir_alu_instr
*if_condition_alu
= ntq_get_alu_parent(if_stmt
->condition
);
1789 enum v3d_qpu_cond cond
;
1790 if (!if_condition_alu
||
1791 !ntq_emit_comparison(c
, if_condition_alu
, &cond
)) {
1792 vir_PF(c
, ntq_get_src(c
, if_stmt
->condition
, 0),
1794 cond
= V3D_QPU_COND_IFNA
;
1798 vir_BRANCH(c
, cond
== V3D_QPU_COND_IFA
?
1799 V3D_QPU_BRANCH_COND_ALLNA
:
1800 V3D_QPU_BRANCH_COND_ALLA
);
1801 vir_link_blocks(c
->cur_block
, else_block
);
1802 vir_link_blocks(c
->cur_block
, then_block
);
1804 /* Process the THEN block. */
1805 vir_set_emit_block(c
, then_block
);
1806 ntq_emit_cf_list(c
, &if_stmt
->then_list
);
1808 if (!empty_else_block
) {
1809 /* At the end of the THEN block, jump to ENDIF */
1810 vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ALWAYS
);
1811 vir_link_blocks(c
->cur_block
, after_block
);
1813 /* Emit the else block. */
1814 vir_set_emit_block(c
, else_block
);
1815 ntq_activate_execute_for_block(c
);
1816 ntq_emit_cf_list(c
, &if_stmt
->else_list
);
1819 vir_link_blocks(c
->cur_block
, after_block
);
1821 vir_set_emit_block(c
, after_block
);
1825 ntq_emit_nonuniform_if(struct v3d_compile
*c
, nir_if
*if_stmt
)
1827 nir_block
*nir_else_block
= nir_if_first_else_block(if_stmt
);
1828 bool empty_else_block
=
1829 (nir_else_block
== nir_if_last_else_block(if_stmt
) &&
1830 exec_list_is_empty(&nir_else_block
->instr_list
));
1832 struct qblock
*then_block
= vir_new_block(c
);
1833 struct qblock
*after_block
= vir_new_block(c
);
1834 struct qblock
*else_block
;
1835 if (empty_else_block
)
1836 else_block
= after_block
;
1838 else_block
= vir_new_block(c
);
1840 bool was_top_level
= false;
1841 if (c
->execute
.file
== QFILE_NULL
) {
1842 c
->execute
= vir_MOV(c
, vir_uniform_ui(c
, 0));
1843 was_top_level
= true;
1846 /* Set up the flags for the IF condition (taking the THEN branch). */
1847 nir_alu_instr
*if_condition_alu
= ntq_get_alu_parent(if_stmt
->condition
);
1848 enum v3d_qpu_cond cond
;
1849 if (!if_condition_alu
||
1850 !ntq_emit_comparison(c
, if_condition_alu
, &cond
)) {
1851 vir_PF(c
, ntq_get_src(c
, if_stmt
->condition
, 0),
1853 cond
= V3D_QPU_COND_IFNA
;
1856 /* Update the flags+cond to mean "Taking the ELSE branch (!cond) and
1857 * was previously active (execute Z) for updating the exec flags.
1859 if (was_top_level
) {
1860 cond
= v3d_qpu_cond_invert(cond
);
1862 struct qinst
*inst
= vir_MOV_dest(c
, vir_reg(QFILE_NULL
, 0),
1864 if (cond
== V3D_QPU_COND_IFA
) {
1865 vir_set_uf(inst
, V3D_QPU_UF_NORNZ
);
1867 vir_set_uf(inst
, V3D_QPU_UF_ANDZ
);
1868 cond
= V3D_QPU_COND_IFA
;
1872 vir_MOV_cond(c
, cond
,
1874 vir_uniform_ui(c
, else_block
->index
));
1876 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1879 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
1880 vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ALLNA
);
1881 vir_link_blocks(c
->cur_block
, else_block
);
1882 vir_link_blocks(c
->cur_block
, then_block
);
1884 /* Process the THEN block. */
1885 vir_set_emit_block(c
, then_block
);
1886 ntq_emit_cf_list(c
, &if_stmt
->then_list
);
1888 if (!empty_else_block
) {
1889 /* Handle the end of the THEN block. First, all currently
1890 * active channels update their execute flags to point to
1893 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
1894 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
,
1895 vir_uniform_ui(c
, after_block
->index
));
1897 /* If everything points at ENDIF, then jump there immediately. */
1898 vir_PF(c
, vir_XOR(c
, c
->execute
,
1899 vir_uniform_ui(c
, after_block
->index
)),
1901 vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ALLA
);
1902 vir_link_blocks(c
->cur_block
, after_block
);
1903 vir_link_blocks(c
->cur_block
, else_block
);
1905 vir_set_emit_block(c
, else_block
);
1906 ntq_activate_execute_for_block(c
);
1907 ntq_emit_cf_list(c
, &if_stmt
->else_list
);
1910 vir_link_blocks(c
->cur_block
, after_block
);
1912 vir_set_emit_block(c
, after_block
);
1914 c
->execute
= c
->undef
;
1916 ntq_activate_execute_for_block(c
);
1920 ntq_emit_if(struct v3d_compile
*c
, nir_if
*nif
)
1922 if (c
->execute
.file
== QFILE_NULL
&&
1923 nir_src_is_dynamically_uniform(nif
->condition
)) {
1924 ntq_emit_uniform_if(c
, nif
);
1926 ntq_emit_nonuniform_if(c
, nif
);
1931 ntq_emit_jump(struct v3d_compile
*c
, nir_jump_instr
*jump
)
1933 switch (jump
->type
) {
1934 case nir_jump_break
:
1935 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
1936 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
,
1937 vir_uniform_ui(c
, c
->loop_break_block
->index
));
1940 case nir_jump_continue
:
1941 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
1942 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
,
1943 vir_uniform_ui(c
, c
->loop_cont_block
->index
));
1946 case nir_jump_return
:
1947 unreachable("All returns shouold be lowered\n");
1952 ntq_emit_instr(struct v3d_compile
*c
, nir_instr
*instr
)
1954 switch (instr
->type
) {
1955 case nir_instr_type_alu
:
1956 ntq_emit_alu(c
, nir_instr_as_alu(instr
));
1959 case nir_instr_type_intrinsic
:
1960 ntq_emit_intrinsic(c
, nir_instr_as_intrinsic(instr
));
1963 case nir_instr_type_load_const
:
1964 ntq_emit_load_const(c
, nir_instr_as_load_const(instr
));
1967 case nir_instr_type_ssa_undef
:
1968 ntq_emit_ssa_undef(c
, nir_instr_as_ssa_undef(instr
));
1971 case nir_instr_type_tex
:
1972 ntq_emit_tex(c
, nir_instr_as_tex(instr
));
1975 case nir_instr_type_jump
:
1976 ntq_emit_jump(c
, nir_instr_as_jump(instr
));
1980 fprintf(stderr
, "Unknown NIR instr type: ");
1981 nir_print_instr(instr
, stderr
);
1982 fprintf(stderr
, "\n");
1988 ntq_emit_block(struct v3d_compile
*c
, nir_block
*block
)
1990 nir_foreach_instr(instr
, block
) {
1991 ntq_emit_instr(c
, instr
);
1995 static void ntq_emit_cf_list(struct v3d_compile
*c
, struct exec_list
*list
);
1998 ntq_emit_loop(struct v3d_compile
*c
, nir_loop
*loop
)
2000 bool was_top_level
= false;
2001 if (c
->execute
.file
== QFILE_NULL
) {
2002 c
->execute
= vir_MOV(c
, vir_uniform_ui(c
, 0));
2003 was_top_level
= true;
2006 struct qblock
*save_loop_cont_block
= c
->loop_cont_block
;
2007 struct qblock
*save_loop_break_block
= c
->loop_break_block
;
2009 c
->loop_cont_block
= vir_new_block(c
);
2010 c
->loop_break_block
= vir_new_block(c
);
2012 vir_link_blocks(c
->cur_block
, c
->loop_cont_block
);
2013 vir_set_emit_block(c
, c
->loop_cont_block
);
2014 ntq_activate_execute_for_block(c
);
2016 ntq_emit_cf_list(c
, &loop
->body
);
2018 /* Re-enable any previous continues now, so our ANYA check below
2021 * XXX: Use the .ORZ flags update, instead.
2023 vir_PF(c
, vir_XOR(c
,
2025 vir_uniform_ui(c
, c
->loop_cont_block
->index
)),
2027 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
, vir_uniform_ui(c
, 0));
2029 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
2031 struct qinst
*branch
= vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ANYA
);
2032 /* Pixels that were not dispatched or have been discarded should not
2033 * contribute to looping again.
2035 branch
->qpu
.branch
.msfign
= V3D_QPU_MSFIGN_P
;
2036 vir_link_blocks(c
->cur_block
, c
->loop_cont_block
);
2037 vir_link_blocks(c
->cur_block
, c
->loop_break_block
);
2039 vir_set_emit_block(c
, c
->loop_break_block
);
2041 c
->execute
= c
->undef
;
2043 ntq_activate_execute_for_block(c
);
2045 c
->loop_break_block
= save_loop_break_block
;
2046 c
->loop_cont_block
= save_loop_cont_block
;
2052 ntq_emit_function(struct v3d_compile
*c
, nir_function_impl
*func
)
2054 fprintf(stderr
, "FUNCTIONS not handled.\n");
2059 ntq_emit_cf_list(struct v3d_compile
*c
, struct exec_list
*list
)
2061 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2062 switch (node
->type
) {
2063 case nir_cf_node_block
:
2064 ntq_emit_block(c
, nir_cf_node_as_block(node
));
2067 case nir_cf_node_if
:
2068 ntq_emit_if(c
, nir_cf_node_as_if(node
));
2071 case nir_cf_node_loop
:
2072 ntq_emit_loop(c
, nir_cf_node_as_loop(node
));
2075 case nir_cf_node_function
:
2076 ntq_emit_function(c
, nir_cf_node_as_function(node
));
2080 fprintf(stderr
, "Unknown NIR node type\n");
2087 ntq_emit_impl(struct v3d_compile
*c
, nir_function_impl
*impl
)
2089 ntq_setup_registers(c
, &impl
->registers
);
2090 ntq_emit_cf_list(c
, &impl
->body
);
2094 nir_to_vir(struct v3d_compile
*c
)
2096 if (c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
) {
2097 c
->payload_w
= vir_MOV(c
, vir_reg(QFILE_REG
, 0));
2098 c
->payload_w_centroid
= vir_MOV(c
, vir_reg(QFILE_REG
, 1));
2099 c
->payload_z
= vir_MOV(c
, vir_reg(QFILE_REG
, 2));
2101 /* XXX perf: We could set the "disable implicit point/line
2102 * varyings" field in the shader record and not emit these, if
2103 * they're not going to be used.
2105 if (c
->fs_key
->is_points
) {
2106 c
->point_x
= emit_fragment_varying(c
, NULL
, 0);
2107 c
->point_y
= emit_fragment_varying(c
, NULL
, 0);
2108 } else if (c
->fs_key
->is_lines
) {
2109 c
->line_x
= emit_fragment_varying(c
, NULL
, 0);
2113 if (c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
)
2114 ntq_setup_fs_inputs(c
);
2116 ntq_setup_vpm_inputs(c
);
2118 ntq_setup_outputs(c
);
2119 ntq_setup_uniforms(c
);
2120 ntq_setup_registers(c
, &c
->s
->registers
);
2122 /* Find the main function and emit the body. */
2123 nir_foreach_function(function
, c
->s
) {
2124 assert(strcmp(function
->name
, "main") == 0);
2125 assert(function
->impl
);
2126 ntq_emit_impl(c
, function
->impl
);
2130 const nir_shader_compiler_options v3d_nir_options
= {
2131 .lower_all_io_to_temps
= true,
2132 .lower_extract_byte
= true,
2133 .lower_extract_word
= true,
2135 .lower_bitfield_insert_to_shifts
= true,
2136 .lower_bitfield_extract_to_shifts
= true,
2137 .lower_bitfield_reverse
= true,
2138 .lower_bit_count
= true,
2139 .lower_pack_unorm_2x16
= true,
2140 .lower_pack_snorm_2x16
= true,
2141 .lower_pack_unorm_4x8
= true,
2142 .lower_pack_snorm_4x8
= true,
2143 .lower_unpack_unorm_4x8
= true,
2144 .lower_unpack_snorm_4x8
= true,
2145 .lower_pack_half_2x16
= true,
2146 .lower_unpack_half_2x16
= true,
2148 .lower_find_lsb
= true,
2150 .lower_flrp32
= true,
2153 .lower_fsqrt
= true,
2154 .lower_ifind_msb
= true,
2155 .lower_ldexp
= true,
2156 .lower_mul_high
= true,
2157 .lower_wpos_pntc
= true,
2158 .native_integers
= true,
2162 * When demoting a shader down to single-threaded, removes the THRSW
2163 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
2167 vir_remove_thrsw(struct v3d_compile
*c
)
2169 vir_for_each_block(block
, c
) {
2170 vir_for_each_inst_safe(inst
, block
) {
2171 if (inst
->qpu
.sig
.thrsw
)
2172 vir_remove_instruction(c
, inst
);
2176 c
->last_thrsw
= NULL
;
2180 vir_emit_last_thrsw(struct v3d_compile
*c
)
2182 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
2183 * switching, so disable threads if we didn't do any TMU ops (each of
2184 * which would have emitted a THRSW).
2186 if (!c
->last_thrsw_at_top_level
&& c
->devinfo
->ver
< 41) {
2189 vir_remove_thrsw(c
);
2193 /* If we're threaded and the last THRSW was in conditional code, then
2194 * we need to emit another one so that we can flag it as the last
2197 if (c
->last_thrsw
&& !c
->last_thrsw_at_top_level
) {
2198 assert(c
->devinfo
->ver
>= 41);
2202 /* If we're threaded, then we need to mark the last THRSW instruction
2203 * so we can emit a pair of them at QPU emit time.
2205 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2206 * post-last-THRSW state, so we can skip this.
2208 if (!c
->last_thrsw
&& c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
) {
2209 assert(c
->devinfo
->ver
>= 41);
2214 c
->last_thrsw
->is_last_thrsw
= true;
2217 /* There's a flag in the shader for "center W is needed for reasons other than
2218 * non-centroid varyings", so we just walk the program after VIR optimization
2219 * to see if it's used. It should be harmless to set even if we only use
2220 * center W for varyings.
2223 vir_check_payload_w(struct v3d_compile
*c
)
2225 if (c
->s
->info
.stage
!= MESA_SHADER_FRAGMENT
)
2228 vir_for_each_inst_inorder(inst
, c
) {
2229 for (int i
= 0; i
< vir_get_nsrc(inst
); i
++) {
2230 if (inst
->src
[i
].file
== QFILE_REG
&&
2231 inst
->src
[i
].index
== 0) {
2232 c
->uses_center_w
= true;
2241 v3d_nir_to_vir(struct v3d_compile
*c
)
2243 if (V3D_DEBUG
& (V3D_DEBUG_NIR
|
2244 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
))) {
2245 fprintf(stderr
, "%s prog %d/%d NIR:\n",
2246 vir_get_stage_name(c
),
2247 c
->program_id
, c
->variant_id
);
2248 nir_print_shader(c
->s
, stderr
);
2253 /* Emit the last THRSW before STVPM and TLB writes. */
2254 vir_emit_last_thrsw(c
);
2256 switch (c
->s
->info
.stage
) {
2257 case MESA_SHADER_FRAGMENT
:
2260 case MESA_SHADER_VERTEX
:
2264 unreachable("bad stage");
2267 if (V3D_DEBUG
& (V3D_DEBUG_VIR
|
2268 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
))) {
2269 fprintf(stderr
, "%s prog %d/%d pre-opt VIR:\n",
2270 vir_get_stage_name(c
),
2271 c
->program_id
, c
->variant_id
);
2273 fprintf(stderr
, "\n");
2277 vir_lower_uniforms(c
);
2279 vir_check_payload_w(c
);
2281 /* XXX perf: On VC4, we do a VIR-level instruction scheduling here.
2282 * We used that on that platform to pipeline TMU writes and reduce the
2283 * number of thread switches, as well as try (mostly successfully) to
2284 * reduce maximum register pressure to allow more threads. We should
2285 * do something of that sort for V3D -- either instruction scheduling
2286 * here, or delay the the THRSW and LDTMUs from our texture
2287 * instructions until the results are needed.
2290 if (V3D_DEBUG
& (V3D_DEBUG_VIR
|
2291 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
))) {
2292 fprintf(stderr
, "%s prog %d/%d VIR:\n",
2293 vir_get_stage_name(c
),
2294 c
->program_id
, c
->variant_id
);
2296 fprintf(stderr
, "\n");
2299 /* Attempt to allocate registers for the temporaries. If we fail,
2300 * reduce thread count and try again.
2302 int min_threads
= (c
->devinfo
->ver
>= 41) ? 2 : 1;
2303 struct qpu_reg
*temp_registers
;
2306 temp_registers
= v3d_register_allocate(c
, &spilled
);
2313 if (c
->threads
== min_threads
) {
2314 fprintf(stderr
, "Failed to register allocate at %d threads:\n",
2323 if (c
->threads
== 1)
2324 vir_remove_thrsw(c
);
2327 v3d_vir_to_qpu(c
, temp_registers
);