src/broadcom/compiler/v3d40_tex.c

   1 /*
   2  * Copyright © 2016-2018 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "v3d_compiler.h"
  25 #include "compiler/nir/nir_deref.h"
  26
  27 /* We don't do any address packing. */
  28 #define __gen_user_data void
  29 #define __gen_address_type uint32_t
  30 #define __gen_address_offset(reloc) (*reloc)
  31 #define __gen_emit_reloc(cl, reloc)
  32 #include "cle/v3d_packet_v41_pack.h"
  33
  34 static void
  35 vir_TMU_WRITE(struct v3d_compile *c, enum v3d_qpu_waddr waddr, struct qreg val,
  36               int *tmu_writes)
  37 {
  38         /* XXX perf: We should figure out how to merge ALU operations
  39          * producing the val with this MOV, when possible.
  40          */
  41         vir_MOV_dest(c, vir_reg(QFILE_MAGIC, waddr), val);
  42
  43         (*tmu_writes)++;
  44 }
  45
  46 static void
  47 vir_WRTMUC(struct v3d_compile *c, enum quniform_contents contents, uint32_t data)
  48 {
  49         struct qinst *inst = vir_NOP(c);
  50         inst->qpu.sig.wrtmuc = true;
  51         inst->uniform = vir_get_uniform_index(c, contents, data);
  52 }
  53
  54 static const struct V3D41_TMU_CONFIG_PARAMETER_1 p1_unpacked_default = {
  55         .per_pixel_mask_enable = true,
  56 };
  57
  58 static const struct V3D41_TMU_CONFIG_PARAMETER_2 p2_unpacked_default = {
  59         .op = V3D_TMU_OP_REGULAR,
  60 };
  61
  62 void
  63 v3d40_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
  64 {
  65         unsigned unit = instr->texture_index;
  66         int tmu_writes = 0;
  67
  68         struct V3D41_TMU_CONFIG_PARAMETER_0 p0_unpacked = {
  69         };
  70
  71         struct V3D41_TMU_CONFIG_PARAMETER_1 p1_unpacked = {
  72                 .output_type_32_bit = (c->key->tex[unit].return_size == 32 &&
  73                                        !instr->is_shadow),
  74
  75                 .unnormalized_coordinates = (instr->sampler_dim ==
  76                                              GLSL_SAMPLER_DIM_RECT),
  77         };
  78
  79         struct V3D41_TMU_CONFIG_PARAMETER_2 p2_unpacked = {
  80                 .op = V3D_TMU_OP_REGULAR,
  81
  82                 .gather_mode = instr->op == nir_texop_tg4,
  83                 .gather_component = instr->component,
  84
  85                 .coefficient_mode = instr->op == nir_texop_txd,
  86
  87                 .disable_autolod = instr->op == nir_texop_tg4
  88         };
  89
  90         int non_array_components = instr->coord_components - instr->is_array;
  91         struct qreg s;
  92
  93         for (unsigned i = 0; i < instr->num_srcs; i++) {
  94                 switch (instr->src[i].src_type) {
  95                 case nir_tex_src_coord:
  96                         /* S triggers the lookup, so save it for the end. */
  97                         s = ntq_get_src(c, instr->src[i].src, 0);
  98
  99                         if (non_array_components > 1) {
 100                                 vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUT,
 101                                               ntq_get_src(c, instr->src[i].src,
 102                                                           1), &tmu_writes);
 103                         }
 104                         if (non_array_components > 2) {
 105                                 vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUR,
 106                                               ntq_get_src(c, instr->src[i].src,
 107                                                           2), &tmu_writes);
 108                         }
 109
 110                         if (instr->is_array) {
 111                                 vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUI,
 112                                               ntq_get_src(c, instr->src[i].src,
 113                                                           instr->coord_components - 1),
 114                                               &tmu_writes);
 115                         }
 116                         break;
 117
 118                 case nir_tex_src_bias:
 119                         vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUB,
 120                                       ntq_get_src(c, instr->src[i].src, 0),
 121                                       &tmu_writes);
 122                         break;
 123
 124                 case nir_tex_src_lod:
 125                         vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUB,
 126                                       ntq_get_src(c, instr->src[i].src, 0),
 127                                       &tmu_writes);
 128
 129                         if (instr->op != nir_texop_txf)
 130                                 p2_unpacked.disable_autolod = true;
 131                         break;
 132
 133                 case nir_tex_src_comparator:
 134                         vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUDREF,
 135                                       ntq_get_src(c, instr->src[i].src, 0),
 136                                       &tmu_writes);
 137                         break;
 138
 139                 case nir_tex_src_offset: {
 140                         if (nir_src_is_const(instr->src[i].src)) {
 141                                 p2_unpacked.offset_s = nir_src_comp_as_int(instr->src[i].src, 0);
 142                                 if (instr->coord_components >= 2)
 143                                         p2_unpacked.offset_t =
 144                                                 nir_src_comp_as_int(instr->src[i].src, 1);
 145                                 if (non_array_components >= 3)
 146                                         p2_unpacked.offset_r =
 147                                                 nir_src_comp_as_int(instr->src[i].src, 2);
 148                         } else {
 149                                 struct qreg mask = vir_uniform_ui(c, 0xf);
 150                                 struct qreg x, y, offset;
 151
 152                                 x = vir_AND(c, ntq_get_src(c, instr->src[i].src,
 153                                                            0), mask);
 154                                 y = vir_AND(c, ntq_get_src(c, instr->src[i].src,
 155                                                            1), mask);
 156                                 offset = vir_OR(c, x,
 157                                                 vir_SHL(c, y,
 158                                                         vir_uniform_ui(c, 4)));
 159
 160                                 vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUOFF,
 161                                               offset, &tmu_writes);
 162                         }
 163                         break;
 164                 }
 165
 166                 default:
 167                         unreachable("unknown texture source");
 168                 }
 169         }
 170
 171         /* Limit the number of channels returned to both how many the NIR
 172          * instruction writes and how many the instruction could produce.
 173          */
 174         assert(instr->dest.is_ssa);
 175         p0_unpacked.return_words_of_texture_data =
 176                 nir_ssa_def_components_read(&instr->dest.ssa);
 177
 178         /* Word enables can't ask for more channels than the output type could
 179          * provide (2 for f16, 4 for 32-bit).
 180          */
 181         assert(!p1_unpacked.output_type_32_bit ||
 182                p0_unpacked.return_words_of_texture_data < (1 << 4));
 183         assert(p1_unpacked.output_type_32_bit ||
 184                p0_unpacked.return_words_of_texture_data < (1 << 2));
 185
 186         assert(p0_unpacked.return_words_of_texture_data != 0);
 187
 188         uint32_t p0_packed;
 189         V3D41_TMU_CONFIG_PARAMETER_0_pack(NULL,
 190                                           (uint8_t *)&p0_packed,
 191                                           &p0_unpacked);
 192
 193         uint32_t p1_packed;
 194         V3D41_TMU_CONFIG_PARAMETER_1_pack(NULL,
 195                                           (uint8_t *)&p1_packed,
 196                                           &p1_unpacked);
 197
 198         uint32_t p2_packed;
 199         V3D41_TMU_CONFIG_PARAMETER_2_pack(NULL,
 200                                           (uint8_t *)&p2_packed,
 201                                           &p2_unpacked);
 202
 203         /* Load unit number into the high bits of the texture or sampler
 204          * address field, which will be be used by the driver to decide which
 205          * texture to put in the actual address field.
 206          */
 207         p0_packed |= unit << 24;
 208         p1_packed |= unit << 24;
 209
 210         vir_WRTMUC(c, QUNIFORM_TMU_CONFIG_P0, p0_packed);
 211         /* XXX perf: Can we skip p1 setup for txf ops? */
 212         vir_WRTMUC(c, QUNIFORM_TMU_CONFIG_P1, p1_packed);
 213         if (memcmp(&p2_unpacked, &p2_unpacked_default, sizeof(p2_unpacked)) != 0)
 214                 vir_WRTMUC(c, QUNIFORM_CONSTANT, p2_packed);
 215
 216         if (instr->op == nir_texop_txf) {
 217                 assert(instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE);
 218                 vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUSF, s, &tmu_writes);
 219         } else if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
 220                 vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUSCM, s, &tmu_writes);
 221         } else {
 222                 vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUS, s, &tmu_writes);
 223         }
 224
 225         vir_emit_thrsw(c);
 226
 227         /* The input FIFO has 16 slots across all threads, so make sure we
 228          * don't overfill our allocation.
 229          */
 230         while (tmu_writes > 16 / c->threads)
 231                 c->threads /= 2;
 232
 233         for (int i = 0; i < 4; i++) {
 234                 if (p0_unpacked.return_words_of_texture_data & (1 << i))
 235                         ntq_store_dest(c, &instr->dest, i, vir_LDTMU(c));
 236         }
 237 }
 238
 239 static void
 240 type_size_align_1(const struct glsl_type *type, unsigned *size, unsigned *align)
 241 {
 242         *size = 1;
 243         *align = 1;
 244 }
 245
 246 static uint32_t
 247 v3d40_image_load_store_tmu_op(nir_intrinsic_instr *instr)
 248 {
 249         switch (instr->intrinsic) {
 250         case nir_intrinsic_image_deref_load:
 251         case nir_intrinsic_image_deref_store:
 252                 return V3D_TMU_OP_REGULAR;
 253         case nir_intrinsic_image_deref_atomic_add:
 254                 return v3d_get_op_for_atomic_add(instr, 3);
 255         case nir_intrinsic_image_deref_atomic_min:
 256                 return V3D_TMU_OP_WRITE_UMIN_FULL_L1_CLEAR;
 257         case nir_intrinsic_image_deref_atomic_max:
 258                 return V3D_TMU_OP_WRITE_UMAX;
 259         case nir_intrinsic_image_deref_atomic_and:
 260                 return V3D_TMU_OP_WRITE_AND_READ_INC;
 261         case nir_intrinsic_image_deref_atomic_or:
 262                 return V3D_TMU_OP_WRITE_OR_READ_DEC;
 263         case nir_intrinsic_image_deref_atomic_xor:
 264                 return V3D_TMU_OP_WRITE_XOR_READ_NOT;
 265         case nir_intrinsic_image_deref_atomic_exchange:
 266                 return V3D_TMU_OP_WRITE_XCHG_READ_FLUSH;
 267         case nir_intrinsic_image_deref_atomic_comp_swap:
 268                 return V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH;
 269         default:
 270                 unreachable("unknown image intrinsic");
 271         };
 272 }
 273
 274 void
 275 v3d40_vir_emit_image_load_store(struct v3d_compile *c,
 276                                 nir_intrinsic_instr *instr)
 277 {
 278         nir_variable *var = nir_intrinsic_get_var(instr, 0);
 279         const struct glsl_type *sampler_type = glsl_without_array(var->type);
 280         unsigned unit = (var->data.driver_location +
 281                          nir_deref_instr_get_const_offset(nir_src_as_deref(instr->src[0]),
 282                                                           type_size_align_1));
 283         int tmu_writes = 0;
 284
 285         struct V3D41_TMU_CONFIG_PARAMETER_0 p0_unpacked = {
 286         };
 287
 288         struct V3D41_TMU_CONFIG_PARAMETER_1 p1_unpacked = {
 289                 .per_pixel_mask_enable = true,
 290                 .output_type_32_bit = v3d_gl_format_is_return_32(var->data.image.format),
 291         };
 292
 293         struct V3D41_TMU_CONFIG_PARAMETER_2 p2_unpacked = { 0 };
 294
 295         p2_unpacked.op = v3d40_image_load_store_tmu_op(instr);
 296
 297         /* If we were able to replace atomic_add for an inc/dec, then we
 298          * need/can to do things slightly different, like not loading the
 299          * amount to add/sub, as that is implicit.
 300          */
 301         bool atomic_add_replaced = (instr->intrinsic == nir_intrinsic_image_deref_atomic_add &&
 302                                     (p2_unpacked.op == V3D_TMU_OP_WRITE_AND_READ_INC ||
 303                                      p2_unpacked.op == V3D_TMU_OP_WRITE_OR_READ_DEC));
 304
 305         bool is_1d = false;
 306         switch (glsl_get_sampler_dim(sampler_type)) {
 307         case GLSL_SAMPLER_DIM_1D:
 308                 is_1d = true;
 309                 break;
 310         case GLSL_SAMPLER_DIM_BUF:
 311                 break;
 312         case GLSL_SAMPLER_DIM_2D:
 313         case GLSL_SAMPLER_DIM_RECT:
 314                 vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUT,
 315                               ntq_get_src(c, instr->src[1], 1), &tmu_writes);
 316                 break;
 317         case GLSL_SAMPLER_DIM_3D:
 318         case GLSL_SAMPLER_DIM_CUBE:
 319                 vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUT,
 320                               ntq_get_src(c, instr->src[1], 1), &tmu_writes);
 321                 vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUR,
 322                               ntq_get_src(c, instr->src[1], 2), &tmu_writes);
 323                 break;
 324         default:
 325                 unreachable("bad image sampler dim");
 326         }
 327
 328         if (glsl_sampler_type_is_array(sampler_type)) {
 329                 vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUI,
 330                               ntq_get_src(c, instr->src[1],
 331                                           is_1d ? 1 : 2), &tmu_writes);
 332         }
 333
 334         /* Limit the number of channels returned to both how many the NIR
 335          * instruction writes and how many the instruction could produce.
 336          */
 337         uint32_t instr_return_channels = nir_intrinsic_dest_components(instr);
 338         if (!p1_unpacked.output_type_32_bit)
 339                 instr_return_channels = (instr_return_channels + 1) / 2;
 340
 341         p0_unpacked.return_words_of_texture_data =
 342                 (1 << instr_return_channels) - 1;
 343
 344         uint32_t p0_packed;
 345         V3D41_TMU_CONFIG_PARAMETER_0_pack(NULL,
 346                                           (uint8_t *)&p0_packed,
 347                                           &p0_unpacked);
 348
 349         uint32_t p1_packed;
 350         V3D41_TMU_CONFIG_PARAMETER_1_pack(NULL,
 351                                           (uint8_t *)&p1_packed,
 352                                           &p1_unpacked);
 353
 354         uint32_t p2_packed;
 355         V3D41_TMU_CONFIG_PARAMETER_2_pack(NULL,
 356                                           (uint8_t *)&p2_packed,
 357                                           &p2_unpacked);
 358
 359         /* Load unit number into the high bits of the texture or sampler
 360          * address field, which will be be used by the driver to decide which
 361          * texture to put in the actual address field.
 362          */
 363         p0_packed |= unit << 24;
 364
 365         vir_WRTMUC(c, QUNIFORM_IMAGE_TMU_CONFIG_P0, p0_packed);
 366         if (memcmp(&p1_unpacked, &p1_unpacked_default, sizeof(p1_unpacked)) != 0)
 367                 vir_WRTMUC(c, QUNIFORM_CONSTANT, p1_packed);
 368         if (memcmp(&p2_unpacked, &p2_unpacked_default, sizeof(p2_unpacked)) != 0)
 369                 vir_WRTMUC(c, QUNIFORM_CONSTANT, p2_packed);
 370
 371         /* Emit the data writes for atomics or image store. */
 372         if (instr->intrinsic != nir_intrinsic_image_deref_load &&
 373             !atomic_add_replaced) {
 374                 /* Vector for stores, or first atomic argument */
 375                 struct qreg src[4];
 376                 for (int i = 0; i < nir_intrinsic_src_components(instr, 3); i++) {
 377                         src[i] = ntq_get_src(c, instr->src[3], i);
 378                         vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUD, src[i],
 379                                       &tmu_writes);
 380                 }
 381
 382                 /* Second atomic argument */
 383                 if (instr->intrinsic ==
 384                     nir_intrinsic_image_deref_atomic_comp_swap) {
 385                         vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUD,
 386                                       ntq_get_src(c, instr->src[4], 0),
 387                                       &tmu_writes);
 388                 }
 389         }
 390
 391         vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUSF, ntq_get_src(c, instr->src[1], 0),
 392                       &tmu_writes);
 393
 394         vir_emit_thrsw(c);
 395
 396         /* The input FIFO has 16 slots across all threads, so make sure we
 397          * don't overfill our allocation.
 398          */
 399         while (tmu_writes > 16 / c->threads)
 400                 c->threads /= 2;
 401
 402         for (int i = 0; i < 4; i++) {
 403                 if (p0_unpacked.return_words_of_texture_data & (1 << i))
 404                         ntq_store_dest(c, &instr->dest, i, vir_LDTMU(c));
 405         }
 406
 407         if (nir_intrinsic_dest_components(instr) == 0)
 408                 vir_TMUWT(c);
 409 }