src/broadcom/compiler/v3d40_tex.c

   1 /*
   2  * Copyright © 2016-2018 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "v3d_compiler.h"
  25 #include "compiler/nir/nir_deref.h"
  26
  27 /* We don't do any address packing. */
  28 #define __gen_user_data void
  29 #define __gen_address_type uint32_t
  30 #define __gen_address_offset(reloc) (*reloc)
  31 #define __gen_emit_reloc(cl, reloc)
  32 #include "cle/v3d_packet_v41_pack.h"
  33
  34 static void
  35 vir_TMU_WRITE(struct v3d_compile *c, enum v3d_qpu_waddr waddr, struct qreg val,
  36               int *tmu_writes)
  37 {
  38         /* XXX perf: We should figure out how to merge ALU operations
  39          * producing the val with this MOV, when possible.
  40          */
  41         vir_MOV_dest(c, vir_reg(QFILE_MAGIC, waddr), val);
  42
  43         (*tmu_writes)++;
  44 }
  45
  46 static void
  47 vir_WRTMUC(struct v3d_compile *c, enum quniform_contents contents, uint32_t data)
  48 {
  49         struct qinst *inst = vir_NOP(c);
  50         inst->qpu.sig.wrtmuc = true;
  51         inst->uniform = vir_get_uniform_index(c, contents, data);
  52 }
  53
  54 static const struct V3D41_TMU_CONFIG_PARAMETER_1 p1_unpacked_default = {
  55         .per_pixel_mask_enable = true,
  56 };
  57
  58 static const struct V3D41_TMU_CONFIG_PARAMETER_2 p2_unpacked_default = {
  59         .op = V3D_TMU_OP_REGULAR,
  60 };
  61
  62 void
  63 v3d40_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
  64 {
  65         unsigned unit = instr->texture_index;
  66         int tmu_writes = 0;
  67
  68         struct V3D41_TMU_CONFIG_PARAMETER_0 p0_unpacked = {
  69         };
  70
  71         struct V3D41_TMU_CONFIG_PARAMETER_1 p1_unpacked = {
  72                 .output_type_32_bit = (c->key->tex[unit].return_size == 32 &&
  73                                        !instr->is_shadow),
  74
  75                 .unnormalized_coordinates = (instr->sampler_dim ==
  76                                              GLSL_SAMPLER_DIM_RECT),
  77         };
  78
  79         struct V3D41_TMU_CONFIG_PARAMETER_2 p2_unpacked = {
  80                 .op = V3D_TMU_OP_REGULAR,
  81
  82                 .gather_mode = instr->op == nir_texop_tg4,
  83                 .gather_component = instr->component,
  84
  85                 .coefficient_mode = instr->op == nir_texop_txd,
  86
  87                 .disable_autolod = instr->op == nir_texop_tg4
  88         };
  89
  90         int non_array_components = instr->coord_components - instr->is_array;
  91         struct qreg s;
  92
  93         for (unsigned i = 0; i < instr->num_srcs; i++) {
  94                 switch (instr->src[i].src_type) {
  95                 case nir_tex_src_coord:
  96                         /* S triggers the lookup, so save it for the end. */
  97                         s = ntq_get_src(c, instr->src[i].src, 0);
  98
  99                         if (non_array_components > 1) {
 100                                 vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUT,
 101                                               ntq_get_src(c, instr->src[i].src,
 102                                                           1), &tmu_writes);
 103                         }
 104                         if (non_array_components > 2) {
 105                                 vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUR,
 106                                               ntq_get_src(c, instr->src[i].src,
 107                                                           2), &tmu_writes);
 108                         }
 109
 110                         if (instr->is_array) {
 111                                 vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUI,
 112                                               ntq_get_src(c, instr->src[i].src,
 113                                                           instr->coord_components - 1),
 114                                               &tmu_writes);
 115                         }
 116                         break;
 117
 118                 case nir_tex_src_bias:
 119                         vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUB,
 120                                       ntq_get_src(c, instr->src[i].src, 0),
 121                                       &tmu_writes);
 122                         break;
 123
 124                 case nir_tex_src_lod:
 125                         vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUB,
 126                                       ntq_get_src(c, instr->src[i].src, 0),
 127                                       &tmu_writes);
 128
 129                         if (instr->op != nir_texop_txf)
 130                                 p2_unpacked.disable_autolod = true;
 131                         break;
 132
 133                 case nir_tex_src_comparator:
 134                         vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUDREF,
 135                                       ntq_get_src(c, instr->src[i].src, 0),
 136                                       &tmu_writes);
 137                         break;
 138
 139                 case nir_tex_src_offset: {
 140                         if (nir_src_is_const(instr->src[i].src)) {
 141                                 nir_const_value *offset =
 142                                         nir_src_as_const_value(instr->src[i].src);
 143
 144                                 p2_unpacked.offset_s = offset->i32[0];
 145                                 if (instr->coord_components >= 2)
 146                                         p2_unpacked.offset_t = offset->i32[1];
 147                                 if (instr->coord_components >= 3)
 148                                         p2_unpacked.offset_r = offset->i32[2];
 149                         } else {
 150                                 struct qreg mask = vir_uniform_ui(c, 0xf);
 151                                 struct qreg x, y, offset;
 152
 153                                 x = vir_AND(c, ntq_get_src(c, instr->src[i].src,
 154                                                            0), mask);
 155                                 y = vir_AND(c, ntq_get_src(c, instr->src[i].src,
 156                                                            1), mask);
 157                                 offset = vir_OR(c, x,
 158                                                 vir_SHL(c, y,
 159                                                         vir_uniform_ui(c, 4)));
 160
 161                                 vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUOFF,
 162                                               offset, &tmu_writes);
 163                         }
 164                         break;
 165                 }
 166
 167                 default:
 168                         unreachable("unknown texture source");
 169                 }
 170         }
 171
 172         /* Limit the number of channels returned to both how many the NIR
 173          * instruction writes and how many the instruction could produce.
 174          */
 175         assert(instr->dest.is_ssa);
 176         p0_unpacked.return_words_of_texture_data =
 177                 nir_ssa_def_components_read(&instr->dest.ssa);
 178
 179         /* Word enables can't ask for more channels than the output type could
 180          * provide (2 for f16, 4 for 32-bit).
 181          */
 182         assert(!p1_unpacked.output_type_32_bit ||
 183                p0_unpacked.return_words_of_texture_data < (1 << 4));
 184         assert(p1_unpacked.output_type_32_bit ||
 185                p0_unpacked.return_words_of_texture_data < (1 << 2));
 186
 187         uint32_t p0_packed;
 188         V3D41_TMU_CONFIG_PARAMETER_0_pack(NULL,
 189                                           (uint8_t *)&p0_packed,
 190                                           &p0_unpacked);
 191
 192         uint32_t p1_packed;
 193         V3D41_TMU_CONFIG_PARAMETER_1_pack(NULL,
 194                                           (uint8_t *)&p1_packed,
 195                                           &p1_unpacked);
 196
 197         uint32_t p2_packed;
 198         V3D41_TMU_CONFIG_PARAMETER_2_pack(NULL,
 199                                           (uint8_t *)&p2_packed,
 200                                           &p2_unpacked);
 201
 202         /* Load unit number into the high bits of the texture or sampler
 203          * address field, which will be be used by the driver to decide which
 204          * texture to put in the actual address field.
 205          */
 206         p0_packed |= unit << 24;
 207         p1_packed |= unit << 24;
 208
 209         vir_WRTMUC(c, QUNIFORM_TMU_CONFIG_P0, p0_packed);
 210         /* XXX perf: Can we skip p1 setup for txf ops? */
 211         vir_WRTMUC(c, QUNIFORM_TMU_CONFIG_P1, p1_packed);
 212         if (memcmp(&p2_unpacked, &p2_unpacked_default, sizeof(p2_unpacked)) != 0)
 213                 vir_WRTMUC(c, QUNIFORM_CONSTANT, p2_packed);
 214
 215         if (instr->op == nir_texop_txf) {
 216                 assert(instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE);
 217                 vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUSF, s, &tmu_writes);
 218         } else if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
 219                 vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUSCM, s, &tmu_writes);
 220         } else {
 221                 vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUS, s, &tmu_writes);
 222         }
 223
 224         vir_emit_thrsw(c);
 225
 226         /* The input FIFO has 16 slots across all threads, so make sure we
 227          * don't overfill our allocation.
 228          */
 229         while (tmu_writes > 16 / c->threads)
 230                 c->threads /= 2;
 231
 232         for (int i = 0; i < 4; i++) {
 233                 if (p0_unpacked.return_words_of_texture_data & (1 << i))
 234                         ntq_store_dest(c, &instr->dest, i, vir_LDTMU(c));
 235         }
 236 }
 237
 238 static void
 239 type_size_align_1(const struct glsl_type *type, unsigned *size, unsigned *align)
 240 {
 241         *size = 1;
 242         *align = 1;
 243 }
 244
 245 void
 246 v3d40_vir_emit_image_load_store(struct v3d_compile *c,
 247                                 nir_intrinsic_instr *instr)
 248 {
 249         nir_variable *var = nir_intrinsic_get_var(instr, 0);
 250         const struct glsl_type *sampler_type = glsl_without_array(var->type);
 251         unsigned unit = (var->data.driver_location +
 252                          nir_deref_instr_get_const_offset(nir_src_as_deref(instr->src[0]),
 253                                                           type_size_align_1));
 254         int tmu_writes = 0;
 255
 256         struct V3D41_TMU_CONFIG_PARAMETER_0 p0_unpacked = {
 257         };
 258
 259         struct V3D41_TMU_CONFIG_PARAMETER_1 p1_unpacked = {
 260                 .per_pixel_mask_enable = true,
 261                 .output_type_32_bit = v3d_gl_format_is_return_32(var->data.image.format),
 262         };
 263
 264         struct V3D41_TMU_CONFIG_PARAMETER_2 p2_unpacked = { 0 };
 265
 266         /* XXX perf: We should turn add/sub of 1 to inc/dec.  Perhaps NIR
 267          * wants to have support for inc/dec?
 268          */
 269         switch (instr->intrinsic) {
 270         case nir_intrinsic_image_deref_load:
 271         case nir_intrinsic_image_deref_store:
 272                 p2_unpacked.op = V3D_TMU_OP_REGULAR;
 273                 break;
 274         case nir_intrinsic_image_deref_atomic_add:
 275                 p2_unpacked.op = V3D_TMU_OP_WRITE_ADD_READ_PREFETCH;
 276                 break;
 277         case nir_intrinsic_image_deref_atomic_min:
 278                 p2_unpacked.op = V3D_TMU_OP_WRITE_UMIN_FULL_L1_CLEAR;
 279                 break;
 280
 281         case nir_intrinsic_image_deref_atomic_max:
 282                 p2_unpacked.op = V3D_TMU_OP_WRITE_UMAX;
 283                 break;
 284         case nir_intrinsic_image_deref_atomic_and:
 285                 p2_unpacked.op = V3D_TMU_OP_WRITE_AND_READ_INC;
 286                 break;
 287         case nir_intrinsic_image_deref_atomic_or:
 288                 p2_unpacked.op = V3D_TMU_OP_WRITE_OR_READ_DEC;
 289                 break;
 290         case nir_intrinsic_image_deref_atomic_xor:
 291                 p2_unpacked.op = V3D_TMU_OP_WRITE_XOR_READ_NOT;
 292                 break;
 293         case nir_intrinsic_image_deref_atomic_exchange:
 294                 p2_unpacked.op = V3D_TMU_OP_WRITE_XCHG_READ_FLUSH;
 295                 break;
 296         case nir_intrinsic_image_deref_atomic_comp_swap:
 297                 p2_unpacked.op = V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH;
 298                 break;
 299         default:
 300                 unreachable("unknown image intrinsic");
 301         };
 302
 303         bool is_1d = false;
 304         switch (glsl_get_sampler_dim(sampler_type)) {
 305         case GLSL_SAMPLER_DIM_1D:
 306                 is_1d = true;
 307                 break;
 308         case GLSL_SAMPLER_DIM_BUF:
 309                 break;
 310         case GLSL_SAMPLER_DIM_2D:
 311         case GLSL_SAMPLER_DIM_RECT:
 312                 vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUT,
 313                               ntq_get_src(c, instr->src[1], 1), &tmu_writes);
 314                 break;
 315         case GLSL_SAMPLER_DIM_3D:
 316         case GLSL_SAMPLER_DIM_CUBE:
 317                 vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUT,
 318                               ntq_get_src(c, instr->src[1], 1), &tmu_writes);
 319                 vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUR,
 320                               ntq_get_src(c, instr->src[1], 2), &tmu_writes);
 321                 break;
 322         default:
 323                 unreachable("bad image sampler dim");
 324         }
 325
 326         if (glsl_sampler_type_is_array(sampler_type)) {
 327                 vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUI,
 328                               ntq_get_src(c, instr->src[1],
 329                                           is_1d ? 1 : 2), &tmu_writes);
 330         }
 331
 332         /* Limit the number of channels returned to both how many the NIR
 333          * instruction writes and how many the instruction could produce.
 334          */
 335         uint32_t instr_return_channels = nir_intrinsic_dest_components(instr);
 336         if (!p1_unpacked.output_type_32_bit)
 337                 instr_return_channels = (instr_return_channels + 1) / 2;
 338
 339         p0_unpacked.return_words_of_texture_data =
 340                 (1 << instr_return_channels) - 1;
 341
 342         uint32_t p0_packed;
 343         V3D41_TMU_CONFIG_PARAMETER_0_pack(NULL,
 344                                           (uint8_t *)&p0_packed,
 345                                           &p0_unpacked);
 346
 347         uint32_t p1_packed;
 348         V3D41_TMU_CONFIG_PARAMETER_1_pack(NULL,
 349                                           (uint8_t *)&p1_packed,
 350                                           &p1_unpacked);
 351
 352         uint32_t p2_packed;
 353         V3D41_TMU_CONFIG_PARAMETER_2_pack(NULL,
 354                                           (uint8_t *)&p2_packed,
 355                                           &p2_unpacked);
 356
 357         /* Load unit number into the high bits of the texture or sampler
 358          * address field, which will be be used by the driver to decide which
 359          * texture to put in the actual address field.
 360          */
 361         p0_packed |= unit << 24;
 362
 363         vir_WRTMUC(c, QUNIFORM_IMAGE_TMU_CONFIG_P0, p0_packed);
 364         if (memcmp(&p1_unpacked, &p1_unpacked_default, sizeof(p1_unpacked)) != 0)
 365                 vir_WRTMUC(c, QUNIFORM_CONSTANT, p1_packed);
 366         if (memcmp(&p2_unpacked, &p2_unpacked_default, sizeof(p2_unpacked)) != 0)
 367                 vir_WRTMUC(c, QUNIFORM_CONSTANT, p2_packed);
 368
 369         /* Emit the data writes for atomics or image store. */
 370         if (instr->intrinsic != nir_intrinsic_image_deref_load) {
 371                 /* Vector for stores, or first atomic argument */
 372                 struct qreg src[4];
 373                 for (int i = 0; i < nir_intrinsic_src_components(instr, 3); i++) {
 374                         src[i] = ntq_get_src(c, instr->src[3], i);
 375                         vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUD, src[i],
 376                                       &tmu_writes);
 377                 }
 378
 379                 /* Second atomic argument */
 380                 if (instr->intrinsic ==
 381                     nir_intrinsic_image_deref_atomic_comp_swap) {
 382                         vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUD,
 383                                       ntq_get_src(c, instr->src[4], 0),
 384                                       &tmu_writes);
 385                 }
 386         }
 387
 388         vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUSF, ntq_get_src(c, instr->src[1], 0),
 389                       &tmu_writes);
 390
 391         vir_emit_thrsw(c);
 392
 393         /* The input FIFO has 16 slots across all threads, so make sure we
 394          * don't overfill our allocation.
 395          */
 396         while (tmu_writes > 16 / c->threads)
 397                 c->threads /= 2;
 398
 399         for (int i = 0; i < 4; i++) {
 400                 if (p0_unpacked.return_words_of_texture_data & (1 << i))
 401                         ntq_store_dest(c, &instr->dest, i, vir_LDTMU(c));
 402         }
 403
 404         if (nir_intrinsic_dest_components(instr) == 0)
 405                 vir_TMUWT(c);
 406 }