2 * Copyright © 2016 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef V3D_COMPILER_H
25 #define V3D_COMPILER_H
34 #include "util/macros.h"
35 #include "common/v3d_debug.h"
36 #include "common/v3d_device_info.h"
37 #include "common/v3d_limits.h"
38 #include "compiler/nir/nir.h"
39 #include "util/list.h"
40 #include "util/u_math.h"
42 #include "qpu/qpu_instr.h"
43 #include "pipe/p_state.h"
47 struct v3d_fs_inputs
{
49 * Array of the meanings of the VPM inputs this shader needs.
51 * It doesn't include those that aren't part of the VPM, like
52 * point/line coordinates.
54 struct v3d_varying_slot
*input_slots
;
59 /** An unused source or destination register. */
62 /** A physical register, such as the W coordinate payload. */
64 /** One of the regsiters for fixed function interactions. */
68 * A virtual register, that will be allocated to actual accumulator
69 * or physical registers later.
74 * VPM reads use this with an index value to say what part of the VPM
80 * Stores an immediate value in the index field that will be used
81 * directly by qpu_load_imm().
86 * Stores an immediate value in the index field that can be turned
87 * into a small immediate field by qpu_encode_small_immediate().
93 * A reference to a QPU register or a virtual temp register.
100 static inline struct qreg
vir_reg(enum qfile file
, uint32_t index
)
102 return (struct qreg
){file
, index
};
105 static inline struct qreg
vir_magic_reg(uint32_t index
)
107 return (struct qreg
){QFILE_MAGIC
, index
};
110 static inline struct qreg
vir_nop_reg(void)
112 return (struct qreg
){QFILE_NULL
, 0};
116 * A reference to an actual register at the QPU level, for register
126 /** Entry in qblock->instructions */
127 struct list_head link
;
130 * The instruction being wrapped. Its condition codes, pack flags,
131 * signals, etc. will all be used, with just the register references
132 * being replaced by the contents of qinst->dst and qinst->src[].
134 struct v3d_qpu_instr qpu
;
136 /* Pre-register-allocation references to src/dst registers */
141 /* If the instruction reads a uniform (other than through src[i].file
142 * == QFILE_UNIF), that uniform's index in c->uniform_contents. ~0
148 enum quniform_contents
{
150 * Indicates that a constant 32-bit value is copied from the program's
155 * Indicates that the program's uniform contents are used as an index
156 * into the GL uniform storage.
161 * Scaling factors from clip coordinates to relative to the viewport
164 * This is used by the coordinate and vertex shaders to produce the
165 * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
166 * point offsets from the viewport ccenter.
168 QUNIFORM_VIEWPORT_X_SCALE
,
169 QUNIFORM_VIEWPORT_Y_SCALE
,
172 QUNIFORM_VIEWPORT_Z_OFFSET
,
173 QUNIFORM_VIEWPORT_Z_SCALE
,
175 QUNIFORM_USER_CLIP_PLANE
,
178 * A reference to a V3D 3.x texture config parameter 0 uniform.
180 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
181 * defines texture type, miplevels, and such. It will be found as a
182 * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
184 QUNIFORM_TEXTURE_CONFIG_P0_0
,
185 QUNIFORM_TEXTURE_CONFIG_P0_1
,
186 QUNIFORM_TEXTURE_CONFIG_P0_2
,
187 QUNIFORM_TEXTURE_CONFIG_P0_3
,
188 QUNIFORM_TEXTURE_CONFIG_P0_4
,
189 QUNIFORM_TEXTURE_CONFIG_P0_5
,
190 QUNIFORM_TEXTURE_CONFIG_P0_6
,
191 QUNIFORM_TEXTURE_CONFIG_P0_7
,
192 QUNIFORM_TEXTURE_CONFIG_P0_8
,
193 QUNIFORM_TEXTURE_CONFIG_P0_9
,
194 QUNIFORM_TEXTURE_CONFIG_P0_10
,
195 QUNIFORM_TEXTURE_CONFIG_P0_11
,
196 QUNIFORM_TEXTURE_CONFIG_P0_12
,
197 QUNIFORM_TEXTURE_CONFIG_P0_13
,
198 QUNIFORM_TEXTURE_CONFIG_P0_14
,
199 QUNIFORM_TEXTURE_CONFIG_P0_15
,
200 QUNIFORM_TEXTURE_CONFIG_P0_16
,
201 QUNIFORM_TEXTURE_CONFIG_P0_17
,
202 QUNIFORM_TEXTURE_CONFIG_P0_18
,
203 QUNIFORM_TEXTURE_CONFIG_P0_19
,
204 QUNIFORM_TEXTURE_CONFIG_P0_20
,
205 QUNIFORM_TEXTURE_CONFIG_P0_21
,
206 QUNIFORM_TEXTURE_CONFIG_P0_22
,
207 QUNIFORM_TEXTURE_CONFIG_P0_23
,
208 QUNIFORM_TEXTURE_CONFIG_P0_24
,
209 QUNIFORM_TEXTURE_CONFIG_P0_25
,
210 QUNIFORM_TEXTURE_CONFIG_P0_26
,
211 QUNIFORM_TEXTURE_CONFIG_P0_27
,
212 QUNIFORM_TEXTURE_CONFIG_P0_28
,
213 QUNIFORM_TEXTURE_CONFIG_P0_29
,
214 QUNIFORM_TEXTURE_CONFIG_P0_30
,
215 QUNIFORM_TEXTURE_CONFIG_P0_31
,
216 QUNIFORM_TEXTURE_CONFIG_P0_32
,
219 * A reference to a V3D 3.x texture config parameter 1 uniform.
221 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
222 * has the pointer to the indirect texture state. Our data[] field
223 * will have a packed p1 value, but the address field will be just
224 * which texture unit's texture should be referenced.
226 QUNIFORM_TEXTURE_CONFIG_P1
,
228 /* A V3D 4.x texture config parameter. The high 8 bits will be
229 * which texture or sampler is being sampled, and the driver must
230 * replace the address field with the appropriate address.
232 QUNIFORM_TMU_CONFIG_P0
,
233 QUNIFORM_TMU_CONFIG_P1
,
235 QUNIFORM_IMAGE_TMU_CONFIG_P0
,
237 QUNIFORM_TEXTURE_FIRST_LEVEL
,
239 QUNIFORM_TEXTURE_WIDTH
,
240 QUNIFORM_TEXTURE_HEIGHT
,
241 QUNIFORM_TEXTURE_DEPTH
,
242 QUNIFORM_TEXTURE_ARRAY_SIZE
,
243 QUNIFORM_TEXTURE_LEVELS
,
247 QUNIFORM_TEXRECT_SCALE_X
,
248 QUNIFORM_TEXRECT_SCALE_Y
,
250 /* Returns the base offset of the SSBO given by the data value. */
251 QUNIFORM_SSBO_OFFSET
,
253 /* Returns the size of the SSBO given by the data value. */
254 QUNIFORM_GET_BUFFER_SIZE
,
256 /* Sizes (in pixels) of a shader image given by the data value. */
257 QUNIFORM_IMAGE_WIDTH
,
258 QUNIFORM_IMAGE_HEIGHT
,
259 QUNIFORM_IMAGE_DEPTH
,
260 QUNIFORM_IMAGE_ARRAY_SIZE
,
266 /* The line width sent to hardware. This includes the expanded width
267 * when anti-aliasing is enabled.
269 QUNIFORM_AA_LINE_WIDTH
,
271 /* Number of workgroups passed to glDispatchCompute in the dimension
272 * selected by the data value.
274 QUNIFORM_NUM_WORK_GROUPS
,
277 * Returns the the offset of the scratch buffer for register spilling.
279 QUNIFORM_SPILL_OFFSET
,
280 QUNIFORM_SPILL_SIZE_PER_THREAD
,
283 * Returns the offset of the shared memory for compute shaders.
285 * This will be accessed using TMU general memory operations, so the
286 * L2T cache will effectively be the shared memory area.
288 QUNIFORM_SHARED_OFFSET
,
291 * Returns the number of layers in the framebuffer.
293 * This is used to cap gl_Layer in geometry shaders to avoid
294 * out-of-bounds accesses into the tile state during binning.
299 static inline uint32_t v3d_unit_data_create(uint32_t unit
, uint32_t value
)
301 assert(value
< (1 << 24));
302 return unit
<< 24 | value
;
305 static inline uint32_t v3d_unit_data_get_unit(uint32_t data
)
310 static inline uint32_t v3d_unit_data_get_offset(uint32_t data
)
312 return data
& 0xffffff;
315 struct v3d_varying_slot
{
316 uint8_t slot_and_component
;
319 static inline struct v3d_varying_slot
320 v3d_slot_from_slot_and_component(uint8_t slot
, uint8_t component
)
322 assert(slot
< 255 / 4);
323 return (struct v3d_varying_slot
){ (slot
<< 2) + component
};
326 static inline uint8_t v3d_slot_get_slot(struct v3d_varying_slot slot
)
328 return slot
.slot_and_component
>> 2;
331 static inline uint8_t v3d_slot_get_component(struct v3d_varying_slot slot
)
333 return slot
.slot_and_component
& 3;
341 uint8_t return_channels
;
345 } tex
[V3D_MAX_TEXTURE_SAMPLERS
];
347 bool is_last_geometry_stage
;
357 bool point_coord_upper_left
;
360 bool sample_coverage
;
361 bool sample_alpha_to_coverage
;
362 bool sample_alpha_to_one
;
364 bool shade_model_flat
;
365 /* Mask of which color render targets are present. */
367 uint8_t swap_color_rb
;
368 /* Mask of which render targets need to be written as 32-bit floats */
369 uint8_t f32_color_rb
;
370 /* Masks of which render targets need to be written as ints/uints.
371 * Used by gallium to work around lost information in TGSI.
373 uint8_t int_color_rb
;
374 uint8_t uint_color_rb
;
376 /* Color format information per render target. Only set when logic
377 * operations are enabled.
380 enum pipe_format format
;
381 const uint8_t *swizzle
;
382 } color_fmt
[V3D_MAX_DRAW_BUFFERS
];
384 uint8_t alpha_test_func
;
385 uint8_t logicop_func
;
386 uint32_t point_sprite_mask
;
388 struct pipe_rt_blend_state blend
;
394 struct v3d_varying_slot used_outputs
[V3D_MAX_FS_INPUTS
];
395 uint8_t num_used_outputs
;
398 bool per_vertex_point_size
;
404 struct v3d_varying_slot used_outputs
[V3D_MAX_ANY_STAGE_INPUTS
];
405 uint8_t num_used_outputs
;
408 bool per_vertex_point_size
;
412 /** A basic block of VIR intructions. */
414 struct list_head link
;
416 struct list_head instructions
;
418 struct set
*predecessors
;
419 struct qblock
*successors
[2];
423 /* Instruction IPs for the first and last instruction of the block.
424 * Set by qpu_schedule.c.
426 uint32_t start_qpu_ip
;
429 /* Instruction IP for the branch instruction of the block. Set by
432 uint32_t branch_qpu_ip
;
434 /** Offset within the uniform stream at the start of the block. */
435 uint32_t start_uniform
;
436 /** Offset within the uniform stream of the branch instruction */
437 uint32_t branch_uniform
;
439 /** @{ used by v3d_vir_live_variables.c */
444 BITSET_WORD
*live_in
;
445 BITSET_WORD
*live_out
;
446 int start_ip
, end_ip
;
450 /** Which util/list.h add mode we should use when inserting an instruction. */
451 enum vir_cursor_mode
{
457 * Tracking structure for where new instructions should be inserted. Create
458 * with one of the vir_after_inst()-style helper functions.
460 * This does not protect against removal of the block or instruction, so we
461 * have an assert in instruction removal to try to catch it.
464 enum vir_cursor_mode mode
;
465 struct list_head
*link
;
468 static inline struct vir_cursor
469 vir_before_inst(struct qinst
*inst
)
471 return (struct vir_cursor
){ vir_cursor_addtail
, &inst
->link
};
474 static inline struct vir_cursor
475 vir_after_inst(struct qinst
*inst
)
477 return (struct vir_cursor
){ vir_cursor_add
, &inst
->link
};
480 static inline struct vir_cursor
481 vir_before_block(struct qblock
*block
)
483 return (struct vir_cursor
){ vir_cursor_add
, &block
->instructions
};
486 static inline struct vir_cursor
487 vir_after_block(struct qblock
*block
)
489 return (struct vir_cursor
){ vir_cursor_addtail
, &block
->instructions
};
493 * Compiler state saved across compiler invocations, for any expensive global
496 struct v3d_compiler
{
497 const struct v3d_device_info
*devinfo
;
498 struct ra_regs
*regs
;
499 unsigned int reg_class_any
[3];
500 unsigned int reg_class_r5
[3];
501 unsigned int reg_class_phys
[3];
502 unsigned int reg_class_phys_or_acc
[3];
506 const struct v3d_device_info
*devinfo
;
508 nir_function_impl
*impl
;
509 struct exec_list
*cf_node_list
;
510 const struct v3d_compiler
*compiler
;
512 void (*debug_output
)(const char *msg
,
513 void *debug_output_data
);
514 void *debug_output_data
;
517 * Mapping from nir_register * or nir_ssa_def * to array of struct
518 * qreg for the values.
520 struct hash_table
*def_ht
;
522 /* For each temp, the instruction generating its value. */
524 uint32_t defs_array_size
;
527 * Inputs to the shader, arranged by TGSI declaration order.
529 * Not all fragment shader QFILE_VARY reads are present in this array.
532 struct qreg
*outputs
;
533 bool msaa_per_sample_output
;
534 struct qreg color_reads
[V3D_MAX_DRAW_BUFFERS
* V3D_MAX_SAMPLES
* 4];
535 struct qreg sample_colors
[V3D_MAX_DRAW_BUFFERS
* V3D_MAX_SAMPLES
* 4];
536 uint32_t inputs_array_size
;
537 uint32_t outputs_array_size
;
538 uint32_t uniforms_array_size
;
540 /* Booleans for whether the corresponding QFILE_VARY[i] is
541 * flat-shaded. This includes gl_FragColor flat-shading, which is
542 * customized based on the shademodel_flat shader key.
544 uint32_t flat_shade_flags
[BITSET_WORDS(V3D_MAX_FS_INPUTS
)];
546 uint32_t noperspective_flags
[BITSET_WORDS(V3D_MAX_FS_INPUTS
)];
548 uint32_t centroid_flags
[BITSET_WORDS(V3D_MAX_FS_INPUTS
)];
552 bool uses_implicit_point_line_varyings
;
554 /* State for whether we're executing on each channel currently. 0 if
555 * yes, otherwise a block number + 1 that the channel jumped to.
558 bool in_control_flow
;
560 struct qreg line_x
, point_x
, point_y
;
563 * Instance ID, which comes in before the vertex attribute payload if
564 * the shader record requests it.
569 * Vertex ID, which comes in before the vertex attribute payload
570 * (after Instance ID) if the shader record requests it.
574 /* Fragment shader payload regs. */
575 struct qreg payload_w
, payload_w_centroid
, payload_z
;
577 struct qreg cs_payload
[2];
578 struct qreg cs_shared_offset
;
579 int local_invocation_index_bits
;
581 uint8_t vattr_sizes
[V3D_MAX_VS_INPUTS
/ 4];
582 uint32_t vpm_output_size
;
584 /* Size in bytes of registers that have been spilled. This is how much
585 * space needs to be available in the spill BO per thread per QPU.
588 /* Shader-db stats */
589 uint32_t spills
, fills
, loops
;
591 * Register spilling's per-thread base address, shared between each
592 * spill/fill's addressing calculations.
594 struct qreg spill_base
;
595 /* Bit vector of which temps may be spilled */
596 BITSET_WORD
*spillable
;
599 * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
601 * This includes those that aren't part of the VPM varyings, like
602 * point/line coordinates.
604 struct v3d_varying_slot input_slots
[V3D_MAX_FS_INPUTS
];
607 * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
608 * of the output is. Used to emit from the VS in the order that the
611 struct v3d_varying_slot
*output_slots
;
613 struct pipe_shader_state
*shader_state
;
615 struct v3d_fs_key
*fs_key
;
616 struct v3d_gs_key
*gs_key
;
617 struct v3d_vs_key
*vs_key
;
619 /* Live ranges of temps. */
620 int *temp_start
, *temp_end
;
621 bool live_intervals_valid
;
623 uint32_t *uniform_data
;
624 enum quniform_contents
*uniform_contents
;
625 uint32_t uniform_array_size
;
626 uint32_t num_uniforms
;
627 uint32_t output_position_index
;
628 nir_variable
*output_color_var
[4];
629 uint32_t output_sample_mask_index
;
634 struct vir_cursor cursor
;
635 struct list_head blocks
;
636 int next_block_index
;
637 struct qblock
*cur_block
;
638 struct qblock
*loop_cont_block
;
639 struct qblock
*loop_break_block
;
642 uint32_t qpu_inst_count
;
643 uint32_t qpu_inst_size
;
644 uint32_t qpu_inst_stalled_count
;
646 /* For the FS, the number of varying inputs not counting the
647 * point/line varyings payload
654 /* Set to compile program in in 1x, 2x, or 4x threaded mode, where
655 * SIG_THREAD_SWITCH is used to hide texturing latency at the cost of
656 * limiting ourselves to the part of the physical reg space.
658 * On V3D 3.x, 2x or 4x divide the physical reg space by 2x or 4x. On
659 * V3D 4.x, all shaders are 2x threaded, and 4x only divides the
660 * physical reg space in half.
663 struct qinst
*last_thrsw
;
664 bool last_thrsw_at_top_level
;
666 bool emitted_tlb_load
;
667 bool lock_scoreboard_on_first_thrsw
;
674 struct v3d_uniform_list
{
675 enum quniform_contents
*contents
;
680 struct v3d_prog_data
{
681 struct v3d_uniform_list uniforms
;
687 /* For threads > 1, whether the program should be dispatched in the
688 * after-final-THRSW state.
695 struct v3d_vs_prog_data
{
696 struct v3d_prog_data base
;
698 bool uses_iid
, uses_vid
;
700 /* Number of components read from each vertex attribute. */
701 uint8_t vattr_sizes
[V3D_MAX_VS_INPUTS
/ 4];
703 /* Total number of components read, for the shader state record. */
704 uint32_t vpm_input_size
;
706 /* Total number of components written, for the shader state record. */
707 uint32_t vpm_output_size
;
709 /* Set if there should be separate VPM segments for input and output.
710 * If unset, vpm_input_size will be 0.
712 bool separate_segments
;
714 /* Value to be programmed in VCM_CACHE_SIZE. */
715 uint8_t vcm_cache_size
;
718 struct v3d_gs_prog_data
{
719 struct v3d_prog_data base
;
721 /* Whether the program reads gl_PrimitiveIDIn */
724 /* Number of components read from each input varying. */
725 uint8_t input_sizes
[V3D_MAX_GS_INPUTS
/ 4];
727 /* Number of inputs */
729 struct v3d_varying_slot input_slots
[V3D_MAX_GS_INPUTS
];
731 /* Total number of components written, for the shader state record. */
732 uint32_t vpm_output_size
;
734 /* Maximum SIMD dispatch width to not exceed VPM output size limits
735 * in the geometry shader. Notice that the final dispatch width has to
736 * be decided at draw time and could be lower based on the VPM pressure
737 * added by other shader stages.
741 /* Output primitive type */
742 uint8_t out_prim_type
;
744 /* Number of GS invocations */
745 uint8_t num_invocations
;
748 struct v3d_fs_prog_data
{
749 struct v3d_prog_data base
;
751 struct v3d_varying_slot input_slots
[V3D_MAX_FS_INPUTS
];
753 /* Array of flat shade flags.
755 * Each entry is only 24 bits (high 8 bits 0), to match the hardware
758 uint32_t flat_shade_flags
[((V3D_MAX_FS_INPUTS
- 1) / 24) + 1];
760 uint32_t noperspective_flags
[((V3D_MAX_FS_INPUTS
- 1) / 24) + 1];
762 uint32_t centroid_flags
[((V3D_MAX_FS_INPUTS
- 1) / 24) + 1];
768 bool uses_implicit_point_line_varyings
;
769 bool lock_scoreboard_on_first_thrsw
;
772 struct v3d_compute_prog_data
{
773 struct v3d_prog_data base
;
774 /* Size in bytes of the workgroup's shared space. */
775 uint32_t shared_size
;
779 vir_has_uniform(struct qinst
*inst
)
781 return inst
->uniform
!= ~0;
784 extern const nir_shader_compiler_options v3d_nir_options
;
786 const struct v3d_compiler
*v3d_compiler_init(const struct v3d_device_info
*devinfo
);
787 void v3d_compiler_free(const struct v3d_compiler
*compiler
);
788 void v3d_optimize_nir(struct nir_shader
*s
);
790 uint64_t *v3d_compile(const struct v3d_compiler
*compiler
,
792 struct v3d_prog_data
**prog_data
,
794 void (*debug_output
)(const char *msg
,
795 void *debug_output_data
),
796 void *debug_output_data
,
797 int program_id
, int variant_id
,
798 uint32_t *final_assembly_size
);
800 void v3d_nir_to_vir(struct v3d_compile
*c
);
802 void vir_compile_destroy(struct v3d_compile
*c
);
803 const char *vir_get_stage_name(struct v3d_compile
*c
);
804 struct qblock
*vir_new_block(struct v3d_compile
*c
);
805 void vir_set_emit_block(struct v3d_compile
*c
, struct qblock
*block
);
806 void vir_link_blocks(struct qblock
*predecessor
, struct qblock
*successor
);
807 struct qblock
*vir_entry_block(struct v3d_compile
*c
);
808 struct qblock
*vir_exit_block(struct v3d_compile
*c
);
809 struct qinst
*vir_add_inst(enum v3d_qpu_add_op op
, struct qreg dst
,
810 struct qreg src0
, struct qreg src1
);
811 struct qinst
*vir_mul_inst(enum v3d_qpu_mul_op op
, struct qreg dst
,
812 struct qreg src0
, struct qreg src1
);
813 struct qinst
*vir_branch_inst(struct v3d_compile
*c
,
814 enum v3d_qpu_branch_cond cond
);
815 void vir_remove_instruction(struct v3d_compile
*c
, struct qinst
*qinst
);
816 uint32_t vir_get_uniform_index(struct v3d_compile
*c
,
817 enum quniform_contents contents
,
819 struct qreg
vir_uniform(struct v3d_compile
*c
,
820 enum quniform_contents contents
,
822 void vir_schedule_instructions(struct v3d_compile
*c
);
823 void v3d_setup_spill_base(struct v3d_compile
*c
);
824 struct v3d_qpu_instr
v3d_qpu_nop(void);
826 struct qreg
vir_emit_def(struct v3d_compile
*c
, struct qinst
*inst
);
827 struct qinst
*vir_emit_nondef(struct v3d_compile
*c
, struct qinst
*inst
);
828 void vir_set_cond(struct qinst
*inst
, enum v3d_qpu_cond cond
);
829 void vir_set_pf(struct qinst
*inst
, enum v3d_qpu_pf pf
);
830 void vir_set_uf(struct qinst
*inst
, enum v3d_qpu_uf uf
);
831 void vir_set_unpack(struct qinst
*inst
, int src
,
832 enum v3d_qpu_input_unpack unpack
);
834 struct qreg
vir_get_temp(struct v3d_compile
*c
);
835 void vir_emit_last_thrsw(struct v3d_compile
*c
);
836 void vir_calculate_live_intervals(struct v3d_compile
*c
);
837 int vir_get_nsrc(struct qinst
*inst
);
838 bool vir_has_side_effects(struct v3d_compile
*c
, struct qinst
*inst
);
839 bool vir_get_add_op(struct qinst
*inst
, enum v3d_qpu_add_op
*op
);
840 bool vir_get_mul_op(struct qinst
*inst
, enum v3d_qpu_mul_op
*op
);
841 bool vir_is_raw_mov(struct qinst
*inst
);
842 bool vir_is_tex(struct qinst
*inst
);
843 bool vir_is_add(struct qinst
*inst
);
844 bool vir_is_mul(struct qinst
*inst
);
845 bool vir_writes_r3(const struct v3d_device_info
*devinfo
, struct qinst
*inst
);
846 bool vir_writes_r4(const struct v3d_device_info
*devinfo
, struct qinst
*inst
);
847 struct qreg
vir_follow_movs(struct v3d_compile
*c
, struct qreg reg
);
848 uint8_t vir_channels_written(struct qinst
*inst
);
849 struct qreg
ntq_get_src(struct v3d_compile
*c
, nir_src src
, int i
);
850 void ntq_store_dest(struct v3d_compile
*c
, nir_dest
*dest
, int chan
,
852 void vir_emit_thrsw(struct v3d_compile
*c
);
854 void vir_dump(struct v3d_compile
*c
);
855 void vir_dump_inst(struct v3d_compile
*c
, struct qinst
*inst
);
856 void vir_dump_uniform(enum quniform_contents contents
, uint32_t data
);
858 void vir_validate(struct v3d_compile
*c
);
860 void vir_optimize(struct v3d_compile
*c
);
861 bool vir_opt_algebraic(struct v3d_compile
*c
);
862 bool vir_opt_constant_folding(struct v3d_compile
*c
);
863 bool vir_opt_copy_propagate(struct v3d_compile
*c
);
864 bool vir_opt_dead_code(struct v3d_compile
*c
);
865 bool vir_opt_peephole_sf(struct v3d_compile
*c
);
866 bool vir_opt_redundant_flags(struct v3d_compile
*c
);
867 bool vir_opt_small_immediates(struct v3d_compile
*c
);
868 bool vir_opt_vpm(struct v3d_compile
*c
);
869 void v3d_nir_lower_blend(nir_shader
*s
, struct v3d_compile
*c
);
870 void v3d_nir_lower_io(nir_shader
*s
, struct v3d_compile
*c
);
871 void v3d_nir_lower_line_smooth(nir_shader
*shader
);
872 void v3d_nir_lower_logic_ops(nir_shader
*s
, struct v3d_compile
*c
);
873 void v3d_nir_lower_scratch(nir_shader
*s
);
874 void v3d_nir_lower_txf_ms(nir_shader
*s
, struct v3d_compile
*c
);
875 void v3d_nir_lower_image_load_store(nir_shader
*s
);
876 void vir_lower_uniforms(struct v3d_compile
*c
);
878 void v3d33_vir_vpm_read_setup(struct v3d_compile
*c
, int num_components
);
879 void v3d33_vir_vpm_write_setup(struct v3d_compile
*c
);
880 void v3d33_vir_emit_tex(struct v3d_compile
*c
, nir_tex_instr
*instr
);
881 void v3d40_vir_emit_tex(struct v3d_compile
*c
, nir_tex_instr
*instr
);
882 void v3d40_vir_emit_image_load_store(struct v3d_compile
*c
,
883 nir_intrinsic_instr
*instr
);
885 void v3d_vir_to_qpu(struct v3d_compile
*c
, struct qpu_reg
*temp_registers
);
886 uint32_t v3d_qpu_schedule_instructions(struct v3d_compile
*c
);
887 void qpu_validate(struct v3d_compile
*c
);
888 struct qpu_reg
*v3d_register_allocate(struct v3d_compile
*c
, bool *spilled
);
889 bool vir_init_reg_sets(struct v3d_compiler
*compiler
);
891 bool v3d_gl_format_is_return_32(GLenum format
);
894 v3d_get_op_for_atomic_add(nir_intrinsic_instr
*instr
, unsigned src
);
897 quniform_contents_is_texture_p0(enum quniform_contents contents
)
899 return (contents
>= QUNIFORM_TEXTURE_CONFIG_P0_0
&&
900 contents
< (QUNIFORM_TEXTURE_CONFIG_P0_0
+
901 V3D_MAX_TEXTURE_SAMPLERS
));
905 vir_in_nonuniform_control_flow(struct v3d_compile
*c
)
907 return c
->execute
.file
!= QFILE_NULL
;
910 static inline struct qreg
911 vir_uniform_ui(struct v3d_compile
*c
, uint32_t ui
)
913 return vir_uniform(c
, QUNIFORM_CONSTANT
, ui
);
916 static inline struct qreg
917 vir_uniform_f(struct v3d_compile
*c
, float f
)
919 return vir_uniform(c
, QUNIFORM_CONSTANT
, fui(f
));
922 #define VIR_ALU0(name, vir_inst, op) \
923 static inline struct qreg \
924 vir_##name(struct v3d_compile *c) \
926 return vir_emit_def(c, vir_inst(op, c->undef, \
927 c->undef, c->undef)); \
929 static inline struct qinst * \
930 vir_##name##_dest(struct v3d_compile *c, struct qreg dest) \
932 return vir_emit_nondef(c, vir_inst(op, dest, \
933 c->undef, c->undef)); \
936 #define VIR_ALU1(name, vir_inst, op) \
937 static inline struct qreg \
938 vir_##name(struct v3d_compile *c, struct qreg a) \
940 return vir_emit_def(c, vir_inst(op, c->undef, \
943 static inline struct qinst * \
944 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
947 return vir_emit_nondef(c, vir_inst(op, dest, a, \
951 #define VIR_ALU2(name, vir_inst, op) \
952 static inline struct qreg \
953 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b) \
955 return vir_emit_def(c, vir_inst(op, c->undef, a, b)); \
957 static inline struct qinst * \
958 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
959 struct qreg a, struct qreg b) \
961 return vir_emit_nondef(c, vir_inst(op, dest, a, b)); \
964 #define VIR_NODST_0(name, vir_inst, op) \
965 static inline struct qinst * \
966 vir_##name(struct v3d_compile *c) \
968 return vir_emit_nondef(c, vir_inst(op, c->undef, \
969 c->undef, c->undef)); \
972 #define VIR_NODST_1(name, vir_inst, op) \
973 static inline struct qinst * \
974 vir_##name(struct v3d_compile *c, struct qreg a) \
976 return vir_emit_nondef(c, vir_inst(op, c->undef, \
980 #define VIR_NODST_2(name, vir_inst, op) \
981 static inline struct qinst * \
982 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b) \
984 return vir_emit_nondef(c, vir_inst(op, c->undef, \
988 #define VIR_SFU(name) \
989 static inline struct qreg \
990 vir_##name(struct v3d_compile *c, struct qreg a) \
992 if (c->devinfo->ver >= 41) { \
993 return vir_emit_def(c, vir_add_inst(V3D_QPU_A_##name, \
997 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_##name), a); \
998 return vir_FMOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4)); \
1001 static inline struct qinst * \
1002 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
1005 if (c->devinfo->ver >= 41) { \
1006 return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_##name, \
1010 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_##name), a); \
1011 return vir_FMOV_dest(c, dest, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4)); \
1015 #define VIR_A_ALU2(name) VIR_ALU2(name, vir_add_inst, V3D_QPU_A_##name)
1016 #define VIR_M_ALU2(name) VIR_ALU2(name, vir_mul_inst, V3D_QPU_M_##name)
1017 #define VIR_A_ALU1(name) VIR_ALU1(name, vir_add_inst, V3D_QPU_A_##name)
1018 #define VIR_M_ALU1(name) VIR_ALU1(name, vir_mul_inst, V3D_QPU_M_##name)
1019 #define VIR_A_ALU0(name) VIR_ALU0(name, vir_add_inst, V3D_QPU_A_##name)
1020 #define VIR_M_ALU0(name) VIR_ALU0(name, vir_mul_inst, V3D_QPU_M_##name)
1021 #define VIR_A_NODST_2(name) VIR_NODST_2(name, vir_add_inst, V3D_QPU_A_##name)
1022 #define VIR_M_NODST_2(name) VIR_NODST_2(name, vir_mul_inst, V3D_QPU_M_##name)
1023 #define VIR_A_NODST_1(name) VIR_NODST_1(name, vir_add_inst, V3D_QPU_A_##name)
1024 #define VIR_M_NODST_1(name) VIR_NODST_1(name, vir_mul_inst, V3D_QPU_M_##name)
1025 #define VIR_A_NODST_0(name) VIR_NODST_0(name, vir_add_inst, V3D_QPU_A_##name)
1048 VIR_A_NODST_2(STVPMV
)
1049 VIR_A_NODST_2(STVPMD
)
1059 VIR_A_ALU1(LDVPMV_IN
)
1060 VIR_A_ALU1(LDVPMV_OUT
)
1061 VIR_A_ALU1(LDVPMD_IN
)
1062 VIR_A_ALU1(LDVPMD_OUT
)
1063 VIR_A_ALU2(LDVPMG_IN
)
1064 VIR_A_ALU2(LDVPMG_OUT
)
1074 VIR_A_ALU0(BARRIERID
)
1075 VIR_A_NODST_1(VPMSETUP
)
1076 VIR_A_NODST_0(VPMWT
)
1099 VIR_M_NODST_2(MULTOP
)
1111 static inline struct qinst
*
1112 vir_MOV_cond(struct v3d_compile
*c
, enum v3d_qpu_cond cond
,
1113 struct qreg dest
, struct qreg src
)
1115 struct qinst
*mov
= vir_MOV_dest(c
, dest
, src
);
1116 vir_set_cond(mov
, cond
);
1120 static inline struct qreg
1121 vir_SEL(struct v3d_compile
*c
, enum v3d_qpu_cond cond
,
1122 struct qreg src0
, struct qreg src1
)
1124 struct qreg t
= vir_get_temp(c
);
1125 vir_MOV_dest(c
, t
, src1
);
1126 vir_MOV_cond(c
, cond
, t
, src0
);
1130 static inline struct qinst
*
1131 vir_NOP(struct v3d_compile
*c
)
1133 return vir_emit_nondef(c
, vir_add_inst(V3D_QPU_A_NOP
,
1134 c
->undef
, c
->undef
, c
->undef
));
1137 static inline struct qreg
1138 vir_LDTMU(struct v3d_compile
*c
)
1140 if (c
->devinfo
->ver
>= 41) {
1141 struct qinst
*ldtmu
= vir_add_inst(V3D_QPU_A_NOP
, c
->undef
,
1142 c
->undef
, c
->undef
);
1143 ldtmu
->qpu
.sig
.ldtmu
= true;
1145 return vir_emit_def(c
, ldtmu
);
1147 vir_NOP(c
)->qpu
.sig
.ldtmu
= true;
1148 return vir_MOV(c
, vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_R4
));
1152 static inline struct qreg
1153 vir_UMUL(struct v3d_compile
*c
, struct qreg src0
, struct qreg src1
)
1155 vir_MULTOP(c
, src0
, src1
);
1156 return vir_UMUL24(c
, src0
, src1
);
1159 static inline struct qreg
1160 vir_TLBU_COLOR_READ(struct v3d_compile
*c
, uint32_t config
)
1162 assert(c
->devinfo
->ver
>= 41); /* XXX */
1163 assert((config
& 0xffffff00) == 0xffffff00);
1165 struct qinst
*ldtlb
= vir_add_inst(V3D_QPU_A_NOP
, c
->undef
,
1166 c
->undef
, c
->undef
);
1167 ldtlb
->qpu
.sig
.ldtlbu
= true;
1168 ldtlb
->uniform
= vir_get_uniform_index(c
, QUNIFORM_CONSTANT
, config
);
1169 return vir_emit_def(c
, ldtlb
);
1172 static inline struct qreg
1173 vir_TLB_COLOR_READ(struct v3d_compile
*c
)
1175 assert(c
->devinfo
->ver
>= 41); /* XXX */
1177 struct qinst
*ldtlb
= vir_add_inst(V3D_QPU_A_NOP
, c
->undef
,
1178 c
->undef
, c
->undef
);
1179 ldtlb
->qpu
.sig
.ldtlb
= true;
1180 return vir_emit_def(c
, ldtlb
);
1184 static inline struct qreg
1185 vir_LOAD_IMM(struct v3d_compile *c, uint32_t val)
1187 return vir_emit_def(c, vir_inst(QOP_LOAD_IMM, c->undef,
1188 vir_reg(QFILE_LOAD_IMM, val), c->undef));
1191 static inline struct qreg
1192 vir_LOAD_IMM_U2(struct v3d_compile *c, uint32_t val)
1194 return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_U2, c->undef,
1195 vir_reg(QFILE_LOAD_IMM, val),
1198 static inline struct qreg
1199 vir_LOAD_IMM_I2(struct v3d_compile *c, uint32_t val)
1201 return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_I2, c->undef,
1202 vir_reg(QFILE_LOAD_IMM, val),
1207 static inline struct qinst
*
1208 vir_BRANCH(struct v3d_compile
*c
, enum v3d_qpu_branch_cond cond
)
1210 /* The actual uniform_data value will be set at scheduling time */
1211 return vir_emit_nondef(c
, vir_branch_inst(c
, cond
));
1214 #define vir_for_each_block(block, c) \
1215 list_for_each_entry(struct qblock, block, &c->blocks, link)
1217 #define vir_for_each_block_rev(block, c) \
1218 list_for_each_entry_rev(struct qblock, block, &c->blocks, link)
1220 /* Loop over the non-NULL members of the successors array. */
1221 #define vir_for_each_successor(succ, block) \
1222 for (struct qblock *succ = block->successors[0]; \
1224 succ = (succ == block->successors[1] ? NULL : \
1225 block->successors[1]))
1227 #define vir_for_each_inst(inst, block) \
1228 list_for_each_entry(struct qinst, inst, &block->instructions, link)
1230 #define vir_for_each_inst_rev(inst, block) \
1231 list_for_each_entry_rev(struct qinst, inst, &block->instructions, link)
1233 #define vir_for_each_inst_safe(inst, block) \
1234 list_for_each_entry_safe(struct qinst, inst, &block->instructions, link)
1236 #define vir_for_each_inst_inorder(inst, c) \
1237 vir_for_each_block(_block, c) \
1238 vir_for_each_inst(inst, _block)
1240 #define vir_for_each_inst_inorder_safe(inst, c) \
1241 vir_for_each_block(_block, c) \
1242 vir_for_each_inst_safe(inst, _block)
1244 #endif /* V3D_COMPILER_H */