v3d: add missing plumbing for VPM load instructions
[mesa.git] / src / broadcom / compiler / v3d_compiler.h
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef V3D_COMPILER_H
25 #define V3D_COMPILER_H
26
27 #include <assert.h>
28 #include <stdio.h>
29 #include <stdlib.h>
30 #include <stdbool.h>
31 #include <stdint.h>
32 #include <string.h>
33
34 #include "util/macros.h"
35 #include "common/v3d_debug.h"
36 #include "common/v3d_device_info.h"
37 #include "common/v3d_limits.h"
38 #include "compiler/nir/nir.h"
39 #include "util/list.h"
40 #include "util/u_math.h"
41
42 #include "qpu/qpu_instr.h"
43 #include "pipe/p_state.h"
44
45 struct nir_builder;
46
47 struct v3d_fs_inputs {
48 /**
49 * Array of the meanings of the VPM inputs this shader needs.
50 *
51 * It doesn't include those that aren't part of the VPM, like
52 * point/line coordinates.
53 */
54 struct v3d_varying_slot *input_slots;
55 uint32_t num_inputs;
56 };
57
58 enum qfile {
59 /** An unused source or destination register. */
60 QFILE_NULL,
61
62 /** A physical register, such as the W coordinate payload. */
63 QFILE_REG,
64 /** One of the regsiters for fixed function interactions. */
65 QFILE_MAGIC,
66
67 /**
68 * A virtual register, that will be allocated to actual accumulator
69 * or physical registers later.
70 */
71 QFILE_TEMP,
72
73 /**
74 * VPM reads use this with an index value to say what part of the VPM
75 * is being read.
76 */
77 QFILE_VPM,
78
79 /**
80 * Stores an immediate value in the index field that will be used
81 * directly by qpu_load_imm().
82 */
83 QFILE_LOAD_IMM,
84
85 /**
86 * Stores an immediate value in the index field that can be turned
87 * into a small immediate field by qpu_encode_small_immediate().
88 */
89 QFILE_SMALL_IMM,
90 };
91
92 /**
93 * A reference to a QPU register or a virtual temp register.
94 */
95 struct qreg {
96 enum qfile file;
97 uint32_t index;
98 };
99
100 static inline struct qreg vir_reg(enum qfile file, uint32_t index)
101 {
102 return (struct qreg){file, index};
103 }
104
105 static inline struct qreg vir_magic_reg(uint32_t index)
106 {
107 return (struct qreg){QFILE_MAGIC, index};
108 }
109
110 static inline struct qreg vir_nop_reg(void)
111 {
112 return (struct qreg){QFILE_NULL, 0};
113 }
114
115 /**
116 * A reference to an actual register at the QPU level, for register
117 * allocation.
118 */
119 struct qpu_reg {
120 bool magic;
121 bool smimm;
122 int index;
123 };
124
125 struct qinst {
126 /** Entry in qblock->instructions */
127 struct list_head link;
128
129 /**
130 * The instruction being wrapped. Its condition codes, pack flags,
131 * signals, etc. will all be used, with just the register references
132 * being replaced by the contents of qinst->dst and qinst->src[].
133 */
134 struct v3d_qpu_instr qpu;
135
136 /* Pre-register-allocation references to src/dst registers */
137 struct qreg dst;
138 struct qreg src[3];
139 bool is_last_thrsw;
140
141 /* If the instruction reads a uniform (other than through src[i].file
142 * == QFILE_UNIF), that uniform's index in c->uniform_contents. ~0
143 * otherwise.
144 */
145 int uniform;
146 };
147
148 enum quniform_contents {
149 /**
150 * Indicates that a constant 32-bit value is copied from the program's
151 * uniform contents.
152 */
153 QUNIFORM_CONSTANT,
154 /**
155 * Indicates that the program's uniform contents are used as an index
156 * into the GL uniform storage.
157 */
158 QUNIFORM_UNIFORM,
159
160 /** @{
161 * Scaling factors from clip coordinates to relative to the viewport
162 * center.
163 *
164 * This is used by the coordinate and vertex shaders to produce the
165 * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
166 * point offsets from the viewport ccenter.
167 */
168 QUNIFORM_VIEWPORT_X_SCALE,
169 QUNIFORM_VIEWPORT_Y_SCALE,
170 /** @} */
171
172 QUNIFORM_VIEWPORT_Z_OFFSET,
173 QUNIFORM_VIEWPORT_Z_SCALE,
174
175 QUNIFORM_USER_CLIP_PLANE,
176
177 /**
178 * A reference to a V3D 3.x texture config parameter 0 uniform.
179 *
180 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
181 * defines texture type, miplevels, and such. It will be found as a
182 * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
183 */
184 QUNIFORM_TEXTURE_CONFIG_P0_0,
185 QUNIFORM_TEXTURE_CONFIG_P0_1,
186 QUNIFORM_TEXTURE_CONFIG_P0_2,
187 QUNIFORM_TEXTURE_CONFIG_P0_3,
188 QUNIFORM_TEXTURE_CONFIG_P0_4,
189 QUNIFORM_TEXTURE_CONFIG_P0_5,
190 QUNIFORM_TEXTURE_CONFIG_P0_6,
191 QUNIFORM_TEXTURE_CONFIG_P0_7,
192 QUNIFORM_TEXTURE_CONFIG_P0_8,
193 QUNIFORM_TEXTURE_CONFIG_P0_9,
194 QUNIFORM_TEXTURE_CONFIG_P0_10,
195 QUNIFORM_TEXTURE_CONFIG_P0_11,
196 QUNIFORM_TEXTURE_CONFIG_P0_12,
197 QUNIFORM_TEXTURE_CONFIG_P0_13,
198 QUNIFORM_TEXTURE_CONFIG_P0_14,
199 QUNIFORM_TEXTURE_CONFIG_P0_15,
200 QUNIFORM_TEXTURE_CONFIG_P0_16,
201 QUNIFORM_TEXTURE_CONFIG_P0_17,
202 QUNIFORM_TEXTURE_CONFIG_P0_18,
203 QUNIFORM_TEXTURE_CONFIG_P0_19,
204 QUNIFORM_TEXTURE_CONFIG_P0_20,
205 QUNIFORM_TEXTURE_CONFIG_P0_21,
206 QUNIFORM_TEXTURE_CONFIG_P0_22,
207 QUNIFORM_TEXTURE_CONFIG_P0_23,
208 QUNIFORM_TEXTURE_CONFIG_P0_24,
209 QUNIFORM_TEXTURE_CONFIG_P0_25,
210 QUNIFORM_TEXTURE_CONFIG_P0_26,
211 QUNIFORM_TEXTURE_CONFIG_P0_27,
212 QUNIFORM_TEXTURE_CONFIG_P0_28,
213 QUNIFORM_TEXTURE_CONFIG_P0_29,
214 QUNIFORM_TEXTURE_CONFIG_P0_30,
215 QUNIFORM_TEXTURE_CONFIG_P0_31,
216 QUNIFORM_TEXTURE_CONFIG_P0_32,
217
218 /**
219 * A reference to a V3D 3.x texture config parameter 1 uniform.
220 *
221 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
222 * has the pointer to the indirect texture state. Our data[] field
223 * will have a packed p1 value, but the address field will be just
224 * which texture unit's texture should be referenced.
225 */
226 QUNIFORM_TEXTURE_CONFIG_P1,
227
228 /* A V3D 4.x texture config parameter. The high 8 bits will be
229 * which texture or sampler is being sampled, and the driver must
230 * replace the address field with the appropriate address.
231 */
232 QUNIFORM_TMU_CONFIG_P0,
233 QUNIFORM_TMU_CONFIG_P1,
234
235 QUNIFORM_IMAGE_TMU_CONFIG_P0,
236
237 QUNIFORM_TEXTURE_FIRST_LEVEL,
238
239 QUNIFORM_TEXTURE_WIDTH,
240 QUNIFORM_TEXTURE_HEIGHT,
241 QUNIFORM_TEXTURE_DEPTH,
242 QUNIFORM_TEXTURE_ARRAY_SIZE,
243 QUNIFORM_TEXTURE_LEVELS,
244
245 QUNIFORM_UBO_ADDR,
246
247 QUNIFORM_TEXRECT_SCALE_X,
248 QUNIFORM_TEXRECT_SCALE_Y,
249
250 /* Returns the base offset of the SSBO given by the data value. */
251 QUNIFORM_SSBO_OFFSET,
252
253 /* Returns the size of the SSBO given by the data value. */
254 QUNIFORM_GET_BUFFER_SIZE,
255
256 /* Sizes (in pixels) of a shader image given by the data value. */
257 QUNIFORM_IMAGE_WIDTH,
258 QUNIFORM_IMAGE_HEIGHT,
259 QUNIFORM_IMAGE_DEPTH,
260 QUNIFORM_IMAGE_ARRAY_SIZE,
261
262 QUNIFORM_ALPHA_REF,
263
264 /* Number of workgroups passed to glDispatchCompute in the dimension
265 * selected by the data value.
266 */
267 QUNIFORM_NUM_WORK_GROUPS,
268
269 /**
270 * Returns the the offset of the scratch buffer for register spilling.
271 */
272 QUNIFORM_SPILL_OFFSET,
273 QUNIFORM_SPILL_SIZE_PER_THREAD,
274
275 /**
276 * Returns the offset of the shared memory for compute shaders.
277 *
278 * This will be accessed using TMU general memory operations, so the
279 * L2T cache will effectively be the shared memory area.
280 */
281 QUNIFORM_SHARED_OFFSET,
282 };
283
284 static inline uint32_t v3d_unit_data_create(uint32_t unit, uint32_t value)
285 {
286 assert(value < (1 << 24));
287 return unit << 24 | value;
288 }
289
290 static inline uint32_t v3d_unit_data_get_unit(uint32_t data)
291 {
292 return data >> 24;
293 }
294
295 static inline uint32_t v3d_unit_data_get_offset(uint32_t data)
296 {
297 return data & 0xffffff;
298 }
299
300 struct v3d_varying_slot {
301 uint8_t slot_and_component;
302 };
303
304 static inline struct v3d_varying_slot
305 v3d_slot_from_slot_and_component(uint8_t slot, uint8_t component)
306 {
307 assert(slot < 255 / 4);
308 return (struct v3d_varying_slot){ (slot << 2) + component };
309 }
310
311 static inline uint8_t v3d_slot_get_slot(struct v3d_varying_slot slot)
312 {
313 return slot.slot_and_component >> 2;
314 }
315
316 static inline uint8_t v3d_slot_get_component(struct v3d_varying_slot slot)
317 {
318 return slot.slot_and_component & 3;
319 }
320
321 struct v3d_key {
322 void *shader_state;
323 struct {
324 uint8_t swizzle[4];
325 uint8_t return_size;
326 uint8_t return_channels;
327 bool clamp_s:1;
328 bool clamp_t:1;
329 bool clamp_r:1;
330 } tex[V3D_MAX_TEXTURE_SAMPLERS];
331 uint8_t ucp_enables;
332 };
333
334 struct v3d_fs_key {
335 struct v3d_key base;
336 bool depth_enabled;
337 bool is_points;
338 bool is_lines;
339 bool alpha_test;
340 bool point_coord_upper_left;
341 bool light_twoside;
342 bool msaa;
343 bool sample_coverage;
344 bool sample_alpha_to_coverage;
345 bool sample_alpha_to_one;
346 bool clamp_color;
347 bool shade_model_flat;
348 /* Mask of which color render targets are present. */
349 uint8_t cbufs;
350 uint8_t swap_color_rb;
351 /* Mask of which render targets need to be written as 32-bit floats */
352 uint8_t f32_color_rb;
353 /* Masks of which render targets need to be written as ints/uints.
354 * Used by gallium to work around lost information in TGSI.
355 */
356 uint8_t int_color_rb;
357 uint8_t uint_color_rb;
358
359 /* Color format information per render target. Only set when logic
360 * operations are enabled.
361 */
362 struct {
363 enum pipe_format format;
364 const uint8_t *swizzle;
365 } color_fmt[V3D_MAX_DRAW_BUFFERS];
366
367 uint8_t alpha_test_func;
368 uint8_t logicop_func;
369 uint32_t point_sprite_mask;
370
371 struct pipe_rt_blend_state blend;
372 };
373
374 struct v3d_vs_key {
375 struct v3d_key base;
376
377 struct v3d_varying_slot used_outputs[V3D_MAX_ANY_STAGE_INPUTS];
378 uint8_t num_used_outputs;
379
380 bool is_coord;
381 bool per_vertex_point_size;
382 bool clamp_color;
383 };
384
385 /** A basic block of VIR intructions. */
386 struct qblock {
387 struct list_head link;
388
389 struct list_head instructions;
390
391 struct set *predecessors;
392 struct qblock *successors[2];
393
394 int index;
395
396 /* Instruction IPs for the first and last instruction of the block.
397 * Set by qpu_schedule.c.
398 */
399 uint32_t start_qpu_ip;
400 uint32_t end_qpu_ip;
401
402 /* Instruction IP for the branch instruction of the block. Set by
403 * qpu_schedule.c.
404 */
405 uint32_t branch_qpu_ip;
406
407 /** Offset within the uniform stream at the start of the block. */
408 uint32_t start_uniform;
409 /** Offset within the uniform stream of the branch instruction */
410 uint32_t branch_uniform;
411
412 /** @{ used by v3d_vir_live_variables.c */
413 BITSET_WORD *def;
414 BITSET_WORD *defin;
415 BITSET_WORD *defout;
416 BITSET_WORD *use;
417 BITSET_WORD *live_in;
418 BITSET_WORD *live_out;
419 int start_ip, end_ip;
420 /** @} */
421 };
422
423 /** Which util/list.h add mode we should use when inserting an instruction. */
424 enum vir_cursor_mode {
425 vir_cursor_add,
426 vir_cursor_addtail,
427 };
428
429 /**
430 * Tracking structure for where new instructions should be inserted. Create
431 * with one of the vir_after_inst()-style helper functions.
432 *
433 * This does not protect against removal of the block or instruction, so we
434 * have an assert in instruction removal to try to catch it.
435 */
436 struct vir_cursor {
437 enum vir_cursor_mode mode;
438 struct list_head *link;
439 };
440
441 static inline struct vir_cursor
442 vir_before_inst(struct qinst *inst)
443 {
444 return (struct vir_cursor){ vir_cursor_addtail, &inst->link };
445 }
446
447 static inline struct vir_cursor
448 vir_after_inst(struct qinst *inst)
449 {
450 return (struct vir_cursor){ vir_cursor_add, &inst->link };
451 }
452
453 static inline struct vir_cursor
454 vir_before_block(struct qblock *block)
455 {
456 return (struct vir_cursor){ vir_cursor_add, &block->instructions };
457 }
458
459 static inline struct vir_cursor
460 vir_after_block(struct qblock *block)
461 {
462 return (struct vir_cursor){ vir_cursor_addtail, &block->instructions };
463 }
464
465 /**
466 * Compiler state saved across compiler invocations, for any expensive global
467 * setup.
468 */
469 struct v3d_compiler {
470 const struct v3d_device_info *devinfo;
471 struct ra_regs *regs;
472 unsigned int reg_class_any[3];
473 unsigned int reg_class_r5[3];
474 unsigned int reg_class_phys[3];
475 unsigned int reg_class_phys_or_acc[3];
476 };
477
478 struct v3d_compile {
479 const struct v3d_device_info *devinfo;
480 nir_shader *s;
481 nir_function_impl *impl;
482 struct exec_list *cf_node_list;
483 const struct v3d_compiler *compiler;
484
485 void (*debug_output)(const char *msg,
486 void *debug_output_data);
487 void *debug_output_data;
488
489 /**
490 * Mapping from nir_register * or nir_ssa_def * to array of struct
491 * qreg for the values.
492 */
493 struct hash_table *def_ht;
494
495 /* For each temp, the instruction generating its value. */
496 struct qinst **defs;
497 uint32_t defs_array_size;
498
499 /**
500 * Inputs to the shader, arranged by TGSI declaration order.
501 *
502 * Not all fragment shader QFILE_VARY reads are present in this array.
503 */
504 struct qreg *inputs;
505 struct qreg *outputs;
506 bool msaa_per_sample_output;
507 struct qreg color_reads[V3D_MAX_DRAW_BUFFERS * V3D_MAX_SAMPLES * 4];
508 struct qreg sample_colors[V3D_MAX_DRAW_BUFFERS * V3D_MAX_SAMPLES * 4];
509 uint32_t inputs_array_size;
510 uint32_t outputs_array_size;
511 uint32_t uniforms_array_size;
512
513 /* Booleans for whether the corresponding QFILE_VARY[i] is
514 * flat-shaded. This includes gl_FragColor flat-shading, which is
515 * customized based on the shademodel_flat shader key.
516 */
517 uint32_t flat_shade_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
518
519 uint32_t noperspective_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
520
521 uint32_t centroid_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
522
523 bool uses_center_w;
524 bool writes_z;
525 bool uses_implicit_point_line_varyings;
526
527 /* State for whether we're executing on each channel currently. 0 if
528 * yes, otherwise a block number + 1 that the channel jumped to.
529 */
530 struct qreg execute;
531 bool in_control_flow;
532
533 struct qreg line_x, point_x, point_y;
534
535 /**
536 * Instance ID, which comes in before the vertex attribute payload if
537 * the shader record requests it.
538 */
539 struct qreg iid;
540
541 /**
542 * Vertex ID, which comes in before the vertex attribute payload
543 * (after Instance ID) if the shader record requests it.
544 */
545 struct qreg vid;
546
547 /* Fragment shader payload regs. */
548 struct qreg payload_w, payload_w_centroid, payload_z;
549
550 struct qreg cs_payload[2];
551 struct qreg cs_shared_offset;
552 int local_invocation_index_bits;
553
554 uint8_t vattr_sizes[V3D_MAX_VS_INPUTS / 4];
555 uint32_t vpm_output_size;
556
557 /* Size in bytes of registers that have been spilled. This is how much
558 * space needs to be available in the spill BO per thread per QPU.
559 */
560 uint32_t spill_size;
561 /* Shader-db stats */
562 uint32_t spills, fills, loops;
563 /**
564 * Register spilling's per-thread base address, shared between each
565 * spill/fill's addressing calculations.
566 */
567 struct qreg spill_base;
568 /* Bit vector of which temps may be spilled */
569 BITSET_WORD *spillable;
570
571 /**
572 * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
573 *
574 * This includes those that aren't part of the VPM varyings, like
575 * point/line coordinates.
576 */
577 struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
578
579 /**
580 * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
581 * of the output is. Used to emit from the VS in the order that the
582 * FS needs.
583 */
584 struct v3d_varying_slot *output_slots;
585
586 struct pipe_shader_state *shader_state;
587 struct v3d_key *key;
588 struct v3d_fs_key *fs_key;
589 struct v3d_vs_key *vs_key;
590
591 /* Live ranges of temps. */
592 int *temp_start, *temp_end;
593 bool live_intervals_valid;
594
595 uint32_t *uniform_data;
596 enum quniform_contents *uniform_contents;
597 uint32_t uniform_array_size;
598 uint32_t num_uniforms;
599 uint32_t output_position_index;
600 nir_variable *output_color_var[4];
601 uint32_t output_sample_mask_index;
602
603 struct qreg undef;
604 uint32_t num_temps;
605
606 struct vir_cursor cursor;
607 struct list_head blocks;
608 int next_block_index;
609 struct qblock *cur_block;
610 struct qblock *loop_cont_block;
611 struct qblock *loop_break_block;
612
613 uint64_t *qpu_insts;
614 uint32_t qpu_inst_count;
615 uint32_t qpu_inst_size;
616 uint32_t qpu_inst_stalled_count;
617
618 /* For the FS, the number of varying inputs not counting the
619 * point/line varyings payload
620 */
621 uint32_t num_inputs;
622
623 uint32_t program_id;
624 uint32_t variant_id;
625
626 /* Set to compile program in in 1x, 2x, or 4x threaded mode, where
627 * SIG_THREAD_SWITCH is used to hide texturing latency at the cost of
628 * limiting ourselves to the part of the physical reg space.
629 *
630 * On V3D 3.x, 2x or 4x divide the physical reg space by 2x or 4x. On
631 * V3D 4.x, all shaders are 2x threaded, and 4x only divides the
632 * physical reg space in half.
633 */
634 uint8_t threads;
635 struct qinst *last_thrsw;
636 bool last_thrsw_at_top_level;
637
638 bool emitted_tlb_load;
639 bool lock_scoreboard_on_first_thrsw;
640
641 bool failed;
642
643 bool tmu_dirty_rcl;
644 };
645
646 struct v3d_uniform_list {
647 enum quniform_contents *contents;
648 uint32_t *data;
649 uint32_t count;
650 };
651
652 struct v3d_prog_data {
653 struct v3d_uniform_list uniforms;
654
655 uint32_t spill_size;
656
657 uint8_t threads;
658
659 /* For threads > 1, whether the program should be dispatched in the
660 * after-final-THRSW state.
661 */
662 bool single_seg;
663
664 bool tmu_dirty_rcl;
665 };
666
667 struct v3d_vs_prog_data {
668 struct v3d_prog_data base;
669
670 bool uses_iid, uses_vid;
671
672 /* Number of components read from each vertex attribute. */
673 uint8_t vattr_sizes[V3D_MAX_VS_INPUTS / 4];
674
675 /* Total number of components read, for the shader state record. */
676 uint32_t vpm_input_size;
677
678 /* Total number of components written, for the shader state record. */
679 uint32_t vpm_output_size;
680
681 /* Set if there should be separate VPM segments for input and output.
682 * If unset, vpm_input_size will be 0.
683 */
684 bool separate_segments;
685
686 /* Value to be programmed in VCM_CACHE_SIZE. */
687 uint8_t vcm_cache_size;
688 };
689
690 struct v3d_fs_prog_data {
691 struct v3d_prog_data base;
692
693 struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
694
695 /* Array of flat shade flags.
696 *
697 * Each entry is only 24 bits (high 8 bits 0), to match the hardware
698 * packet layout.
699 */
700 uint32_t flat_shade_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
701
702 uint32_t noperspective_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
703
704 uint32_t centroid_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
705
706 uint8_t num_inputs;
707 bool writes_z;
708 bool disable_ez;
709 bool uses_center_w;
710 bool uses_implicit_point_line_varyings;
711 bool lock_scoreboard_on_first_thrsw;
712 };
713
714 struct v3d_compute_prog_data {
715 struct v3d_prog_data base;
716 /* Size in bytes of the workgroup's shared space. */
717 uint32_t shared_size;
718 };
719
720 static inline bool
721 vir_has_uniform(struct qinst *inst)
722 {
723 return inst->uniform != ~0;
724 }
725
726 extern const nir_shader_compiler_options v3d_nir_options;
727
728 const struct v3d_compiler *v3d_compiler_init(const struct v3d_device_info *devinfo);
729 void v3d_compiler_free(const struct v3d_compiler *compiler);
730 void v3d_optimize_nir(struct nir_shader *s);
731
732 uint64_t *v3d_compile(const struct v3d_compiler *compiler,
733 struct v3d_key *key,
734 struct v3d_prog_data **prog_data,
735 nir_shader *s,
736 void (*debug_output)(const char *msg,
737 void *debug_output_data),
738 void *debug_output_data,
739 int program_id, int variant_id,
740 uint32_t *final_assembly_size);
741
742 void v3d_nir_to_vir(struct v3d_compile *c);
743
744 void vir_compile_destroy(struct v3d_compile *c);
745 const char *vir_get_stage_name(struct v3d_compile *c);
746 struct qblock *vir_new_block(struct v3d_compile *c);
747 void vir_set_emit_block(struct v3d_compile *c, struct qblock *block);
748 void vir_link_blocks(struct qblock *predecessor, struct qblock *successor);
749 struct qblock *vir_entry_block(struct v3d_compile *c);
750 struct qblock *vir_exit_block(struct v3d_compile *c);
751 struct qinst *vir_add_inst(enum v3d_qpu_add_op op, struct qreg dst,
752 struct qreg src0, struct qreg src1);
753 struct qinst *vir_mul_inst(enum v3d_qpu_mul_op op, struct qreg dst,
754 struct qreg src0, struct qreg src1);
755 struct qinst *vir_branch_inst(struct v3d_compile *c,
756 enum v3d_qpu_branch_cond cond);
757 void vir_remove_instruction(struct v3d_compile *c, struct qinst *qinst);
758 uint32_t vir_get_uniform_index(struct v3d_compile *c,
759 enum quniform_contents contents,
760 uint32_t data);
761 struct qreg vir_uniform(struct v3d_compile *c,
762 enum quniform_contents contents,
763 uint32_t data);
764 void vir_schedule_instructions(struct v3d_compile *c);
765 void v3d_setup_spill_base(struct v3d_compile *c);
766 struct v3d_qpu_instr v3d_qpu_nop(void);
767
768 struct qreg vir_emit_def(struct v3d_compile *c, struct qinst *inst);
769 struct qinst *vir_emit_nondef(struct v3d_compile *c, struct qinst *inst);
770 void vir_set_cond(struct qinst *inst, enum v3d_qpu_cond cond);
771 void vir_set_pf(struct qinst *inst, enum v3d_qpu_pf pf);
772 void vir_set_uf(struct qinst *inst, enum v3d_qpu_uf uf);
773 void vir_set_unpack(struct qinst *inst, int src,
774 enum v3d_qpu_input_unpack unpack);
775
776 struct qreg vir_get_temp(struct v3d_compile *c);
777 void vir_emit_last_thrsw(struct v3d_compile *c);
778 void vir_calculate_live_intervals(struct v3d_compile *c);
779 int vir_get_nsrc(struct qinst *inst);
780 bool vir_has_side_effects(struct v3d_compile *c, struct qinst *inst);
781 bool vir_get_add_op(struct qinst *inst, enum v3d_qpu_add_op *op);
782 bool vir_get_mul_op(struct qinst *inst, enum v3d_qpu_mul_op *op);
783 bool vir_is_raw_mov(struct qinst *inst);
784 bool vir_is_tex(struct qinst *inst);
785 bool vir_is_add(struct qinst *inst);
786 bool vir_is_mul(struct qinst *inst);
787 bool vir_writes_r3(const struct v3d_device_info *devinfo, struct qinst *inst);
788 bool vir_writes_r4(const struct v3d_device_info *devinfo, struct qinst *inst);
789 struct qreg vir_follow_movs(struct v3d_compile *c, struct qreg reg);
790 uint8_t vir_channels_written(struct qinst *inst);
791 struct qreg ntq_get_src(struct v3d_compile *c, nir_src src, int i);
792 void ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
793 struct qreg result);
794 void vir_emit_thrsw(struct v3d_compile *c);
795
796 void vir_dump(struct v3d_compile *c);
797 void vir_dump_inst(struct v3d_compile *c, struct qinst *inst);
798 void vir_dump_uniform(enum quniform_contents contents, uint32_t data);
799
800 void vir_validate(struct v3d_compile *c);
801
802 void vir_optimize(struct v3d_compile *c);
803 bool vir_opt_algebraic(struct v3d_compile *c);
804 bool vir_opt_constant_folding(struct v3d_compile *c);
805 bool vir_opt_copy_propagate(struct v3d_compile *c);
806 bool vir_opt_dead_code(struct v3d_compile *c);
807 bool vir_opt_peephole_sf(struct v3d_compile *c);
808 bool vir_opt_redundant_flags(struct v3d_compile *c);
809 bool vir_opt_small_immediates(struct v3d_compile *c);
810 bool vir_opt_vpm(struct v3d_compile *c);
811 void v3d_nir_lower_blend(nir_shader *s, struct v3d_compile *c);
812 void v3d_nir_lower_io(nir_shader *s, struct v3d_compile *c);
813 void v3d_nir_lower_logic_ops(nir_shader *s, struct v3d_compile *c);
814 void v3d_nir_lower_scratch(nir_shader *s);
815 void v3d_nir_lower_txf_ms(nir_shader *s, struct v3d_compile *c);
816 void v3d_nir_lower_image_load_store(nir_shader *s);
817 void vir_lower_uniforms(struct v3d_compile *c);
818
819 void v3d33_vir_vpm_read_setup(struct v3d_compile *c, int num_components);
820 void v3d33_vir_vpm_write_setup(struct v3d_compile *c);
821 void v3d33_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr);
822 void v3d40_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr);
823 void v3d40_vir_emit_image_load_store(struct v3d_compile *c,
824 nir_intrinsic_instr *instr);
825
826 void v3d_vir_to_qpu(struct v3d_compile *c, struct qpu_reg *temp_registers);
827 uint32_t v3d_qpu_schedule_instructions(struct v3d_compile *c);
828 void qpu_validate(struct v3d_compile *c);
829 struct qpu_reg *v3d_register_allocate(struct v3d_compile *c, bool *spilled);
830 bool vir_init_reg_sets(struct v3d_compiler *compiler);
831
832 bool v3d_gl_format_is_return_32(GLenum format);
833
834 uint32_t
835 v3d_get_op_for_atomic_add(nir_intrinsic_instr *instr, unsigned src);
836
837 static inline bool
838 quniform_contents_is_texture_p0(enum quniform_contents contents)
839 {
840 return (contents >= QUNIFORM_TEXTURE_CONFIG_P0_0 &&
841 contents < (QUNIFORM_TEXTURE_CONFIG_P0_0 +
842 V3D_MAX_TEXTURE_SAMPLERS));
843 }
844
845 static inline bool
846 vir_in_nonuniform_control_flow(struct v3d_compile *c)
847 {
848 return c->execute.file != QFILE_NULL;
849 }
850
851 static inline struct qreg
852 vir_uniform_ui(struct v3d_compile *c, uint32_t ui)
853 {
854 return vir_uniform(c, QUNIFORM_CONSTANT, ui);
855 }
856
857 static inline struct qreg
858 vir_uniform_f(struct v3d_compile *c, float f)
859 {
860 return vir_uniform(c, QUNIFORM_CONSTANT, fui(f));
861 }
862
863 #define VIR_ALU0(name, vir_inst, op) \
864 static inline struct qreg \
865 vir_##name(struct v3d_compile *c) \
866 { \
867 return vir_emit_def(c, vir_inst(op, c->undef, \
868 c->undef, c->undef)); \
869 } \
870 static inline struct qinst * \
871 vir_##name##_dest(struct v3d_compile *c, struct qreg dest) \
872 { \
873 return vir_emit_nondef(c, vir_inst(op, dest, \
874 c->undef, c->undef)); \
875 }
876
877 #define VIR_ALU1(name, vir_inst, op) \
878 static inline struct qreg \
879 vir_##name(struct v3d_compile *c, struct qreg a) \
880 { \
881 return vir_emit_def(c, vir_inst(op, c->undef, \
882 a, c->undef)); \
883 } \
884 static inline struct qinst * \
885 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
886 struct qreg a) \
887 { \
888 return vir_emit_nondef(c, vir_inst(op, dest, a, \
889 c->undef)); \
890 }
891
892 #define VIR_ALU2(name, vir_inst, op) \
893 static inline struct qreg \
894 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b) \
895 { \
896 return vir_emit_def(c, vir_inst(op, c->undef, a, b)); \
897 } \
898 static inline struct qinst * \
899 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
900 struct qreg a, struct qreg b) \
901 { \
902 return vir_emit_nondef(c, vir_inst(op, dest, a, b)); \
903 }
904
905 #define VIR_NODST_0(name, vir_inst, op) \
906 static inline struct qinst * \
907 vir_##name(struct v3d_compile *c) \
908 { \
909 return vir_emit_nondef(c, vir_inst(op, c->undef, \
910 c->undef, c->undef)); \
911 }
912
913 #define VIR_NODST_1(name, vir_inst, op) \
914 static inline struct qinst * \
915 vir_##name(struct v3d_compile *c, struct qreg a) \
916 { \
917 return vir_emit_nondef(c, vir_inst(op, c->undef, \
918 a, c->undef)); \
919 }
920
921 #define VIR_NODST_2(name, vir_inst, op) \
922 static inline struct qinst * \
923 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b) \
924 { \
925 return vir_emit_nondef(c, vir_inst(op, c->undef, \
926 a, b)); \
927 }
928
929 #define VIR_SFU(name) \
930 static inline struct qreg \
931 vir_##name(struct v3d_compile *c, struct qreg a) \
932 { \
933 if (c->devinfo->ver >= 41) { \
934 return vir_emit_def(c, vir_add_inst(V3D_QPU_A_##name, \
935 c->undef, \
936 a, c->undef)); \
937 } else { \
938 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_##name), a); \
939 return vir_FMOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4)); \
940 } \
941 } \
942 static inline struct qinst * \
943 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
944 struct qreg a) \
945 { \
946 if (c->devinfo->ver >= 41) { \
947 return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_##name, \
948 dest, \
949 a, c->undef)); \
950 } else { \
951 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_##name), a); \
952 return vir_FMOV_dest(c, dest, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4)); \
953 } \
954 }
955
956 #define VIR_A_ALU2(name) VIR_ALU2(name, vir_add_inst, V3D_QPU_A_##name)
957 #define VIR_M_ALU2(name) VIR_ALU2(name, vir_mul_inst, V3D_QPU_M_##name)
958 #define VIR_A_ALU1(name) VIR_ALU1(name, vir_add_inst, V3D_QPU_A_##name)
959 #define VIR_M_ALU1(name) VIR_ALU1(name, vir_mul_inst, V3D_QPU_M_##name)
960 #define VIR_A_ALU0(name) VIR_ALU0(name, vir_add_inst, V3D_QPU_A_##name)
961 #define VIR_M_ALU0(name) VIR_ALU0(name, vir_mul_inst, V3D_QPU_M_##name)
962 #define VIR_A_NODST_2(name) VIR_NODST_2(name, vir_add_inst, V3D_QPU_A_##name)
963 #define VIR_M_NODST_2(name) VIR_NODST_2(name, vir_mul_inst, V3D_QPU_M_##name)
964 #define VIR_A_NODST_1(name) VIR_NODST_1(name, vir_add_inst, V3D_QPU_A_##name)
965 #define VIR_M_NODST_1(name) VIR_NODST_1(name, vir_mul_inst, V3D_QPU_M_##name)
966 #define VIR_A_NODST_0(name) VIR_NODST_0(name, vir_add_inst, V3D_QPU_A_##name)
967
968 VIR_A_ALU2(FADD)
969 VIR_A_ALU2(VFPACK)
970 VIR_A_ALU2(FSUB)
971 VIR_A_ALU2(FMIN)
972 VIR_A_ALU2(FMAX)
973
974 VIR_A_ALU2(ADD)
975 VIR_A_ALU2(SUB)
976 VIR_A_ALU2(SHL)
977 VIR_A_ALU2(SHR)
978 VIR_A_ALU2(ASR)
979 VIR_A_ALU2(ROR)
980 VIR_A_ALU2(MIN)
981 VIR_A_ALU2(MAX)
982 VIR_A_ALU2(UMIN)
983 VIR_A_ALU2(UMAX)
984 VIR_A_ALU2(AND)
985 VIR_A_ALU2(OR)
986 VIR_A_ALU2(XOR)
987 VIR_A_ALU2(VADD)
988 VIR_A_ALU2(VSUB)
989 VIR_A_NODST_2(STVPMV)
990 VIR_A_ALU1(NOT)
991 VIR_A_ALU1(NEG)
992 VIR_A_ALU1(FLAPUSH)
993 VIR_A_ALU1(FLBPUSH)
994 VIR_A_ALU1(FLPOP)
995 VIR_A_ALU1(SETMSF)
996 VIR_A_ALU1(SETREVF)
997 VIR_A_ALU0(TIDX)
998 VIR_A_ALU0(EIDX)
999 VIR_A_ALU1(LDVPMV_IN)
1000 VIR_A_ALU1(LDVPMV_OUT)
1001 VIR_A_ALU1(LDVPMD_IN)
1002 VIR_A_ALU1(LDVPMD_OUT)
1003 VIR_A_ALU2(LDVPMG_IN)
1004 VIR_A_ALU2(LDVPMG_OUT)
1005 VIR_A_ALU0(TMUWT)
1006
1007 VIR_A_ALU0(FXCD)
1008 VIR_A_ALU0(XCD)
1009 VIR_A_ALU0(FYCD)
1010 VIR_A_ALU0(YCD)
1011 VIR_A_ALU0(MSF)
1012 VIR_A_ALU0(REVF)
1013 VIR_A_ALU0(BARRIERID)
1014 VIR_A_NODST_1(VPMSETUP)
1015 VIR_A_NODST_0(VPMWT)
1016 VIR_A_ALU2(FCMP)
1017 VIR_A_ALU2(VFMAX)
1018
1019 VIR_A_ALU1(FROUND)
1020 VIR_A_ALU1(FTOIN)
1021 VIR_A_ALU1(FTRUNC)
1022 VIR_A_ALU1(FTOIZ)
1023 VIR_A_ALU1(FFLOOR)
1024 VIR_A_ALU1(FTOUZ)
1025 VIR_A_ALU1(FCEIL)
1026 VIR_A_ALU1(FTOC)
1027
1028 VIR_A_ALU1(FDX)
1029 VIR_A_ALU1(FDY)
1030
1031 VIR_A_ALU1(ITOF)
1032 VIR_A_ALU1(CLZ)
1033 VIR_A_ALU1(UTOF)
1034
1035 VIR_M_ALU2(UMUL24)
1036 VIR_M_ALU2(FMUL)
1037 VIR_M_ALU2(SMUL24)
1038 VIR_M_NODST_2(MULTOP)
1039
1040 VIR_M_ALU1(MOV)
1041 VIR_M_ALU1(FMOV)
1042
1043 VIR_SFU(RECIP)
1044 VIR_SFU(RSQRT)
1045 VIR_SFU(EXP)
1046 VIR_SFU(LOG)
1047 VIR_SFU(SIN)
1048 VIR_SFU(RSQRT2)
1049
1050 static inline struct qinst *
1051 vir_MOV_cond(struct v3d_compile *c, enum v3d_qpu_cond cond,
1052 struct qreg dest, struct qreg src)
1053 {
1054 struct qinst *mov = vir_MOV_dest(c, dest, src);
1055 vir_set_cond(mov, cond);
1056 return mov;
1057 }
1058
1059 static inline struct qreg
1060 vir_SEL(struct v3d_compile *c, enum v3d_qpu_cond cond,
1061 struct qreg src0, struct qreg src1)
1062 {
1063 struct qreg t = vir_get_temp(c);
1064 vir_MOV_dest(c, t, src1);
1065 vir_MOV_cond(c, cond, t, src0);
1066 return t;
1067 }
1068
1069 static inline struct qinst *
1070 vir_NOP(struct v3d_compile *c)
1071 {
1072 return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_NOP,
1073 c->undef, c->undef, c->undef));
1074 }
1075
1076 static inline struct qreg
1077 vir_LDTMU(struct v3d_compile *c)
1078 {
1079 if (c->devinfo->ver >= 41) {
1080 struct qinst *ldtmu = vir_add_inst(V3D_QPU_A_NOP, c->undef,
1081 c->undef, c->undef);
1082 ldtmu->qpu.sig.ldtmu = true;
1083
1084 return vir_emit_def(c, ldtmu);
1085 } else {
1086 vir_NOP(c)->qpu.sig.ldtmu = true;
1087 return vir_MOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4));
1088 }
1089 }
1090
1091 static inline struct qreg
1092 vir_UMUL(struct v3d_compile *c, struct qreg src0, struct qreg src1)
1093 {
1094 vir_MULTOP(c, src0, src1);
1095 return vir_UMUL24(c, src0, src1);
1096 }
1097
1098 static inline struct qreg
1099 vir_TLBU_COLOR_READ(struct v3d_compile *c, uint32_t config)
1100 {
1101 assert(c->devinfo->ver >= 41); /* XXX */
1102 assert((config & 0xffffff00) == 0xffffff00);
1103
1104 struct qinst *ldtlb = vir_add_inst(V3D_QPU_A_NOP, c->undef,
1105 c->undef, c->undef);
1106 ldtlb->qpu.sig.ldtlbu = true;
1107 ldtlb->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT, config);
1108 return vir_emit_def(c, ldtlb);
1109 }
1110
1111 static inline struct qreg
1112 vir_TLB_COLOR_READ(struct v3d_compile *c)
1113 {
1114 assert(c->devinfo->ver >= 41); /* XXX */
1115
1116 struct qinst *ldtlb = vir_add_inst(V3D_QPU_A_NOP, c->undef,
1117 c->undef, c->undef);
1118 ldtlb->qpu.sig.ldtlb = true;
1119 return vir_emit_def(c, ldtlb);
1120 }
1121
1122 /*
1123 static inline struct qreg
1124 vir_LOAD_IMM(struct v3d_compile *c, uint32_t val)
1125 {
1126 return vir_emit_def(c, vir_inst(QOP_LOAD_IMM, c->undef,
1127 vir_reg(QFILE_LOAD_IMM, val), c->undef));
1128 }
1129
1130 static inline struct qreg
1131 vir_LOAD_IMM_U2(struct v3d_compile *c, uint32_t val)
1132 {
1133 return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_U2, c->undef,
1134 vir_reg(QFILE_LOAD_IMM, val),
1135 c->undef));
1136 }
1137 static inline struct qreg
1138 vir_LOAD_IMM_I2(struct v3d_compile *c, uint32_t val)
1139 {
1140 return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_I2, c->undef,
1141 vir_reg(QFILE_LOAD_IMM, val),
1142 c->undef));
1143 }
1144 */
1145
1146 static inline struct qinst *
1147 vir_BRANCH(struct v3d_compile *c, enum v3d_qpu_branch_cond cond)
1148 {
1149 /* The actual uniform_data value will be set at scheduling time */
1150 return vir_emit_nondef(c, vir_branch_inst(c, cond));
1151 }
1152
1153 #define vir_for_each_block(block, c) \
1154 list_for_each_entry(struct qblock, block, &c->blocks, link)
1155
1156 #define vir_for_each_block_rev(block, c) \
1157 list_for_each_entry_rev(struct qblock, block, &c->blocks, link)
1158
1159 /* Loop over the non-NULL members of the successors array. */
1160 #define vir_for_each_successor(succ, block) \
1161 for (struct qblock *succ = block->successors[0]; \
1162 succ != NULL; \
1163 succ = (succ == block->successors[1] ? NULL : \
1164 block->successors[1]))
1165
1166 #define vir_for_each_inst(inst, block) \
1167 list_for_each_entry(struct qinst, inst, &block->instructions, link)
1168
1169 #define vir_for_each_inst_rev(inst, block) \
1170 list_for_each_entry_rev(struct qinst, inst, &block->instructions, link)
1171
1172 #define vir_for_each_inst_safe(inst, block) \
1173 list_for_each_entry_safe(struct qinst, inst, &block->instructions, link)
1174
1175 #define vir_for_each_inst_inorder(inst, c) \
1176 vir_for_each_block(_block, c) \
1177 vir_for_each_inst(inst, _block)
1178
1179 #define vir_for_each_inst_inorder_safe(inst, c) \
1180 vir_for_each_block(_block, c) \
1181 vir_for_each_inst_safe(inst, _block)
1182
1183 #endif /* V3D_COMPILER_H */