2 * Copyright © 2016 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef V3D_COMPILER_H
25 #define V3D_COMPILER_H
34 #include "util/macros.h"
35 #include "common/v3d_debug.h"
36 #include "common/v3d_device_info.h"
37 #include "common/v3d_limits.h"
38 #include "compiler/nir/nir.h"
39 #include "util/list.h"
40 #include "util/u_math.h"
42 #include "qpu/qpu_instr.h"
43 #include "pipe/p_state.h"
47 struct v3d_fs_inputs
{
49 * Array of the meanings of the VPM inputs this shader needs.
51 * It doesn't include those that aren't part of the VPM, like
52 * point/line coordinates.
54 struct v3d_varying_slot
*input_slots
;
59 /** An unused source or destination register. */
62 /** A physical register, such as the W coordinate payload. */
64 /** One of the regsiters for fixed function interactions. */
68 * A virtual register, that will be allocated to actual accumulator
69 * or physical registers later.
74 * VPM reads use this with an index value to say what part of the VPM
80 * Stores an immediate value in the index field that will be used
81 * directly by qpu_load_imm().
86 * Stores an immediate value in the index field that can be turned
87 * into a small immediate field by qpu_encode_small_immediate().
93 * A reference to a QPU register or a virtual temp register.
100 static inline struct qreg
vir_reg(enum qfile file
, uint32_t index
)
102 return (struct qreg
){file
, index
};
105 static inline struct qreg
vir_magic_reg(uint32_t index
)
107 return (struct qreg
){QFILE_MAGIC
, index
};
110 static inline struct qreg
vir_nop_reg(void)
112 return (struct qreg
){QFILE_NULL
, 0};
116 * A reference to an actual register at the QPU level, for register
126 /** Entry in qblock->instructions */
127 struct list_head link
;
130 * The instruction being wrapped. Its condition codes, pack flags,
131 * signals, etc. will all be used, with just the register references
132 * being replaced by the contents of qinst->dst and qinst->src[].
134 struct v3d_qpu_instr qpu
;
136 /* Pre-register-allocation references to src/dst registers */
141 /* If the instruction reads a uniform (other than through src[i].file
142 * == QFILE_UNIF), that uniform's index in c->uniform_contents. ~0
148 enum quniform_contents
{
150 * Indicates that a constant 32-bit value is copied from the program's
155 * Indicates that the program's uniform contents are used as an index
156 * into the GL uniform storage.
161 * Scaling factors from clip coordinates to relative to the viewport
164 * This is used by the coordinate and vertex shaders to produce the
165 * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
166 * point offsets from the viewport ccenter.
168 QUNIFORM_VIEWPORT_X_SCALE
,
169 QUNIFORM_VIEWPORT_Y_SCALE
,
172 QUNIFORM_VIEWPORT_Z_OFFSET
,
173 QUNIFORM_VIEWPORT_Z_SCALE
,
175 QUNIFORM_USER_CLIP_PLANE
,
178 * A reference to a V3D 3.x texture config parameter 0 uniform.
180 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
181 * defines texture type, miplevels, and such. It will be found as a
182 * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
184 QUNIFORM_TEXTURE_CONFIG_P0_0
,
185 QUNIFORM_TEXTURE_CONFIG_P0_1
,
186 QUNIFORM_TEXTURE_CONFIG_P0_2
,
187 QUNIFORM_TEXTURE_CONFIG_P0_3
,
188 QUNIFORM_TEXTURE_CONFIG_P0_4
,
189 QUNIFORM_TEXTURE_CONFIG_P0_5
,
190 QUNIFORM_TEXTURE_CONFIG_P0_6
,
191 QUNIFORM_TEXTURE_CONFIG_P0_7
,
192 QUNIFORM_TEXTURE_CONFIG_P0_8
,
193 QUNIFORM_TEXTURE_CONFIG_P0_9
,
194 QUNIFORM_TEXTURE_CONFIG_P0_10
,
195 QUNIFORM_TEXTURE_CONFIG_P0_11
,
196 QUNIFORM_TEXTURE_CONFIG_P0_12
,
197 QUNIFORM_TEXTURE_CONFIG_P0_13
,
198 QUNIFORM_TEXTURE_CONFIG_P0_14
,
199 QUNIFORM_TEXTURE_CONFIG_P0_15
,
200 QUNIFORM_TEXTURE_CONFIG_P0_16
,
201 QUNIFORM_TEXTURE_CONFIG_P0_17
,
202 QUNIFORM_TEXTURE_CONFIG_P0_18
,
203 QUNIFORM_TEXTURE_CONFIG_P0_19
,
204 QUNIFORM_TEXTURE_CONFIG_P0_20
,
205 QUNIFORM_TEXTURE_CONFIG_P0_21
,
206 QUNIFORM_TEXTURE_CONFIG_P0_22
,
207 QUNIFORM_TEXTURE_CONFIG_P0_23
,
208 QUNIFORM_TEXTURE_CONFIG_P0_24
,
209 QUNIFORM_TEXTURE_CONFIG_P0_25
,
210 QUNIFORM_TEXTURE_CONFIG_P0_26
,
211 QUNIFORM_TEXTURE_CONFIG_P0_27
,
212 QUNIFORM_TEXTURE_CONFIG_P0_28
,
213 QUNIFORM_TEXTURE_CONFIG_P0_29
,
214 QUNIFORM_TEXTURE_CONFIG_P0_30
,
215 QUNIFORM_TEXTURE_CONFIG_P0_31
,
216 QUNIFORM_TEXTURE_CONFIG_P0_32
,
219 * A reference to a V3D 3.x texture config parameter 1 uniform.
221 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
222 * has the pointer to the indirect texture state. Our data[] field
223 * will have a packed p1 value, but the address field will be just
224 * which texture unit's texture should be referenced.
226 QUNIFORM_TEXTURE_CONFIG_P1
,
228 /* A V3D 4.x texture config parameter. The high 8 bits will be
229 * which texture or sampler is being sampled, and the driver must
230 * replace the address field with the appropriate address.
232 QUNIFORM_TMU_CONFIG_P0
,
233 QUNIFORM_TMU_CONFIG_P1
,
235 QUNIFORM_IMAGE_TMU_CONFIG_P0
,
237 QUNIFORM_TEXTURE_FIRST_LEVEL
,
239 QUNIFORM_TEXTURE_WIDTH
,
240 QUNIFORM_TEXTURE_HEIGHT
,
241 QUNIFORM_TEXTURE_DEPTH
,
242 QUNIFORM_TEXTURE_ARRAY_SIZE
,
243 QUNIFORM_TEXTURE_LEVELS
,
247 QUNIFORM_TEXRECT_SCALE_X
,
248 QUNIFORM_TEXRECT_SCALE_Y
,
250 /* Returns the base offset of the SSBO given by the data value. */
251 QUNIFORM_SSBO_OFFSET
,
253 /* Returns the size of the SSBO given by the data value. */
254 QUNIFORM_GET_BUFFER_SIZE
,
256 /* Sizes (in pixels) of a shader image given by the data value. */
257 QUNIFORM_IMAGE_WIDTH
,
258 QUNIFORM_IMAGE_HEIGHT
,
259 QUNIFORM_IMAGE_DEPTH
,
260 QUNIFORM_IMAGE_ARRAY_SIZE
,
264 /* Number of workgroups passed to glDispatchCompute in the dimension
265 * selected by the data value.
267 QUNIFORM_NUM_WORK_GROUPS
,
270 * Returns the the offset of the scratch buffer for register spilling.
272 QUNIFORM_SPILL_OFFSET
,
273 QUNIFORM_SPILL_SIZE_PER_THREAD
,
276 * Returns the offset of the shared memory for compute shaders.
278 * This will be accessed using TMU general memory operations, so the
279 * L2T cache will effectively be the shared memory area.
281 QUNIFORM_SHARED_OFFSET
,
284 static inline uint32_t v3d_unit_data_create(uint32_t unit
, uint32_t value
)
286 assert(value
< (1 << 24));
287 return unit
<< 24 | value
;
290 static inline uint32_t v3d_unit_data_get_unit(uint32_t data
)
295 static inline uint32_t v3d_unit_data_get_offset(uint32_t data
)
297 return data
& 0xffffff;
300 struct v3d_varying_slot
{
301 uint8_t slot_and_component
;
304 static inline struct v3d_varying_slot
305 v3d_slot_from_slot_and_component(uint8_t slot
, uint8_t component
)
307 assert(slot
< 255 / 4);
308 return (struct v3d_varying_slot
){ (slot
<< 2) + component
};
311 static inline uint8_t v3d_slot_get_slot(struct v3d_varying_slot slot
)
313 return slot
.slot_and_component
>> 2;
316 static inline uint8_t v3d_slot_get_component(struct v3d_varying_slot slot
)
318 return slot
.slot_and_component
& 3;
326 uint8_t return_channels
;
330 } tex
[V3D_MAX_TEXTURE_SAMPLERS
];
332 bool is_last_geometry_stage
;
341 bool point_coord_upper_left
;
344 bool sample_coverage
;
345 bool sample_alpha_to_coverage
;
346 bool sample_alpha_to_one
;
348 bool shade_model_flat
;
349 /* Mask of which color render targets are present. */
351 uint8_t swap_color_rb
;
352 /* Mask of which render targets need to be written as 32-bit floats */
353 uint8_t f32_color_rb
;
354 /* Masks of which render targets need to be written as ints/uints.
355 * Used by gallium to work around lost information in TGSI.
357 uint8_t int_color_rb
;
358 uint8_t uint_color_rb
;
360 /* Color format information per render target. Only set when logic
361 * operations are enabled.
364 enum pipe_format format
;
365 const uint8_t *swizzle
;
366 } color_fmt
[V3D_MAX_DRAW_BUFFERS
];
368 uint8_t alpha_test_func
;
369 uint8_t logicop_func
;
370 uint32_t point_sprite_mask
;
372 struct pipe_rt_blend_state blend
;
378 struct v3d_varying_slot used_outputs
[V3D_MAX_FS_INPUTS
];
379 uint8_t num_used_outputs
;
382 bool per_vertex_point_size
;
388 struct v3d_varying_slot used_outputs
[V3D_MAX_ANY_STAGE_INPUTS
];
389 uint8_t num_used_outputs
;
392 bool per_vertex_point_size
;
396 /** A basic block of VIR intructions. */
398 struct list_head link
;
400 struct list_head instructions
;
402 struct set
*predecessors
;
403 struct qblock
*successors
[2];
407 /* Instruction IPs for the first and last instruction of the block.
408 * Set by qpu_schedule.c.
410 uint32_t start_qpu_ip
;
413 /* Instruction IP for the branch instruction of the block. Set by
416 uint32_t branch_qpu_ip
;
418 /** Offset within the uniform stream at the start of the block. */
419 uint32_t start_uniform
;
420 /** Offset within the uniform stream of the branch instruction */
421 uint32_t branch_uniform
;
423 /** @{ used by v3d_vir_live_variables.c */
428 BITSET_WORD
*live_in
;
429 BITSET_WORD
*live_out
;
430 int start_ip
, end_ip
;
434 /** Which util/list.h add mode we should use when inserting an instruction. */
435 enum vir_cursor_mode
{
441 * Tracking structure for where new instructions should be inserted. Create
442 * with one of the vir_after_inst()-style helper functions.
444 * This does not protect against removal of the block or instruction, so we
445 * have an assert in instruction removal to try to catch it.
448 enum vir_cursor_mode mode
;
449 struct list_head
*link
;
452 static inline struct vir_cursor
453 vir_before_inst(struct qinst
*inst
)
455 return (struct vir_cursor
){ vir_cursor_addtail
, &inst
->link
};
458 static inline struct vir_cursor
459 vir_after_inst(struct qinst
*inst
)
461 return (struct vir_cursor
){ vir_cursor_add
, &inst
->link
};
464 static inline struct vir_cursor
465 vir_before_block(struct qblock
*block
)
467 return (struct vir_cursor
){ vir_cursor_add
, &block
->instructions
};
470 static inline struct vir_cursor
471 vir_after_block(struct qblock
*block
)
473 return (struct vir_cursor
){ vir_cursor_addtail
, &block
->instructions
};
477 * Compiler state saved across compiler invocations, for any expensive global
480 struct v3d_compiler
{
481 const struct v3d_device_info
*devinfo
;
482 struct ra_regs
*regs
;
483 unsigned int reg_class_any
[3];
484 unsigned int reg_class_r5
[3];
485 unsigned int reg_class_phys
[3];
486 unsigned int reg_class_phys_or_acc
[3];
490 const struct v3d_device_info
*devinfo
;
492 nir_function_impl
*impl
;
493 struct exec_list
*cf_node_list
;
494 const struct v3d_compiler
*compiler
;
496 void (*debug_output
)(const char *msg
,
497 void *debug_output_data
);
498 void *debug_output_data
;
501 * Mapping from nir_register * or nir_ssa_def * to array of struct
502 * qreg for the values.
504 struct hash_table
*def_ht
;
506 /* For each temp, the instruction generating its value. */
508 uint32_t defs_array_size
;
511 * Inputs to the shader, arranged by TGSI declaration order.
513 * Not all fragment shader QFILE_VARY reads are present in this array.
516 struct qreg
*outputs
;
517 bool msaa_per_sample_output
;
518 struct qreg color_reads
[V3D_MAX_DRAW_BUFFERS
* V3D_MAX_SAMPLES
* 4];
519 struct qreg sample_colors
[V3D_MAX_DRAW_BUFFERS
* V3D_MAX_SAMPLES
* 4];
520 uint32_t inputs_array_size
;
521 uint32_t outputs_array_size
;
522 uint32_t uniforms_array_size
;
524 /* Booleans for whether the corresponding QFILE_VARY[i] is
525 * flat-shaded. This includes gl_FragColor flat-shading, which is
526 * customized based on the shademodel_flat shader key.
528 uint32_t flat_shade_flags
[BITSET_WORDS(V3D_MAX_FS_INPUTS
)];
530 uint32_t noperspective_flags
[BITSET_WORDS(V3D_MAX_FS_INPUTS
)];
532 uint32_t centroid_flags
[BITSET_WORDS(V3D_MAX_FS_INPUTS
)];
536 bool uses_implicit_point_line_varyings
;
538 /* State for whether we're executing on each channel currently. 0 if
539 * yes, otherwise a block number + 1 that the channel jumped to.
542 bool in_control_flow
;
544 struct qreg line_x
, point_x
, point_y
;
547 * Instance ID, which comes in before the vertex attribute payload if
548 * the shader record requests it.
553 * Vertex ID, which comes in before the vertex attribute payload
554 * (after Instance ID) if the shader record requests it.
558 /* Fragment shader payload regs. */
559 struct qreg payload_w
, payload_w_centroid
, payload_z
;
561 struct qreg cs_payload
[2];
562 struct qreg cs_shared_offset
;
563 int local_invocation_index_bits
;
565 uint8_t vattr_sizes
[V3D_MAX_VS_INPUTS
/ 4];
566 uint8_t gs_input_sizes
[V3D_MAX_GS_INPUTS
];
567 uint32_t vpm_output_size
;
569 /* Size in bytes of registers that have been spilled. This is how much
570 * space needs to be available in the spill BO per thread per QPU.
573 /* Shader-db stats */
574 uint32_t spills
, fills
, loops
;
576 * Register spilling's per-thread base address, shared between each
577 * spill/fill's addressing calculations.
579 struct qreg spill_base
;
580 /* Bit vector of which temps may be spilled */
581 BITSET_WORD
*spillable
;
584 * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
586 * This includes those that aren't part of the VPM varyings, like
587 * point/line coordinates.
589 struct v3d_varying_slot input_slots
[V3D_MAX_FS_INPUTS
];
592 * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
593 * of the output is. Used to emit from the VS in the order that the
596 struct v3d_varying_slot
*output_slots
;
598 struct pipe_shader_state
*shader_state
;
600 struct v3d_fs_key
*fs_key
;
601 struct v3d_gs_key
*gs_key
;
602 struct v3d_vs_key
*vs_key
;
604 /* Live ranges of temps. */
605 int *temp_start
, *temp_end
;
606 bool live_intervals_valid
;
608 uint32_t *uniform_data
;
609 enum quniform_contents
*uniform_contents
;
610 uint32_t uniform_array_size
;
611 uint32_t num_uniforms
;
612 uint32_t output_position_index
;
613 nir_variable
*output_color_var
[4];
614 uint32_t output_sample_mask_index
;
619 struct vir_cursor cursor
;
620 struct list_head blocks
;
621 int next_block_index
;
622 struct qblock
*cur_block
;
623 struct qblock
*loop_cont_block
;
624 struct qblock
*loop_break_block
;
627 uint32_t qpu_inst_count
;
628 uint32_t qpu_inst_size
;
629 uint32_t qpu_inst_stalled_count
;
631 /* For the FS, the number of varying inputs not counting the
632 * point/line varyings payload
639 /* Set to compile program in in 1x, 2x, or 4x threaded mode, where
640 * SIG_THREAD_SWITCH is used to hide texturing latency at the cost of
641 * limiting ourselves to the part of the physical reg space.
643 * On V3D 3.x, 2x or 4x divide the physical reg space by 2x or 4x. On
644 * V3D 4.x, all shaders are 2x threaded, and 4x only divides the
645 * physical reg space in half.
648 struct qinst
*last_thrsw
;
649 bool last_thrsw_at_top_level
;
651 bool emitted_tlb_load
;
652 bool lock_scoreboard_on_first_thrsw
;
659 struct v3d_uniform_list
{
660 enum quniform_contents
*contents
;
665 struct v3d_prog_data
{
666 struct v3d_uniform_list uniforms
;
672 /* For threads > 1, whether the program should be dispatched in the
673 * after-final-THRSW state.
680 struct v3d_vs_prog_data
{
681 struct v3d_prog_data base
;
683 bool uses_iid
, uses_vid
;
685 /* Number of components read from each vertex attribute. */
686 uint8_t vattr_sizes
[V3D_MAX_VS_INPUTS
/ 4];
688 /* Total number of components read, for the shader state record. */
689 uint32_t vpm_input_size
;
691 /* Total number of components written, for the shader state record. */
692 uint32_t vpm_output_size
;
694 /* Set if there should be separate VPM segments for input and output.
695 * If unset, vpm_input_size will be 0.
697 bool separate_segments
;
699 /* Value to be programmed in VCM_CACHE_SIZE. */
700 uint8_t vcm_cache_size
;
703 struct v3d_gs_prog_data
{
704 struct v3d_prog_data base
;
706 /* Whether the program reads gl_PrimitiveIDIn */
709 /* Number of components read from each input varying. */
710 uint8_t input_sizes
[V3D_MAX_GS_INPUTS
/ 4];
712 /* Number of inputs */
714 struct v3d_varying_slot input_slots
[V3D_MAX_GS_INPUTS
];
716 /* Total number of components written, for the shader state record. */
717 uint32_t vpm_output_size
;
719 /* Maximum SIMD dispatch width to not exceed VPM output size limits
720 * in the geometry shader. Notice that the final dispatch width has to
721 * be decided at draw time and could be lower based on the VPM pressure
722 * added by other shader stages.
726 /* Output primitive type */
727 uint8_t out_prim_type
;
729 /* Number of GS invocations */
730 uint8_t num_invocations
;
733 struct v3d_fs_prog_data
{
734 struct v3d_prog_data base
;
736 struct v3d_varying_slot input_slots
[V3D_MAX_FS_INPUTS
];
738 /* Array of flat shade flags.
740 * Each entry is only 24 bits (high 8 bits 0), to match the hardware
743 uint32_t flat_shade_flags
[((V3D_MAX_FS_INPUTS
- 1) / 24) + 1];
745 uint32_t noperspective_flags
[((V3D_MAX_FS_INPUTS
- 1) / 24) + 1];
747 uint32_t centroid_flags
[((V3D_MAX_FS_INPUTS
- 1) / 24) + 1];
753 bool uses_implicit_point_line_varyings
;
754 bool lock_scoreboard_on_first_thrsw
;
757 struct v3d_compute_prog_data
{
758 struct v3d_prog_data base
;
759 /* Size in bytes of the workgroup's shared space. */
760 uint32_t shared_size
;
764 vir_has_uniform(struct qinst
*inst
)
766 return inst
->uniform
!= ~0;
769 extern const nir_shader_compiler_options v3d_nir_options
;
771 const struct v3d_compiler
*v3d_compiler_init(const struct v3d_device_info
*devinfo
);
772 void v3d_compiler_free(const struct v3d_compiler
*compiler
);
773 void v3d_optimize_nir(struct nir_shader
*s
);
775 uint64_t *v3d_compile(const struct v3d_compiler
*compiler
,
777 struct v3d_prog_data
**prog_data
,
779 void (*debug_output
)(const char *msg
,
780 void *debug_output_data
),
781 void *debug_output_data
,
782 int program_id
, int variant_id
,
783 uint32_t *final_assembly_size
);
785 void v3d_nir_to_vir(struct v3d_compile
*c
);
787 void vir_compile_destroy(struct v3d_compile
*c
);
788 const char *vir_get_stage_name(struct v3d_compile
*c
);
789 struct qblock
*vir_new_block(struct v3d_compile
*c
);
790 void vir_set_emit_block(struct v3d_compile
*c
, struct qblock
*block
);
791 void vir_link_blocks(struct qblock
*predecessor
, struct qblock
*successor
);
792 struct qblock
*vir_entry_block(struct v3d_compile
*c
);
793 struct qblock
*vir_exit_block(struct v3d_compile
*c
);
794 struct qinst
*vir_add_inst(enum v3d_qpu_add_op op
, struct qreg dst
,
795 struct qreg src0
, struct qreg src1
);
796 struct qinst
*vir_mul_inst(enum v3d_qpu_mul_op op
, struct qreg dst
,
797 struct qreg src0
, struct qreg src1
);
798 struct qinst
*vir_branch_inst(struct v3d_compile
*c
,
799 enum v3d_qpu_branch_cond cond
);
800 void vir_remove_instruction(struct v3d_compile
*c
, struct qinst
*qinst
);
801 uint32_t vir_get_uniform_index(struct v3d_compile
*c
,
802 enum quniform_contents contents
,
804 struct qreg
vir_uniform(struct v3d_compile
*c
,
805 enum quniform_contents contents
,
807 void vir_schedule_instructions(struct v3d_compile
*c
);
808 void v3d_setup_spill_base(struct v3d_compile
*c
);
809 struct v3d_qpu_instr
v3d_qpu_nop(void);
811 struct qreg
vir_emit_def(struct v3d_compile
*c
, struct qinst
*inst
);
812 struct qinst
*vir_emit_nondef(struct v3d_compile
*c
, struct qinst
*inst
);
813 void vir_set_cond(struct qinst
*inst
, enum v3d_qpu_cond cond
);
814 void vir_set_pf(struct qinst
*inst
, enum v3d_qpu_pf pf
);
815 void vir_set_uf(struct qinst
*inst
, enum v3d_qpu_uf uf
);
816 void vir_set_unpack(struct qinst
*inst
, int src
,
817 enum v3d_qpu_input_unpack unpack
);
819 struct qreg
vir_get_temp(struct v3d_compile
*c
);
820 void vir_emit_last_thrsw(struct v3d_compile
*c
);
821 void vir_calculate_live_intervals(struct v3d_compile
*c
);
822 int vir_get_nsrc(struct qinst
*inst
);
823 bool vir_has_side_effects(struct v3d_compile
*c
, struct qinst
*inst
);
824 bool vir_get_add_op(struct qinst
*inst
, enum v3d_qpu_add_op
*op
);
825 bool vir_get_mul_op(struct qinst
*inst
, enum v3d_qpu_mul_op
*op
);
826 bool vir_is_raw_mov(struct qinst
*inst
);
827 bool vir_is_tex(struct qinst
*inst
);
828 bool vir_is_add(struct qinst
*inst
);
829 bool vir_is_mul(struct qinst
*inst
);
830 bool vir_writes_r3(const struct v3d_device_info
*devinfo
, struct qinst
*inst
);
831 bool vir_writes_r4(const struct v3d_device_info
*devinfo
, struct qinst
*inst
);
832 struct qreg
vir_follow_movs(struct v3d_compile
*c
, struct qreg reg
);
833 uint8_t vir_channels_written(struct qinst
*inst
);
834 struct qreg
ntq_get_src(struct v3d_compile
*c
, nir_src src
, int i
);
835 void ntq_store_dest(struct v3d_compile
*c
, nir_dest
*dest
, int chan
,
837 void vir_emit_thrsw(struct v3d_compile
*c
);
839 void vir_dump(struct v3d_compile
*c
);
840 void vir_dump_inst(struct v3d_compile
*c
, struct qinst
*inst
);
841 void vir_dump_uniform(enum quniform_contents contents
, uint32_t data
);
843 void vir_validate(struct v3d_compile
*c
);
845 void vir_optimize(struct v3d_compile
*c
);
846 bool vir_opt_algebraic(struct v3d_compile
*c
);
847 bool vir_opt_constant_folding(struct v3d_compile
*c
);
848 bool vir_opt_copy_propagate(struct v3d_compile
*c
);
849 bool vir_opt_dead_code(struct v3d_compile
*c
);
850 bool vir_opt_peephole_sf(struct v3d_compile
*c
);
851 bool vir_opt_redundant_flags(struct v3d_compile
*c
);
852 bool vir_opt_small_immediates(struct v3d_compile
*c
);
853 bool vir_opt_vpm(struct v3d_compile
*c
);
854 void v3d_nir_lower_blend(nir_shader
*s
, struct v3d_compile
*c
);
855 void v3d_nir_lower_io(nir_shader
*s
, struct v3d_compile
*c
);
856 void v3d_nir_lower_logic_ops(nir_shader
*s
, struct v3d_compile
*c
);
857 void v3d_nir_lower_scratch(nir_shader
*s
);
858 void v3d_nir_lower_txf_ms(nir_shader
*s
, struct v3d_compile
*c
);
859 void v3d_nir_lower_image_load_store(nir_shader
*s
);
860 void vir_lower_uniforms(struct v3d_compile
*c
);
862 void v3d33_vir_vpm_read_setup(struct v3d_compile
*c
, int num_components
);
863 void v3d33_vir_vpm_write_setup(struct v3d_compile
*c
);
864 void v3d33_vir_emit_tex(struct v3d_compile
*c
, nir_tex_instr
*instr
);
865 void v3d40_vir_emit_tex(struct v3d_compile
*c
, nir_tex_instr
*instr
);
866 void v3d40_vir_emit_image_load_store(struct v3d_compile
*c
,
867 nir_intrinsic_instr
*instr
);
869 void v3d_vir_to_qpu(struct v3d_compile
*c
, struct qpu_reg
*temp_registers
);
870 uint32_t v3d_qpu_schedule_instructions(struct v3d_compile
*c
);
871 void qpu_validate(struct v3d_compile
*c
);
872 struct qpu_reg
*v3d_register_allocate(struct v3d_compile
*c
, bool *spilled
);
873 bool vir_init_reg_sets(struct v3d_compiler
*compiler
);
875 bool v3d_gl_format_is_return_32(GLenum format
);
878 v3d_get_op_for_atomic_add(nir_intrinsic_instr
*instr
, unsigned src
);
881 quniform_contents_is_texture_p0(enum quniform_contents contents
)
883 return (contents
>= QUNIFORM_TEXTURE_CONFIG_P0_0
&&
884 contents
< (QUNIFORM_TEXTURE_CONFIG_P0_0
+
885 V3D_MAX_TEXTURE_SAMPLERS
));
889 vir_in_nonuniform_control_flow(struct v3d_compile
*c
)
891 return c
->execute
.file
!= QFILE_NULL
;
894 static inline struct qreg
895 vir_uniform_ui(struct v3d_compile
*c
, uint32_t ui
)
897 return vir_uniform(c
, QUNIFORM_CONSTANT
, ui
);
900 static inline struct qreg
901 vir_uniform_f(struct v3d_compile
*c
, float f
)
903 return vir_uniform(c
, QUNIFORM_CONSTANT
, fui(f
));
906 #define VIR_ALU0(name, vir_inst, op) \
907 static inline struct qreg \
908 vir_##name(struct v3d_compile *c) \
910 return vir_emit_def(c, vir_inst(op, c->undef, \
911 c->undef, c->undef)); \
913 static inline struct qinst * \
914 vir_##name##_dest(struct v3d_compile *c, struct qreg dest) \
916 return vir_emit_nondef(c, vir_inst(op, dest, \
917 c->undef, c->undef)); \
920 #define VIR_ALU1(name, vir_inst, op) \
921 static inline struct qreg \
922 vir_##name(struct v3d_compile *c, struct qreg a) \
924 return vir_emit_def(c, vir_inst(op, c->undef, \
927 static inline struct qinst * \
928 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
931 return vir_emit_nondef(c, vir_inst(op, dest, a, \
935 #define VIR_ALU2(name, vir_inst, op) \
936 static inline struct qreg \
937 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b) \
939 return vir_emit_def(c, vir_inst(op, c->undef, a, b)); \
941 static inline struct qinst * \
942 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
943 struct qreg a, struct qreg b) \
945 return vir_emit_nondef(c, vir_inst(op, dest, a, b)); \
948 #define VIR_NODST_0(name, vir_inst, op) \
949 static inline struct qinst * \
950 vir_##name(struct v3d_compile *c) \
952 return vir_emit_nondef(c, vir_inst(op, c->undef, \
953 c->undef, c->undef)); \
956 #define VIR_NODST_1(name, vir_inst, op) \
957 static inline struct qinst * \
958 vir_##name(struct v3d_compile *c, struct qreg a) \
960 return vir_emit_nondef(c, vir_inst(op, c->undef, \
964 #define VIR_NODST_2(name, vir_inst, op) \
965 static inline struct qinst * \
966 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b) \
968 return vir_emit_nondef(c, vir_inst(op, c->undef, \
972 #define VIR_SFU(name) \
973 static inline struct qreg \
974 vir_##name(struct v3d_compile *c, struct qreg a) \
976 if (c->devinfo->ver >= 41) { \
977 return vir_emit_def(c, vir_add_inst(V3D_QPU_A_##name, \
981 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_##name), a); \
982 return vir_FMOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4)); \
985 static inline struct qinst * \
986 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
989 if (c->devinfo->ver >= 41) { \
990 return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_##name, \
994 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_##name), a); \
995 return vir_FMOV_dest(c, dest, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4)); \
999 #define VIR_A_ALU2(name) VIR_ALU2(name, vir_add_inst, V3D_QPU_A_##name)
1000 #define VIR_M_ALU2(name) VIR_ALU2(name, vir_mul_inst, V3D_QPU_M_##name)
1001 #define VIR_A_ALU1(name) VIR_ALU1(name, vir_add_inst, V3D_QPU_A_##name)
1002 #define VIR_M_ALU1(name) VIR_ALU1(name, vir_mul_inst, V3D_QPU_M_##name)
1003 #define VIR_A_ALU0(name) VIR_ALU0(name, vir_add_inst, V3D_QPU_A_##name)
1004 #define VIR_M_ALU0(name) VIR_ALU0(name, vir_mul_inst, V3D_QPU_M_##name)
1005 #define VIR_A_NODST_2(name) VIR_NODST_2(name, vir_add_inst, V3D_QPU_A_##name)
1006 #define VIR_M_NODST_2(name) VIR_NODST_2(name, vir_mul_inst, V3D_QPU_M_##name)
1007 #define VIR_A_NODST_1(name) VIR_NODST_1(name, vir_add_inst, V3D_QPU_A_##name)
1008 #define VIR_M_NODST_1(name) VIR_NODST_1(name, vir_mul_inst, V3D_QPU_M_##name)
1009 #define VIR_A_NODST_0(name) VIR_NODST_0(name, vir_add_inst, V3D_QPU_A_##name)
1032 VIR_A_NODST_2(STVPMV
)
1042 VIR_A_ALU1(LDVPMV_IN
)
1043 VIR_A_ALU1(LDVPMV_OUT
)
1044 VIR_A_ALU1(LDVPMD_IN
)
1045 VIR_A_ALU1(LDVPMD_OUT
)
1046 VIR_A_ALU2(LDVPMG_IN
)
1047 VIR_A_ALU2(LDVPMG_OUT
)
1057 VIR_A_ALU0(BARRIERID
)
1058 VIR_A_NODST_1(VPMSETUP
)
1059 VIR_A_NODST_0(VPMWT
)
1082 VIR_M_NODST_2(MULTOP
)
1094 static inline struct qinst
*
1095 vir_MOV_cond(struct v3d_compile
*c
, enum v3d_qpu_cond cond
,
1096 struct qreg dest
, struct qreg src
)
1098 struct qinst
*mov
= vir_MOV_dest(c
, dest
, src
);
1099 vir_set_cond(mov
, cond
);
1103 static inline struct qreg
1104 vir_SEL(struct v3d_compile
*c
, enum v3d_qpu_cond cond
,
1105 struct qreg src0
, struct qreg src1
)
1107 struct qreg t
= vir_get_temp(c
);
1108 vir_MOV_dest(c
, t
, src1
);
1109 vir_MOV_cond(c
, cond
, t
, src0
);
1113 static inline struct qinst
*
1114 vir_NOP(struct v3d_compile
*c
)
1116 return vir_emit_nondef(c
, vir_add_inst(V3D_QPU_A_NOP
,
1117 c
->undef
, c
->undef
, c
->undef
));
1120 static inline struct qreg
1121 vir_LDTMU(struct v3d_compile
*c
)
1123 if (c
->devinfo
->ver
>= 41) {
1124 struct qinst
*ldtmu
= vir_add_inst(V3D_QPU_A_NOP
, c
->undef
,
1125 c
->undef
, c
->undef
);
1126 ldtmu
->qpu
.sig
.ldtmu
= true;
1128 return vir_emit_def(c
, ldtmu
);
1130 vir_NOP(c
)->qpu
.sig
.ldtmu
= true;
1131 return vir_MOV(c
, vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_R4
));
1135 static inline struct qreg
1136 vir_UMUL(struct v3d_compile
*c
, struct qreg src0
, struct qreg src1
)
1138 vir_MULTOP(c
, src0
, src1
);
1139 return vir_UMUL24(c
, src0
, src1
);
1142 static inline struct qreg
1143 vir_TLBU_COLOR_READ(struct v3d_compile
*c
, uint32_t config
)
1145 assert(c
->devinfo
->ver
>= 41); /* XXX */
1146 assert((config
& 0xffffff00) == 0xffffff00);
1148 struct qinst
*ldtlb
= vir_add_inst(V3D_QPU_A_NOP
, c
->undef
,
1149 c
->undef
, c
->undef
);
1150 ldtlb
->qpu
.sig
.ldtlbu
= true;
1151 ldtlb
->uniform
= vir_get_uniform_index(c
, QUNIFORM_CONSTANT
, config
);
1152 return vir_emit_def(c
, ldtlb
);
1155 static inline struct qreg
1156 vir_TLB_COLOR_READ(struct v3d_compile
*c
)
1158 assert(c
->devinfo
->ver
>= 41); /* XXX */
1160 struct qinst
*ldtlb
= vir_add_inst(V3D_QPU_A_NOP
, c
->undef
,
1161 c
->undef
, c
->undef
);
1162 ldtlb
->qpu
.sig
.ldtlb
= true;
1163 return vir_emit_def(c
, ldtlb
);
1167 static inline struct qreg
1168 vir_LOAD_IMM(struct v3d_compile *c, uint32_t val)
1170 return vir_emit_def(c, vir_inst(QOP_LOAD_IMM, c->undef,
1171 vir_reg(QFILE_LOAD_IMM, val), c->undef));
1174 static inline struct qreg
1175 vir_LOAD_IMM_U2(struct v3d_compile *c, uint32_t val)
1177 return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_U2, c->undef,
1178 vir_reg(QFILE_LOAD_IMM, val),
1181 static inline struct qreg
1182 vir_LOAD_IMM_I2(struct v3d_compile *c, uint32_t val)
1184 return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_I2, c->undef,
1185 vir_reg(QFILE_LOAD_IMM, val),
1190 static inline struct qinst
*
1191 vir_BRANCH(struct v3d_compile
*c
, enum v3d_qpu_branch_cond cond
)
1193 /* The actual uniform_data value will be set at scheduling time */
1194 return vir_emit_nondef(c
, vir_branch_inst(c
, cond
));
1197 #define vir_for_each_block(block, c) \
1198 list_for_each_entry(struct qblock, block, &c->blocks, link)
1200 #define vir_for_each_block_rev(block, c) \
1201 list_for_each_entry_rev(struct qblock, block, &c->blocks, link)
1203 /* Loop over the non-NULL members of the successors array. */
1204 #define vir_for_each_successor(succ, block) \
1205 for (struct qblock *succ = block->successors[0]; \
1207 succ = (succ == block->successors[1] ? NULL : \
1208 block->successors[1]))
1210 #define vir_for_each_inst(inst, block) \
1211 list_for_each_entry(struct qinst, inst, &block->instructions, link)
1213 #define vir_for_each_inst_rev(inst, block) \
1214 list_for_each_entry_rev(struct qinst, inst, &block->instructions, link)
1216 #define vir_for_each_inst_safe(inst, block) \
1217 list_for_each_entry_safe(struct qinst, inst, &block->instructions, link)
1219 #define vir_for_each_inst_inorder(inst, c) \
1220 vir_for_each_block(_block, c) \
1221 vir_for_each_inst(inst, _block)
1223 #define vir_for_each_inst_inorder_safe(inst, c) \
1224 vir_for_each_block(_block, c) \
1225 vir_for_each_inst_safe(inst, _block)
1227 #endif /* V3D_COMPILER_H */