v3d: compute appropriate VPM memory configuration for geometry shader workloads
[mesa.git] / src / broadcom / compiler / v3d_compiler.h
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef V3D_COMPILER_H
25 #define V3D_COMPILER_H
26
27 #include <assert.h>
28 #include <stdio.h>
29 #include <stdlib.h>
30 #include <stdbool.h>
31 #include <stdint.h>
32 #include <string.h>
33
34 #include "util/macros.h"
35 #include "common/v3d_debug.h"
36 #include "common/v3d_device_info.h"
37 #include "common/v3d_limits.h"
38 #include "compiler/nir/nir.h"
39 #include "util/list.h"
40 #include "util/u_math.h"
41
42 #include "qpu/qpu_instr.h"
43 #include "pipe/p_state.h"
44
45 struct nir_builder;
46
47 struct v3d_fs_inputs {
48 /**
49 * Array of the meanings of the VPM inputs this shader needs.
50 *
51 * It doesn't include those that aren't part of the VPM, like
52 * point/line coordinates.
53 */
54 struct v3d_varying_slot *input_slots;
55 uint32_t num_inputs;
56 };
57
58 enum qfile {
59 /** An unused source or destination register. */
60 QFILE_NULL,
61
62 /** A physical register, such as the W coordinate payload. */
63 QFILE_REG,
64 /** One of the regsiters for fixed function interactions. */
65 QFILE_MAGIC,
66
67 /**
68 * A virtual register, that will be allocated to actual accumulator
69 * or physical registers later.
70 */
71 QFILE_TEMP,
72
73 /**
74 * VPM reads use this with an index value to say what part of the VPM
75 * is being read.
76 */
77 QFILE_VPM,
78
79 /**
80 * Stores an immediate value in the index field that will be used
81 * directly by qpu_load_imm().
82 */
83 QFILE_LOAD_IMM,
84
85 /**
86 * Stores an immediate value in the index field that can be turned
87 * into a small immediate field by qpu_encode_small_immediate().
88 */
89 QFILE_SMALL_IMM,
90 };
91
92 /**
93 * A reference to a QPU register or a virtual temp register.
94 */
95 struct qreg {
96 enum qfile file;
97 uint32_t index;
98 };
99
100 static inline struct qreg vir_reg(enum qfile file, uint32_t index)
101 {
102 return (struct qreg){file, index};
103 }
104
105 static inline struct qreg vir_magic_reg(uint32_t index)
106 {
107 return (struct qreg){QFILE_MAGIC, index};
108 }
109
110 static inline struct qreg vir_nop_reg(void)
111 {
112 return (struct qreg){QFILE_NULL, 0};
113 }
114
115 /**
116 * A reference to an actual register at the QPU level, for register
117 * allocation.
118 */
119 struct qpu_reg {
120 bool magic;
121 bool smimm;
122 int index;
123 };
124
125 struct qinst {
126 /** Entry in qblock->instructions */
127 struct list_head link;
128
129 /**
130 * The instruction being wrapped. Its condition codes, pack flags,
131 * signals, etc. will all be used, with just the register references
132 * being replaced by the contents of qinst->dst and qinst->src[].
133 */
134 struct v3d_qpu_instr qpu;
135
136 /* Pre-register-allocation references to src/dst registers */
137 struct qreg dst;
138 struct qreg src[3];
139 bool is_last_thrsw;
140
141 /* If the instruction reads a uniform (other than through src[i].file
142 * == QFILE_UNIF), that uniform's index in c->uniform_contents. ~0
143 * otherwise.
144 */
145 int uniform;
146 };
147
148 enum quniform_contents {
149 /**
150 * Indicates that a constant 32-bit value is copied from the program's
151 * uniform contents.
152 */
153 QUNIFORM_CONSTANT,
154 /**
155 * Indicates that the program's uniform contents are used as an index
156 * into the GL uniform storage.
157 */
158 QUNIFORM_UNIFORM,
159
160 /** @{
161 * Scaling factors from clip coordinates to relative to the viewport
162 * center.
163 *
164 * This is used by the coordinate and vertex shaders to produce the
165 * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
166 * point offsets from the viewport ccenter.
167 */
168 QUNIFORM_VIEWPORT_X_SCALE,
169 QUNIFORM_VIEWPORT_Y_SCALE,
170 /** @} */
171
172 QUNIFORM_VIEWPORT_Z_OFFSET,
173 QUNIFORM_VIEWPORT_Z_SCALE,
174
175 QUNIFORM_USER_CLIP_PLANE,
176
177 /**
178 * A reference to a V3D 3.x texture config parameter 0 uniform.
179 *
180 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
181 * defines texture type, miplevels, and such. It will be found as a
182 * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
183 */
184 QUNIFORM_TEXTURE_CONFIG_P0_0,
185 QUNIFORM_TEXTURE_CONFIG_P0_1,
186 QUNIFORM_TEXTURE_CONFIG_P0_2,
187 QUNIFORM_TEXTURE_CONFIG_P0_3,
188 QUNIFORM_TEXTURE_CONFIG_P0_4,
189 QUNIFORM_TEXTURE_CONFIG_P0_5,
190 QUNIFORM_TEXTURE_CONFIG_P0_6,
191 QUNIFORM_TEXTURE_CONFIG_P0_7,
192 QUNIFORM_TEXTURE_CONFIG_P0_8,
193 QUNIFORM_TEXTURE_CONFIG_P0_9,
194 QUNIFORM_TEXTURE_CONFIG_P0_10,
195 QUNIFORM_TEXTURE_CONFIG_P0_11,
196 QUNIFORM_TEXTURE_CONFIG_P0_12,
197 QUNIFORM_TEXTURE_CONFIG_P0_13,
198 QUNIFORM_TEXTURE_CONFIG_P0_14,
199 QUNIFORM_TEXTURE_CONFIG_P0_15,
200 QUNIFORM_TEXTURE_CONFIG_P0_16,
201 QUNIFORM_TEXTURE_CONFIG_P0_17,
202 QUNIFORM_TEXTURE_CONFIG_P0_18,
203 QUNIFORM_TEXTURE_CONFIG_P0_19,
204 QUNIFORM_TEXTURE_CONFIG_P0_20,
205 QUNIFORM_TEXTURE_CONFIG_P0_21,
206 QUNIFORM_TEXTURE_CONFIG_P0_22,
207 QUNIFORM_TEXTURE_CONFIG_P0_23,
208 QUNIFORM_TEXTURE_CONFIG_P0_24,
209 QUNIFORM_TEXTURE_CONFIG_P0_25,
210 QUNIFORM_TEXTURE_CONFIG_P0_26,
211 QUNIFORM_TEXTURE_CONFIG_P0_27,
212 QUNIFORM_TEXTURE_CONFIG_P0_28,
213 QUNIFORM_TEXTURE_CONFIG_P0_29,
214 QUNIFORM_TEXTURE_CONFIG_P0_30,
215 QUNIFORM_TEXTURE_CONFIG_P0_31,
216 QUNIFORM_TEXTURE_CONFIG_P0_32,
217
218 /**
219 * A reference to a V3D 3.x texture config parameter 1 uniform.
220 *
221 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
222 * has the pointer to the indirect texture state. Our data[] field
223 * will have a packed p1 value, but the address field will be just
224 * which texture unit's texture should be referenced.
225 */
226 QUNIFORM_TEXTURE_CONFIG_P1,
227
228 /* A V3D 4.x texture config parameter. The high 8 bits will be
229 * which texture or sampler is being sampled, and the driver must
230 * replace the address field with the appropriate address.
231 */
232 QUNIFORM_TMU_CONFIG_P0,
233 QUNIFORM_TMU_CONFIG_P1,
234
235 QUNIFORM_IMAGE_TMU_CONFIG_P0,
236
237 QUNIFORM_TEXTURE_FIRST_LEVEL,
238
239 QUNIFORM_TEXTURE_WIDTH,
240 QUNIFORM_TEXTURE_HEIGHT,
241 QUNIFORM_TEXTURE_DEPTH,
242 QUNIFORM_TEXTURE_ARRAY_SIZE,
243 QUNIFORM_TEXTURE_LEVELS,
244
245 QUNIFORM_UBO_ADDR,
246
247 QUNIFORM_TEXRECT_SCALE_X,
248 QUNIFORM_TEXRECT_SCALE_Y,
249
250 /* Returns the base offset of the SSBO given by the data value. */
251 QUNIFORM_SSBO_OFFSET,
252
253 /* Returns the size of the SSBO given by the data value. */
254 QUNIFORM_GET_BUFFER_SIZE,
255
256 /* Sizes (in pixels) of a shader image given by the data value. */
257 QUNIFORM_IMAGE_WIDTH,
258 QUNIFORM_IMAGE_HEIGHT,
259 QUNIFORM_IMAGE_DEPTH,
260 QUNIFORM_IMAGE_ARRAY_SIZE,
261
262 QUNIFORM_ALPHA_REF,
263
264 /* Number of workgroups passed to glDispatchCompute in the dimension
265 * selected by the data value.
266 */
267 QUNIFORM_NUM_WORK_GROUPS,
268
269 /**
270 * Returns the the offset of the scratch buffer for register spilling.
271 */
272 QUNIFORM_SPILL_OFFSET,
273 QUNIFORM_SPILL_SIZE_PER_THREAD,
274
275 /**
276 * Returns the offset of the shared memory for compute shaders.
277 *
278 * This will be accessed using TMU general memory operations, so the
279 * L2T cache will effectively be the shared memory area.
280 */
281 QUNIFORM_SHARED_OFFSET,
282 };
283
284 static inline uint32_t v3d_unit_data_create(uint32_t unit, uint32_t value)
285 {
286 assert(value < (1 << 24));
287 return unit << 24 | value;
288 }
289
290 static inline uint32_t v3d_unit_data_get_unit(uint32_t data)
291 {
292 return data >> 24;
293 }
294
295 static inline uint32_t v3d_unit_data_get_offset(uint32_t data)
296 {
297 return data & 0xffffff;
298 }
299
300 struct v3d_varying_slot {
301 uint8_t slot_and_component;
302 };
303
304 static inline struct v3d_varying_slot
305 v3d_slot_from_slot_and_component(uint8_t slot, uint8_t component)
306 {
307 assert(slot < 255 / 4);
308 return (struct v3d_varying_slot){ (slot << 2) + component };
309 }
310
311 static inline uint8_t v3d_slot_get_slot(struct v3d_varying_slot slot)
312 {
313 return slot.slot_and_component >> 2;
314 }
315
316 static inline uint8_t v3d_slot_get_component(struct v3d_varying_slot slot)
317 {
318 return slot.slot_and_component & 3;
319 }
320
321 struct v3d_key {
322 void *shader_state;
323 struct {
324 uint8_t swizzle[4];
325 uint8_t return_size;
326 uint8_t return_channels;
327 bool clamp_s:1;
328 bool clamp_t:1;
329 bool clamp_r:1;
330 } tex[V3D_MAX_TEXTURE_SAMPLERS];
331 uint8_t ucp_enables;
332 bool is_last_geometry_stage;
333 };
334
335 struct v3d_fs_key {
336 struct v3d_key base;
337 bool depth_enabled;
338 bool is_points;
339 bool is_lines;
340 bool alpha_test;
341 bool point_coord_upper_left;
342 bool light_twoside;
343 bool msaa;
344 bool sample_coverage;
345 bool sample_alpha_to_coverage;
346 bool sample_alpha_to_one;
347 bool clamp_color;
348 bool shade_model_flat;
349 /* Mask of which color render targets are present. */
350 uint8_t cbufs;
351 uint8_t swap_color_rb;
352 /* Mask of which render targets need to be written as 32-bit floats */
353 uint8_t f32_color_rb;
354 /* Masks of which render targets need to be written as ints/uints.
355 * Used by gallium to work around lost information in TGSI.
356 */
357 uint8_t int_color_rb;
358 uint8_t uint_color_rb;
359
360 /* Color format information per render target. Only set when logic
361 * operations are enabled.
362 */
363 struct {
364 enum pipe_format format;
365 const uint8_t *swizzle;
366 } color_fmt[V3D_MAX_DRAW_BUFFERS];
367
368 uint8_t alpha_test_func;
369 uint8_t logicop_func;
370 uint32_t point_sprite_mask;
371
372 struct pipe_rt_blend_state blend;
373 };
374
375 struct v3d_gs_key {
376 struct v3d_key base;
377
378 struct v3d_varying_slot used_outputs[V3D_MAX_FS_INPUTS];
379 uint8_t num_used_outputs;
380
381 bool is_coord;
382 bool per_vertex_point_size;
383 };
384
385 struct v3d_vs_key {
386 struct v3d_key base;
387
388 struct v3d_varying_slot used_outputs[V3D_MAX_ANY_STAGE_INPUTS];
389 uint8_t num_used_outputs;
390
391 bool is_coord;
392 bool per_vertex_point_size;
393 bool clamp_color;
394 };
395
396 /** A basic block of VIR intructions. */
397 struct qblock {
398 struct list_head link;
399
400 struct list_head instructions;
401
402 struct set *predecessors;
403 struct qblock *successors[2];
404
405 int index;
406
407 /* Instruction IPs for the first and last instruction of the block.
408 * Set by qpu_schedule.c.
409 */
410 uint32_t start_qpu_ip;
411 uint32_t end_qpu_ip;
412
413 /* Instruction IP for the branch instruction of the block. Set by
414 * qpu_schedule.c.
415 */
416 uint32_t branch_qpu_ip;
417
418 /** Offset within the uniform stream at the start of the block. */
419 uint32_t start_uniform;
420 /** Offset within the uniform stream of the branch instruction */
421 uint32_t branch_uniform;
422
423 /** @{ used by v3d_vir_live_variables.c */
424 BITSET_WORD *def;
425 BITSET_WORD *defin;
426 BITSET_WORD *defout;
427 BITSET_WORD *use;
428 BITSET_WORD *live_in;
429 BITSET_WORD *live_out;
430 int start_ip, end_ip;
431 /** @} */
432 };
433
434 /** Which util/list.h add mode we should use when inserting an instruction. */
435 enum vir_cursor_mode {
436 vir_cursor_add,
437 vir_cursor_addtail,
438 };
439
440 /**
441 * Tracking structure for where new instructions should be inserted. Create
442 * with one of the vir_after_inst()-style helper functions.
443 *
444 * This does not protect against removal of the block or instruction, so we
445 * have an assert in instruction removal to try to catch it.
446 */
447 struct vir_cursor {
448 enum vir_cursor_mode mode;
449 struct list_head *link;
450 };
451
452 static inline struct vir_cursor
453 vir_before_inst(struct qinst *inst)
454 {
455 return (struct vir_cursor){ vir_cursor_addtail, &inst->link };
456 }
457
458 static inline struct vir_cursor
459 vir_after_inst(struct qinst *inst)
460 {
461 return (struct vir_cursor){ vir_cursor_add, &inst->link };
462 }
463
464 static inline struct vir_cursor
465 vir_before_block(struct qblock *block)
466 {
467 return (struct vir_cursor){ vir_cursor_add, &block->instructions };
468 }
469
470 static inline struct vir_cursor
471 vir_after_block(struct qblock *block)
472 {
473 return (struct vir_cursor){ vir_cursor_addtail, &block->instructions };
474 }
475
476 /**
477 * Compiler state saved across compiler invocations, for any expensive global
478 * setup.
479 */
480 struct v3d_compiler {
481 const struct v3d_device_info *devinfo;
482 struct ra_regs *regs;
483 unsigned int reg_class_any[3];
484 unsigned int reg_class_r5[3];
485 unsigned int reg_class_phys[3];
486 unsigned int reg_class_phys_or_acc[3];
487 };
488
489 struct v3d_compile {
490 const struct v3d_device_info *devinfo;
491 nir_shader *s;
492 nir_function_impl *impl;
493 struct exec_list *cf_node_list;
494 const struct v3d_compiler *compiler;
495
496 void (*debug_output)(const char *msg,
497 void *debug_output_data);
498 void *debug_output_data;
499
500 /**
501 * Mapping from nir_register * or nir_ssa_def * to array of struct
502 * qreg for the values.
503 */
504 struct hash_table *def_ht;
505
506 /* For each temp, the instruction generating its value. */
507 struct qinst **defs;
508 uint32_t defs_array_size;
509
510 /**
511 * Inputs to the shader, arranged by TGSI declaration order.
512 *
513 * Not all fragment shader QFILE_VARY reads are present in this array.
514 */
515 struct qreg *inputs;
516 struct qreg *outputs;
517 bool msaa_per_sample_output;
518 struct qreg color_reads[V3D_MAX_DRAW_BUFFERS * V3D_MAX_SAMPLES * 4];
519 struct qreg sample_colors[V3D_MAX_DRAW_BUFFERS * V3D_MAX_SAMPLES * 4];
520 uint32_t inputs_array_size;
521 uint32_t outputs_array_size;
522 uint32_t uniforms_array_size;
523
524 /* Booleans for whether the corresponding QFILE_VARY[i] is
525 * flat-shaded. This includes gl_FragColor flat-shading, which is
526 * customized based on the shademodel_flat shader key.
527 */
528 uint32_t flat_shade_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
529
530 uint32_t noperspective_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
531
532 uint32_t centroid_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
533
534 bool uses_center_w;
535 bool writes_z;
536 bool uses_implicit_point_line_varyings;
537
538 /* State for whether we're executing on each channel currently. 0 if
539 * yes, otherwise a block number + 1 that the channel jumped to.
540 */
541 struct qreg execute;
542 bool in_control_flow;
543
544 struct qreg line_x, point_x, point_y;
545
546 /**
547 * Instance ID, which comes in before the vertex attribute payload if
548 * the shader record requests it.
549 */
550 struct qreg iid;
551
552 /**
553 * Vertex ID, which comes in before the vertex attribute payload
554 * (after Instance ID) if the shader record requests it.
555 */
556 struct qreg vid;
557
558 /* Fragment shader payload regs. */
559 struct qreg payload_w, payload_w_centroid, payload_z;
560
561 struct qreg cs_payload[2];
562 struct qreg cs_shared_offset;
563 int local_invocation_index_bits;
564
565 uint8_t vattr_sizes[V3D_MAX_VS_INPUTS / 4];
566 uint8_t gs_input_sizes[V3D_MAX_GS_INPUTS];
567 uint32_t vpm_output_size;
568
569 /* Size in bytes of registers that have been spilled. This is how much
570 * space needs to be available in the spill BO per thread per QPU.
571 */
572 uint32_t spill_size;
573 /* Shader-db stats */
574 uint32_t spills, fills, loops;
575 /**
576 * Register spilling's per-thread base address, shared between each
577 * spill/fill's addressing calculations.
578 */
579 struct qreg spill_base;
580 /* Bit vector of which temps may be spilled */
581 BITSET_WORD *spillable;
582
583 /**
584 * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
585 *
586 * This includes those that aren't part of the VPM varyings, like
587 * point/line coordinates.
588 */
589 struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
590
591 /**
592 * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
593 * of the output is. Used to emit from the VS in the order that the
594 * FS needs.
595 */
596 struct v3d_varying_slot *output_slots;
597
598 struct pipe_shader_state *shader_state;
599 struct v3d_key *key;
600 struct v3d_fs_key *fs_key;
601 struct v3d_gs_key *gs_key;
602 struct v3d_vs_key *vs_key;
603
604 /* Live ranges of temps. */
605 int *temp_start, *temp_end;
606 bool live_intervals_valid;
607
608 uint32_t *uniform_data;
609 enum quniform_contents *uniform_contents;
610 uint32_t uniform_array_size;
611 uint32_t num_uniforms;
612 uint32_t output_position_index;
613 nir_variable *output_color_var[4];
614 uint32_t output_sample_mask_index;
615
616 struct qreg undef;
617 uint32_t num_temps;
618
619 struct vir_cursor cursor;
620 struct list_head blocks;
621 int next_block_index;
622 struct qblock *cur_block;
623 struct qblock *loop_cont_block;
624 struct qblock *loop_break_block;
625
626 uint64_t *qpu_insts;
627 uint32_t qpu_inst_count;
628 uint32_t qpu_inst_size;
629 uint32_t qpu_inst_stalled_count;
630
631 /* For the FS, the number of varying inputs not counting the
632 * point/line varyings payload
633 */
634 uint32_t num_inputs;
635
636 uint32_t program_id;
637 uint32_t variant_id;
638
639 /* Set to compile program in in 1x, 2x, or 4x threaded mode, where
640 * SIG_THREAD_SWITCH is used to hide texturing latency at the cost of
641 * limiting ourselves to the part of the physical reg space.
642 *
643 * On V3D 3.x, 2x or 4x divide the physical reg space by 2x or 4x. On
644 * V3D 4.x, all shaders are 2x threaded, and 4x only divides the
645 * physical reg space in half.
646 */
647 uint8_t threads;
648 struct qinst *last_thrsw;
649 bool last_thrsw_at_top_level;
650
651 bool emitted_tlb_load;
652 bool lock_scoreboard_on_first_thrsw;
653
654 bool failed;
655
656 bool tmu_dirty_rcl;
657 };
658
659 struct v3d_uniform_list {
660 enum quniform_contents *contents;
661 uint32_t *data;
662 uint32_t count;
663 };
664
665 struct v3d_prog_data {
666 struct v3d_uniform_list uniforms;
667
668 uint32_t spill_size;
669
670 uint8_t threads;
671
672 /* For threads > 1, whether the program should be dispatched in the
673 * after-final-THRSW state.
674 */
675 bool single_seg;
676
677 bool tmu_dirty_rcl;
678 };
679
680 struct v3d_vs_prog_data {
681 struct v3d_prog_data base;
682
683 bool uses_iid, uses_vid;
684
685 /* Number of components read from each vertex attribute. */
686 uint8_t vattr_sizes[V3D_MAX_VS_INPUTS / 4];
687
688 /* Total number of components read, for the shader state record. */
689 uint32_t vpm_input_size;
690
691 /* Total number of components written, for the shader state record. */
692 uint32_t vpm_output_size;
693
694 /* Set if there should be separate VPM segments for input and output.
695 * If unset, vpm_input_size will be 0.
696 */
697 bool separate_segments;
698
699 /* Value to be programmed in VCM_CACHE_SIZE. */
700 uint8_t vcm_cache_size;
701 };
702
703 struct v3d_gs_prog_data {
704 struct v3d_prog_data base;
705
706 /* Whether the program reads gl_PrimitiveIDIn */
707 bool uses_pid;
708
709 /* Number of components read from each input varying. */
710 uint8_t input_sizes[V3D_MAX_GS_INPUTS / 4];
711
712 /* Number of inputs */
713 uint8_t num_inputs;
714 struct v3d_varying_slot input_slots[V3D_MAX_GS_INPUTS];
715
716 /* Total number of components written, for the shader state record. */
717 uint32_t vpm_output_size;
718
719 /* Maximum SIMD dispatch width to not exceed VPM output size limits
720 * in the geometry shader. Notice that the final dispatch width has to
721 * be decided at draw time and could be lower based on the VPM pressure
722 * added by other shader stages.
723 */
724 uint8_t simd_width;
725
726 /* Output primitive type */
727 uint8_t out_prim_type;
728
729 /* Number of GS invocations */
730 uint8_t num_invocations;
731 };
732
733 struct v3d_fs_prog_data {
734 struct v3d_prog_data base;
735
736 struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
737
738 /* Array of flat shade flags.
739 *
740 * Each entry is only 24 bits (high 8 bits 0), to match the hardware
741 * packet layout.
742 */
743 uint32_t flat_shade_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
744
745 uint32_t noperspective_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
746
747 uint32_t centroid_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
748
749 uint8_t num_inputs;
750 bool writes_z;
751 bool disable_ez;
752 bool uses_center_w;
753 bool uses_implicit_point_line_varyings;
754 bool lock_scoreboard_on_first_thrsw;
755 };
756
757 struct v3d_compute_prog_data {
758 struct v3d_prog_data base;
759 /* Size in bytes of the workgroup's shared space. */
760 uint32_t shared_size;
761 };
762
763 static inline bool
764 vir_has_uniform(struct qinst *inst)
765 {
766 return inst->uniform != ~0;
767 }
768
769 extern const nir_shader_compiler_options v3d_nir_options;
770
771 const struct v3d_compiler *v3d_compiler_init(const struct v3d_device_info *devinfo);
772 void v3d_compiler_free(const struct v3d_compiler *compiler);
773 void v3d_optimize_nir(struct nir_shader *s);
774
775 uint64_t *v3d_compile(const struct v3d_compiler *compiler,
776 struct v3d_key *key,
777 struct v3d_prog_data **prog_data,
778 nir_shader *s,
779 void (*debug_output)(const char *msg,
780 void *debug_output_data),
781 void *debug_output_data,
782 int program_id, int variant_id,
783 uint32_t *final_assembly_size);
784
785 void v3d_nir_to_vir(struct v3d_compile *c);
786
787 void vir_compile_destroy(struct v3d_compile *c);
788 const char *vir_get_stage_name(struct v3d_compile *c);
789 struct qblock *vir_new_block(struct v3d_compile *c);
790 void vir_set_emit_block(struct v3d_compile *c, struct qblock *block);
791 void vir_link_blocks(struct qblock *predecessor, struct qblock *successor);
792 struct qblock *vir_entry_block(struct v3d_compile *c);
793 struct qblock *vir_exit_block(struct v3d_compile *c);
794 struct qinst *vir_add_inst(enum v3d_qpu_add_op op, struct qreg dst,
795 struct qreg src0, struct qreg src1);
796 struct qinst *vir_mul_inst(enum v3d_qpu_mul_op op, struct qreg dst,
797 struct qreg src0, struct qreg src1);
798 struct qinst *vir_branch_inst(struct v3d_compile *c,
799 enum v3d_qpu_branch_cond cond);
800 void vir_remove_instruction(struct v3d_compile *c, struct qinst *qinst);
801 uint32_t vir_get_uniform_index(struct v3d_compile *c,
802 enum quniform_contents contents,
803 uint32_t data);
804 struct qreg vir_uniform(struct v3d_compile *c,
805 enum quniform_contents contents,
806 uint32_t data);
807 void vir_schedule_instructions(struct v3d_compile *c);
808 void v3d_setup_spill_base(struct v3d_compile *c);
809 struct v3d_qpu_instr v3d_qpu_nop(void);
810
811 struct qreg vir_emit_def(struct v3d_compile *c, struct qinst *inst);
812 struct qinst *vir_emit_nondef(struct v3d_compile *c, struct qinst *inst);
813 void vir_set_cond(struct qinst *inst, enum v3d_qpu_cond cond);
814 void vir_set_pf(struct qinst *inst, enum v3d_qpu_pf pf);
815 void vir_set_uf(struct qinst *inst, enum v3d_qpu_uf uf);
816 void vir_set_unpack(struct qinst *inst, int src,
817 enum v3d_qpu_input_unpack unpack);
818
819 struct qreg vir_get_temp(struct v3d_compile *c);
820 void vir_emit_last_thrsw(struct v3d_compile *c);
821 void vir_calculate_live_intervals(struct v3d_compile *c);
822 int vir_get_nsrc(struct qinst *inst);
823 bool vir_has_side_effects(struct v3d_compile *c, struct qinst *inst);
824 bool vir_get_add_op(struct qinst *inst, enum v3d_qpu_add_op *op);
825 bool vir_get_mul_op(struct qinst *inst, enum v3d_qpu_mul_op *op);
826 bool vir_is_raw_mov(struct qinst *inst);
827 bool vir_is_tex(struct qinst *inst);
828 bool vir_is_add(struct qinst *inst);
829 bool vir_is_mul(struct qinst *inst);
830 bool vir_writes_r3(const struct v3d_device_info *devinfo, struct qinst *inst);
831 bool vir_writes_r4(const struct v3d_device_info *devinfo, struct qinst *inst);
832 struct qreg vir_follow_movs(struct v3d_compile *c, struct qreg reg);
833 uint8_t vir_channels_written(struct qinst *inst);
834 struct qreg ntq_get_src(struct v3d_compile *c, nir_src src, int i);
835 void ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
836 struct qreg result);
837 void vir_emit_thrsw(struct v3d_compile *c);
838
839 void vir_dump(struct v3d_compile *c);
840 void vir_dump_inst(struct v3d_compile *c, struct qinst *inst);
841 void vir_dump_uniform(enum quniform_contents contents, uint32_t data);
842
843 void vir_validate(struct v3d_compile *c);
844
845 void vir_optimize(struct v3d_compile *c);
846 bool vir_opt_algebraic(struct v3d_compile *c);
847 bool vir_opt_constant_folding(struct v3d_compile *c);
848 bool vir_opt_copy_propagate(struct v3d_compile *c);
849 bool vir_opt_dead_code(struct v3d_compile *c);
850 bool vir_opt_peephole_sf(struct v3d_compile *c);
851 bool vir_opt_redundant_flags(struct v3d_compile *c);
852 bool vir_opt_small_immediates(struct v3d_compile *c);
853 bool vir_opt_vpm(struct v3d_compile *c);
854 void v3d_nir_lower_blend(nir_shader *s, struct v3d_compile *c);
855 void v3d_nir_lower_io(nir_shader *s, struct v3d_compile *c);
856 void v3d_nir_lower_logic_ops(nir_shader *s, struct v3d_compile *c);
857 void v3d_nir_lower_scratch(nir_shader *s);
858 void v3d_nir_lower_txf_ms(nir_shader *s, struct v3d_compile *c);
859 void v3d_nir_lower_image_load_store(nir_shader *s);
860 void vir_lower_uniforms(struct v3d_compile *c);
861
862 void v3d33_vir_vpm_read_setup(struct v3d_compile *c, int num_components);
863 void v3d33_vir_vpm_write_setup(struct v3d_compile *c);
864 void v3d33_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr);
865 void v3d40_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr);
866 void v3d40_vir_emit_image_load_store(struct v3d_compile *c,
867 nir_intrinsic_instr *instr);
868
869 void v3d_vir_to_qpu(struct v3d_compile *c, struct qpu_reg *temp_registers);
870 uint32_t v3d_qpu_schedule_instructions(struct v3d_compile *c);
871 void qpu_validate(struct v3d_compile *c);
872 struct qpu_reg *v3d_register_allocate(struct v3d_compile *c, bool *spilled);
873 bool vir_init_reg_sets(struct v3d_compiler *compiler);
874
875 bool v3d_gl_format_is_return_32(GLenum format);
876
877 uint32_t
878 v3d_get_op_for_atomic_add(nir_intrinsic_instr *instr, unsigned src);
879
880 static inline bool
881 quniform_contents_is_texture_p0(enum quniform_contents contents)
882 {
883 return (contents >= QUNIFORM_TEXTURE_CONFIG_P0_0 &&
884 contents < (QUNIFORM_TEXTURE_CONFIG_P0_0 +
885 V3D_MAX_TEXTURE_SAMPLERS));
886 }
887
888 static inline bool
889 vir_in_nonuniform_control_flow(struct v3d_compile *c)
890 {
891 return c->execute.file != QFILE_NULL;
892 }
893
894 static inline struct qreg
895 vir_uniform_ui(struct v3d_compile *c, uint32_t ui)
896 {
897 return vir_uniform(c, QUNIFORM_CONSTANT, ui);
898 }
899
900 static inline struct qreg
901 vir_uniform_f(struct v3d_compile *c, float f)
902 {
903 return vir_uniform(c, QUNIFORM_CONSTANT, fui(f));
904 }
905
906 #define VIR_ALU0(name, vir_inst, op) \
907 static inline struct qreg \
908 vir_##name(struct v3d_compile *c) \
909 { \
910 return vir_emit_def(c, vir_inst(op, c->undef, \
911 c->undef, c->undef)); \
912 } \
913 static inline struct qinst * \
914 vir_##name##_dest(struct v3d_compile *c, struct qreg dest) \
915 { \
916 return vir_emit_nondef(c, vir_inst(op, dest, \
917 c->undef, c->undef)); \
918 }
919
920 #define VIR_ALU1(name, vir_inst, op) \
921 static inline struct qreg \
922 vir_##name(struct v3d_compile *c, struct qreg a) \
923 { \
924 return vir_emit_def(c, vir_inst(op, c->undef, \
925 a, c->undef)); \
926 } \
927 static inline struct qinst * \
928 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
929 struct qreg a) \
930 { \
931 return vir_emit_nondef(c, vir_inst(op, dest, a, \
932 c->undef)); \
933 }
934
935 #define VIR_ALU2(name, vir_inst, op) \
936 static inline struct qreg \
937 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b) \
938 { \
939 return vir_emit_def(c, vir_inst(op, c->undef, a, b)); \
940 } \
941 static inline struct qinst * \
942 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
943 struct qreg a, struct qreg b) \
944 { \
945 return vir_emit_nondef(c, vir_inst(op, dest, a, b)); \
946 }
947
948 #define VIR_NODST_0(name, vir_inst, op) \
949 static inline struct qinst * \
950 vir_##name(struct v3d_compile *c) \
951 { \
952 return vir_emit_nondef(c, vir_inst(op, c->undef, \
953 c->undef, c->undef)); \
954 }
955
956 #define VIR_NODST_1(name, vir_inst, op) \
957 static inline struct qinst * \
958 vir_##name(struct v3d_compile *c, struct qreg a) \
959 { \
960 return vir_emit_nondef(c, vir_inst(op, c->undef, \
961 a, c->undef)); \
962 }
963
964 #define VIR_NODST_2(name, vir_inst, op) \
965 static inline struct qinst * \
966 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b) \
967 { \
968 return vir_emit_nondef(c, vir_inst(op, c->undef, \
969 a, b)); \
970 }
971
972 #define VIR_SFU(name) \
973 static inline struct qreg \
974 vir_##name(struct v3d_compile *c, struct qreg a) \
975 { \
976 if (c->devinfo->ver >= 41) { \
977 return vir_emit_def(c, vir_add_inst(V3D_QPU_A_##name, \
978 c->undef, \
979 a, c->undef)); \
980 } else { \
981 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_##name), a); \
982 return vir_FMOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4)); \
983 } \
984 } \
985 static inline struct qinst * \
986 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
987 struct qreg a) \
988 { \
989 if (c->devinfo->ver >= 41) { \
990 return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_##name, \
991 dest, \
992 a, c->undef)); \
993 } else { \
994 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_##name), a); \
995 return vir_FMOV_dest(c, dest, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4)); \
996 } \
997 }
998
999 #define VIR_A_ALU2(name) VIR_ALU2(name, vir_add_inst, V3D_QPU_A_##name)
1000 #define VIR_M_ALU2(name) VIR_ALU2(name, vir_mul_inst, V3D_QPU_M_##name)
1001 #define VIR_A_ALU1(name) VIR_ALU1(name, vir_add_inst, V3D_QPU_A_##name)
1002 #define VIR_M_ALU1(name) VIR_ALU1(name, vir_mul_inst, V3D_QPU_M_##name)
1003 #define VIR_A_ALU0(name) VIR_ALU0(name, vir_add_inst, V3D_QPU_A_##name)
1004 #define VIR_M_ALU0(name) VIR_ALU0(name, vir_mul_inst, V3D_QPU_M_##name)
1005 #define VIR_A_NODST_2(name) VIR_NODST_2(name, vir_add_inst, V3D_QPU_A_##name)
1006 #define VIR_M_NODST_2(name) VIR_NODST_2(name, vir_mul_inst, V3D_QPU_M_##name)
1007 #define VIR_A_NODST_1(name) VIR_NODST_1(name, vir_add_inst, V3D_QPU_A_##name)
1008 #define VIR_M_NODST_1(name) VIR_NODST_1(name, vir_mul_inst, V3D_QPU_M_##name)
1009 #define VIR_A_NODST_0(name) VIR_NODST_0(name, vir_add_inst, V3D_QPU_A_##name)
1010
1011 VIR_A_ALU2(FADD)
1012 VIR_A_ALU2(VFPACK)
1013 VIR_A_ALU2(FSUB)
1014 VIR_A_ALU2(FMIN)
1015 VIR_A_ALU2(FMAX)
1016
1017 VIR_A_ALU2(ADD)
1018 VIR_A_ALU2(SUB)
1019 VIR_A_ALU2(SHL)
1020 VIR_A_ALU2(SHR)
1021 VIR_A_ALU2(ASR)
1022 VIR_A_ALU2(ROR)
1023 VIR_A_ALU2(MIN)
1024 VIR_A_ALU2(MAX)
1025 VIR_A_ALU2(UMIN)
1026 VIR_A_ALU2(UMAX)
1027 VIR_A_ALU2(AND)
1028 VIR_A_ALU2(OR)
1029 VIR_A_ALU2(XOR)
1030 VIR_A_ALU2(VADD)
1031 VIR_A_ALU2(VSUB)
1032 VIR_A_NODST_2(STVPMV)
1033 VIR_A_ALU1(NOT)
1034 VIR_A_ALU1(NEG)
1035 VIR_A_ALU1(FLAPUSH)
1036 VIR_A_ALU1(FLBPUSH)
1037 VIR_A_ALU1(FLPOP)
1038 VIR_A_ALU1(SETMSF)
1039 VIR_A_ALU1(SETREVF)
1040 VIR_A_ALU0(TIDX)
1041 VIR_A_ALU0(EIDX)
1042 VIR_A_ALU1(LDVPMV_IN)
1043 VIR_A_ALU1(LDVPMV_OUT)
1044 VIR_A_ALU1(LDVPMD_IN)
1045 VIR_A_ALU1(LDVPMD_OUT)
1046 VIR_A_ALU2(LDVPMG_IN)
1047 VIR_A_ALU2(LDVPMG_OUT)
1048 VIR_A_ALU0(TMUWT)
1049
1050 VIR_A_ALU0(IID)
1051 VIR_A_ALU0(FXCD)
1052 VIR_A_ALU0(XCD)
1053 VIR_A_ALU0(FYCD)
1054 VIR_A_ALU0(YCD)
1055 VIR_A_ALU0(MSF)
1056 VIR_A_ALU0(REVF)
1057 VIR_A_ALU0(BARRIERID)
1058 VIR_A_NODST_1(VPMSETUP)
1059 VIR_A_NODST_0(VPMWT)
1060 VIR_A_ALU2(FCMP)
1061 VIR_A_ALU2(VFMAX)
1062
1063 VIR_A_ALU1(FROUND)
1064 VIR_A_ALU1(FTOIN)
1065 VIR_A_ALU1(FTRUNC)
1066 VIR_A_ALU1(FTOIZ)
1067 VIR_A_ALU1(FFLOOR)
1068 VIR_A_ALU1(FTOUZ)
1069 VIR_A_ALU1(FCEIL)
1070 VIR_A_ALU1(FTOC)
1071
1072 VIR_A_ALU1(FDX)
1073 VIR_A_ALU1(FDY)
1074
1075 VIR_A_ALU1(ITOF)
1076 VIR_A_ALU1(CLZ)
1077 VIR_A_ALU1(UTOF)
1078
1079 VIR_M_ALU2(UMUL24)
1080 VIR_M_ALU2(FMUL)
1081 VIR_M_ALU2(SMUL24)
1082 VIR_M_NODST_2(MULTOP)
1083
1084 VIR_M_ALU1(MOV)
1085 VIR_M_ALU1(FMOV)
1086
1087 VIR_SFU(RECIP)
1088 VIR_SFU(RSQRT)
1089 VIR_SFU(EXP)
1090 VIR_SFU(LOG)
1091 VIR_SFU(SIN)
1092 VIR_SFU(RSQRT2)
1093
1094 static inline struct qinst *
1095 vir_MOV_cond(struct v3d_compile *c, enum v3d_qpu_cond cond,
1096 struct qreg dest, struct qreg src)
1097 {
1098 struct qinst *mov = vir_MOV_dest(c, dest, src);
1099 vir_set_cond(mov, cond);
1100 return mov;
1101 }
1102
1103 static inline struct qreg
1104 vir_SEL(struct v3d_compile *c, enum v3d_qpu_cond cond,
1105 struct qreg src0, struct qreg src1)
1106 {
1107 struct qreg t = vir_get_temp(c);
1108 vir_MOV_dest(c, t, src1);
1109 vir_MOV_cond(c, cond, t, src0);
1110 return t;
1111 }
1112
1113 static inline struct qinst *
1114 vir_NOP(struct v3d_compile *c)
1115 {
1116 return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_NOP,
1117 c->undef, c->undef, c->undef));
1118 }
1119
1120 static inline struct qreg
1121 vir_LDTMU(struct v3d_compile *c)
1122 {
1123 if (c->devinfo->ver >= 41) {
1124 struct qinst *ldtmu = vir_add_inst(V3D_QPU_A_NOP, c->undef,
1125 c->undef, c->undef);
1126 ldtmu->qpu.sig.ldtmu = true;
1127
1128 return vir_emit_def(c, ldtmu);
1129 } else {
1130 vir_NOP(c)->qpu.sig.ldtmu = true;
1131 return vir_MOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4));
1132 }
1133 }
1134
1135 static inline struct qreg
1136 vir_UMUL(struct v3d_compile *c, struct qreg src0, struct qreg src1)
1137 {
1138 vir_MULTOP(c, src0, src1);
1139 return vir_UMUL24(c, src0, src1);
1140 }
1141
1142 static inline struct qreg
1143 vir_TLBU_COLOR_READ(struct v3d_compile *c, uint32_t config)
1144 {
1145 assert(c->devinfo->ver >= 41); /* XXX */
1146 assert((config & 0xffffff00) == 0xffffff00);
1147
1148 struct qinst *ldtlb = vir_add_inst(V3D_QPU_A_NOP, c->undef,
1149 c->undef, c->undef);
1150 ldtlb->qpu.sig.ldtlbu = true;
1151 ldtlb->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT, config);
1152 return vir_emit_def(c, ldtlb);
1153 }
1154
1155 static inline struct qreg
1156 vir_TLB_COLOR_READ(struct v3d_compile *c)
1157 {
1158 assert(c->devinfo->ver >= 41); /* XXX */
1159
1160 struct qinst *ldtlb = vir_add_inst(V3D_QPU_A_NOP, c->undef,
1161 c->undef, c->undef);
1162 ldtlb->qpu.sig.ldtlb = true;
1163 return vir_emit_def(c, ldtlb);
1164 }
1165
1166 /*
1167 static inline struct qreg
1168 vir_LOAD_IMM(struct v3d_compile *c, uint32_t val)
1169 {
1170 return vir_emit_def(c, vir_inst(QOP_LOAD_IMM, c->undef,
1171 vir_reg(QFILE_LOAD_IMM, val), c->undef));
1172 }
1173
1174 static inline struct qreg
1175 vir_LOAD_IMM_U2(struct v3d_compile *c, uint32_t val)
1176 {
1177 return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_U2, c->undef,
1178 vir_reg(QFILE_LOAD_IMM, val),
1179 c->undef));
1180 }
1181 static inline struct qreg
1182 vir_LOAD_IMM_I2(struct v3d_compile *c, uint32_t val)
1183 {
1184 return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_I2, c->undef,
1185 vir_reg(QFILE_LOAD_IMM, val),
1186 c->undef));
1187 }
1188 */
1189
1190 static inline struct qinst *
1191 vir_BRANCH(struct v3d_compile *c, enum v3d_qpu_branch_cond cond)
1192 {
1193 /* The actual uniform_data value will be set at scheduling time */
1194 return vir_emit_nondef(c, vir_branch_inst(c, cond));
1195 }
1196
1197 #define vir_for_each_block(block, c) \
1198 list_for_each_entry(struct qblock, block, &c->blocks, link)
1199
1200 #define vir_for_each_block_rev(block, c) \
1201 list_for_each_entry_rev(struct qblock, block, &c->blocks, link)
1202
1203 /* Loop over the non-NULL members of the successors array. */
1204 #define vir_for_each_successor(succ, block) \
1205 for (struct qblock *succ = block->successors[0]; \
1206 succ != NULL; \
1207 succ = (succ == block->successors[1] ? NULL : \
1208 block->successors[1]))
1209
1210 #define vir_for_each_inst(inst, block) \
1211 list_for_each_entry(struct qinst, inst, &block->instructions, link)
1212
1213 #define vir_for_each_inst_rev(inst, block) \
1214 list_for_each_entry_rev(struct qinst, inst, &block->instructions, link)
1215
1216 #define vir_for_each_inst_safe(inst, block) \
1217 list_for_each_entry_safe(struct qinst, inst, &block->instructions, link)
1218
1219 #define vir_for_each_inst_inorder(inst, c) \
1220 vir_for_each_block(_block, c) \
1221 vir_for_each_inst(inst, _block)
1222
1223 #define vir_for_each_inst_inorder_safe(inst, c) \
1224 vir_for_each_block(_block, c) \
1225 vir_for_each_inst_safe(inst, _block)
1226
1227 #endif /* V3D_COMPILER_H */