src/broadcom/compiler/v3d_compiler.h

   1 /*
   2  * Copyright © 2016 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef V3D_COMPILER_H
  25 #define V3D_COMPILER_H
  26
  27 #include <assert.h>
  28 #include <stdio.h>
  29 #include <stdlib.h>
  30 #include <stdbool.h>
  31 #include <stdint.h>
  32 #include <string.h>
  33
  34 #include "util/macros.h"
  35 #include "common/v3d_debug.h"
  36 #include "common/v3d_device_info.h"
  37 #include "common/v3d_limits.h"
  38 #include "compiler/nir/nir.h"
  39 #include "util/list.h"
  40 #include "util/u_math.h"
  41
  42 #include "qpu/qpu_instr.h"
  43 #include "pipe/p_state.h"
  44
  45 struct nir_builder;
  46
  47 struct v3d_fs_inputs {
  48         /**
  49          * Array of the meanings of the VPM inputs this shader needs.
  50          *
  51          * It doesn't include those that aren't part of the VPM, like
  52          * point/line coordinates.
  53          */
  54         struct v3d_varying_slot *input_slots;
  55         uint32_t num_inputs;
  56 };
  57
  58 enum qfile {
  59         /** An unused source or destination register. */
  60         QFILE_NULL,
  61
  62         /** A physical register, such as the W coordinate payload. */
  63         QFILE_REG,
  64         /** One of the regsiters for fixed function interactions. */
  65         QFILE_MAGIC,
  66
  67         /**
  68          *  A virtual register, that will be allocated to actual accumulator
  69          * or physical registers later.
  70          */
  71         QFILE_TEMP,
  72
  73         /**
  74          * VPM reads use this with an index value to say what part of the VPM
  75          * is being read.
  76          */
  77         QFILE_VPM,
  78
  79         /**
  80          * Stores an immediate value in the index field that will be used
  81          * directly by qpu_load_imm().
  82          */
  83         QFILE_LOAD_IMM,
  84
  85         /**
  86          * Stores an immediate value in the index field that can be turned
  87          * into a small immediate field by qpu_encode_small_immediate().
  88          */
  89         QFILE_SMALL_IMM,
  90 };
  91
  92 /**
  93  * A reference to a QPU register or a virtual temp register.
  94  */
  95 struct qreg {
  96         enum qfile file;
  97         uint32_t index;
  98 };
  99
 100 static inline struct qreg vir_reg(enum qfile file, uint32_t index)
 101 {
 102         return (struct qreg){file, index};
 103 }
 104
 105 static inline struct qreg vir_magic_reg(uint32_t index)
 106 {
 107         return (struct qreg){QFILE_MAGIC, index};
 108 }
 109
 110 static inline struct qreg vir_nop_reg(void)
 111 {
 112         return (struct qreg){QFILE_NULL, 0};
 113 }
 114
 115 /**
 116  * A reference to an actual register at the QPU level, for register
 117  * allocation.
 118  */
 119 struct qpu_reg {
 120         bool magic;
 121         bool smimm;
 122         int index;
 123 };
 124
 125 struct qinst {
 126         /** Entry in qblock->instructions */
 127         struct list_head link;
 128
 129         /**
 130          * The instruction being wrapped.  Its condition codes, pack flags,
 131          * signals, etc. will all be used, with just the register references
 132          * being replaced by the contents of qinst->dst and qinst->src[].
 133          */
 134         struct v3d_qpu_instr qpu;
 135
 136         /* Pre-register-allocation references to src/dst registers */
 137         struct qreg dst;
 138         struct qreg src[3];
 139         bool is_last_thrsw;
 140
 141         /* If the instruction reads a uniform (other than through src[i].file
 142          * == QFILE_UNIF), that uniform's index in c->uniform_contents.  ~0
 143          * otherwise.
 144          */
 145         int uniform;
 146 };
 147
 148 enum quniform_contents {
 149         /**
 150          * Indicates that a constant 32-bit value is copied from the program's
 151          * uniform contents.
 152          */
 153         QUNIFORM_CONSTANT,
 154         /**
 155          * Indicates that the program's uniform contents are used as an index
 156          * into the GL uniform storage.
 157          */
 158         QUNIFORM_UNIFORM,
 159
 160         /** @{
 161          * Scaling factors from clip coordinates to relative to the viewport
 162          * center.
 163          *
 164          * This is used by the coordinate and vertex shaders to produce the
 165          * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
 166          * point offsets from the viewport ccenter.
 167          */
 168         QUNIFORM_VIEWPORT_X_SCALE,
 169         QUNIFORM_VIEWPORT_Y_SCALE,
 170         /** @} */
 171
 172         QUNIFORM_VIEWPORT_Z_OFFSET,
 173         QUNIFORM_VIEWPORT_Z_SCALE,
 174
 175         QUNIFORM_USER_CLIP_PLANE,
 176
 177         /**
 178          * A reference to a V3D 3.x texture config parameter 0 uniform.
 179          *
 180          * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
 181          * defines texture type, miplevels, and such.  It will be found as a
 182          * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
 183          */
 184         QUNIFORM_TEXTURE_CONFIG_P0_0,
 185         QUNIFORM_TEXTURE_CONFIG_P0_1,
 186         QUNIFORM_TEXTURE_CONFIG_P0_2,
 187         QUNIFORM_TEXTURE_CONFIG_P0_3,
 188         QUNIFORM_TEXTURE_CONFIG_P0_4,
 189         QUNIFORM_TEXTURE_CONFIG_P0_5,
 190         QUNIFORM_TEXTURE_CONFIG_P0_6,
 191         QUNIFORM_TEXTURE_CONFIG_P0_7,
 192         QUNIFORM_TEXTURE_CONFIG_P0_8,
 193         QUNIFORM_TEXTURE_CONFIG_P0_9,
 194         QUNIFORM_TEXTURE_CONFIG_P0_10,
 195         QUNIFORM_TEXTURE_CONFIG_P0_11,
 196         QUNIFORM_TEXTURE_CONFIG_P0_12,
 197         QUNIFORM_TEXTURE_CONFIG_P0_13,
 198         QUNIFORM_TEXTURE_CONFIG_P0_14,
 199         QUNIFORM_TEXTURE_CONFIG_P0_15,
 200         QUNIFORM_TEXTURE_CONFIG_P0_16,
 201         QUNIFORM_TEXTURE_CONFIG_P0_17,
 202         QUNIFORM_TEXTURE_CONFIG_P0_18,
 203         QUNIFORM_TEXTURE_CONFIG_P0_19,
 204         QUNIFORM_TEXTURE_CONFIG_P0_20,
 205         QUNIFORM_TEXTURE_CONFIG_P0_21,
 206         QUNIFORM_TEXTURE_CONFIG_P0_22,
 207         QUNIFORM_TEXTURE_CONFIG_P0_23,
 208         QUNIFORM_TEXTURE_CONFIG_P0_24,
 209         QUNIFORM_TEXTURE_CONFIG_P0_25,
 210         QUNIFORM_TEXTURE_CONFIG_P0_26,
 211         QUNIFORM_TEXTURE_CONFIG_P0_27,
 212         QUNIFORM_TEXTURE_CONFIG_P0_28,
 213         QUNIFORM_TEXTURE_CONFIG_P0_29,
 214         QUNIFORM_TEXTURE_CONFIG_P0_30,
 215         QUNIFORM_TEXTURE_CONFIG_P0_31,
 216         QUNIFORM_TEXTURE_CONFIG_P0_32,
 217
 218         /**
 219          * A reference to a V3D 3.x texture config parameter 1 uniform.
 220          *
 221          * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
 222          * has the pointer to the indirect texture state.  Our data[] field
 223          * will have a packed p1 value, but the address field will be just
 224          * which texture unit's texture should be referenced.
 225          */
 226         QUNIFORM_TEXTURE_CONFIG_P1,
 227
 228         /* A V3D 4.x texture config parameter.  The high 8 bits will be
 229          * which texture or sampler is being sampled, and the driver must
 230          * replace the address field with the appropriate address.
 231          */
 232         QUNIFORM_TMU_CONFIG_P0,
 233         QUNIFORM_TMU_CONFIG_P1,
 234
 235         QUNIFORM_IMAGE_TMU_CONFIG_P0,
 236
 237         QUNIFORM_TEXTURE_FIRST_LEVEL,
 238
 239         QUNIFORM_TEXTURE_WIDTH,
 240         QUNIFORM_TEXTURE_HEIGHT,
 241         QUNIFORM_TEXTURE_DEPTH,
 242         QUNIFORM_TEXTURE_ARRAY_SIZE,
 243         QUNIFORM_TEXTURE_LEVELS,
 244
 245         QUNIFORM_UBO_ADDR,
 246
 247         QUNIFORM_TEXRECT_SCALE_X,
 248         QUNIFORM_TEXRECT_SCALE_Y,
 249
 250         /* Returns the base offset of the SSBO given by the data value. */
 251         QUNIFORM_SSBO_OFFSET,
 252
 253         /* Returns the size of the SSBO given by the data value. */
 254         QUNIFORM_GET_BUFFER_SIZE,
 255
 256         /* Sizes (in pixels) of a shader image given by the data value. */
 257         QUNIFORM_IMAGE_WIDTH,
 258         QUNIFORM_IMAGE_HEIGHT,
 259         QUNIFORM_IMAGE_DEPTH,
 260         QUNIFORM_IMAGE_ARRAY_SIZE,
 261
 262         QUNIFORM_ALPHA_REF,
 263
 264         /* Number of workgroups passed to glDispatchCompute in the dimension
 265          * selected by the data value.
 266          */
 267         QUNIFORM_NUM_WORK_GROUPS,
 268
 269         /**
 270          * Returns the the offset of the scratch buffer for register spilling.
 271          */
 272         QUNIFORM_SPILL_OFFSET,
 273         QUNIFORM_SPILL_SIZE_PER_THREAD,
 274
 275         /**
 276          * Returns the offset of the shared memory for compute shaders.
 277          *
 278          * This will be accessed using TMU general memory operations, so the
 279          * L2T cache will effectively be the shared memory area.
 280          */
 281         QUNIFORM_SHARED_OFFSET,
 282 };
 283
 284 static inline uint32_t v3d_unit_data_create(uint32_t unit, uint32_t value)
 285 {
 286         assert(value < (1 << 24));
 287         return unit << 24 | value;
 288 }
 289
 290 static inline uint32_t v3d_unit_data_get_unit(uint32_t data)
 291 {
 292         return data >> 24;
 293 }
 294
 295 static inline uint32_t v3d_unit_data_get_offset(uint32_t data)
 296 {
 297         return data & 0xffffff;
 298 }
 299
 300 struct v3d_varying_slot {
 301         uint8_t slot_and_component;
 302 };
 303
 304 static inline struct v3d_varying_slot
 305 v3d_slot_from_slot_and_component(uint8_t slot, uint8_t component)
 306 {
 307         assert(slot < 255 / 4);
 308         return (struct v3d_varying_slot){ (slot << 2) + component };
 309 }
 310
 311 static inline uint8_t v3d_slot_get_slot(struct v3d_varying_slot slot)
 312 {
 313         return slot.slot_and_component >> 2;
 314 }
 315
 316 static inline uint8_t v3d_slot_get_component(struct v3d_varying_slot slot)
 317 {
 318         return slot.slot_and_component & 3;
 319 }
 320
 321 struct v3d_key {
 322         void *shader_state;
 323         struct {
 324                 uint8_t swizzle[4];
 325                 uint8_t return_size;
 326                 uint8_t return_channels;
 327                 bool clamp_s:1;
 328                 bool clamp_t:1;
 329                 bool clamp_r:1;
 330         } tex[V3D_MAX_TEXTURE_SAMPLERS];
 331         uint8_t ucp_enables;
 332 };
 333
 334 struct v3d_fs_key {
 335         struct v3d_key base;
 336         bool depth_enabled;
 337         bool is_points;
 338         bool is_lines;
 339         bool alpha_test;
 340         bool point_coord_upper_left;
 341         bool light_twoside;
 342         bool msaa;
 343         bool sample_coverage;
 344         bool sample_alpha_to_coverage;
 345         bool sample_alpha_to_one;
 346         bool clamp_color;
 347         bool shade_model_flat;
 348         /* Mask of which color render targets are present. */
 349         uint8_t cbufs;
 350         uint8_t swap_color_rb;
 351         /* Mask of which render targets need to be written as 32-bit floats */
 352         uint8_t f32_color_rb;
 353         /* Masks of which render targets need to be written as ints/uints.
 354          * Used by gallium to work around lost information in TGSI.
 355          */
 356         uint8_t int_color_rb;
 357         uint8_t uint_color_rb;
 358
 359         /* Color format information per render target. Only set when logic
 360          * operations are enabled.
 361          */
 362         struct {
 363                 enum pipe_format format;
 364                 const uint8_t *swizzle;
 365         } color_fmt[V3D_MAX_DRAW_BUFFERS];
 366
 367         uint8_t alpha_test_func;
 368         uint8_t logicop_func;
 369         uint32_t point_sprite_mask;
 370
 371         struct pipe_rt_blend_state blend;
 372 };
 373
 374 struct v3d_vs_key {
 375         struct v3d_key base;
 376
 377         struct v3d_varying_slot fs_inputs[V3D_MAX_FS_INPUTS];
 378         uint8_t num_fs_inputs;
 379
 380         bool is_coord;
 381         bool per_vertex_point_size;
 382         bool clamp_color;
 383 };
 384
 385 /** A basic block of VIR intructions. */
 386 struct qblock {
 387         struct list_head link;
 388
 389         struct list_head instructions;
 390
 391         struct set *predecessors;
 392         struct qblock *successors[2];
 393
 394         int index;
 395
 396         /* Instruction IPs for the first and last instruction of the block.
 397          * Set by qpu_schedule.c.
 398          */
 399         uint32_t start_qpu_ip;
 400         uint32_t end_qpu_ip;
 401
 402         /* Instruction IP for the branch instruction of the block.  Set by
 403          * qpu_schedule.c.
 404          */
 405         uint32_t branch_qpu_ip;
 406
 407         /** Offset within the uniform stream at the start of the block. */
 408         uint32_t start_uniform;
 409         /** Offset within the uniform stream of the branch instruction */
 410         uint32_t branch_uniform;
 411
 412         /** @{ used by v3d_vir_live_variables.c */
 413         BITSET_WORD *def;
 414         BITSET_WORD *defin;
 415         BITSET_WORD *defout;
 416         BITSET_WORD *use;
 417         BITSET_WORD *live_in;
 418         BITSET_WORD *live_out;
 419         int start_ip, end_ip;
 420         /** @} */
 421 };
 422
 423 /** Which util/list.h add mode we should use when inserting an instruction. */
 424 enum vir_cursor_mode {
 425         vir_cursor_add,
 426         vir_cursor_addtail,
 427 };
 428
 429 /**
 430  * Tracking structure for where new instructions should be inserted.  Create
 431  * with one of the vir_after_inst()-style helper functions.
 432  *
 433  * This does not protect against removal of the block or instruction, so we
 434  * have an assert in instruction removal to try to catch it.
 435  */
 436 struct vir_cursor {
 437         enum vir_cursor_mode mode;
 438         struct list_head *link;
 439 };
 440
 441 static inline struct vir_cursor
 442 vir_before_inst(struct qinst *inst)
 443 {
 444         return (struct vir_cursor){ vir_cursor_addtail, &inst->link };
 445 }
 446
 447 static inline struct vir_cursor
 448 vir_after_inst(struct qinst *inst)
 449 {
 450         return (struct vir_cursor){ vir_cursor_add, &inst->link };
 451 }
 452
 453 static inline struct vir_cursor
 454 vir_before_block(struct qblock *block)
 455 {
 456         return (struct vir_cursor){ vir_cursor_add, &block->instructions };
 457 }
 458
 459 static inline struct vir_cursor
 460 vir_after_block(struct qblock *block)
 461 {
 462         return (struct vir_cursor){ vir_cursor_addtail, &block->instructions };
 463 }
 464
 465 /**
 466  * Compiler state saved across compiler invocations, for any expensive global
 467  * setup.
 468  */
 469 struct v3d_compiler {
 470         const struct v3d_device_info *devinfo;
 471         struct ra_regs *regs;
 472         unsigned int reg_class_any[3];
 473         unsigned int reg_class_r5[3];
 474         unsigned int reg_class_phys[3];
 475         unsigned int reg_class_phys_or_acc[3];
 476 };
 477
 478 struct v3d_compile {
 479         const struct v3d_device_info *devinfo;
 480         nir_shader *s;
 481         nir_function_impl *impl;
 482         struct exec_list *cf_node_list;
 483         const struct v3d_compiler *compiler;
 484
 485         void (*debug_output)(const char *msg,
 486                              void *debug_output_data);
 487         void *debug_output_data;
 488
 489         /**
 490          * Mapping from nir_register * or nir_ssa_def * to array of struct
 491          * qreg for the values.
 492          */
 493         struct hash_table *def_ht;
 494
 495         /* For each temp, the instruction generating its value. */
 496         struct qinst **defs;
 497         uint32_t defs_array_size;
 498
 499         /**
 500          * Inputs to the shader, arranged by TGSI declaration order.
 501          *
 502          * Not all fragment shader QFILE_VARY reads are present in this array.
 503          */
 504         struct qreg *inputs;
 505         struct qreg *outputs;
 506         bool msaa_per_sample_output;
 507         struct qreg color_reads[V3D_MAX_DRAW_BUFFERS * V3D_MAX_SAMPLES * 4];
 508         struct qreg sample_colors[V3D_MAX_DRAW_BUFFERS * V3D_MAX_SAMPLES * 4];
 509         uint32_t inputs_array_size;
 510         uint32_t outputs_array_size;
 511         uint32_t uniforms_array_size;
 512
 513         /* Booleans for whether the corresponding QFILE_VARY[i] is
 514          * flat-shaded.  This includes gl_FragColor flat-shading, which is
 515          * customized based on the shademodel_flat shader key.
 516          */
 517         uint32_t flat_shade_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
 518
 519         uint32_t noperspective_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
 520
 521         uint32_t centroid_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
 522
 523         bool uses_center_w;
 524         bool writes_z;
 525         bool uses_implicit_point_line_varyings;
 526
 527         /* State for whether we're executing on each channel currently.  0 if
 528          * yes, otherwise a block number + 1 that the channel jumped to.
 529          */
 530         struct qreg execute;
 531         bool in_control_flow;
 532
 533         struct qreg line_x, point_x, point_y;
 534
 535         /**
 536          * Instance ID, which comes in before the vertex attribute payload if
 537          * the shader record requests it.
 538          */
 539         struct qreg iid;
 540
 541         /**
 542          * Vertex ID, which comes in before the vertex attribute payload
 543          * (after Instance ID) if the shader record requests it.
 544          */
 545         struct qreg vid;
 546
 547         /* Fragment shader payload regs. */
 548         struct qreg payload_w, payload_w_centroid, payload_z;
 549
 550         struct qreg cs_payload[2];
 551         struct qreg cs_shared_offset;
 552         int local_invocation_index_bits;
 553
 554         uint8_t vattr_sizes[V3D_MAX_VS_INPUTS / 4];
 555         uint32_t vpm_output_size;
 556
 557         /* Size in bytes of registers that have been spilled. This is how much
 558          * space needs to be available in the spill BO per thread per QPU.
 559          */
 560         uint32_t spill_size;
 561         /* Shader-db stats */
 562         uint32_t spills, fills, loops;
 563         /**
 564          * Register spilling's per-thread base address, shared between each
 565          * spill/fill's addressing calculations.
 566          */
 567         struct qreg spill_base;
 568         /* Bit vector of which temps may be spilled */
 569         BITSET_WORD *spillable;
 570
 571         /**
 572          * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
 573          *
 574          * This includes those that aren't part of the VPM varyings, like
 575          * point/line coordinates.
 576          */
 577         struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
 578
 579         /**
 580          * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
 581          * of the output is.  Used to emit from the VS in the order that the
 582          * FS needs.
 583          */
 584         struct v3d_varying_slot *output_slots;
 585
 586         struct pipe_shader_state *shader_state;
 587         struct v3d_key *key;
 588         struct v3d_fs_key *fs_key;
 589         struct v3d_vs_key *vs_key;
 590
 591         /* Live ranges of temps. */
 592         int *temp_start, *temp_end;
 593         bool live_intervals_valid;
 594
 595         uint32_t *uniform_data;
 596         enum quniform_contents *uniform_contents;
 597         uint32_t uniform_array_size;
 598         uint32_t num_uniforms;
 599         uint32_t output_position_index;
 600         nir_variable *output_color_var[4];
 601         uint32_t output_sample_mask_index;
 602
 603         struct qreg undef;
 604         uint32_t num_temps;
 605
 606         struct vir_cursor cursor;
 607         struct list_head blocks;
 608         int next_block_index;
 609         struct qblock *cur_block;
 610         struct qblock *loop_cont_block;
 611         struct qblock *loop_break_block;
 612
 613         uint64_t *qpu_insts;
 614         uint32_t qpu_inst_count;
 615         uint32_t qpu_inst_size;
 616
 617         /* For the FS, the number of varying inputs not counting the
 618          * point/line varyings payload
 619          */
 620         uint32_t num_inputs;
 621
 622         uint32_t program_id;
 623         uint32_t variant_id;
 624
 625         /* Set to compile program in in 1x, 2x, or 4x threaded mode, where
 626          * SIG_THREAD_SWITCH is used to hide texturing latency at the cost of
 627          * limiting ourselves to the part of the physical reg space.
 628          *
 629          * On V3D 3.x, 2x or 4x divide the physical reg space by 2x or 4x.  On
 630          * V3D 4.x, all shaders are 2x threaded, and 4x only divides the
 631          * physical reg space in half.
 632          */
 633         uint8_t threads;
 634         struct qinst *last_thrsw;
 635         bool last_thrsw_at_top_level;
 636
 637         bool failed;
 638 };
 639
 640 struct v3d_uniform_list {
 641         enum quniform_contents *contents;
 642         uint32_t *data;
 643         uint32_t count;
 644 };
 645
 646 struct v3d_prog_data {
 647         struct v3d_uniform_list uniforms;
 648
 649         uint32_t spill_size;
 650
 651         uint8_t threads;
 652
 653         /* For threads > 1, whether the program should be dispatched in the
 654          * after-final-THRSW state.
 655          */
 656         bool single_seg;
 657 };
 658
 659 struct v3d_vs_prog_data {
 660         struct v3d_prog_data base;
 661
 662         bool uses_iid, uses_vid;
 663
 664         /* Number of components read from each vertex attribute. */
 665         uint8_t vattr_sizes[V3D_MAX_VS_INPUTS / 4];
 666
 667         /* Total number of components read, for the shader state record. */
 668         uint32_t vpm_input_size;
 669
 670         /* Total number of components written, for the shader state record. */
 671         uint32_t vpm_output_size;
 672
 673         /* Set if there should be separate VPM segments for input and output.
 674          * If unset, vpm_input_size will be 0.
 675          */
 676         bool separate_segments;
 677
 678         /* Value to be programmed in VCM_CACHE_SIZE. */
 679         uint8_t vcm_cache_size;
 680 };
 681
 682 struct v3d_fs_prog_data {
 683         struct v3d_prog_data base;
 684
 685         struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
 686
 687         /* Array of flat shade flags.
 688          *
 689          * Each entry is only 24 bits (high 8 bits 0), to match the hardware
 690          * packet layout.
 691          */
 692         uint32_t flat_shade_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
 693
 694         uint32_t noperspective_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
 695
 696         uint32_t centroid_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
 697
 698         uint8_t num_inputs;
 699         bool writes_z;
 700         bool disable_ez;
 701         bool uses_center_w;
 702         bool uses_implicit_point_line_varyings;
 703 };
 704
 705 struct v3d_compute_prog_data {
 706         struct v3d_prog_data base;
 707         /* Size in bytes of the workgroup's shared space. */
 708         uint32_t shared_size;
 709 };
 710
 711 static inline bool
 712 vir_has_uniform(struct qinst *inst)
 713 {
 714         return inst->uniform != ~0;
 715 }
 716
 717 /* Special nir_load_input intrinsic index for loading the current TLB
 718  * destination color.
 719  */
 720 #define V3D_NIR_TLB_COLOR_READ_INPUT            2000000000
 721
 722 #define V3D_NIR_MS_MASK_OUTPUT                  2000000000
 723
 724 extern const nir_shader_compiler_options v3d_nir_options;
 725
 726 const struct v3d_compiler *v3d_compiler_init(const struct v3d_device_info *devinfo);
 727 void v3d_compiler_free(const struct v3d_compiler *compiler);
 728 void v3d_optimize_nir(struct nir_shader *s);
 729
 730 uint64_t *v3d_compile(const struct v3d_compiler *compiler,
 731                       struct v3d_key *key,
 732                       struct v3d_prog_data **prog_data,
 733                       nir_shader *s,
 734                       void (*debug_output)(const char *msg,
 735                                            void *debug_output_data),
 736                       void *debug_output_data,
 737                       int program_id, int variant_id,
 738                       uint32_t *final_assembly_size);
 739
 740 void v3d_nir_to_vir(struct v3d_compile *c);
 741
 742 void vir_compile_destroy(struct v3d_compile *c);
 743 const char *vir_get_stage_name(struct v3d_compile *c);
 744 struct qblock *vir_new_block(struct v3d_compile *c);
 745 void vir_set_emit_block(struct v3d_compile *c, struct qblock *block);
 746 void vir_link_blocks(struct qblock *predecessor, struct qblock *successor);
 747 struct qblock *vir_entry_block(struct v3d_compile *c);
 748 struct qblock *vir_exit_block(struct v3d_compile *c);
 749 struct qinst *vir_add_inst(enum v3d_qpu_add_op op, struct qreg dst,
 750                            struct qreg src0, struct qreg src1);
 751 struct qinst *vir_mul_inst(enum v3d_qpu_mul_op op, struct qreg dst,
 752                            struct qreg src0, struct qreg src1);
 753 struct qinst *vir_branch_inst(struct v3d_compile *c,
 754                               enum v3d_qpu_branch_cond cond);
 755 void vir_remove_instruction(struct v3d_compile *c, struct qinst *qinst);
 756 uint32_t vir_get_uniform_index(struct v3d_compile *c,
 757                                enum quniform_contents contents,
 758                                uint32_t data);
 759 struct qreg vir_uniform(struct v3d_compile *c,
 760                         enum quniform_contents contents,
 761                         uint32_t data);
 762 void vir_schedule_instructions(struct v3d_compile *c);
 763 void v3d_setup_spill_base(struct v3d_compile *c);
 764 struct v3d_qpu_instr v3d_qpu_nop(void);
 765
 766 struct qreg vir_emit_def(struct v3d_compile *c, struct qinst *inst);
 767 struct qinst *vir_emit_nondef(struct v3d_compile *c, struct qinst *inst);
 768 void vir_set_cond(struct qinst *inst, enum v3d_qpu_cond cond);
 769 void vir_set_pf(struct qinst *inst, enum v3d_qpu_pf pf);
 770 void vir_set_uf(struct qinst *inst, enum v3d_qpu_uf uf);
 771 void vir_set_unpack(struct qinst *inst, int src,
 772                     enum v3d_qpu_input_unpack unpack);
 773
 774 struct qreg vir_get_temp(struct v3d_compile *c);
 775 void vir_emit_last_thrsw(struct v3d_compile *c);
 776 void vir_calculate_live_intervals(struct v3d_compile *c);
 777 int vir_get_nsrc(struct qinst *inst);
 778 bool vir_has_side_effects(struct v3d_compile *c, struct qinst *inst);
 779 bool vir_get_add_op(struct qinst *inst, enum v3d_qpu_add_op *op);
 780 bool vir_get_mul_op(struct qinst *inst, enum v3d_qpu_mul_op *op);
 781 bool vir_is_raw_mov(struct qinst *inst);
 782 bool vir_is_tex(struct qinst *inst);
 783 bool vir_is_add(struct qinst *inst);
 784 bool vir_is_mul(struct qinst *inst);
 785 bool vir_writes_r3(const struct v3d_device_info *devinfo, struct qinst *inst);
 786 bool vir_writes_r4(const struct v3d_device_info *devinfo, struct qinst *inst);
 787 struct qreg vir_follow_movs(struct v3d_compile *c, struct qreg reg);
 788 uint8_t vir_channels_written(struct qinst *inst);
 789 struct qreg ntq_get_src(struct v3d_compile *c, nir_src src, int i);
 790 void ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
 791                     struct qreg result);
 792 void vir_emit_thrsw(struct v3d_compile *c);
 793
 794 void vir_dump(struct v3d_compile *c);
 795 void vir_dump_inst(struct v3d_compile *c, struct qinst *inst);
 796 void vir_dump_uniform(enum quniform_contents contents, uint32_t data);
 797
 798 void vir_validate(struct v3d_compile *c);
 799
 800 void vir_optimize(struct v3d_compile *c);
 801 bool vir_opt_algebraic(struct v3d_compile *c);
 802 bool vir_opt_constant_folding(struct v3d_compile *c);
 803 bool vir_opt_copy_propagate(struct v3d_compile *c);
 804 bool vir_opt_dead_code(struct v3d_compile *c);
 805 bool vir_opt_peephole_sf(struct v3d_compile *c);
 806 bool vir_opt_redundant_flags(struct v3d_compile *c);
 807 bool vir_opt_small_immediates(struct v3d_compile *c);
 808 bool vir_opt_vpm(struct v3d_compile *c);
 809 void v3d_nir_lower_blend(nir_shader *s, struct v3d_compile *c);
 810 void v3d_nir_lower_io(nir_shader *s, struct v3d_compile *c);
 811 void v3d_nir_lower_scratch(nir_shader *s);
 812 void v3d_nir_lower_txf_ms(nir_shader *s, struct v3d_compile *c);
 813 void v3d_nir_lower_image_load_store(nir_shader *s);
 814 void vir_lower_uniforms(struct v3d_compile *c);
 815
 816 void v3d33_vir_vpm_read_setup(struct v3d_compile *c, int num_components);
 817 void v3d33_vir_vpm_write_setup(struct v3d_compile *c);
 818 void v3d33_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr);
 819 void v3d40_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr);
 820 void v3d40_vir_emit_image_load_store(struct v3d_compile *c,
 821                                      nir_intrinsic_instr *instr);
 822
 823 void v3d_vir_to_qpu(struct v3d_compile *c, struct qpu_reg *temp_registers);
 824 uint32_t v3d_qpu_schedule_instructions(struct v3d_compile *c);
 825 void qpu_validate(struct v3d_compile *c);
 826 struct qpu_reg *v3d_register_allocate(struct v3d_compile *c, bool *spilled);
 827 bool vir_init_reg_sets(struct v3d_compiler *compiler);
 828
 829 bool v3d_gl_format_is_return_32(GLenum format);
 830
 831 static inline bool
 832 quniform_contents_is_texture_p0(enum quniform_contents contents)
 833 {
 834         return (contents >= QUNIFORM_TEXTURE_CONFIG_P0_0 &&
 835                 contents < (QUNIFORM_TEXTURE_CONFIG_P0_0 +
 836                             V3D_MAX_TEXTURE_SAMPLERS));
 837 }
 838
 839 static inline bool
 840 vir_in_nonuniform_control_flow(struct v3d_compile *c)
 841 {
 842         return c->execute.file != QFILE_NULL;
 843 }
 844
 845 static inline struct qreg
 846 vir_uniform_ui(struct v3d_compile *c, uint32_t ui)
 847 {
 848         return vir_uniform(c, QUNIFORM_CONSTANT, ui);
 849 }
 850
 851 static inline struct qreg
 852 vir_uniform_f(struct v3d_compile *c, float f)
 853 {
 854         return vir_uniform(c, QUNIFORM_CONSTANT, fui(f));
 855 }
 856
 857 #define VIR_ALU0(name, vir_inst, op)                                     \
 858 static inline struct qreg                                                \
 859 vir_##name(struct v3d_compile *c)                                        \
 860 {                                                                        \
 861         return vir_emit_def(c, vir_inst(op, c->undef,                    \
 862                                         c->undef, c->undef));            \
 863 }                                                                        \
 864 static inline struct qinst *                                             \
 865 vir_##name##_dest(struct v3d_compile *c, struct qreg dest)               \
 866 {                                                                        \
 867         return vir_emit_nondef(c, vir_inst(op, dest,                     \
 868                                            c->undef, c->undef));         \
 869 }
 870
 871 #define VIR_ALU1(name, vir_inst, op)                                     \
 872 static inline struct qreg                                                \
 873 vir_##name(struct v3d_compile *c, struct qreg a)                         \
 874 {                                                                        \
 875         return vir_emit_def(c, vir_inst(op, c->undef,                    \
 876                                         a, c->undef));                   \
 877 }                                                                        \
 878 static inline struct qinst *                                             \
 879 vir_##name##_dest(struct v3d_compile *c, struct qreg dest,               \
 880                   struct qreg a)                                         \
 881 {                                                                        \
 882         return vir_emit_nondef(c, vir_inst(op, dest, a,          \
 883                                            c->undef));                   \
 884 }
 885
 886 #define VIR_ALU2(name, vir_inst, op)                                       \
 887 static inline struct qreg                                                \
 888 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b)          \
 889 {                                                                        \
 890         return vir_emit_def(c, vir_inst(op, c->undef, a, b));    \
 891 }                                                                        \
 892 static inline struct qinst *                                             \
 893 vir_##name##_dest(struct v3d_compile *c, struct qreg dest,               \
 894                   struct qreg a, struct qreg b)                          \
 895 {                                                                        \
 896         return vir_emit_nondef(c, vir_inst(op, dest, a, b));     \
 897 }
 898
 899 #define VIR_NODST_0(name, vir_inst, op)                                 \
 900 static inline struct qinst *                                            \
 901 vir_##name(struct v3d_compile *c)                                       \
 902 {                                                                       \
 903         return vir_emit_nondef(c, vir_inst(op, c->undef,                \
 904                                            c->undef, c->undef));        \
 905 }
 906
 907 #define VIR_NODST_1(name, vir_inst, op)                                               \
 908 static inline struct qinst *                                            \
 909 vir_##name(struct v3d_compile *c, struct qreg a)                        \
 910 {                                                                       \
 911         return vir_emit_nondef(c, vir_inst(op, c->undef,        \
 912                                            a, c->undef));               \
 913 }
 914
 915 #define VIR_NODST_2(name, vir_inst, op)                                               \
 916 static inline struct qinst *                                            \
 917 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b)         \
 918 {                                                                       \
 919         return vir_emit_nondef(c, vir_inst(op, c->undef,                \
 920                                            a, b));                      \
 921 }
 922
 923 #define VIR_SFU(name)                                                      \
 924 static inline struct qreg                                                \
 925 vir_##name(struct v3d_compile *c, struct qreg a)                         \
 926 {                                                                        \
 927         if (c->devinfo->ver >= 41) {                                     \
 928                 return vir_emit_def(c, vir_add_inst(V3D_QPU_A_##name,    \
 929                                                     c->undef,            \
 930                                                     a, c->undef));       \
 931         } else {                                                         \
 932                 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_##name), a); \
 933                 return vir_FMOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4)); \
 934         }                                                                \
 935 }                                                                        \
 936 static inline struct qinst *                                             \
 937 vir_##name##_dest(struct v3d_compile *c, struct qreg dest,               \
 938                   struct qreg a)                                         \
 939 {                                                                        \
 940         if (c->devinfo->ver >= 41) {                                     \
 941                 return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_##name, \
 942                                                        dest,             \
 943                                                        a, c->undef));    \
 944         } else {                                                         \
 945                 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_##name), a); \
 946                 return vir_FMOV_dest(c, dest, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4)); \
 947         }                                                                \
 948 }
 949
 950 #define VIR_A_ALU2(name) VIR_ALU2(name, vir_add_inst, V3D_QPU_A_##name)
 951 #define VIR_M_ALU2(name) VIR_ALU2(name, vir_mul_inst, V3D_QPU_M_##name)
 952 #define VIR_A_ALU1(name) VIR_ALU1(name, vir_add_inst, V3D_QPU_A_##name)
 953 #define VIR_M_ALU1(name) VIR_ALU1(name, vir_mul_inst, V3D_QPU_M_##name)
 954 #define VIR_A_ALU0(name) VIR_ALU0(name, vir_add_inst, V3D_QPU_A_##name)
 955 #define VIR_M_ALU0(name) VIR_ALU0(name, vir_mul_inst, V3D_QPU_M_##name)
 956 #define VIR_A_NODST_2(name) VIR_NODST_2(name, vir_add_inst, V3D_QPU_A_##name)
 957 #define VIR_M_NODST_2(name) VIR_NODST_2(name, vir_mul_inst, V3D_QPU_M_##name)
 958 #define VIR_A_NODST_1(name) VIR_NODST_1(name, vir_add_inst, V3D_QPU_A_##name)
 959 #define VIR_M_NODST_1(name) VIR_NODST_1(name, vir_mul_inst, V3D_QPU_M_##name)
 960 #define VIR_A_NODST_0(name) VIR_NODST_0(name, vir_add_inst, V3D_QPU_A_##name)
 961
 962 VIR_A_ALU2(FADD)
 963 VIR_A_ALU2(VFPACK)
 964 VIR_A_ALU2(FSUB)
 965 VIR_A_ALU2(FMIN)
 966 VIR_A_ALU2(FMAX)
 967
 968 VIR_A_ALU2(ADD)
 969 VIR_A_ALU2(SUB)
 970 VIR_A_ALU2(SHL)
 971 VIR_A_ALU2(SHR)
 972 VIR_A_ALU2(ASR)
 973 VIR_A_ALU2(ROR)
 974 VIR_A_ALU2(MIN)
 975 VIR_A_ALU2(MAX)
 976 VIR_A_ALU2(UMIN)
 977 VIR_A_ALU2(UMAX)
 978 VIR_A_ALU2(AND)
 979 VIR_A_ALU2(OR)
 980 VIR_A_ALU2(XOR)
 981 VIR_A_ALU2(VADD)
 982 VIR_A_ALU2(VSUB)
 983 VIR_A_NODST_2(STVPMV)
 984 VIR_A_ALU1(NOT)
 985 VIR_A_ALU1(NEG)
 986 VIR_A_ALU1(FLAPUSH)
 987 VIR_A_ALU1(FLBPUSH)
 988 VIR_A_ALU1(FLPOP)
 989 VIR_A_ALU1(SETMSF)
 990 VIR_A_ALU1(SETREVF)
 991 VIR_A_ALU0(TIDX)
 992 VIR_A_ALU0(EIDX)
 993 VIR_A_ALU1(LDVPMV_IN)
 994 VIR_A_ALU1(LDVPMV_OUT)
 995 VIR_A_ALU0(TMUWT)
 996
 997 VIR_A_ALU0(FXCD)
 998 VIR_A_ALU0(XCD)
 999 VIR_A_ALU0(FYCD)
1000 VIR_A_ALU0(YCD)
1001 VIR_A_ALU0(MSF)
1002 VIR_A_ALU0(REVF)
1003 VIR_A_ALU0(BARRIERID)
1004 VIR_A_NODST_1(VPMSETUP)
1005 VIR_A_NODST_0(VPMWT)
1006 VIR_A_ALU2(FCMP)
1007 VIR_A_ALU2(VFMAX)
1008
1009 VIR_A_ALU1(FROUND)
1010 VIR_A_ALU1(FTOIN)
1011 VIR_A_ALU1(FTRUNC)
1012 VIR_A_ALU1(FTOIZ)
1013 VIR_A_ALU1(FFLOOR)
1014 VIR_A_ALU1(FTOUZ)
1015 VIR_A_ALU1(FCEIL)
1016 VIR_A_ALU1(FTOC)
1017
1018 VIR_A_ALU1(FDX)
1019 VIR_A_ALU1(FDY)
1020
1021 VIR_A_ALU1(ITOF)
1022 VIR_A_ALU1(CLZ)
1023 VIR_A_ALU1(UTOF)
1024
1025 VIR_M_ALU2(UMUL24)
1026 VIR_M_ALU2(FMUL)
1027 VIR_M_ALU2(SMUL24)
1028 VIR_M_NODST_2(MULTOP)
1029
1030 VIR_M_ALU1(MOV)
1031 VIR_M_ALU1(FMOV)
1032
1033 VIR_SFU(RECIP)
1034 VIR_SFU(RSQRT)
1035 VIR_SFU(EXP)
1036 VIR_SFU(LOG)
1037 VIR_SFU(SIN)
1038 VIR_SFU(RSQRT2)
1039
1040 static inline struct qinst *
1041 vir_MOV_cond(struct v3d_compile *c, enum v3d_qpu_cond cond,
1042              struct qreg dest, struct qreg src)
1043 {
1044         struct qinst *mov = vir_MOV_dest(c, dest, src);
1045         vir_set_cond(mov, cond);
1046         return mov;
1047 }
1048
1049 static inline struct qreg
1050 vir_SEL(struct v3d_compile *c, enum v3d_qpu_cond cond,
1051         struct qreg src0, struct qreg src1)
1052 {
1053         struct qreg t = vir_get_temp(c);
1054         vir_MOV_dest(c, t, src1);
1055         vir_MOV_cond(c, cond, t, src0);
1056         return t;
1057 }
1058
1059 static inline struct qinst *
1060 vir_NOP(struct v3d_compile *c)
1061 {
1062         return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_NOP,
1063                                                c->undef, c->undef, c->undef));
1064 }
1065
1066 static inline struct qreg
1067 vir_LDTMU(struct v3d_compile *c)
1068 {
1069         if (c->devinfo->ver >= 41) {
1070                 struct qinst *ldtmu = vir_add_inst(V3D_QPU_A_NOP, c->undef,
1071                                                    c->undef, c->undef);
1072                 ldtmu->qpu.sig.ldtmu = true;
1073
1074                 return vir_emit_def(c, ldtmu);
1075         } else {
1076                 vir_NOP(c)->qpu.sig.ldtmu = true;
1077                 return vir_MOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4));
1078         }
1079 }
1080
1081 static inline struct qreg
1082 vir_UMUL(struct v3d_compile *c, struct qreg src0, struct qreg src1)
1083 {
1084         vir_MULTOP(c, src0, src1);
1085         return vir_UMUL24(c, src0, src1);
1086 }
1087
1088 static inline struct qreg
1089 vir_TLBU_COLOR_READ(struct v3d_compile *c, uint32_t config)
1090 {
1091         assert(c->devinfo->ver >= 41); /* XXX */
1092         assert((config & 0xffffff00) == 0xffffff00);
1093
1094         struct qinst *ldtlb = vir_add_inst(V3D_QPU_A_NOP, c->undef,
1095                                            c->undef, c->undef);
1096         ldtlb->qpu.sig.ldtlbu = true;
1097         ldtlb->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT, config);
1098         return vir_emit_def(c, ldtlb);
1099 }
1100
1101 static inline struct qreg
1102 vir_TLB_COLOR_READ(struct v3d_compile *c)
1103 {
1104         assert(c->devinfo->ver >= 41); /* XXX */
1105
1106         struct qinst *ldtlb = vir_add_inst(V3D_QPU_A_NOP, c->undef,
1107                                            c->undef, c->undef);
1108         ldtlb->qpu.sig.ldtlb = true;
1109         return vir_emit_def(c, ldtlb);
1110 }
1111
1112 /*
1113 static inline struct qreg
1114 vir_LOAD_IMM(struct v3d_compile *c, uint32_t val)
1115 {
1116         return vir_emit_def(c, vir_inst(QOP_LOAD_IMM, c->undef,
1117                                         vir_reg(QFILE_LOAD_IMM, val), c->undef));
1118 }
1119
1120 static inline struct qreg
1121 vir_LOAD_IMM_U2(struct v3d_compile *c, uint32_t val)
1122 {
1123         return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_U2, c->undef,
1124                                         vir_reg(QFILE_LOAD_IMM, val),
1125                                         c->undef));
1126 }
1127 static inline struct qreg
1128 vir_LOAD_IMM_I2(struct v3d_compile *c, uint32_t val)
1129 {
1130         return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_I2, c->undef,
1131                                         vir_reg(QFILE_LOAD_IMM, val),
1132                                         c->undef));
1133 }
1134 */
1135
1136 static inline struct qinst *
1137 vir_BRANCH(struct v3d_compile *c, enum v3d_qpu_branch_cond cond)
1138 {
1139         /* The actual uniform_data value will be set at scheduling time */
1140         return vir_emit_nondef(c, vir_branch_inst(c, cond));
1141 }
1142
1143 #define vir_for_each_block(block, c)                                    \
1144         list_for_each_entry(struct qblock, block, &c->blocks, link)
1145
1146 #define vir_for_each_block_rev(block, c)                                \
1147         list_for_each_entry_rev(struct qblock, block, &c->blocks, link)
1148
1149 /* Loop over the non-NULL members of the successors array. */
1150 #define vir_for_each_successor(succ, block)                             \
1151         for (struct qblock *succ = block->successors[0];                \
1152              succ != NULL;                                              \
1153              succ = (succ == block->successors[1] ? NULL :              \
1154                      block->successors[1]))
1155
1156 #define vir_for_each_inst(inst, block)                                  \
1157         list_for_each_entry(struct qinst, inst, &block->instructions, link)
1158
1159 #define vir_for_each_inst_rev(inst, block)                                  \
1160         list_for_each_entry_rev(struct qinst, inst, &block->instructions, link)
1161
1162 #define vir_for_each_inst_safe(inst, block)                             \
1163         list_for_each_entry_safe(struct qinst, inst, &block->instructions, link)
1164
1165 #define vir_for_each_inst_inorder(inst, c)                              \
1166         vir_for_each_block(_block, c)                                   \
1167                 vir_for_each_inst(inst, _block)
1168
1169 #define vir_for_each_inst_inorder_safe(inst, c)                         \
1170         vir_for_each_block(_block, c)                                   \
1171                 vir_for_each_inst_safe(inst, _block)
1172
1173 #endif /* V3D_COMPILER_H */