2 * Copyright © 2016 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef V3D_COMPILER_H
25 #define V3D_COMPILER_H
34 #include "util/macros.h"
35 #include "common/v3d_debug.h"
36 #include "common/v3d_device_info.h"
37 #include "common/v3d_limits.h"
38 #include "compiler/nir/nir.h"
39 #include "util/list.h"
40 #include "util/u_math.h"
42 #include "qpu/qpu_instr.h"
43 #include "pipe/p_state.h"
47 struct v3d_fs_inputs
{
49 * Array of the meanings of the VPM inputs this shader needs.
51 * It doesn't include those that aren't part of the VPM, like
52 * point/line coordinates.
54 struct v3d_varying_slot
*input_slots
;
59 /** An unused source or destination register. */
62 /** A physical register, such as the W coordinate payload. */
64 /** One of the regsiters for fixed function interactions. */
68 * A virtual register, that will be allocated to actual accumulator
69 * or physical registers later.
76 * VPM reads use this with an index value to say what part of the VPM
82 * Stores an immediate value in the index field that will be used
83 * directly by qpu_load_imm().
88 * Stores an immediate value in the index field that can be turned
89 * into a small immediate field by qpu_encode_small_immediate().
95 * A reference to a QPU register or a virtual temp register.
102 static inline struct qreg
vir_reg(enum qfile file
, uint32_t index
)
104 return (struct qreg
){file
, index
};
107 static inline struct qreg
vir_nop_reg(void)
109 return (struct qreg
){QFILE_NULL
, 0};
113 * A reference to an actual register at the QPU level, for register
123 /** Entry in qblock->instructions */
124 struct list_head link
;
127 * The instruction being wrapped. Its condition codes, pack flags,
128 * signals, etc. will all be used, with just the register references
129 * being replaced by the contents of qinst->dst and qinst->src[].
131 struct v3d_qpu_instr qpu
;
133 /* Pre-register-allocation references to src/dst registers */
138 /* If the instruction reads a uniform (other than through src[i].file
139 * == QFILE_UNIF), that uniform's index in c->uniform_contents. ~0
145 enum quniform_contents
{
147 * Indicates that a constant 32-bit value is copied from the program's
152 * Indicates that the program's uniform contents are used as an index
153 * into the GL uniform storage.
158 * Scaling factors from clip coordinates to relative to the viewport
161 * This is used by the coordinate and vertex shaders to produce the
162 * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
163 * point offsets from the viewport ccenter.
165 QUNIFORM_VIEWPORT_X_SCALE
,
166 QUNIFORM_VIEWPORT_Y_SCALE
,
169 QUNIFORM_VIEWPORT_Z_OFFSET
,
170 QUNIFORM_VIEWPORT_Z_SCALE
,
172 QUNIFORM_USER_CLIP_PLANE
,
175 * A reference to a V3D 3.x texture config parameter 0 uniform.
177 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
178 * defines texture type, miplevels, and such. It will be found as a
179 * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
181 QUNIFORM_TEXTURE_CONFIG_P0_0
,
182 QUNIFORM_TEXTURE_CONFIG_P0_1
,
183 QUNIFORM_TEXTURE_CONFIG_P0_2
,
184 QUNIFORM_TEXTURE_CONFIG_P0_3
,
185 QUNIFORM_TEXTURE_CONFIG_P0_4
,
186 QUNIFORM_TEXTURE_CONFIG_P0_5
,
187 QUNIFORM_TEXTURE_CONFIG_P0_6
,
188 QUNIFORM_TEXTURE_CONFIG_P0_7
,
189 QUNIFORM_TEXTURE_CONFIG_P0_8
,
190 QUNIFORM_TEXTURE_CONFIG_P0_9
,
191 QUNIFORM_TEXTURE_CONFIG_P0_10
,
192 QUNIFORM_TEXTURE_CONFIG_P0_11
,
193 QUNIFORM_TEXTURE_CONFIG_P0_12
,
194 QUNIFORM_TEXTURE_CONFIG_P0_13
,
195 QUNIFORM_TEXTURE_CONFIG_P0_14
,
196 QUNIFORM_TEXTURE_CONFIG_P0_15
,
197 QUNIFORM_TEXTURE_CONFIG_P0_16
,
198 QUNIFORM_TEXTURE_CONFIG_P0_17
,
199 QUNIFORM_TEXTURE_CONFIG_P0_18
,
200 QUNIFORM_TEXTURE_CONFIG_P0_19
,
201 QUNIFORM_TEXTURE_CONFIG_P0_20
,
202 QUNIFORM_TEXTURE_CONFIG_P0_21
,
203 QUNIFORM_TEXTURE_CONFIG_P0_22
,
204 QUNIFORM_TEXTURE_CONFIG_P0_23
,
205 QUNIFORM_TEXTURE_CONFIG_P0_24
,
206 QUNIFORM_TEXTURE_CONFIG_P0_25
,
207 QUNIFORM_TEXTURE_CONFIG_P0_26
,
208 QUNIFORM_TEXTURE_CONFIG_P0_27
,
209 QUNIFORM_TEXTURE_CONFIG_P0_28
,
210 QUNIFORM_TEXTURE_CONFIG_P0_29
,
211 QUNIFORM_TEXTURE_CONFIG_P0_30
,
212 QUNIFORM_TEXTURE_CONFIG_P0_31
,
213 QUNIFORM_TEXTURE_CONFIG_P0_32
,
216 * A reference to a V3D 3.x texture config parameter 1 uniform.
218 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
219 * has the pointer to the indirect texture state. Our data[] field
220 * will have a packed p1 value, but the address field will be just
221 * which texture unit's texture should be referenced.
223 QUNIFORM_TEXTURE_CONFIG_P1
,
225 /* A V3D 4.x texture config parameter. The high 8 bits will be
226 * which texture or sampler is being sampled, and the driver must
227 * replace the address field with the appropriate address.
229 QUNIFORM_TMU_CONFIG_P0
,
230 QUNIFORM_TMU_CONFIG_P1
,
232 QUNIFORM_IMAGE_TMU_CONFIG_P0
,
234 QUNIFORM_TEXTURE_FIRST_LEVEL
,
236 QUNIFORM_TEXTURE_WIDTH
,
237 QUNIFORM_TEXTURE_HEIGHT
,
238 QUNIFORM_TEXTURE_DEPTH
,
239 QUNIFORM_TEXTURE_ARRAY_SIZE
,
240 QUNIFORM_TEXTURE_LEVELS
,
244 QUNIFORM_TEXRECT_SCALE_X
,
245 QUNIFORM_TEXRECT_SCALE_Y
,
247 /* Returns the base offset of the SSBO given by the data value. */
248 QUNIFORM_SSBO_OFFSET
,
250 /* Returns the size of the SSBO given by the data value. */
251 QUNIFORM_GET_BUFFER_SIZE
,
253 /* Sizes (in pixels) of a shader image given by the data value. */
254 QUNIFORM_IMAGE_WIDTH
,
255 QUNIFORM_IMAGE_HEIGHT
,
256 QUNIFORM_IMAGE_DEPTH
,
257 QUNIFORM_IMAGE_ARRAY_SIZE
,
261 /* Number of workgroups passed to glDispatchCompute in the dimension
262 * selected by the data value.
264 QUNIFORM_NUM_WORK_GROUPS
,
267 * Returns the the offset of the scratch buffer for register spilling.
269 QUNIFORM_SPILL_OFFSET
,
270 QUNIFORM_SPILL_SIZE_PER_THREAD
,
273 * Returns the offset of the shared memory for compute shaders.
275 * This will be accessed using TMU general memory operations, so the
276 * L2T cache will effectively be the shared memory area.
278 QUNIFORM_SHARED_OFFSET
,
281 static inline uint32_t v3d_tmu_config_data_create(uint32_t unit
, uint32_t value
)
283 return unit
<< 24 | value
;
286 static inline uint32_t v3d_tmu_config_data_get_unit(uint32_t data
)
291 static inline uint32_t v3d_tmu_config_data_get_value(uint32_t data
)
293 return data
& 0xffffff;
296 struct v3d_varying_slot
{
297 uint8_t slot_and_component
;
300 static inline struct v3d_varying_slot
301 v3d_slot_from_slot_and_component(uint8_t slot
, uint8_t component
)
303 assert(slot
< 255 / 4);
304 return (struct v3d_varying_slot
){ (slot
<< 2) + component
};
307 static inline uint8_t v3d_slot_get_slot(struct v3d_varying_slot slot
)
309 return slot
.slot_and_component
>> 2;
312 static inline uint8_t v3d_slot_get_component(struct v3d_varying_slot slot
)
314 return slot
.slot_and_component
& 3;
317 struct v3d_ubo_range
{
319 * offset in bytes from the start of the ubo where this range is
322 * Only set once used is set.
327 * offset in bytes from the start of the gallium uniforms where the
332 /** size in bytes of this ubo range */
341 uint8_t return_channels
;
345 } tex
[V3D_MAX_TEXTURE_SAMPLERS
];
355 bool point_coord_upper_left
;
358 bool sample_coverage
;
359 bool sample_alpha_to_coverage
;
360 bool sample_alpha_to_one
;
362 bool shade_model_flat
;
363 /* Mask of which color render targets are present. */
365 uint8_t swap_color_rb
;
366 /* Mask of which render targets need to be written as 32-bit floats */
367 uint8_t f32_color_rb
;
368 /* Masks of which render targets need to be written as ints/uints.
369 * Used by gallium to work around lost information in TGSI.
371 uint8_t int_color_rb
;
372 uint8_t uint_color_rb
;
373 uint8_t alpha_test_func
;
374 uint8_t logicop_func
;
375 uint32_t point_sprite_mask
;
377 struct pipe_rt_blend_state blend
;
383 struct v3d_varying_slot fs_inputs
[V3D_MAX_FS_INPUTS
];
384 uint8_t num_fs_inputs
;
387 bool per_vertex_point_size
;
391 /** A basic block of VIR intructions. */
393 struct list_head link
;
395 struct list_head instructions
;
397 struct set
*predecessors
;
398 struct qblock
*successors
[2];
402 /* Instruction IPs for the first and last instruction of the block.
403 * Set by qpu_schedule.c.
405 uint32_t start_qpu_ip
;
408 /* Instruction IP for the branch instruction of the block. Set by
411 uint32_t branch_qpu_ip
;
413 /** Offset within the uniform stream at the start of the block. */
414 uint32_t start_uniform
;
415 /** Offset within the uniform stream of the branch instruction */
416 uint32_t branch_uniform
;
418 /** @{ used by v3d_vir_live_variables.c */
423 BITSET_WORD
*live_in
;
424 BITSET_WORD
*live_out
;
425 int start_ip
, end_ip
;
429 /** Which util/list.h add mode we should use when inserting an instruction. */
430 enum vir_cursor_mode
{
436 * Tracking structure for where new instructions should be inserted. Create
437 * with one of the vir_after_inst()-style helper functions.
439 * This does not protect against removal of the block or instruction, so we
440 * have an assert in instruction removal to try to catch it.
443 enum vir_cursor_mode mode
;
444 struct list_head
*link
;
447 static inline struct vir_cursor
448 vir_before_inst(struct qinst
*inst
)
450 return (struct vir_cursor
){ vir_cursor_addtail
, &inst
->link
};
453 static inline struct vir_cursor
454 vir_after_inst(struct qinst
*inst
)
456 return (struct vir_cursor
){ vir_cursor_add
, &inst
->link
};
459 static inline struct vir_cursor
460 vir_before_block(struct qblock
*block
)
462 return (struct vir_cursor
){ vir_cursor_add
, &block
->instructions
};
465 static inline struct vir_cursor
466 vir_after_block(struct qblock
*block
)
468 return (struct vir_cursor
){ vir_cursor_addtail
, &block
->instructions
};
472 * Compiler state saved across compiler invocations, for any expensive global
475 struct v3d_compiler
{
476 const struct v3d_device_info
*devinfo
;
477 struct ra_regs
*regs
;
478 unsigned int reg_class_any
[3];
479 unsigned int reg_class_r5
[3];
480 unsigned int reg_class_phys
[3];
481 unsigned int reg_class_phys_or_acc
[3];
485 const struct v3d_device_info
*devinfo
;
487 nir_function_impl
*impl
;
488 struct exec_list
*cf_node_list
;
489 const struct v3d_compiler
*compiler
;
491 void (*debug_output
)(const char *msg
,
492 void *debug_output_data
);
493 void *debug_output_data
;
496 * Mapping from nir_register * or nir_ssa_def * to array of struct
497 * qreg for the values.
499 struct hash_table
*def_ht
;
501 /* For each temp, the instruction generating its value. */
503 uint32_t defs_array_size
;
506 * Inputs to the shader, arranged by TGSI declaration order.
508 * Not all fragment shader QFILE_VARY reads are present in this array.
511 struct qreg
*outputs
;
512 bool msaa_per_sample_output
;
513 struct qreg color_reads
[V3D_MAX_SAMPLES
];
514 struct qreg sample_colors
[V3D_MAX_SAMPLES
];
515 uint32_t inputs_array_size
;
516 uint32_t outputs_array_size
;
517 uint32_t uniforms_array_size
;
519 /* Booleans for whether the corresponding QFILE_VARY[i] is
520 * flat-shaded. This includes gl_FragColor flat-shading, which is
521 * customized based on the shademodel_flat shader key.
523 uint32_t flat_shade_flags
[BITSET_WORDS(V3D_MAX_FS_INPUTS
)];
525 uint32_t noperspective_flags
[BITSET_WORDS(V3D_MAX_FS_INPUTS
)];
527 uint32_t centroid_flags
[BITSET_WORDS(V3D_MAX_FS_INPUTS
)];
532 struct v3d_ubo_range
*ubo_ranges
;
533 bool *ubo_range_used
;
534 uint32_t ubo_ranges_array_size
;
535 /** Number of uniform areas tracked in ubo_ranges. */
536 uint32_t num_ubo_ranges
;
537 uint32_t next_ubo_dst_offset
;
539 /* State for whether we're executing on each channel currently. 0 if
540 * yes, otherwise a block number + 1 that the channel jumped to.
543 bool in_control_flow
;
545 struct qreg line_x
, point_x
, point_y
;
548 * Instance ID, which comes in before the vertex attribute payload if
549 * the shader record requests it.
554 * Vertex ID, which comes in before the vertex attribute payload
555 * (after Instance ID) if the shader record requests it.
559 /* Fragment shader payload regs. */
560 struct qreg payload_w
, payload_w_centroid
, payload_z
;
562 struct qreg cs_payload
[2];
563 struct qreg cs_shared_offset
;
564 int local_invocation_index_bits
;
566 uint8_t vattr_sizes
[V3D_MAX_VS_INPUTS
/ 4];
567 uint32_t vpm_output_size
;
569 /* Size in bytes of registers that have been spilled. This is how much
570 * space needs to be available in the spill BO per thread per QPU.
573 /* Shader-db stats */
574 uint32_t spills
, fills
, loops
;
576 * Register spilling's per-thread base address, shared between each
577 * spill/fill's addressing calculations.
579 struct qreg spill_base
;
580 /* Bit vector of which temps may be spilled */
581 BITSET_WORD
*spillable
;
584 * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
586 * This includes those that aren't part of the VPM varyings, like
587 * point/line coordinates.
589 struct v3d_varying_slot input_slots
[V3D_MAX_FS_INPUTS
];
592 * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
593 * of the output is. Used to emit from the VS in the order that the
596 struct v3d_varying_slot
*output_slots
;
598 struct pipe_shader_state
*shader_state
;
600 struct v3d_fs_key
*fs_key
;
601 struct v3d_vs_key
*vs_key
;
603 /* Live ranges of temps. */
604 int *temp_start
, *temp_end
;
605 bool live_intervals_valid
;
607 uint32_t *uniform_data
;
608 enum quniform_contents
*uniform_contents
;
609 uint32_t uniform_array_size
;
610 uint32_t num_uniforms
;
611 uint32_t output_position_index
;
612 nir_variable
*output_color_var
[4];
613 uint32_t output_sample_mask_index
;
618 struct vir_cursor cursor
;
619 struct list_head blocks
;
620 int next_block_index
;
621 struct qblock
*cur_block
;
622 struct qblock
*loop_cont_block
;
623 struct qblock
*loop_break_block
;
626 uint32_t qpu_inst_count
;
627 uint32_t qpu_inst_size
;
629 /* For the FS, the number of varying inputs not counting the
630 * point/line varyings payload
635 * Number of inputs from num_inputs remaining to be queued to the read
638 uint32_t num_inputs_remaining
;
640 /* Number of inputs currently in the read FIFO for the VS/CS */
641 uint32_t num_inputs_in_fifo
;
643 /** Next offset in the VPM to read from in the VS/CS */
644 uint32_t vpm_read_offset
;
649 /* Set to compile program in in 1x, 2x, or 4x threaded mode, where
650 * SIG_THREAD_SWITCH is used to hide texturing latency at the cost of
651 * limiting ourselves to the part of the physical reg space.
653 * On V3D 3.x, 2x or 4x divide the physical reg space by 2x or 4x. On
654 * V3D 4.x, all shaders are 2x threaded, and 4x only divides the
655 * physical reg space in half.
658 struct qinst
*last_thrsw
;
659 bool last_thrsw_at_top_level
;
664 struct v3d_uniform_list
{
665 enum quniform_contents
*contents
;
670 struct v3d_prog_data
{
671 struct v3d_uniform_list uniforms
;
673 struct v3d_ubo_range
*ubo_ranges
;
674 uint32_t num_ubo_ranges
;
680 /* For threads > 1, whether the program should be dispatched in the
681 * after-final-THRSW state.
686 struct v3d_vs_prog_data
{
687 struct v3d_prog_data base
;
689 bool uses_iid
, uses_vid
;
691 /* Number of components read from each vertex attribute. */
692 uint8_t vattr_sizes
[V3D_MAX_VS_INPUTS
/ 4];
694 /* Total number of components read, for the shader state record. */
695 uint32_t vpm_input_size
;
697 /* Total number of components written, for the shader state record. */
698 uint32_t vpm_output_size
;
700 /* Set if there should be separate VPM segments for input and output.
701 * If unset, vpm_input_size will be 0.
703 bool separate_segments
;
705 /* Value to be programmed in VCM_CACHE_SIZE. */
706 uint8_t vcm_cache_size
;
709 struct v3d_fs_prog_data
{
710 struct v3d_prog_data base
;
712 struct v3d_varying_slot input_slots
[V3D_MAX_FS_INPUTS
];
714 /* Array of flat shade flags.
716 * Each entry is only 24 bits (high 8 bits 0), to match the hardware
719 uint32_t flat_shade_flags
[((V3D_MAX_FS_INPUTS
- 1) / 24) + 1];
721 uint32_t noperspective_flags
[((V3D_MAX_FS_INPUTS
- 1) / 24) + 1];
723 uint32_t centroid_flags
[((V3D_MAX_FS_INPUTS
- 1) / 24) + 1];
732 vir_has_uniform(struct qinst
*inst
)
734 return inst
->uniform
!= ~0;
737 /* Special nir_load_input intrinsic index for loading the current TLB
740 #define V3D_NIR_TLB_COLOR_READ_INPUT 2000000000
742 #define V3D_NIR_MS_MASK_OUTPUT 2000000000
744 extern const nir_shader_compiler_options v3d_nir_options
;
746 const struct v3d_compiler
*v3d_compiler_init(const struct v3d_device_info
*devinfo
);
747 void v3d_compiler_free(const struct v3d_compiler
*compiler
);
748 void v3d_optimize_nir(struct nir_shader
*s
);
750 uint64_t *v3d_compile(const struct v3d_compiler
*compiler
,
752 struct v3d_prog_data
**prog_data
,
754 void (*debug_output
)(const char *msg
,
755 void *debug_output_data
),
756 void *debug_output_data
,
757 int program_id
, int variant_id
,
758 uint32_t *final_assembly_size
);
760 void v3d_nir_to_vir(struct v3d_compile
*c
);
762 void vir_compile_destroy(struct v3d_compile
*c
);
763 const char *vir_get_stage_name(struct v3d_compile
*c
);
764 struct qblock
*vir_new_block(struct v3d_compile
*c
);
765 void vir_set_emit_block(struct v3d_compile
*c
, struct qblock
*block
);
766 void vir_link_blocks(struct qblock
*predecessor
, struct qblock
*successor
);
767 struct qblock
*vir_entry_block(struct v3d_compile
*c
);
768 struct qblock
*vir_exit_block(struct v3d_compile
*c
);
769 struct qinst
*vir_add_inst(enum v3d_qpu_add_op op
, struct qreg dst
,
770 struct qreg src0
, struct qreg src1
);
771 struct qinst
*vir_mul_inst(enum v3d_qpu_mul_op op
, struct qreg dst
,
772 struct qreg src0
, struct qreg src1
);
773 struct qinst
*vir_branch_inst(struct v3d_compile
*c
,
774 enum v3d_qpu_branch_cond cond
);
775 void vir_remove_instruction(struct v3d_compile
*c
, struct qinst
*qinst
);
776 uint32_t vir_get_uniform_index(struct v3d_compile
*c
,
777 enum quniform_contents contents
,
779 struct qreg
vir_uniform(struct v3d_compile
*c
,
780 enum quniform_contents contents
,
782 void vir_schedule_instructions(struct v3d_compile
*c
);
783 struct v3d_qpu_instr
v3d_qpu_nop(void);
785 struct qreg
vir_emit_def(struct v3d_compile
*c
, struct qinst
*inst
);
786 struct qinst
*vir_emit_nondef(struct v3d_compile
*c
, struct qinst
*inst
);
787 void vir_set_cond(struct qinst
*inst
, enum v3d_qpu_cond cond
);
788 void vir_set_pf(struct qinst
*inst
, enum v3d_qpu_pf pf
);
789 void vir_set_uf(struct qinst
*inst
, enum v3d_qpu_uf uf
);
790 void vir_set_unpack(struct qinst
*inst
, int src
,
791 enum v3d_qpu_input_unpack unpack
);
793 struct qreg
vir_get_temp(struct v3d_compile
*c
);
794 void vir_emit_last_thrsw(struct v3d_compile
*c
);
795 void vir_calculate_live_intervals(struct v3d_compile
*c
);
796 int vir_get_nsrc(struct qinst
*inst
);
797 bool vir_has_side_effects(struct v3d_compile
*c
, struct qinst
*inst
);
798 bool vir_get_add_op(struct qinst
*inst
, enum v3d_qpu_add_op
*op
);
799 bool vir_get_mul_op(struct qinst
*inst
, enum v3d_qpu_mul_op
*op
);
800 bool vir_is_raw_mov(struct qinst
*inst
);
801 bool vir_is_tex(struct qinst
*inst
);
802 bool vir_is_add(struct qinst
*inst
);
803 bool vir_is_mul(struct qinst
*inst
);
804 bool vir_writes_r3(const struct v3d_device_info
*devinfo
, struct qinst
*inst
);
805 bool vir_writes_r4(const struct v3d_device_info
*devinfo
, struct qinst
*inst
);
806 struct qreg
vir_follow_movs(struct v3d_compile
*c
, struct qreg reg
);
807 uint8_t vir_channels_written(struct qinst
*inst
);
808 struct qreg
ntq_get_src(struct v3d_compile
*c
, nir_src src
, int i
);
809 void ntq_store_dest(struct v3d_compile
*c
, nir_dest
*dest
, int chan
,
811 void vir_emit_thrsw(struct v3d_compile
*c
);
813 void vir_dump(struct v3d_compile
*c
);
814 void vir_dump_inst(struct v3d_compile
*c
, struct qinst
*inst
);
815 void vir_dump_uniform(enum quniform_contents contents
, uint32_t data
);
817 void vir_validate(struct v3d_compile
*c
);
819 void vir_optimize(struct v3d_compile
*c
);
820 bool vir_opt_algebraic(struct v3d_compile
*c
);
821 bool vir_opt_constant_folding(struct v3d_compile
*c
);
822 bool vir_opt_copy_propagate(struct v3d_compile
*c
);
823 bool vir_opt_dead_code(struct v3d_compile
*c
);
824 bool vir_opt_peephole_sf(struct v3d_compile
*c
);
825 bool vir_opt_small_immediates(struct v3d_compile
*c
);
826 bool vir_opt_vpm(struct v3d_compile
*c
);
827 void v3d_nir_lower_blend(nir_shader
*s
, struct v3d_compile
*c
);
828 void v3d_nir_lower_io(nir_shader
*s
, struct v3d_compile
*c
);
829 void v3d_nir_lower_txf_ms(nir_shader
*s
, struct v3d_compile
*c
);
830 void v3d_nir_lower_image_load_store(nir_shader
*s
);
831 void vir_lower_uniforms(struct v3d_compile
*c
);
833 void v3d33_vir_vpm_read_setup(struct v3d_compile
*c
, int num_components
);
834 void v3d33_vir_vpm_write_setup(struct v3d_compile
*c
);
835 void v3d33_vir_emit_tex(struct v3d_compile
*c
, nir_tex_instr
*instr
);
836 void v3d40_vir_emit_tex(struct v3d_compile
*c
, nir_tex_instr
*instr
);
837 void v3d40_vir_emit_image_load_store(struct v3d_compile
*c
,
838 nir_intrinsic_instr
*instr
);
840 void v3d_vir_to_qpu(struct v3d_compile
*c
, struct qpu_reg
*temp_registers
);
841 uint32_t v3d_qpu_schedule_instructions(struct v3d_compile
*c
);
842 void qpu_validate(struct v3d_compile
*c
);
843 struct qpu_reg
*v3d_register_allocate(struct v3d_compile
*c
, bool *spilled
);
844 bool vir_init_reg_sets(struct v3d_compiler
*compiler
);
846 bool v3d_gl_format_is_return_32(GLenum format
);
849 quniform_contents_is_texture_p0(enum quniform_contents contents
)
851 return (contents
>= QUNIFORM_TEXTURE_CONFIG_P0_0
&&
852 contents
< (QUNIFORM_TEXTURE_CONFIG_P0_0
+
853 V3D_MAX_TEXTURE_SAMPLERS
));
857 vir_in_nonuniform_control_flow(struct v3d_compile
*c
)
859 return c
->execute
.file
!= QFILE_NULL
;
862 static inline struct qreg
863 vir_uniform_ui(struct v3d_compile
*c
, uint32_t ui
)
865 return vir_uniform(c
, QUNIFORM_CONSTANT
, ui
);
868 static inline struct qreg
869 vir_uniform_f(struct v3d_compile
*c
, float f
)
871 return vir_uniform(c
, QUNIFORM_CONSTANT
, fui(f
));
874 #define VIR_ALU0(name, vir_inst, op) \
875 static inline struct qreg \
876 vir_##name(struct v3d_compile *c) \
878 return vir_emit_def(c, vir_inst(op, c->undef, \
879 c->undef, c->undef)); \
881 static inline struct qinst * \
882 vir_##name##_dest(struct v3d_compile *c, struct qreg dest) \
884 return vir_emit_nondef(c, vir_inst(op, dest, \
885 c->undef, c->undef)); \
888 #define VIR_ALU1(name, vir_inst, op) \
889 static inline struct qreg \
890 vir_##name(struct v3d_compile *c, struct qreg a) \
892 return vir_emit_def(c, vir_inst(op, c->undef, \
895 static inline struct qinst * \
896 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
899 return vir_emit_nondef(c, vir_inst(op, dest, a, \
903 #define VIR_ALU2(name, vir_inst, op) \
904 static inline struct qreg \
905 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b) \
907 return vir_emit_def(c, vir_inst(op, c->undef, a, b)); \
909 static inline struct qinst * \
910 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
911 struct qreg a, struct qreg b) \
913 return vir_emit_nondef(c, vir_inst(op, dest, a, b)); \
916 #define VIR_NODST_0(name, vir_inst, op) \
917 static inline struct qinst * \
918 vir_##name(struct v3d_compile *c) \
920 return vir_emit_nondef(c, vir_inst(op, c->undef, \
921 c->undef, c->undef)); \
924 #define VIR_NODST_1(name, vir_inst, op) \
925 static inline struct qinst * \
926 vir_##name(struct v3d_compile *c, struct qreg a) \
928 return vir_emit_nondef(c, vir_inst(op, c->undef, \
932 #define VIR_NODST_2(name, vir_inst, op) \
933 static inline struct qinst * \
934 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b) \
936 return vir_emit_nondef(c, vir_inst(op, c->undef, \
940 #define VIR_SFU(name) \
941 static inline struct qreg \
942 vir_##name(struct v3d_compile *c, struct qreg a) \
944 if (c->devinfo->ver >= 41) { \
945 return vir_emit_def(c, vir_add_inst(V3D_QPU_A_##name, \
949 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_##name), a); \
950 return vir_FMOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4)); \
953 static inline struct qinst * \
954 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
957 if (c->devinfo->ver >= 41) { \
958 return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_##name, \
962 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_##name), a); \
963 return vir_FMOV_dest(c, dest, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4)); \
967 #define VIR_A_ALU2(name) VIR_ALU2(name, vir_add_inst, V3D_QPU_A_##name)
968 #define VIR_M_ALU2(name) VIR_ALU2(name, vir_mul_inst, V3D_QPU_M_##name)
969 #define VIR_A_ALU1(name) VIR_ALU1(name, vir_add_inst, V3D_QPU_A_##name)
970 #define VIR_M_ALU1(name) VIR_ALU1(name, vir_mul_inst, V3D_QPU_M_##name)
971 #define VIR_A_ALU0(name) VIR_ALU0(name, vir_add_inst, V3D_QPU_A_##name)
972 #define VIR_M_ALU0(name) VIR_ALU0(name, vir_mul_inst, V3D_QPU_M_##name)
973 #define VIR_A_NODST_2(name) VIR_NODST_2(name, vir_add_inst, V3D_QPU_A_##name)
974 #define VIR_M_NODST_2(name) VIR_NODST_2(name, vir_mul_inst, V3D_QPU_M_##name)
975 #define VIR_A_NODST_1(name) VIR_NODST_1(name, vir_add_inst, V3D_QPU_A_##name)
976 #define VIR_M_NODST_1(name) VIR_NODST_1(name, vir_mul_inst, V3D_QPU_M_##name)
977 #define VIR_A_NODST_0(name) VIR_NODST_0(name, vir_add_inst, V3D_QPU_A_##name)
1000 VIR_A_NODST_2(STVPMV
)
1010 VIR_A_ALU1(LDVPMV_IN
)
1011 VIR_A_ALU1(LDVPMV_OUT
)
1020 VIR_A_ALU0(BARRIERID
)
1021 VIR_A_NODST_1(VPMSETUP
)
1022 VIR_A_NODST_0(VPMWT
)
1045 VIR_M_NODST_2(MULTOP
)
1057 static inline struct qinst
*
1058 vir_MOV_cond(struct v3d_compile
*c
, enum v3d_qpu_cond cond
,
1059 struct qreg dest
, struct qreg src
)
1061 struct qinst
*mov
= vir_MOV_dest(c
, dest
, src
);
1062 vir_set_cond(mov
, cond
);
1066 static inline struct qreg
1067 vir_SEL(struct v3d_compile
*c
, enum v3d_qpu_cond cond
,
1068 struct qreg src0
, struct qreg src1
)
1070 struct qreg t
= vir_get_temp(c
);
1071 vir_MOV_dest(c
, t
, src1
);
1072 vir_MOV_cond(c
, cond
, t
, src0
);
1076 static inline struct qinst
*
1077 vir_NOP(struct v3d_compile
*c
)
1079 return vir_emit_nondef(c
, vir_add_inst(V3D_QPU_A_NOP
,
1080 c
->undef
, c
->undef
, c
->undef
));
1083 static inline struct qreg
1084 vir_LDTMU(struct v3d_compile
*c
)
1086 if (c
->devinfo
->ver
>= 41) {
1087 struct qinst
*ldtmu
= vir_add_inst(V3D_QPU_A_NOP
, c
->undef
,
1088 c
->undef
, c
->undef
);
1089 ldtmu
->qpu
.sig
.ldtmu
= true;
1091 return vir_emit_def(c
, ldtmu
);
1093 vir_NOP(c
)->qpu
.sig
.ldtmu
= true;
1094 return vir_MOV(c
, vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_R4
));
1098 static inline struct qreg
1099 vir_UMUL(struct v3d_compile
*c
, struct qreg src0
, struct qreg src1
)
1101 vir_MULTOP(c
, src0
, src1
);
1102 return vir_UMUL24(c
, src0
, src1
);
1106 static inline struct qreg
1107 vir_LOAD_IMM(struct v3d_compile *c, uint32_t val)
1109 return vir_emit_def(c, vir_inst(QOP_LOAD_IMM, c->undef,
1110 vir_reg(QFILE_LOAD_IMM, val), c->undef));
1113 static inline struct qreg
1114 vir_LOAD_IMM_U2(struct v3d_compile *c, uint32_t val)
1116 return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_U2, c->undef,
1117 vir_reg(QFILE_LOAD_IMM, val),
1120 static inline struct qreg
1121 vir_LOAD_IMM_I2(struct v3d_compile *c, uint32_t val)
1123 return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_I2, c->undef,
1124 vir_reg(QFILE_LOAD_IMM, val),
1129 static inline struct qinst
*
1130 vir_BRANCH(struct v3d_compile
*c
, enum v3d_qpu_branch_cond cond
)
1132 /* The actual uniform_data value will be set at scheduling time */
1133 return vir_emit_nondef(c
, vir_branch_inst(c
, cond
));
1136 #define vir_for_each_block(block, c) \
1137 list_for_each_entry(struct qblock, block, &c->blocks, link)
1139 #define vir_for_each_block_rev(block, c) \
1140 list_for_each_entry_rev(struct qblock, block, &c->blocks, link)
1142 /* Loop over the non-NULL members of the successors array. */
1143 #define vir_for_each_successor(succ, block) \
1144 for (struct qblock *succ = block->successors[0]; \
1146 succ = (succ == block->successors[1] ? NULL : \
1147 block->successors[1]))
1149 #define vir_for_each_inst(inst, block) \
1150 list_for_each_entry(struct qinst, inst, &block->instructions, link)
1152 #define vir_for_each_inst_rev(inst, block) \
1153 list_for_each_entry_rev(struct qinst, inst, &block->instructions, link)
1155 #define vir_for_each_inst_safe(inst, block) \
1156 list_for_each_entry_safe(struct qinst, inst, &block->instructions, link)
1158 #define vir_for_each_inst_inorder(inst, c) \
1159 vir_for_each_block(_block, c) \
1160 vir_for_each_inst(inst, _block)
1162 #define vir_for_each_inst_inorder_safe(inst, c) \
1163 vir_for_each_block(_block, c) \
1164 vir_for_each_inst_safe(inst, _block)
1166 #endif /* V3D_COMPILER_H */