src/broadcom/compiler/v3d_compiler.h

   1 /*
   2  * Copyright © 2016 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef V3D_COMPILER_H
  25 #define V3D_COMPILER_H
  26
  27 #include <assert.h>
  28 #include <stdio.h>
  29 #include <stdlib.h>
  30 #include <stdbool.h>
  31 #include <stdint.h>
  32 #include <string.h>
  33
  34 #include "util/macros.h"
  35 #include "common/v3d_debug.h"
  36 #include "compiler/nir/nir.h"
  37 #include "util/list.h"
  38 #include "util/u_math.h"
  39
  40 #include "qpu/qpu_instr.h"
  41 #include "pipe/p_state.h"
  42
  43 #define V3D_MAX_TEXTURE_SAMPLERS 32
  44 #define V3D_MAX_SAMPLES 4
  45 #define V3D_MAX_FS_INPUTS 64
  46 #define V3D_MAX_VS_INPUTS 64
  47
  48 struct nir_builder;
  49
  50 struct v3d_fs_inputs {
  51         /**
  52          * Array of the meanings of the VPM inputs this shader needs.
  53          *
  54          * It doesn't include those that aren't part of the VPM, like
  55          * point/line coordinates.
  56          */
  57         struct v3d_varying_slot *input_slots;
  58         uint32_t num_inputs;
  59 };
  60
  61 enum qfile {
  62         /** An unused source or destination register. */
  63         QFILE_NULL,
  64
  65         /** A physical register, such as the W coordinate payload. */
  66         QFILE_REG,
  67         /** One of the regsiters for fixed function interactions. */
  68         QFILE_MAGIC,
  69
  70         /**
  71          *  A virtual register, that will be allocated to actual accumulator
  72          * or physical registers later.
  73          */
  74         QFILE_TEMP,
  75         QFILE_VARY,
  76         QFILE_UNIF,
  77         QFILE_TLB,
  78         QFILE_TLBU,
  79
  80         /**
  81          * VPM reads use this with an index value to say what part of the VPM
  82          * is being read.
  83          */
  84         QFILE_VPM,
  85
  86         /**
  87          * Stores an immediate value in the index field that will be used
  88          * directly by qpu_load_imm().
  89          */
  90         QFILE_LOAD_IMM,
  91
  92         /**
  93          * Stores an immediate value in the index field that can be turned
  94          * into a small immediate field by qpu_encode_small_immediate().
  95          */
  96         QFILE_SMALL_IMM,
  97 };
  98
  99 /**
 100  * A reference to a QPU register or a virtual temp register.
 101  */
 102 struct qreg {
 103         enum qfile file;
 104         uint32_t index;
 105 };
 106
 107 static inline struct qreg vir_reg(enum qfile file, uint32_t index)
 108 {
 109         return (struct qreg){file, index};
 110 }
 111
 112 /**
 113  * A reference to an actual register at the QPU level, for register
 114  * allocation.
 115  */
 116 struct qpu_reg {
 117         bool magic;
 118         int index;
 119 };
 120
 121 struct qinst {
 122         /** Entry in qblock->instructions */
 123         struct list_head link;
 124
 125         /**
 126          * The instruction being wrapped.  Its condition codes, pack flags,
 127          * signals, etc. will all be used, with just the register references
 128          * being replaced by the contents of qinst->dst and qinst->src[].
 129          */
 130         struct v3d_qpu_instr qpu;
 131
 132         /* Pre-register-allocation references to src/dst registers */
 133         struct qreg dst;
 134         struct qreg src[3];
 135         bool cond_is_exec_mask;
 136         bool has_implicit_uniform;
 137
 138         /* After vir_to_qpu.c: If instr reads a uniform, which uniform from
 139          * the uncompiled stream it is.
 140          */
 141         int uniform;
 142 };
 143
 144 enum quniform_contents {
 145         /**
 146          * Indicates that a constant 32-bit value is copied from the program's
 147          * uniform contents.
 148          */
 149         QUNIFORM_CONSTANT,
 150         /**
 151          * Indicates that the program's uniform contents are used as an index
 152          * into the GL uniform storage.
 153          */
 154         QUNIFORM_UNIFORM,
 155
 156         /** @{
 157          * Scaling factors from clip coordinates to relative to the viewport
 158          * center.
 159          *
 160          * This is used by the coordinate and vertex shaders to produce the
 161          * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
 162          * point offsets from the viewport ccenter.
 163          */
 164         QUNIFORM_VIEWPORT_X_SCALE,
 165         QUNIFORM_VIEWPORT_Y_SCALE,
 166         /** @} */
 167
 168         QUNIFORM_VIEWPORT_Z_OFFSET,
 169         QUNIFORM_VIEWPORT_Z_SCALE,
 170
 171         QUNIFORM_USER_CLIP_PLANE,
 172
 173         /**
 174          * A reference to a texture config parameter 0 uniform.
 175          *
 176          * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
 177          * defines texture type, miplevels, and such.  It will be found as a
 178          * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
 179          */
 180         QUNIFORM_TEXTURE_CONFIG_P0_0,
 181         QUNIFORM_TEXTURE_CONFIG_P0_1,
 182         QUNIFORM_TEXTURE_CONFIG_P0_2,
 183         QUNIFORM_TEXTURE_CONFIG_P0_3,
 184         QUNIFORM_TEXTURE_CONFIG_P0_4,
 185         QUNIFORM_TEXTURE_CONFIG_P0_5,
 186         QUNIFORM_TEXTURE_CONFIG_P0_6,
 187         QUNIFORM_TEXTURE_CONFIG_P0_7,
 188         QUNIFORM_TEXTURE_CONFIG_P0_8,
 189         QUNIFORM_TEXTURE_CONFIG_P0_9,
 190         QUNIFORM_TEXTURE_CONFIG_P0_10,
 191         QUNIFORM_TEXTURE_CONFIG_P0_11,
 192         QUNIFORM_TEXTURE_CONFIG_P0_12,
 193         QUNIFORM_TEXTURE_CONFIG_P0_13,
 194         QUNIFORM_TEXTURE_CONFIG_P0_14,
 195         QUNIFORM_TEXTURE_CONFIG_P0_15,
 196         QUNIFORM_TEXTURE_CONFIG_P0_16,
 197         QUNIFORM_TEXTURE_CONFIG_P0_17,
 198         QUNIFORM_TEXTURE_CONFIG_P0_18,
 199         QUNIFORM_TEXTURE_CONFIG_P0_19,
 200         QUNIFORM_TEXTURE_CONFIG_P0_20,
 201         QUNIFORM_TEXTURE_CONFIG_P0_21,
 202         QUNIFORM_TEXTURE_CONFIG_P0_22,
 203         QUNIFORM_TEXTURE_CONFIG_P0_23,
 204         QUNIFORM_TEXTURE_CONFIG_P0_24,
 205         QUNIFORM_TEXTURE_CONFIG_P0_25,
 206         QUNIFORM_TEXTURE_CONFIG_P0_26,
 207         QUNIFORM_TEXTURE_CONFIG_P0_27,
 208         QUNIFORM_TEXTURE_CONFIG_P0_28,
 209         QUNIFORM_TEXTURE_CONFIG_P0_29,
 210         QUNIFORM_TEXTURE_CONFIG_P0_30,
 211         QUNIFORM_TEXTURE_CONFIG_P0_31,
 212         QUNIFORM_TEXTURE_CONFIG_P0_32,
 213
 214         /**
 215          * A reference to a texture config parameter 1 uniform.
 216          *
 217          * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
 218          * has the pointer to the indirect texture state.  Our data[] field
 219          * will have a packed p1 value, but the address field will be just
 220          * which texture unit's texture should be referenced.
 221          */
 222         QUNIFORM_TEXTURE_CONFIG_P1,
 223
 224         QUNIFORM_TEXTURE_FIRST_LEVEL,
 225
 226         QUNIFORM_TEXTURE_WIDTH,
 227         QUNIFORM_TEXTURE_HEIGHT,
 228         QUNIFORM_TEXTURE_DEPTH,
 229         QUNIFORM_TEXTURE_ARRAY_SIZE,
 230         QUNIFORM_TEXTURE_LEVELS,
 231
 232         QUNIFORM_UBO_ADDR,
 233
 234         QUNIFORM_TEXRECT_SCALE_X,
 235         QUNIFORM_TEXRECT_SCALE_Y,
 236
 237         QUNIFORM_TEXTURE_BORDER_COLOR,
 238
 239         QUNIFORM_STENCIL,
 240
 241         QUNIFORM_ALPHA_REF,
 242         QUNIFORM_SAMPLE_MASK,
 243 };
 244
 245 struct v3d_varying_slot {
 246         uint8_t slot_and_component;
 247 };
 248
 249 static inline struct v3d_varying_slot
 250 v3d_slot_from_slot_and_component(uint8_t slot, uint8_t component)
 251 {
 252         assert(slot < 255 / 4);
 253         return (struct v3d_varying_slot){ (slot << 2) + component };
 254 }
 255
 256 static inline uint8_t v3d_slot_get_slot(struct v3d_varying_slot slot)
 257 {
 258         return slot.slot_and_component >> 2;
 259 }
 260
 261 static inline uint8_t v3d_slot_get_component(struct v3d_varying_slot slot)
 262 {
 263         return slot.slot_and_component & 3;
 264 }
 265
 266 struct v3d_ubo_range {
 267         /**
 268          * offset in bytes from the start of the ubo where this range is
 269          * uploaded.
 270          *
 271          * Only set once used is set.
 272          */
 273         uint32_t dst_offset;
 274
 275         /**
 276          * offset in bytes from the start of the gallium uniforms where the
 277          * data comes from.
 278          */
 279         uint32_t src_offset;
 280
 281         /** size in bytes of this ubo range */
 282         uint32_t size;
 283 };
 284
 285 struct v3d_key {
 286         void *shader_state;
 287         struct {
 288                 uint8_t swizzle[4];
 289                 uint8_t return_size;
 290                 uint8_t return_channels;
 291                 union {
 292                         struct {
 293                                 unsigned compare_mode:1;
 294                                 unsigned compare_func:3;
 295                                 bool clamp_s:1;
 296                                 bool clamp_t:1;
 297                                 bool clamp_r:1;
 298                         };
 299                         struct {
 300                                 uint16_t msaa_width, msaa_height;
 301                         };
 302                 };
 303         } tex[V3D_MAX_TEXTURE_SAMPLERS];
 304         uint8_t ucp_enables;
 305 };
 306
 307 struct v3d_fs_key {
 308         struct v3d_key base;
 309         bool depth_enabled;
 310         bool is_points;
 311         bool is_lines;
 312         bool alpha_test;
 313         bool point_coord_upper_left;
 314         bool light_twoside;
 315         bool msaa;
 316         bool sample_coverage;
 317         bool sample_alpha_to_coverage;
 318         bool sample_alpha_to_one;
 319         bool clamp_color;
 320         bool shade_model_flat;
 321         uint8_t nr_cbufs;
 322         uint8_t swap_color_rb;
 323         /* Mask of which render targets need to be written as 32-bit floats */
 324         uint8_t f32_color_rb;
 325         uint8_t alpha_test_func;
 326         uint8_t logicop_func;
 327         uint32_t point_sprite_mask;
 328
 329         struct pipe_rt_blend_state blend;
 330 };
 331
 332 struct v3d_vs_key {
 333         struct v3d_key base;
 334
 335         struct v3d_varying_slot fs_inputs[V3D_MAX_FS_INPUTS];
 336         uint8_t num_fs_inputs;
 337
 338         bool is_coord;
 339         bool per_vertex_point_size;
 340         bool clamp_color;
 341 };
 342
 343 /** A basic block of VIR intructions. */
 344 struct qblock {
 345         struct list_head link;
 346
 347         struct list_head instructions;
 348
 349         struct set *predecessors;
 350         struct qblock *successors[2];
 351
 352         int index;
 353
 354         /* Instruction IPs for the first and last instruction of the block.
 355          * Set by qpu_schedule.c.
 356          */
 357         uint32_t start_qpu_ip;
 358         uint32_t end_qpu_ip;
 359
 360         /* Instruction IP for the branch instruction of the block.  Set by
 361          * qpu_schedule.c.
 362          */
 363         uint32_t branch_qpu_ip;
 364
 365         /** Offset within the uniform stream at the start of the block. */
 366         uint32_t start_uniform;
 367         /** Offset within the uniform stream of the branch instruction */
 368         uint32_t branch_uniform;
 369
 370         /** @{ used by v3d_vir_live_variables.c */
 371         BITSET_WORD *def;
 372         BITSET_WORD *use;
 373         BITSET_WORD *live_in;
 374         BITSET_WORD *live_out;
 375         int start_ip, end_ip;
 376         /** @} */
 377 };
 378
 379 /**
 380  * Compiler state saved across compiler invocations, for any expensive global
 381  * setup.
 382  */
 383 struct v3d_compiler {
 384         const struct v3d_device_info *devinfo;
 385         struct ra_regs *regs;
 386         unsigned int reg_class[3];
 387 };
 388
 389 struct v3d_compile {
 390         const struct v3d_device_info *devinfo;
 391         nir_shader *s;
 392         nir_function_impl *impl;
 393         struct exec_list *cf_node_list;
 394         const struct v3d_compiler *compiler;
 395
 396         /**
 397          * Mapping from nir_register * or nir_ssa_def * to array of struct
 398          * qreg for the values.
 399          */
 400         struct hash_table *def_ht;
 401
 402         /* For each temp, the instruction generating its value. */
 403         struct qinst **defs;
 404         uint32_t defs_array_size;
 405
 406         /**
 407          * Inputs to the shader, arranged by TGSI declaration order.
 408          *
 409          * Not all fragment shader QFILE_VARY reads are present in this array.
 410          */
 411         struct qreg *inputs;
 412         struct qreg *outputs;
 413         bool msaa_per_sample_output;
 414         struct qreg color_reads[V3D_MAX_SAMPLES];
 415         struct qreg sample_colors[V3D_MAX_SAMPLES];
 416         uint32_t inputs_array_size;
 417         uint32_t outputs_array_size;
 418         uint32_t uniforms_array_size;
 419
 420         /* Booleans for whether the corresponding QFILE_VARY[i] is
 421          * flat-shaded.  This includes gl_FragColor flat-shading, which is
 422          * customized based on the shademodel_flat shader key.
 423          */
 424         uint32_t flat_shade_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
 425
 426         struct v3d_ubo_range *ubo_ranges;
 427         bool *ubo_range_used;
 428         uint32_t ubo_ranges_array_size;
 429         /** Number of uniform areas tracked in ubo_ranges. */
 430         uint32_t num_ubo_ranges;
 431         uint32_t next_ubo_dst_offset;
 432
 433         /* State for whether we're executing on each channel currently.  0 if
 434          * yes, otherwise a block number + 1 that the channel jumped to.
 435          */
 436         struct qreg execute;
 437
 438         struct qreg line_x, point_x, point_y;
 439
 440         /**
 441          * Instance ID, which comes in before the vertex attribute payload if
 442          * the shader record requests it.
 443          */
 444         struct qreg iid;
 445
 446         /**
 447          * Vertex ID, which comes in before the vertex attribute payload
 448          * (after Instance ID) if the shader record requests it.
 449          */
 450         struct qreg vid;
 451
 452         /* Fragment shader payload regs. */
 453         struct qreg payload_w, payload_w_centroid, payload_z;
 454
 455         uint8_t vattr_sizes[V3D_MAX_VS_INPUTS];
 456         uint32_t num_vpm_writes;
 457
 458         /**
 459          * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
 460          *
 461          * This includes those that aren't part of the VPM varyings, like
 462          * point/line coordinates.
 463          */
 464         struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
 465
 466         /**
 467          * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
 468          * of the output is.  Used to emit from the VS in the order that the
 469          * FS needs.
 470          */
 471         struct v3d_varying_slot *output_slots;
 472
 473         struct pipe_shader_state *shader_state;
 474         struct v3d_key *key;
 475         struct v3d_fs_key *fs_key;
 476         struct v3d_vs_key *vs_key;
 477
 478         /* Live ranges of temps. */
 479         int *temp_start, *temp_end;
 480
 481         uint32_t *uniform_data;
 482         enum quniform_contents *uniform_contents;
 483         uint32_t uniform_array_size;
 484         uint32_t num_uniforms;
 485         uint32_t num_outputs;
 486         uint32_t output_position_index;
 487         nir_variable *output_color_var[4];
 488         uint32_t output_point_size_index;
 489         uint32_t output_sample_mask_index;
 490
 491         struct qreg undef;
 492         uint32_t num_temps;
 493
 494         struct list_head blocks;
 495         int next_block_index;
 496         struct qblock *cur_block;
 497         struct qblock *loop_cont_block;
 498         struct qblock *loop_break_block;
 499
 500         uint64_t *qpu_insts;
 501         uint32_t qpu_inst_count;
 502         uint32_t qpu_inst_size;
 503
 504         /* For the FS, the number of varying inputs not counting the
 505          * point/line varyings payload
 506          */
 507         uint32_t num_inputs;
 508
 509         /**
 510          * Number of inputs from num_inputs remaining to be queued to the read
 511          * FIFO in the VS/CS.
 512          */
 513         uint32_t num_inputs_remaining;
 514
 515         /* Number of inputs currently in the read FIFO for the VS/CS */
 516         uint32_t num_inputs_in_fifo;
 517
 518         /** Next offset in the VPM to read from in the VS/CS */
 519         uint32_t vpm_read_offset;
 520
 521         uint32_t program_id;
 522         uint32_t variant_id;
 523
 524         /* Set to compile program in threaded FS mode, where SIG_THREAD_SWITCH
 525          * is used to hide texturing latency at the cost of limiting ourselves
 526          * to the bottom half of physical reg space.
 527          */
 528         bool fs_threaded;
 529
 530         bool last_thrsw_at_top_level;
 531
 532         bool failed;
 533 };
 534
 535 struct v3d_uniform_list {
 536         enum quniform_contents *contents;
 537         uint32_t *data;
 538         uint32_t count;
 539 };
 540
 541 struct v3d_prog_data {
 542         struct v3d_uniform_list uniforms;
 543
 544         struct v3d_ubo_range *ubo_ranges;
 545         uint32_t num_ubo_ranges;
 546         uint32_t ubo_size;
 547
 548         uint8_t num_inputs;
 549
 550 };
 551
 552 struct v3d_vs_prog_data {
 553         struct v3d_prog_data base;
 554
 555         bool uses_iid, uses_vid;
 556
 557         /* Number of components read from each vertex attribute. */
 558         uint8_t vattr_sizes[32];
 559
 560         /* Total number of components read, for the shader state record. */
 561         uint32_t vpm_input_size;
 562
 563         /* Total number of components written, for the shader state record. */
 564         uint32_t vpm_output_size;
 565 };
 566
 567 struct v3d_fs_prog_data {
 568         struct v3d_prog_data base;
 569
 570         struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
 571
 572         /* Array of flat shade flags.
 573          *
 574          * Each entry is only 24 bits (high 8 bits 0), to match the hardware
 575          * packet layout.
 576          */
 577         uint32_t flat_shade_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
 578
 579         bool writes_z;
 580         bool discard;
 581 };
 582
 583 /* Special nir_load_input intrinsic index for loading the current TLB
 584  * destination color.
 585  */
 586 #define V3D_NIR_TLB_COLOR_READ_INPUT            2000000000
 587
 588 #define V3D_NIR_MS_MASK_OUTPUT                  2000000000
 589
 590 extern const nir_shader_compiler_options v3d_nir_options;
 591
 592 const struct v3d_compiler *v3d_compiler_init(const struct v3d_device_info *devinfo);
 593 void v3d_compiler_free(const struct v3d_compiler *compiler);
 594 void v3d_optimize_nir(struct nir_shader *s);
 595
 596 uint64_t *v3d_compile_vs(const struct v3d_compiler *compiler,
 597                          struct v3d_vs_key *key,
 598                          struct v3d_vs_prog_data *prog_data,
 599                          nir_shader *s,
 600                          int program_id, int variant_id,
 601                          uint32_t *final_assembly_size);
 602
 603 uint64_t *v3d_compile_fs(const struct v3d_compiler *compiler,
 604                          struct v3d_fs_key *key,
 605                          struct v3d_fs_prog_data *prog_data,
 606                          nir_shader *s,
 607                          int program_id, int variant_id,
 608                          uint32_t *final_assembly_size);
 609
 610 void v3d_nir_to_vir(struct v3d_compile *c);
 611
 612 void vir_compile_destroy(struct v3d_compile *c);
 613 const char *vir_get_stage_name(struct v3d_compile *c);
 614 struct qblock *vir_new_block(struct v3d_compile *c);
 615 void vir_set_emit_block(struct v3d_compile *c, struct qblock *block);
 616 void vir_link_blocks(struct qblock *predecessor, struct qblock *successor);
 617 struct qblock *vir_entry_block(struct v3d_compile *c);
 618 struct qblock *vir_exit_block(struct v3d_compile *c);
 619 struct qinst *vir_add_inst(enum v3d_qpu_add_op op, struct qreg dst,
 620                            struct qreg src0, struct qreg src1);
 621 struct qinst *vir_mul_inst(enum v3d_qpu_mul_op op, struct qreg dst,
 622                            struct qreg src0, struct qreg src1);
 623 struct qinst *vir_branch_inst(enum v3d_qpu_branch_cond cond, struct qreg src0);
 624 void vir_remove_instruction(struct v3d_compile *c, struct qinst *qinst);
 625 struct qreg vir_uniform(struct v3d_compile *c,
 626                         enum quniform_contents contents,
 627                         uint32_t data);
 628 void vir_schedule_instructions(struct v3d_compile *c);
 629 struct v3d_qpu_instr v3d_qpu_nop(void);
 630
 631 struct qreg vir_emit_def(struct v3d_compile *c, struct qinst *inst);
 632 struct qinst *vir_emit_nondef(struct v3d_compile *c, struct qinst *inst);
 633 void vir_set_cond(struct qinst *inst, enum v3d_qpu_cond cond);
 634 void vir_set_pf(struct qinst *inst, enum v3d_qpu_pf pf);
 635 void vir_set_unpack(struct qinst *inst, int src,
 636                     enum v3d_qpu_input_unpack unpack);
 637
 638 struct qreg vir_get_temp(struct v3d_compile *c);
 639 void vir_calculate_live_intervals(struct v3d_compile *c);
 640 bool vir_has_implicit_uniform(struct qinst *inst);
 641 int vir_get_implicit_uniform_src(struct qinst *inst);
 642 int vir_get_non_sideband_nsrc(struct qinst *inst);
 643 int vir_get_nsrc(struct qinst *inst);
 644 bool vir_has_side_effects(struct v3d_compile *c, struct qinst *inst);
 645 bool vir_get_add_op(struct qinst *inst, enum v3d_qpu_add_op *op);
 646 bool vir_get_mul_op(struct qinst *inst, enum v3d_qpu_mul_op *op);
 647 bool vir_is_raw_mov(struct qinst *inst);
 648 bool vir_is_tex(struct qinst *inst);
 649 bool vir_is_add(struct qinst *inst);
 650 bool vir_is_mul(struct qinst *inst);
 651 bool vir_is_float_input(struct qinst *inst);
 652 bool vir_depends_on_flags(struct qinst *inst);
 653 bool vir_writes_r3(struct qinst *inst);
 654 bool vir_writes_r4(struct qinst *inst);
 655 struct qreg vir_follow_movs(struct v3d_compile *c, struct qreg reg);
 656 uint8_t vir_channels_written(struct qinst *inst);
 657
 658 void vir_dump(struct v3d_compile *c);
 659 void vir_dump_inst(struct v3d_compile *c, struct qinst *inst);
 660
 661 void vir_validate(struct v3d_compile *c);
 662
 663 void vir_optimize(struct v3d_compile *c);
 664 bool vir_opt_algebraic(struct v3d_compile *c);
 665 bool vir_opt_constant_folding(struct v3d_compile *c);
 666 bool vir_opt_copy_propagate(struct v3d_compile *c);
 667 bool vir_opt_dead_code(struct v3d_compile *c);
 668 bool vir_opt_peephole_sf(struct v3d_compile *c);
 669 bool vir_opt_small_immediates(struct v3d_compile *c);
 670 bool vir_opt_vpm(struct v3d_compile *c);
 671 void v3d_nir_lower_blend(nir_shader *s, struct v3d_compile *c);
 672 void v3d_nir_lower_io(nir_shader *s, struct v3d_compile *c);
 673 void v3d_nir_lower_txf_ms(nir_shader *s, struct v3d_compile *c);
 674 void vir_lower_uniforms(struct v3d_compile *c);
 675
 676 void v3d_vir_to_qpu(struct v3d_compile *c);
 677 uint32_t v3d_qpu_schedule_instructions(struct v3d_compile *c);
 678 void qpu_validate(struct v3d_compile *c);
 679 struct qpu_reg *v3d_register_allocate(struct v3d_compile *c);
 680 bool vir_init_reg_sets(struct v3d_compiler *compiler);
 681
 682 void vir_PF(struct v3d_compile *c, struct qreg src, enum v3d_qpu_pf pf);
 683
 684 static inline bool
 685 quniform_contents_is_texture_p0(enum quniform_contents contents)
 686 {
 687         return (contents >= QUNIFORM_TEXTURE_CONFIG_P0_0 &&
 688                 contents < (QUNIFORM_TEXTURE_CONFIG_P0_0 +
 689                             V3D_MAX_TEXTURE_SAMPLERS));
 690 }
 691
 692 static inline struct qreg
 693 vir_uniform_ui(struct v3d_compile *c, uint32_t ui)
 694 {
 695         return vir_uniform(c, QUNIFORM_CONSTANT, ui);
 696 }
 697
 698 static inline struct qreg
 699 vir_uniform_f(struct v3d_compile *c, float f)
 700 {
 701         return vir_uniform(c, QUNIFORM_CONSTANT, fui(f));
 702 }
 703
 704 #define VIR_ALU0(name, vir_inst, op)                                     \
 705 static inline struct qreg                                                \
 706 vir_##name(struct v3d_compile *c)                                        \
 707 {                                                                        \
 708         return vir_emit_def(c, vir_inst(op, c->undef,                    \
 709                                         c->undef, c->undef));            \
 710 }                                                                        \
 711 static inline struct qinst *                                             \
 712 vir_##name##_dest(struct v3d_compile *c, struct qreg dest)               \
 713 {                                                                        \
 714         return vir_emit_nondef(c, vir_inst(op, dest,                     \
 715                                            c->undef, c->undef));         \
 716 }
 717
 718 #define VIR_ALU1(name, vir_inst, op)                                     \
 719 static inline struct qreg                                                \
 720 vir_##name(struct v3d_compile *c, struct qreg a)                         \
 721 {                                                                        \
 722         return vir_emit_def(c, vir_inst(op, c->undef,                    \
 723                                         a, c->undef));                   \
 724 }                                                                        \
 725 static inline struct qinst *                                             \
 726 vir_##name##_dest(struct v3d_compile *c, struct qreg dest,               \
 727                   struct qreg a)                                         \
 728 {                                                                        \
 729         return vir_emit_nondef(c, vir_inst(op, dest, a,          \
 730                                            c->undef));                   \
 731 }
 732
 733 #define VIR_ALU2(name, vir_inst, op)                                       \
 734 static inline struct qreg                                                \
 735 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b)          \
 736 {                                                                        \
 737         return vir_emit_def(c, vir_inst(op, c->undef, a, b));    \
 738 }                                                                        \
 739 static inline struct qinst *                                             \
 740 vir_##name##_dest(struct v3d_compile *c, struct qreg dest,               \
 741                   struct qreg a, struct qreg b)                          \
 742 {                                                                        \
 743         return vir_emit_nondef(c, vir_inst(op, dest, a, b));     \
 744 }
 745
 746 #define VIR_NODST_1(name, vir_inst, op)                                               \
 747 static inline struct qinst *                                            \
 748 vir_##name(struct v3d_compile *c, struct qreg a)                        \
 749 {                                                                       \
 750         return vir_emit_nondef(c, vir_inst(op, c->undef,        \
 751                                            a, c->undef));               \
 752 }
 753
 754 #define VIR_NODST_2(name, vir_inst, op)                                               \
 755 static inline struct qinst *                                            \
 756 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b)         \
 757 {                                                                       \
 758         return vir_emit_nondef(c, vir_inst(op, c->undef,                \
 759                                            a, b));                      \
 760 }
 761
 762 #define VIR_A_ALU2(name) VIR_ALU2(name, vir_add_inst, V3D_QPU_A_##name)
 763 #define VIR_M_ALU2(name) VIR_ALU2(name, vir_mul_inst, V3D_QPU_M_##name)
 764 #define VIR_A_ALU1(name) VIR_ALU1(name, vir_add_inst, V3D_QPU_A_##name)
 765 #define VIR_M_ALU1(name) VIR_ALU1(name, vir_mul_inst, V3D_QPU_M_##name)
 766 #define VIR_A_ALU0(name) VIR_ALU0(name, vir_add_inst, V3D_QPU_A_##name)
 767 #define VIR_M_ALU0(name) VIR_ALU0(name, vir_mul_inst, V3D_QPU_M_##name)
 768 #define VIR_A_NODST_2(name) VIR_NODST_2(name, vir_add_inst, V3D_QPU_A_##name)
 769 #define VIR_M_NODST_2(name) VIR_NODST_2(name, vir_mul_inst, V3D_QPU_M_##name)
 770 #define VIR_A_NODST_1(name) VIR_NODST_1(name, vir_add_inst, V3D_QPU_A_##name)
 771 #define VIR_M_NODST_1(name) VIR_NODST_1(name, vir_mul_inst, V3D_QPU_M_##name)
 772
 773 VIR_A_ALU2(FADD)
 774 VIR_A_ALU2(VFPACK)
 775 VIR_A_ALU2(FSUB)
 776 VIR_A_ALU2(FMIN)
 777 VIR_A_ALU2(FMAX)
 778
 779 VIR_A_ALU2(ADD)
 780 VIR_A_ALU2(SUB)
 781 VIR_A_ALU2(SHL)
 782 VIR_A_ALU2(SHR)
 783 VIR_A_ALU2(ASR)
 784 VIR_A_ALU2(ROR)
 785 VIR_A_ALU2(MIN)
 786 VIR_A_ALU2(MAX)
 787 VIR_A_ALU2(UMIN)
 788 VIR_A_ALU2(UMAX)
 789 VIR_A_ALU2(AND)
 790 VIR_A_ALU2(OR)
 791 VIR_A_ALU2(XOR)
 792 VIR_A_ALU2(VADD)
 793 VIR_A_ALU2(VSUB)
 794 VIR_A_ALU1(NOT)
 795 VIR_A_ALU1(NEG)
 796 VIR_A_ALU1(FLAPUSH)
 797 VIR_A_ALU1(FLBPUSH)
 798 VIR_A_ALU1(FLBPOP)
 799 VIR_A_ALU1(SETMSF)
 800 VIR_A_ALU1(SETREVF)
 801 VIR_A_ALU1(TIDX)
 802 VIR_A_ALU1(EIDX)
 803
 804 VIR_A_ALU0(FXCD)
 805 VIR_A_ALU0(XCD)
 806 VIR_A_ALU0(FYCD)
 807 VIR_A_ALU0(YCD)
 808 VIR_A_ALU0(MSF)
 809 VIR_A_ALU0(REVF)
 810 VIR_A_NODST_1(VPMSETUP)
 811 VIR_A_ALU2(FCMP)
 812 VIR_A_ALU2(VFMAX)
 813
 814 VIR_A_ALU1(FROUND)
 815 VIR_A_ALU1(FTOIN)
 816 VIR_A_ALU1(FTRUNC)
 817 VIR_A_ALU1(FTOIZ)
 818 VIR_A_ALU1(FFLOOR)
 819 VIR_A_ALU1(FTOUZ)
 820 VIR_A_ALU1(FCEIL)
 821 VIR_A_ALU1(FTOC)
 822
 823 VIR_A_ALU1(FDX)
 824 VIR_A_ALU1(FDY)
 825
 826 VIR_A_ALU1(ITOF)
 827 VIR_A_ALU1(CLZ)
 828 VIR_A_ALU1(UTOF)
 829
 830 VIR_M_ALU2(UMUL24)
 831 VIR_M_ALU2(FMUL)
 832 VIR_M_ALU2(SMUL24)
 833 VIR_M_NODST_2(MULTOP)
 834
 835 VIR_M_ALU1(MOV)
 836 VIR_M_ALU1(FMOV)
 837
 838 static inline struct qinst *
 839 vir_MOV_cond(struct v3d_compile *c, enum v3d_qpu_cond cond,
 840              struct qreg dest, struct qreg src)
 841 {
 842         struct qinst *mov = vir_MOV_dest(c, dest, src);
 843         vir_set_cond(mov, cond);
 844         return mov;
 845 }
 846
 847 static inline struct qreg
 848 vir_SEL(struct v3d_compile *c, enum v3d_qpu_cond cond,
 849         struct qreg src0, struct qreg src1)
 850 {
 851         struct qreg t = vir_get_temp(c);
 852         vir_MOV_dest(c, t, src1);
 853         vir_MOV_cond(c, cond, t, src0);
 854         return t;
 855 }
 856
 857 static inline void
 858 vir_VPM_WRITE(struct v3d_compile *c, struct qreg val)
 859 {
 860         vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM), val);
 861 }
 862
 863 static inline struct qinst *
 864 vir_NOP(struct v3d_compile *c)
 865 {
 866         return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_NOP,
 867                                                c->undef, c->undef, c->undef));
 868 }
 869 /*
 870 static inline struct qreg
 871 vir_LOAD_IMM(struct v3d_compile *c, uint32_t val)
 872 {
 873         return vir_emit_def(c, vir_inst(QOP_LOAD_IMM, c->undef,
 874                                         vir_reg(QFILE_LOAD_IMM, val), c->undef));
 875 }
 876
 877 static inline struct qreg
 878 vir_LOAD_IMM_U2(struct v3d_compile *c, uint32_t val)
 879 {
 880         return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_U2, c->undef,
 881                                         vir_reg(QFILE_LOAD_IMM, val),
 882                                         c->undef));
 883 }
 884 static inline struct qreg
 885 vir_LOAD_IMM_I2(struct v3d_compile *c, uint32_t val)
 886 {
 887         return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_I2, c->undef,
 888                                         vir_reg(QFILE_LOAD_IMM, val),
 889                                         c->undef));
 890 }
 891 */
 892
 893 static inline struct qinst *
 894 vir_BRANCH(struct v3d_compile *c, enum v3d_qpu_cond cond)
 895 {
 896         /* The actual uniform_data value will be set at scheduling time */
 897         return vir_emit_nondef(c, vir_branch_inst(cond, vir_uniform_ui(c, 0)));
 898 }
 899
 900 #define vir_for_each_block(block, c)                                    \
 901         list_for_each_entry(struct qblock, block, &c->blocks, link)
 902
 903 #define vir_for_each_block_rev(block, c)                                \
 904         list_for_each_entry_rev(struct qblock, block, &c->blocks, link)
 905
 906 /* Loop over the non-NULL members of the successors array. */
 907 #define vir_for_each_successor(succ, block)                             \
 908         for (struct qblock *succ = block->successors[0];                \
 909              succ != NULL;                                              \
 910              succ = (succ == block->successors[1] ? NULL :              \
 911                      block->successors[1]))
 912
 913 #define vir_for_each_inst(inst, block)                                  \
 914         list_for_each_entry(struct qinst, inst, &block->instructions, link)
 915
 916 #define vir_for_each_inst_rev(inst, block)                                  \
 917         list_for_each_entry_rev(struct qinst, inst, &block->instructions, link)
 918
 919 #define vir_for_each_inst_safe(inst, block)                             \
 920         list_for_each_entry_safe(struct qinst, inst, &block->instructions, link)
 921
 922 #define vir_for_each_inst_inorder(inst, c)                              \
 923         vir_for_each_block(_block, c)                                   \
 924                 vir_for_each_inst(inst, _block)
 925
 926 #endif /* V3D_COMPILER_H */