a5f99d3dae8eb8899bdb3f50eeaf4f0584a6a596
[mesa.git] / src / broadcom / compiler / v3d_compiler.h
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef V3D_COMPILER_H
25 #define V3D_COMPILER_H
26
27 #include <assert.h>
28 #include <stdio.h>
29 #include <stdlib.h>
30 #include <stdbool.h>
31 #include <stdint.h>
32 #include <string.h>
33
34 #include "util/macros.h"
35 #include "common/v3d_debug.h"
36 #include "common/v3d_device_info.h"
37 #include "compiler/nir/nir.h"
38 #include "util/list.h"
39 #include "util/u_math.h"
40
41 #include "qpu/qpu_instr.h"
42 #include "pipe/p_state.h"
43
44 #define V3D_MAX_TEXTURE_SAMPLERS 32
45 #define V3D_MAX_SAMPLES 4
46 #define V3D_MAX_FS_INPUTS 64
47 #define V3D_MAX_VS_INPUTS 64
48
49 struct nir_builder;
50
51 struct v3d_fs_inputs {
52 /**
53 * Array of the meanings of the VPM inputs this shader needs.
54 *
55 * It doesn't include those that aren't part of the VPM, like
56 * point/line coordinates.
57 */
58 struct v3d_varying_slot *input_slots;
59 uint32_t num_inputs;
60 };
61
62 enum qfile {
63 /** An unused source or destination register. */
64 QFILE_NULL,
65
66 /** A physical register, such as the W coordinate payload. */
67 QFILE_REG,
68 /** One of the regsiters for fixed function interactions. */
69 QFILE_MAGIC,
70
71 /**
72 * A virtual register, that will be allocated to actual accumulator
73 * or physical registers later.
74 */
75 QFILE_TEMP,
76 QFILE_UNIF,
77 QFILE_TLB,
78 QFILE_TLBU,
79
80 /**
81 * VPM reads use this with an index value to say what part of the VPM
82 * is being read.
83 */
84 QFILE_VPM,
85
86 /**
87 * Stores an immediate value in the index field that will be used
88 * directly by qpu_load_imm().
89 */
90 QFILE_LOAD_IMM,
91
92 /**
93 * Stores an immediate value in the index field that can be turned
94 * into a small immediate field by qpu_encode_small_immediate().
95 */
96 QFILE_SMALL_IMM,
97 };
98
99 /**
100 * A reference to a QPU register or a virtual temp register.
101 */
102 struct qreg {
103 enum qfile file;
104 uint32_t index;
105 };
106
107 static inline struct qreg vir_reg(enum qfile file, uint32_t index)
108 {
109 return (struct qreg){file, index};
110 }
111
112 /**
113 * A reference to an actual register at the QPU level, for register
114 * allocation.
115 */
116 struct qpu_reg {
117 bool magic;
118 bool smimm;
119 int index;
120 };
121
122 struct qinst {
123 /** Entry in qblock->instructions */
124 struct list_head link;
125
126 /**
127 * The instruction being wrapped. Its condition codes, pack flags,
128 * signals, etc. will all be used, with just the register references
129 * being replaced by the contents of qinst->dst and qinst->src[].
130 */
131 struct v3d_qpu_instr qpu;
132
133 /* Pre-register-allocation references to src/dst registers */
134 struct qreg dst;
135 struct qreg src[3];
136 bool cond_is_exec_mask;
137 bool has_implicit_uniform;
138 bool is_last_thrsw;
139
140 /* After vir_to_qpu.c: If instr reads a uniform, which uniform from
141 * the uncompiled stream it is.
142 */
143 int uniform;
144 };
145
146 enum quniform_contents {
147 /**
148 * Indicates that a constant 32-bit value is copied from the program's
149 * uniform contents.
150 */
151 QUNIFORM_CONSTANT,
152 /**
153 * Indicates that the program's uniform contents are used as an index
154 * into the GL uniform storage.
155 */
156 QUNIFORM_UNIFORM,
157
158 /** @{
159 * Scaling factors from clip coordinates to relative to the viewport
160 * center.
161 *
162 * This is used by the coordinate and vertex shaders to produce the
163 * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
164 * point offsets from the viewport ccenter.
165 */
166 QUNIFORM_VIEWPORT_X_SCALE,
167 QUNIFORM_VIEWPORT_Y_SCALE,
168 /** @} */
169
170 QUNIFORM_VIEWPORT_Z_OFFSET,
171 QUNIFORM_VIEWPORT_Z_SCALE,
172
173 QUNIFORM_USER_CLIP_PLANE,
174
175 /**
176 * A reference to a V3D 3.x texture config parameter 0 uniform.
177 *
178 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
179 * defines texture type, miplevels, and such. It will be found as a
180 * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
181 */
182 QUNIFORM_TEXTURE_CONFIG_P0_0,
183 QUNIFORM_TEXTURE_CONFIG_P0_1,
184 QUNIFORM_TEXTURE_CONFIG_P0_2,
185 QUNIFORM_TEXTURE_CONFIG_P0_3,
186 QUNIFORM_TEXTURE_CONFIG_P0_4,
187 QUNIFORM_TEXTURE_CONFIG_P0_5,
188 QUNIFORM_TEXTURE_CONFIG_P0_6,
189 QUNIFORM_TEXTURE_CONFIG_P0_7,
190 QUNIFORM_TEXTURE_CONFIG_P0_8,
191 QUNIFORM_TEXTURE_CONFIG_P0_9,
192 QUNIFORM_TEXTURE_CONFIG_P0_10,
193 QUNIFORM_TEXTURE_CONFIG_P0_11,
194 QUNIFORM_TEXTURE_CONFIG_P0_12,
195 QUNIFORM_TEXTURE_CONFIG_P0_13,
196 QUNIFORM_TEXTURE_CONFIG_P0_14,
197 QUNIFORM_TEXTURE_CONFIG_P0_15,
198 QUNIFORM_TEXTURE_CONFIG_P0_16,
199 QUNIFORM_TEXTURE_CONFIG_P0_17,
200 QUNIFORM_TEXTURE_CONFIG_P0_18,
201 QUNIFORM_TEXTURE_CONFIG_P0_19,
202 QUNIFORM_TEXTURE_CONFIG_P0_20,
203 QUNIFORM_TEXTURE_CONFIG_P0_21,
204 QUNIFORM_TEXTURE_CONFIG_P0_22,
205 QUNIFORM_TEXTURE_CONFIG_P0_23,
206 QUNIFORM_TEXTURE_CONFIG_P0_24,
207 QUNIFORM_TEXTURE_CONFIG_P0_25,
208 QUNIFORM_TEXTURE_CONFIG_P0_26,
209 QUNIFORM_TEXTURE_CONFIG_P0_27,
210 QUNIFORM_TEXTURE_CONFIG_P0_28,
211 QUNIFORM_TEXTURE_CONFIG_P0_29,
212 QUNIFORM_TEXTURE_CONFIG_P0_30,
213 QUNIFORM_TEXTURE_CONFIG_P0_31,
214 QUNIFORM_TEXTURE_CONFIG_P0_32,
215
216 /**
217 * A reference to a V3D 3.x texture config parameter 1 uniform.
218 *
219 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
220 * has the pointer to the indirect texture state. Our data[] field
221 * will have a packed p1 value, but the address field will be just
222 * which texture unit's texture should be referenced.
223 */
224 QUNIFORM_TEXTURE_CONFIG_P1,
225
226 /* A V3D 4.x texture config parameter. The high 8 bits will be
227 * which texture or sampler is being sampled, and the driver must
228 * replace the address field with the appropriate address.
229 */
230 QUNIFORM_TMU_CONFIG_P0,
231 QUNIFORM_TMU_CONFIG_P1,
232
233 QUNIFORM_IMAGE_TMU_CONFIG_P0,
234
235 QUNIFORM_TEXTURE_FIRST_LEVEL,
236
237 QUNIFORM_TEXTURE_WIDTH,
238 QUNIFORM_TEXTURE_HEIGHT,
239 QUNIFORM_TEXTURE_DEPTH,
240 QUNIFORM_TEXTURE_ARRAY_SIZE,
241 QUNIFORM_TEXTURE_LEVELS,
242
243 QUNIFORM_UBO_ADDR,
244
245 QUNIFORM_TEXRECT_SCALE_X,
246 QUNIFORM_TEXRECT_SCALE_Y,
247
248 /* Returns the base offset of the SSBO given by the data value. */
249 QUNIFORM_SSBO_OFFSET,
250
251 /* Returns the size of the SSBO given by the data value. */
252 QUNIFORM_GET_BUFFER_SIZE,
253
254 /* Sizes (in pixels) of a shader image given by the data value. */
255 QUNIFORM_IMAGE_WIDTH,
256 QUNIFORM_IMAGE_HEIGHT,
257 QUNIFORM_IMAGE_DEPTH,
258 QUNIFORM_IMAGE_ARRAY_SIZE,
259
260 QUNIFORM_ALPHA_REF,
261
262 /**
263 * Returns the the offset of the scratch buffer for register spilling.
264 */
265 QUNIFORM_SPILL_OFFSET,
266 QUNIFORM_SPILL_SIZE_PER_THREAD,
267 };
268
269 static inline uint32_t v3d_tmu_config_data_create(uint32_t unit, uint32_t value)
270 {
271 return unit << 24 | value;
272 }
273
274 static inline uint32_t v3d_tmu_config_data_get_unit(uint32_t data)
275 {
276 return data >> 24;
277 }
278
279 static inline uint32_t v3d_tmu_config_data_get_value(uint32_t data)
280 {
281 return data & 0xffffff;
282 }
283
284 struct v3d_varying_slot {
285 uint8_t slot_and_component;
286 };
287
288 static inline struct v3d_varying_slot
289 v3d_slot_from_slot_and_component(uint8_t slot, uint8_t component)
290 {
291 assert(slot < 255 / 4);
292 return (struct v3d_varying_slot){ (slot << 2) + component };
293 }
294
295 static inline uint8_t v3d_slot_get_slot(struct v3d_varying_slot slot)
296 {
297 return slot.slot_and_component >> 2;
298 }
299
300 static inline uint8_t v3d_slot_get_component(struct v3d_varying_slot slot)
301 {
302 return slot.slot_and_component & 3;
303 }
304
305 struct v3d_ubo_range {
306 /**
307 * offset in bytes from the start of the ubo where this range is
308 * uploaded.
309 *
310 * Only set once used is set.
311 */
312 uint32_t dst_offset;
313
314 /**
315 * offset in bytes from the start of the gallium uniforms where the
316 * data comes from.
317 */
318 uint32_t src_offset;
319
320 /** size in bytes of this ubo range */
321 uint32_t size;
322 };
323
324 struct v3d_key {
325 void *shader_state;
326 struct {
327 uint8_t swizzle[4];
328 uint8_t return_size;
329 uint8_t return_channels;
330 bool clamp_s:1;
331 bool clamp_t:1;
332 bool clamp_r:1;
333 } tex[V3D_MAX_TEXTURE_SAMPLERS];
334 uint8_t ucp_enables;
335 };
336
337 struct v3d_fs_key {
338 struct v3d_key base;
339 bool depth_enabled;
340 bool is_points;
341 bool is_lines;
342 bool alpha_test;
343 bool point_coord_upper_left;
344 bool light_twoside;
345 bool msaa;
346 bool sample_coverage;
347 bool sample_alpha_to_coverage;
348 bool sample_alpha_to_one;
349 bool clamp_color;
350 bool shade_model_flat;
351 uint8_t nr_cbufs;
352 uint8_t swap_color_rb;
353 /* Mask of which render targets need to be written as 32-bit floats */
354 uint8_t f32_color_rb;
355 /* Masks of which render targets need to be written as ints/uints.
356 * Used by gallium to work around lost information in TGSI.
357 */
358 uint8_t int_color_rb;
359 uint8_t uint_color_rb;
360 uint8_t alpha_test_func;
361 uint8_t logicop_func;
362 uint32_t point_sprite_mask;
363
364 struct pipe_rt_blend_state blend;
365 };
366
367 struct v3d_vs_key {
368 struct v3d_key base;
369
370 struct v3d_varying_slot fs_inputs[V3D_MAX_FS_INPUTS];
371 uint8_t num_fs_inputs;
372
373 bool is_coord;
374 bool per_vertex_point_size;
375 bool clamp_color;
376 };
377
378 /** A basic block of VIR intructions. */
379 struct qblock {
380 struct list_head link;
381
382 struct list_head instructions;
383
384 struct set *predecessors;
385 struct qblock *successors[2];
386
387 int index;
388
389 /* Instruction IPs for the first and last instruction of the block.
390 * Set by qpu_schedule.c.
391 */
392 uint32_t start_qpu_ip;
393 uint32_t end_qpu_ip;
394
395 /* Instruction IP for the branch instruction of the block. Set by
396 * qpu_schedule.c.
397 */
398 uint32_t branch_qpu_ip;
399
400 /** Offset within the uniform stream at the start of the block. */
401 uint32_t start_uniform;
402 /** Offset within the uniform stream of the branch instruction */
403 uint32_t branch_uniform;
404
405 /** @{ used by v3d_vir_live_variables.c */
406 BITSET_WORD *def;
407 BITSET_WORD *use;
408 BITSET_WORD *live_in;
409 BITSET_WORD *live_out;
410 int start_ip, end_ip;
411 /** @} */
412 };
413
414 /** Which util/list.h add mode we should use when inserting an instruction. */
415 enum vir_cursor_mode {
416 vir_cursor_add,
417 vir_cursor_addtail,
418 };
419
420 /**
421 * Tracking structure for where new instructions should be inserted. Create
422 * with one of the vir_after_inst()-style helper functions.
423 *
424 * This does not protect against removal of the block or instruction, so we
425 * have an assert in instruction removal to try to catch it.
426 */
427 struct vir_cursor {
428 enum vir_cursor_mode mode;
429 struct list_head *link;
430 };
431
432 static inline struct vir_cursor
433 vir_before_inst(struct qinst *inst)
434 {
435 return (struct vir_cursor){ vir_cursor_addtail, &inst->link };
436 }
437
438 static inline struct vir_cursor
439 vir_after_inst(struct qinst *inst)
440 {
441 return (struct vir_cursor){ vir_cursor_add, &inst->link };
442 }
443
444 static inline struct vir_cursor
445 vir_before_block(struct qblock *block)
446 {
447 return (struct vir_cursor){ vir_cursor_add, &block->instructions };
448 }
449
450 static inline struct vir_cursor
451 vir_after_block(struct qblock *block)
452 {
453 return (struct vir_cursor){ vir_cursor_addtail, &block->instructions };
454 }
455
456 /**
457 * Compiler state saved across compiler invocations, for any expensive global
458 * setup.
459 */
460 struct v3d_compiler {
461 const struct v3d_device_info *devinfo;
462 struct ra_regs *regs;
463 unsigned int reg_class_phys[3];
464 unsigned int reg_class_phys_or_acc[3];
465 };
466
467 struct v3d_compile {
468 const struct v3d_device_info *devinfo;
469 nir_shader *s;
470 nir_function_impl *impl;
471 struct exec_list *cf_node_list;
472 const struct v3d_compiler *compiler;
473
474 void (*debug_output)(const char *msg,
475 void *debug_output_data);
476 void *debug_output_data;
477
478 /**
479 * Mapping from nir_register * or nir_ssa_def * to array of struct
480 * qreg for the values.
481 */
482 struct hash_table *def_ht;
483
484 /* For each temp, the instruction generating its value. */
485 struct qinst **defs;
486 uint32_t defs_array_size;
487
488 /**
489 * Inputs to the shader, arranged by TGSI declaration order.
490 *
491 * Not all fragment shader QFILE_VARY reads are present in this array.
492 */
493 struct qreg *inputs;
494 struct qreg *outputs;
495 bool msaa_per_sample_output;
496 struct qreg color_reads[V3D_MAX_SAMPLES];
497 struct qreg sample_colors[V3D_MAX_SAMPLES];
498 uint32_t inputs_array_size;
499 uint32_t outputs_array_size;
500 uint32_t uniforms_array_size;
501
502 /* Booleans for whether the corresponding QFILE_VARY[i] is
503 * flat-shaded. This includes gl_FragColor flat-shading, which is
504 * customized based on the shademodel_flat shader key.
505 */
506 uint32_t flat_shade_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
507
508 uint32_t noperspective_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
509
510 uint32_t centroid_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
511
512 bool uses_center_w;
513
514 struct v3d_ubo_range *ubo_ranges;
515 bool *ubo_range_used;
516 uint32_t ubo_ranges_array_size;
517 /** Number of uniform areas tracked in ubo_ranges. */
518 uint32_t num_ubo_ranges;
519 uint32_t next_ubo_dst_offset;
520
521 /* State for whether we're executing on each channel currently. 0 if
522 * yes, otherwise a block number + 1 that the channel jumped to.
523 */
524 struct qreg execute;
525
526 struct qreg line_x, point_x, point_y;
527
528 /**
529 * Instance ID, which comes in before the vertex attribute payload if
530 * the shader record requests it.
531 */
532 struct qreg iid;
533
534 /**
535 * Vertex ID, which comes in before the vertex attribute payload
536 * (after Instance ID) if the shader record requests it.
537 */
538 struct qreg vid;
539
540 /* Fragment shader payload regs. */
541 struct qreg payload_w, payload_w_centroid, payload_z;
542
543 uint8_t vattr_sizes[V3D_MAX_VS_INPUTS];
544 uint32_t num_vpm_writes;
545
546 /* Size in bytes of registers that have been spilled. This is how much
547 * space needs to be available in the spill BO per thread per QPU.
548 */
549 uint32_t spill_size;
550 /* Shader-db stats */
551 uint32_t spills, fills, loops;
552 /**
553 * Register spilling's per-thread base address, shared between each
554 * spill/fill's addressing calculations.
555 */
556 struct qreg spill_base;
557 /* Bit vector of which temps may be spilled */
558 BITSET_WORD *spillable;
559
560 /**
561 * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
562 *
563 * This includes those that aren't part of the VPM varyings, like
564 * point/line coordinates.
565 */
566 struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
567
568 /**
569 * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
570 * of the output is. Used to emit from the VS in the order that the
571 * FS needs.
572 */
573 struct v3d_varying_slot *output_slots;
574
575 struct pipe_shader_state *shader_state;
576 struct v3d_key *key;
577 struct v3d_fs_key *fs_key;
578 struct v3d_vs_key *vs_key;
579
580 /* Live ranges of temps. */
581 int *temp_start, *temp_end;
582 bool live_intervals_valid;
583
584 uint32_t *uniform_data;
585 enum quniform_contents *uniform_contents;
586 uint32_t uniform_array_size;
587 uint32_t num_uniforms;
588 uint32_t num_outputs;
589 uint32_t output_position_index;
590 nir_variable *output_color_var[4];
591 uint32_t output_point_size_index;
592 uint32_t output_sample_mask_index;
593
594 struct qreg undef;
595 uint32_t num_temps;
596
597 struct vir_cursor cursor;
598 struct list_head blocks;
599 int next_block_index;
600 struct qblock *cur_block;
601 struct qblock *loop_cont_block;
602 struct qblock *loop_break_block;
603
604 uint64_t *qpu_insts;
605 uint32_t qpu_inst_count;
606 uint32_t qpu_inst_size;
607
608 /* For the FS, the number of varying inputs not counting the
609 * point/line varyings payload
610 */
611 uint32_t num_inputs;
612
613 /**
614 * Number of inputs from num_inputs remaining to be queued to the read
615 * FIFO in the VS/CS.
616 */
617 uint32_t num_inputs_remaining;
618
619 /* Number of inputs currently in the read FIFO for the VS/CS */
620 uint32_t num_inputs_in_fifo;
621
622 /** Next offset in the VPM to read from in the VS/CS */
623 uint32_t vpm_read_offset;
624
625 uint32_t program_id;
626 uint32_t variant_id;
627
628 /* Set to compile program in in 1x, 2x, or 4x threaded mode, where
629 * SIG_THREAD_SWITCH is used to hide texturing latency at the cost of
630 * limiting ourselves to the part of the physical reg space.
631 *
632 * On V3D 3.x, 2x or 4x divide the physical reg space by 2x or 4x. On
633 * V3D 4.x, all shaders are 2x threaded, and 4x only divides the
634 * physical reg space in half.
635 */
636 uint8_t threads;
637 struct qinst *last_thrsw;
638 bool last_thrsw_at_top_level;
639
640 bool failed;
641 };
642
643 struct v3d_uniform_list {
644 enum quniform_contents *contents;
645 uint32_t *data;
646 uint32_t count;
647 };
648
649 struct v3d_prog_data {
650 struct v3d_uniform_list uniforms;
651
652 struct v3d_ubo_range *ubo_ranges;
653 uint32_t num_ubo_ranges;
654 uint32_t ubo_size;
655 uint32_t spill_size;
656
657 uint8_t num_inputs;
658 uint8_t threads;
659
660 /* For threads > 1, whether the program should be dispatched in the
661 * after-final-THRSW state.
662 */
663 bool single_seg;
664 };
665
666 struct v3d_vs_prog_data {
667 struct v3d_prog_data base;
668
669 bool uses_iid, uses_vid;
670
671 /* Number of components read from each vertex attribute. */
672 uint8_t vattr_sizes[32];
673
674 /* Total number of components read, for the shader state record. */
675 uint32_t vpm_input_size;
676
677 /* Total number of components written, for the shader state record. */
678 uint32_t vpm_output_size;
679
680 /* Set if there should be separate VPM segments for input and output.
681 * If unset, vpm_input_size will be 0.
682 */
683 bool separate_segments;
684
685 /* Value to be programmed in VCM_CACHE_SIZE. */
686 uint8_t vcm_cache_size;
687 };
688
689 struct v3d_fs_prog_data {
690 struct v3d_prog_data base;
691
692 struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
693
694 /* Array of flat shade flags.
695 *
696 * Each entry is only 24 bits (high 8 bits 0), to match the hardware
697 * packet layout.
698 */
699 uint32_t flat_shade_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
700
701 uint32_t noperspective_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
702
703 uint32_t centroid_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
704
705 bool writes_z;
706 bool discard;
707 bool uses_center_w;
708 };
709
710 /* Special nir_load_input intrinsic index for loading the current TLB
711 * destination color.
712 */
713 #define V3D_NIR_TLB_COLOR_READ_INPUT 2000000000
714
715 #define V3D_NIR_MS_MASK_OUTPUT 2000000000
716
717 extern const nir_shader_compiler_options v3d_nir_options;
718
719 const struct v3d_compiler *v3d_compiler_init(const struct v3d_device_info *devinfo);
720 void v3d_compiler_free(const struct v3d_compiler *compiler);
721 void v3d_optimize_nir(struct nir_shader *s);
722
723 uint64_t *v3d_compile(const struct v3d_compiler *compiler,
724 struct v3d_key *key,
725 struct v3d_prog_data **prog_data,
726 nir_shader *s,
727 void (*debug_output)(const char *msg,
728 void *debug_output_data),
729 void *debug_output_data,
730 int program_id, int variant_id,
731 uint32_t *final_assembly_size);
732
733 void v3d_nir_to_vir(struct v3d_compile *c);
734
735 void vir_compile_destroy(struct v3d_compile *c);
736 const char *vir_get_stage_name(struct v3d_compile *c);
737 struct qblock *vir_new_block(struct v3d_compile *c);
738 void vir_set_emit_block(struct v3d_compile *c, struct qblock *block);
739 void vir_link_blocks(struct qblock *predecessor, struct qblock *successor);
740 struct qblock *vir_entry_block(struct v3d_compile *c);
741 struct qblock *vir_exit_block(struct v3d_compile *c);
742 struct qinst *vir_add_inst(enum v3d_qpu_add_op op, struct qreg dst,
743 struct qreg src0, struct qreg src1);
744 struct qinst *vir_mul_inst(enum v3d_qpu_mul_op op, struct qreg dst,
745 struct qreg src0, struct qreg src1);
746 struct qinst *vir_branch_inst(enum v3d_qpu_branch_cond cond, struct qreg src0);
747 void vir_remove_instruction(struct v3d_compile *c, struct qinst *qinst);
748 struct qreg vir_uniform(struct v3d_compile *c,
749 enum quniform_contents contents,
750 uint32_t data);
751 void vir_schedule_instructions(struct v3d_compile *c);
752 struct v3d_qpu_instr v3d_qpu_nop(void);
753
754 struct qreg vir_emit_def(struct v3d_compile *c, struct qinst *inst);
755 struct qinst *vir_emit_nondef(struct v3d_compile *c, struct qinst *inst);
756 void vir_set_cond(struct qinst *inst, enum v3d_qpu_cond cond);
757 void vir_set_pf(struct qinst *inst, enum v3d_qpu_pf pf);
758 void vir_set_uf(struct qinst *inst, enum v3d_qpu_uf uf);
759 void vir_set_unpack(struct qinst *inst, int src,
760 enum v3d_qpu_input_unpack unpack);
761
762 struct qreg vir_get_temp(struct v3d_compile *c);
763 void vir_emit_last_thrsw(struct v3d_compile *c);
764 void vir_calculate_live_intervals(struct v3d_compile *c);
765 bool vir_has_implicit_uniform(struct qinst *inst);
766 int vir_get_implicit_uniform_src(struct qinst *inst);
767 int vir_get_non_sideband_nsrc(struct qinst *inst);
768 int vir_get_nsrc(struct qinst *inst);
769 bool vir_has_side_effects(struct v3d_compile *c, struct qinst *inst);
770 bool vir_get_add_op(struct qinst *inst, enum v3d_qpu_add_op *op);
771 bool vir_get_mul_op(struct qinst *inst, enum v3d_qpu_mul_op *op);
772 bool vir_is_raw_mov(struct qinst *inst);
773 bool vir_is_tex(struct qinst *inst);
774 bool vir_is_add(struct qinst *inst);
775 bool vir_is_mul(struct qinst *inst);
776 bool vir_is_float_input(struct qinst *inst);
777 bool vir_writes_r3(const struct v3d_device_info *devinfo, struct qinst *inst);
778 bool vir_writes_r4(const struct v3d_device_info *devinfo, struct qinst *inst);
779 struct qreg vir_follow_movs(struct v3d_compile *c, struct qreg reg);
780 uint8_t vir_channels_written(struct qinst *inst);
781 struct qreg ntq_get_src(struct v3d_compile *c, nir_src src, int i);
782 void ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
783 struct qreg result);
784 void vir_emit_thrsw(struct v3d_compile *c);
785
786 void vir_dump(struct v3d_compile *c);
787 void vir_dump_inst(struct v3d_compile *c, struct qinst *inst);
788 void vir_dump_uniform(enum quniform_contents contents, uint32_t data);
789
790 void vir_validate(struct v3d_compile *c);
791
792 void vir_optimize(struct v3d_compile *c);
793 bool vir_opt_algebraic(struct v3d_compile *c);
794 bool vir_opt_constant_folding(struct v3d_compile *c);
795 bool vir_opt_copy_propagate(struct v3d_compile *c);
796 bool vir_opt_dead_code(struct v3d_compile *c);
797 bool vir_opt_peephole_sf(struct v3d_compile *c);
798 bool vir_opt_small_immediates(struct v3d_compile *c);
799 bool vir_opt_vpm(struct v3d_compile *c);
800 void v3d_nir_lower_blend(nir_shader *s, struct v3d_compile *c);
801 void v3d_nir_lower_io(nir_shader *s, struct v3d_compile *c);
802 void v3d_nir_lower_txf_ms(nir_shader *s, struct v3d_compile *c);
803 void v3d_nir_lower_image_load_store(nir_shader *s);
804 void vir_lower_uniforms(struct v3d_compile *c);
805
806 void v3d33_vir_vpm_read_setup(struct v3d_compile *c, int num_components);
807 void v3d33_vir_vpm_write_setup(struct v3d_compile *c);
808 void v3d33_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr);
809 void v3d40_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr);
810 void v3d40_vir_emit_image_load_store(struct v3d_compile *c,
811 nir_intrinsic_instr *instr);
812
813 void v3d_vir_to_qpu(struct v3d_compile *c, struct qpu_reg *temp_registers);
814 uint32_t v3d_qpu_schedule_instructions(struct v3d_compile *c);
815 void qpu_validate(struct v3d_compile *c);
816 struct qpu_reg *v3d_register_allocate(struct v3d_compile *c, bool *spilled);
817 bool vir_init_reg_sets(struct v3d_compiler *compiler);
818
819 bool v3d_gl_format_is_return_32(GLenum format);
820
821 void vir_PF(struct v3d_compile *c, struct qreg src, enum v3d_qpu_pf pf);
822
823 static inline bool
824 quniform_contents_is_texture_p0(enum quniform_contents contents)
825 {
826 return (contents >= QUNIFORM_TEXTURE_CONFIG_P0_0 &&
827 contents < (QUNIFORM_TEXTURE_CONFIG_P0_0 +
828 V3D_MAX_TEXTURE_SAMPLERS));
829 }
830
831 static inline struct qreg
832 vir_uniform_ui(struct v3d_compile *c, uint32_t ui)
833 {
834 return vir_uniform(c, QUNIFORM_CONSTANT, ui);
835 }
836
837 static inline struct qreg
838 vir_uniform_f(struct v3d_compile *c, float f)
839 {
840 return vir_uniform(c, QUNIFORM_CONSTANT, fui(f));
841 }
842
843 #define VIR_ALU0(name, vir_inst, op) \
844 static inline struct qreg \
845 vir_##name(struct v3d_compile *c) \
846 { \
847 return vir_emit_def(c, vir_inst(op, c->undef, \
848 c->undef, c->undef)); \
849 } \
850 static inline struct qinst * \
851 vir_##name##_dest(struct v3d_compile *c, struct qreg dest) \
852 { \
853 return vir_emit_nondef(c, vir_inst(op, dest, \
854 c->undef, c->undef)); \
855 }
856
857 #define VIR_ALU1(name, vir_inst, op) \
858 static inline struct qreg \
859 vir_##name(struct v3d_compile *c, struct qreg a) \
860 { \
861 return vir_emit_def(c, vir_inst(op, c->undef, \
862 a, c->undef)); \
863 } \
864 static inline struct qinst * \
865 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
866 struct qreg a) \
867 { \
868 return vir_emit_nondef(c, vir_inst(op, dest, a, \
869 c->undef)); \
870 }
871
872 #define VIR_ALU2(name, vir_inst, op) \
873 static inline struct qreg \
874 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b) \
875 { \
876 return vir_emit_def(c, vir_inst(op, c->undef, a, b)); \
877 } \
878 static inline struct qinst * \
879 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
880 struct qreg a, struct qreg b) \
881 { \
882 return vir_emit_nondef(c, vir_inst(op, dest, a, b)); \
883 }
884
885 #define VIR_NODST_0(name, vir_inst, op) \
886 static inline struct qinst * \
887 vir_##name(struct v3d_compile *c) \
888 { \
889 return vir_emit_nondef(c, vir_inst(op, c->undef, \
890 c->undef, c->undef)); \
891 }
892
893 #define VIR_NODST_1(name, vir_inst, op) \
894 static inline struct qinst * \
895 vir_##name(struct v3d_compile *c, struct qreg a) \
896 { \
897 return vir_emit_nondef(c, vir_inst(op, c->undef, \
898 a, c->undef)); \
899 }
900
901 #define VIR_NODST_2(name, vir_inst, op) \
902 static inline struct qinst * \
903 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b) \
904 { \
905 return vir_emit_nondef(c, vir_inst(op, c->undef, \
906 a, b)); \
907 }
908
909 #define VIR_SFU(name) \
910 static inline struct qreg \
911 vir_##name(struct v3d_compile *c, struct qreg a) \
912 { \
913 if (c->devinfo->ver >= 41) { \
914 return vir_emit_def(c, vir_add_inst(V3D_QPU_A_##name, \
915 c->undef, \
916 a, c->undef)); \
917 } else { \
918 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_##name), a); \
919 return vir_FMOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4)); \
920 } \
921 } \
922 static inline struct qinst * \
923 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
924 struct qreg a) \
925 { \
926 if (c->devinfo->ver >= 41) { \
927 return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_##name, \
928 dest, \
929 a, c->undef)); \
930 } else { \
931 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_##name), a); \
932 return vir_FMOV_dest(c, dest, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4)); \
933 } \
934 }
935
936 #define VIR_A_ALU2(name) VIR_ALU2(name, vir_add_inst, V3D_QPU_A_##name)
937 #define VIR_M_ALU2(name) VIR_ALU2(name, vir_mul_inst, V3D_QPU_M_##name)
938 #define VIR_A_ALU1(name) VIR_ALU1(name, vir_add_inst, V3D_QPU_A_##name)
939 #define VIR_M_ALU1(name) VIR_ALU1(name, vir_mul_inst, V3D_QPU_M_##name)
940 #define VIR_A_ALU0(name) VIR_ALU0(name, vir_add_inst, V3D_QPU_A_##name)
941 #define VIR_M_ALU0(name) VIR_ALU0(name, vir_mul_inst, V3D_QPU_M_##name)
942 #define VIR_A_NODST_2(name) VIR_NODST_2(name, vir_add_inst, V3D_QPU_A_##name)
943 #define VIR_M_NODST_2(name) VIR_NODST_2(name, vir_mul_inst, V3D_QPU_M_##name)
944 #define VIR_A_NODST_1(name) VIR_NODST_1(name, vir_add_inst, V3D_QPU_A_##name)
945 #define VIR_M_NODST_1(name) VIR_NODST_1(name, vir_mul_inst, V3D_QPU_M_##name)
946 #define VIR_A_NODST_0(name) VIR_NODST_0(name, vir_add_inst, V3D_QPU_A_##name)
947
948 VIR_A_ALU2(FADD)
949 VIR_A_ALU2(VFPACK)
950 VIR_A_ALU2(FSUB)
951 VIR_A_ALU2(FMIN)
952 VIR_A_ALU2(FMAX)
953
954 VIR_A_ALU2(ADD)
955 VIR_A_ALU2(SUB)
956 VIR_A_ALU2(SHL)
957 VIR_A_ALU2(SHR)
958 VIR_A_ALU2(ASR)
959 VIR_A_ALU2(ROR)
960 VIR_A_ALU2(MIN)
961 VIR_A_ALU2(MAX)
962 VIR_A_ALU2(UMIN)
963 VIR_A_ALU2(UMAX)
964 VIR_A_ALU2(AND)
965 VIR_A_ALU2(OR)
966 VIR_A_ALU2(XOR)
967 VIR_A_ALU2(VADD)
968 VIR_A_ALU2(VSUB)
969 VIR_A_NODST_2(STVPMV)
970 VIR_A_ALU1(NOT)
971 VIR_A_ALU1(NEG)
972 VIR_A_ALU1(FLAPUSH)
973 VIR_A_ALU1(FLBPUSH)
974 VIR_A_ALU1(FLPOP)
975 VIR_A_ALU1(SETMSF)
976 VIR_A_ALU1(SETREVF)
977 VIR_A_ALU0(TIDX)
978 VIR_A_ALU0(EIDX)
979 VIR_A_ALU1(LDVPMV_IN)
980 VIR_A_ALU1(LDVPMV_OUT)
981 VIR_A_ALU0(TMUWT)
982
983 VIR_A_ALU0(FXCD)
984 VIR_A_ALU0(XCD)
985 VIR_A_ALU0(FYCD)
986 VIR_A_ALU0(YCD)
987 VIR_A_ALU0(MSF)
988 VIR_A_ALU0(REVF)
989 VIR_A_NODST_1(VPMSETUP)
990 VIR_A_NODST_0(VPMWT)
991 VIR_A_ALU2(FCMP)
992 VIR_A_ALU2(VFMAX)
993
994 VIR_A_ALU1(FROUND)
995 VIR_A_ALU1(FTOIN)
996 VIR_A_ALU1(FTRUNC)
997 VIR_A_ALU1(FTOIZ)
998 VIR_A_ALU1(FFLOOR)
999 VIR_A_ALU1(FTOUZ)
1000 VIR_A_ALU1(FCEIL)
1001 VIR_A_ALU1(FTOC)
1002
1003 VIR_A_ALU1(FDX)
1004 VIR_A_ALU1(FDY)
1005
1006 VIR_A_ALU1(ITOF)
1007 VIR_A_ALU1(CLZ)
1008 VIR_A_ALU1(UTOF)
1009
1010 VIR_M_ALU2(UMUL24)
1011 VIR_M_ALU2(FMUL)
1012 VIR_M_ALU2(SMUL24)
1013 VIR_M_NODST_2(MULTOP)
1014
1015 VIR_M_ALU1(MOV)
1016 VIR_M_ALU1(FMOV)
1017
1018 VIR_SFU(RECIP)
1019 VIR_SFU(RSQRT)
1020 VIR_SFU(EXP)
1021 VIR_SFU(LOG)
1022 VIR_SFU(SIN)
1023 VIR_SFU(RSQRT2)
1024
1025 static inline struct qinst *
1026 vir_MOV_cond(struct v3d_compile *c, enum v3d_qpu_cond cond,
1027 struct qreg dest, struct qreg src)
1028 {
1029 struct qinst *mov = vir_MOV_dest(c, dest, src);
1030 vir_set_cond(mov, cond);
1031 return mov;
1032 }
1033
1034 static inline struct qreg
1035 vir_SEL(struct v3d_compile *c, enum v3d_qpu_cond cond,
1036 struct qreg src0, struct qreg src1)
1037 {
1038 struct qreg t = vir_get_temp(c);
1039 vir_MOV_dest(c, t, src1);
1040 vir_MOV_cond(c, cond, t, src0);
1041 return t;
1042 }
1043
1044 static inline struct qinst *
1045 vir_NOP(struct v3d_compile *c)
1046 {
1047 return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_NOP,
1048 c->undef, c->undef, c->undef));
1049 }
1050
1051 static inline struct qreg
1052 vir_LDTMU(struct v3d_compile *c)
1053 {
1054 if (c->devinfo->ver >= 41) {
1055 struct qinst *ldtmu = vir_add_inst(V3D_QPU_A_NOP, c->undef,
1056 c->undef, c->undef);
1057 ldtmu->qpu.sig.ldtmu = true;
1058
1059 return vir_emit_def(c, ldtmu);
1060 } else {
1061 vir_NOP(c)->qpu.sig.ldtmu = true;
1062 return vir_MOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4));
1063 }
1064 }
1065
1066 static inline struct qreg
1067 vir_UMUL(struct v3d_compile *c, struct qreg src0, struct qreg src1)
1068 {
1069 vir_MULTOP(c, src0, src1);
1070 return vir_UMUL24(c, src0, src1);
1071 }
1072
1073 /*
1074 static inline struct qreg
1075 vir_LOAD_IMM(struct v3d_compile *c, uint32_t val)
1076 {
1077 return vir_emit_def(c, vir_inst(QOP_LOAD_IMM, c->undef,
1078 vir_reg(QFILE_LOAD_IMM, val), c->undef));
1079 }
1080
1081 static inline struct qreg
1082 vir_LOAD_IMM_U2(struct v3d_compile *c, uint32_t val)
1083 {
1084 return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_U2, c->undef,
1085 vir_reg(QFILE_LOAD_IMM, val),
1086 c->undef));
1087 }
1088 static inline struct qreg
1089 vir_LOAD_IMM_I2(struct v3d_compile *c, uint32_t val)
1090 {
1091 return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_I2, c->undef,
1092 vir_reg(QFILE_LOAD_IMM, val),
1093 c->undef));
1094 }
1095 */
1096
1097 static inline struct qinst *
1098 vir_BRANCH(struct v3d_compile *c, enum v3d_qpu_branch_cond cond)
1099 {
1100 /* The actual uniform_data value will be set at scheduling time */
1101 return vir_emit_nondef(c, vir_branch_inst(cond, vir_uniform_ui(c, 0)));
1102 }
1103
1104 #define vir_for_each_block(block, c) \
1105 list_for_each_entry(struct qblock, block, &c->blocks, link)
1106
1107 #define vir_for_each_block_rev(block, c) \
1108 list_for_each_entry_rev(struct qblock, block, &c->blocks, link)
1109
1110 /* Loop over the non-NULL members of the successors array. */
1111 #define vir_for_each_successor(succ, block) \
1112 for (struct qblock *succ = block->successors[0]; \
1113 succ != NULL; \
1114 succ = (succ == block->successors[1] ? NULL : \
1115 block->successors[1]))
1116
1117 #define vir_for_each_inst(inst, block) \
1118 list_for_each_entry(struct qinst, inst, &block->instructions, link)
1119
1120 #define vir_for_each_inst_rev(inst, block) \
1121 list_for_each_entry_rev(struct qinst, inst, &block->instructions, link)
1122
1123 #define vir_for_each_inst_safe(inst, block) \
1124 list_for_each_entry_safe(struct qinst, inst, &block->instructions, link)
1125
1126 #define vir_for_each_inst_inorder(inst, c) \
1127 vir_for_each_block(_block, c) \
1128 vir_for_each_inst(inst, _block)
1129
1130 #endif /* V3D_COMPILER_H */