src/broadcom/compiler/v3d_compiler.h

   1 /*
   2  * Copyright © 2016 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef V3D_COMPILER_H
  25 #define V3D_COMPILER_H
  26
  27 #include <assert.h>
  28 #include <stdio.h>
  29 #include <stdlib.h>
  30 #include <stdbool.h>
  31 #include <stdint.h>
  32 #include <string.h>
  33
  34 #include "util/macros.h"
  35 #include "common/v3d_debug.h"
  36 #include "common/v3d_device_info.h"
  37 #include "compiler/nir/nir.h"
  38 #include "util/list.h"
  39 #include "util/u_math.h"
  40
  41 #include "qpu/qpu_instr.h"
  42 #include "pipe/p_state.h"
  43
  44 #define V3D_MAX_TEXTURE_SAMPLERS 32
  45 #define V3D_MAX_SAMPLES 4
  46 #define V3D_MAX_FS_INPUTS 64
  47 #define V3D_MAX_VS_INPUTS 64
  48
  49 struct nir_builder;
  50
  51 struct v3d_fs_inputs {
  52         /**
  53          * Array of the meanings of the VPM inputs this shader needs.
  54          *
  55          * It doesn't include those that aren't part of the VPM, like
  56          * point/line coordinates.
  57          */
  58         struct v3d_varying_slot *input_slots;
  59         uint32_t num_inputs;
  60 };
  61
  62 enum qfile {
  63         /** An unused source or destination register. */
  64         QFILE_NULL,
  65
  66         /** A physical register, such as the W coordinate payload. */
  67         QFILE_REG,
  68         /** One of the regsiters for fixed function interactions. */
  69         QFILE_MAGIC,
  70
  71         /**
  72          *  A virtual register, that will be allocated to actual accumulator
  73          * or physical registers later.
  74          */
  75         QFILE_TEMP,
  76         QFILE_UNIF,
  77         QFILE_TLB,
  78         QFILE_TLBU,
  79
  80         /**
  81          * VPM reads use this with an index value to say what part of the VPM
  82          * is being read.
  83          */
  84         QFILE_VPM,
  85
  86         /**
  87          * Stores an immediate value in the index field that will be used
  88          * directly by qpu_load_imm().
  89          */
  90         QFILE_LOAD_IMM,
  91
  92         /**
  93          * Stores an immediate value in the index field that can be turned
  94          * into a small immediate field by qpu_encode_small_immediate().
  95          */
  96         QFILE_SMALL_IMM,
  97 };
  98
  99 /**
 100  * A reference to a QPU register or a virtual temp register.
 101  */
 102 struct qreg {
 103         enum qfile file;
 104         uint32_t index;
 105 };
 106
 107 static inline struct qreg vir_reg(enum qfile file, uint32_t index)
 108 {
 109         return (struct qreg){file, index};
 110 }
 111
 112 /**
 113  * A reference to an actual register at the QPU level, for register
 114  * allocation.
 115  */
 116 struct qpu_reg {
 117         bool magic;
 118         bool smimm;
 119         int index;
 120 };
 121
 122 struct qinst {
 123         /** Entry in qblock->instructions */
 124         struct list_head link;
 125
 126         /**
 127          * The instruction being wrapped.  Its condition codes, pack flags,
 128          * signals, etc. will all be used, with just the register references
 129          * being replaced by the contents of qinst->dst and qinst->src[].
 130          */
 131         struct v3d_qpu_instr qpu;
 132
 133         /* Pre-register-allocation references to src/dst registers */
 134         struct qreg dst;
 135         struct qreg src[3];
 136         bool cond_is_exec_mask;
 137         bool has_implicit_uniform;
 138         bool is_last_thrsw;
 139
 140         /* After vir_to_qpu.c: If instr reads a uniform, which uniform from
 141          * the uncompiled stream it is.
 142          */
 143         int uniform;
 144 };
 145
 146 enum quniform_contents {
 147         /**
 148          * Indicates that a constant 32-bit value is copied from the program's
 149          * uniform contents.
 150          */
 151         QUNIFORM_CONSTANT,
 152         /**
 153          * Indicates that the program's uniform contents are used as an index
 154          * into the GL uniform storage.
 155          */
 156         QUNIFORM_UNIFORM,
 157
 158         /** @{
 159          * Scaling factors from clip coordinates to relative to the viewport
 160          * center.
 161          *
 162          * This is used by the coordinate and vertex shaders to produce the
 163          * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
 164          * point offsets from the viewport ccenter.
 165          */
 166         QUNIFORM_VIEWPORT_X_SCALE,
 167         QUNIFORM_VIEWPORT_Y_SCALE,
 168         /** @} */
 169
 170         QUNIFORM_VIEWPORT_Z_OFFSET,
 171         QUNIFORM_VIEWPORT_Z_SCALE,
 172
 173         QUNIFORM_USER_CLIP_PLANE,
 174
 175         /**
 176          * A reference to a V3D 3.x texture config parameter 0 uniform.
 177          *
 178          * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
 179          * defines texture type, miplevels, and such.  It will be found as a
 180          * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
 181          */
 182         QUNIFORM_TEXTURE_CONFIG_P0_0,
 183         QUNIFORM_TEXTURE_CONFIG_P0_1,
 184         QUNIFORM_TEXTURE_CONFIG_P0_2,
 185         QUNIFORM_TEXTURE_CONFIG_P0_3,
 186         QUNIFORM_TEXTURE_CONFIG_P0_4,
 187         QUNIFORM_TEXTURE_CONFIG_P0_5,
 188         QUNIFORM_TEXTURE_CONFIG_P0_6,
 189         QUNIFORM_TEXTURE_CONFIG_P0_7,
 190         QUNIFORM_TEXTURE_CONFIG_P0_8,
 191         QUNIFORM_TEXTURE_CONFIG_P0_9,
 192         QUNIFORM_TEXTURE_CONFIG_P0_10,
 193         QUNIFORM_TEXTURE_CONFIG_P0_11,
 194         QUNIFORM_TEXTURE_CONFIG_P0_12,
 195         QUNIFORM_TEXTURE_CONFIG_P0_13,
 196         QUNIFORM_TEXTURE_CONFIG_P0_14,
 197         QUNIFORM_TEXTURE_CONFIG_P0_15,
 198         QUNIFORM_TEXTURE_CONFIG_P0_16,
 199         QUNIFORM_TEXTURE_CONFIG_P0_17,
 200         QUNIFORM_TEXTURE_CONFIG_P0_18,
 201         QUNIFORM_TEXTURE_CONFIG_P0_19,
 202         QUNIFORM_TEXTURE_CONFIG_P0_20,
 203         QUNIFORM_TEXTURE_CONFIG_P0_21,
 204         QUNIFORM_TEXTURE_CONFIG_P0_22,
 205         QUNIFORM_TEXTURE_CONFIG_P0_23,
 206         QUNIFORM_TEXTURE_CONFIG_P0_24,
 207         QUNIFORM_TEXTURE_CONFIG_P0_25,
 208         QUNIFORM_TEXTURE_CONFIG_P0_26,
 209         QUNIFORM_TEXTURE_CONFIG_P0_27,
 210         QUNIFORM_TEXTURE_CONFIG_P0_28,
 211         QUNIFORM_TEXTURE_CONFIG_P0_29,
 212         QUNIFORM_TEXTURE_CONFIG_P0_30,
 213         QUNIFORM_TEXTURE_CONFIG_P0_31,
 214         QUNIFORM_TEXTURE_CONFIG_P0_32,
 215
 216         /**
 217          * A reference to a V3D 3.x texture config parameter 1 uniform.
 218          *
 219          * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
 220          * has the pointer to the indirect texture state.  Our data[] field
 221          * will have a packed p1 value, but the address field will be just
 222          * which texture unit's texture should be referenced.
 223          */
 224         QUNIFORM_TEXTURE_CONFIG_P1,
 225
 226         /* A V3D 4.x texture config parameter.  The high 8 bits will be
 227          * which texture or sampler is being sampled, and the driver must
 228          * replace the address field with the appropriate address.
 229          */
 230         QUNIFORM_TMU_CONFIG_P0,
 231         QUNIFORM_TMU_CONFIG_P1,
 232
 233         QUNIFORM_IMAGE_TMU_CONFIG_P0,
 234
 235         QUNIFORM_TEXTURE_FIRST_LEVEL,
 236
 237         QUNIFORM_TEXTURE_WIDTH,
 238         QUNIFORM_TEXTURE_HEIGHT,
 239         QUNIFORM_TEXTURE_DEPTH,
 240         QUNIFORM_TEXTURE_ARRAY_SIZE,
 241         QUNIFORM_TEXTURE_LEVELS,
 242
 243         QUNIFORM_UBO_ADDR,
 244
 245         QUNIFORM_TEXRECT_SCALE_X,
 246         QUNIFORM_TEXRECT_SCALE_Y,
 247
 248         /* Returns the base offset of the SSBO given by the data value. */
 249         QUNIFORM_SSBO_OFFSET,
 250
 251         /* Returns the size of the SSBO given by the data value. */
 252         QUNIFORM_GET_BUFFER_SIZE,
 253
 254         /* Sizes (in pixels) of a shader image given by the data value. */
 255         QUNIFORM_IMAGE_WIDTH,
 256         QUNIFORM_IMAGE_HEIGHT,
 257         QUNIFORM_IMAGE_DEPTH,
 258         QUNIFORM_IMAGE_ARRAY_SIZE,
 259
 260         QUNIFORM_ALPHA_REF,
 261
 262         /* Number of workgroups passed to glDispatchCompute in the dimension
 263          * selected by the data value.
 264          */
 265         QUNIFORM_NUM_WORK_GROUPS,
 266
 267         /**
 268          * Returns the the offset of the scratch buffer for register spilling.
 269          */
 270         QUNIFORM_SPILL_OFFSET,
 271         QUNIFORM_SPILL_SIZE_PER_THREAD,
 272 };
 273
 274 static inline uint32_t v3d_tmu_config_data_create(uint32_t unit, uint32_t value)
 275 {
 276         return unit << 24 | value;
 277 }
 278
 279 static inline uint32_t v3d_tmu_config_data_get_unit(uint32_t data)
 280 {
 281         return data >> 24;
 282 }
 283
 284 static inline uint32_t v3d_tmu_config_data_get_value(uint32_t data)
 285 {
 286         return data & 0xffffff;
 287 }
 288
 289 struct v3d_varying_slot {
 290         uint8_t slot_and_component;
 291 };
 292
 293 static inline struct v3d_varying_slot
 294 v3d_slot_from_slot_and_component(uint8_t slot, uint8_t component)
 295 {
 296         assert(slot < 255 / 4);
 297         return (struct v3d_varying_slot){ (slot << 2) + component };
 298 }
 299
 300 static inline uint8_t v3d_slot_get_slot(struct v3d_varying_slot slot)
 301 {
 302         return slot.slot_and_component >> 2;
 303 }
 304
 305 static inline uint8_t v3d_slot_get_component(struct v3d_varying_slot slot)
 306 {
 307         return slot.slot_and_component & 3;
 308 }
 309
 310 struct v3d_ubo_range {
 311         /**
 312          * offset in bytes from the start of the ubo where this range is
 313          * uploaded.
 314          *
 315          * Only set once used is set.
 316          */
 317         uint32_t dst_offset;
 318
 319         /**
 320          * offset in bytes from the start of the gallium uniforms where the
 321          * data comes from.
 322          */
 323         uint32_t src_offset;
 324
 325         /** size in bytes of this ubo range */
 326         uint32_t size;
 327 };
 328
 329 struct v3d_key {
 330         void *shader_state;
 331         struct {
 332                 uint8_t swizzle[4];
 333                 uint8_t return_size;
 334                 uint8_t return_channels;
 335                 bool clamp_s:1;
 336                 bool clamp_t:1;
 337                 bool clamp_r:1;
 338         } tex[V3D_MAX_TEXTURE_SAMPLERS];
 339         uint8_t ucp_enables;
 340 };
 341
 342 struct v3d_fs_key {
 343         struct v3d_key base;
 344         bool depth_enabled;
 345         bool is_points;
 346         bool is_lines;
 347         bool alpha_test;
 348         bool point_coord_upper_left;
 349         bool light_twoside;
 350         bool msaa;
 351         bool sample_coverage;
 352         bool sample_alpha_to_coverage;
 353         bool sample_alpha_to_one;
 354         bool clamp_color;
 355         bool shade_model_flat;
 356         uint8_t nr_cbufs;
 357         uint8_t swap_color_rb;
 358         /* Mask of which render targets need to be written as 32-bit floats */
 359         uint8_t f32_color_rb;
 360         /* Masks of which render targets need to be written as ints/uints.
 361          * Used by gallium to work around lost information in TGSI.
 362          */
 363         uint8_t int_color_rb;
 364         uint8_t uint_color_rb;
 365         uint8_t alpha_test_func;
 366         uint8_t logicop_func;
 367         uint32_t point_sprite_mask;
 368
 369         struct pipe_rt_blend_state blend;
 370 };
 371
 372 struct v3d_vs_key {
 373         struct v3d_key base;
 374
 375         struct v3d_varying_slot fs_inputs[V3D_MAX_FS_INPUTS];
 376         uint8_t num_fs_inputs;
 377
 378         bool is_coord;
 379         bool per_vertex_point_size;
 380         bool clamp_color;
 381 };
 382
 383 /** A basic block of VIR intructions. */
 384 struct qblock {
 385         struct list_head link;
 386
 387         struct list_head instructions;
 388
 389         struct set *predecessors;
 390         struct qblock *successors[2];
 391
 392         int index;
 393
 394         /* Instruction IPs for the first and last instruction of the block.
 395          * Set by qpu_schedule.c.
 396          */
 397         uint32_t start_qpu_ip;
 398         uint32_t end_qpu_ip;
 399
 400         /* Instruction IP for the branch instruction of the block.  Set by
 401          * qpu_schedule.c.
 402          */
 403         uint32_t branch_qpu_ip;
 404
 405         /** Offset within the uniform stream at the start of the block. */
 406         uint32_t start_uniform;
 407         /** Offset within the uniform stream of the branch instruction */
 408         uint32_t branch_uniform;
 409
 410         /** @{ used by v3d_vir_live_variables.c */
 411         BITSET_WORD *def;
 412         BITSET_WORD *use;
 413         BITSET_WORD *live_in;
 414         BITSET_WORD *live_out;
 415         int start_ip, end_ip;
 416         /** @} */
 417 };
 418
 419 /** Which util/list.h add mode we should use when inserting an instruction. */
 420 enum vir_cursor_mode {
 421         vir_cursor_add,
 422         vir_cursor_addtail,
 423 };
 424
 425 /**
 426  * Tracking structure for where new instructions should be inserted.  Create
 427  * with one of the vir_after_inst()-style helper functions.
 428  *
 429  * This does not protect against removal of the block or instruction, so we
 430  * have an assert in instruction removal to try to catch it.
 431  */
 432 struct vir_cursor {
 433         enum vir_cursor_mode mode;
 434         struct list_head *link;
 435 };
 436
 437 static inline struct vir_cursor
 438 vir_before_inst(struct qinst *inst)
 439 {
 440         return (struct vir_cursor){ vir_cursor_addtail, &inst->link };
 441 }
 442
 443 static inline struct vir_cursor
 444 vir_after_inst(struct qinst *inst)
 445 {
 446         return (struct vir_cursor){ vir_cursor_add, &inst->link };
 447 }
 448
 449 static inline struct vir_cursor
 450 vir_before_block(struct qblock *block)
 451 {
 452         return (struct vir_cursor){ vir_cursor_add, &block->instructions };
 453 }
 454
 455 static inline struct vir_cursor
 456 vir_after_block(struct qblock *block)
 457 {
 458         return (struct vir_cursor){ vir_cursor_addtail, &block->instructions };
 459 }
 460
 461 /**
 462  * Compiler state saved across compiler invocations, for any expensive global
 463  * setup.
 464  */
 465 struct v3d_compiler {
 466         const struct v3d_device_info *devinfo;
 467         struct ra_regs *regs;
 468         unsigned int reg_class_phys[3];
 469         unsigned int reg_class_phys_or_acc[3];
 470 };
 471
 472 struct v3d_compile {
 473         const struct v3d_device_info *devinfo;
 474         nir_shader *s;
 475         nir_function_impl *impl;
 476         struct exec_list *cf_node_list;
 477         const struct v3d_compiler *compiler;
 478
 479         void (*debug_output)(const char *msg,
 480                              void *debug_output_data);
 481         void *debug_output_data;
 482
 483         /**
 484          * Mapping from nir_register * or nir_ssa_def * to array of struct
 485          * qreg for the values.
 486          */
 487         struct hash_table *def_ht;
 488
 489         /* For each temp, the instruction generating its value. */
 490         struct qinst **defs;
 491         uint32_t defs_array_size;
 492
 493         /**
 494          * Inputs to the shader, arranged by TGSI declaration order.
 495          *
 496          * Not all fragment shader QFILE_VARY reads are present in this array.
 497          */
 498         struct qreg *inputs;
 499         struct qreg *outputs;
 500         bool msaa_per_sample_output;
 501         struct qreg color_reads[V3D_MAX_SAMPLES];
 502         struct qreg sample_colors[V3D_MAX_SAMPLES];
 503         uint32_t inputs_array_size;
 504         uint32_t outputs_array_size;
 505         uint32_t uniforms_array_size;
 506
 507         /* Booleans for whether the corresponding QFILE_VARY[i] is
 508          * flat-shaded.  This includes gl_FragColor flat-shading, which is
 509          * customized based on the shademodel_flat shader key.
 510          */
 511         uint32_t flat_shade_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
 512
 513         uint32_t noperspective_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
 514
 515         uint32_t centroid_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
 516
 517         bool uses_center_w;
 518
 519         struct v3d_ubo_range *ubo_ranges;
 520         bool *ubo_range_used;
 521         uint32_t ubo_ranges_array_size;
 522         /** Number of uniform areas tracked in ubo_ranges. */
 523         uint32_t num_ubo_ranges;
 524         uint32_t next_ubo_dst_offset;
 525
 526         /* State for whether we're executing on each channel currently.  0 if
 527          * yes, otherwise a block number + 1 that the channel jumped to.
 528          */
 529         struct qreg execute;
 530
 531         struct qreg line_x, point_x, point_y;
 532
 533         /**
 534          * Instance ID, which comes in before the vertex attribute payload if
 535          * the shader record requests it.
 536          */
 537         struct qreg iid;
 538
 539         /**
 540          * Vertex ID, which comes in before the vertex attribute payload
 541          * (after Instance ID) if the shader record requests it.
 542          */
 543         struct qreg vid;
 544
 545         /* Fragment shader payload regs. */
 546         struct qreg payload_w, payload_w_centroid, payload_z;
 547
 548         struct qreg cs_payload[2];
 549         int local_invocation_index_bits;
 550
 551         uint8_t vattr_sizes[V3D_MAX_VS_INPUTS];
 552         uint32_t num_vpm_writes;
 553
 554         /* Size in bytes of registers that have been spilled. This is how much
 555          * space needs to be available in the spill BO per thread per QPU.
 556          */
 557         uint32_t spill_size;
 558         /* Shader-db stats */
 559         uint32_t spills, fills, loops;
 560         /**
 561          * Register spilling's per-thread base address, shared between each
 562          * spill/fill's addressing calculations.
 563          */
 564         struct qreg spill_base;
 565         /* Bit vector of which temps may be spilled */
 566         BITSET_WORD *spillable;
 567
 568         /**
 569          * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
 570          *
 571          * This includes those that aren't part of the VPM varyings, like
 572          * point/line coordinates.
 573          */
 574         struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
 575
 576         /**
 577          * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
 578          * of the output is.  Used to emit from the VS in the order that the
 579          * FS needs.
 580          */
 581         struct v3d_varying_slot *output_slots;
 582
 583         struct pipe_shader_state *shader_state;
 584         struct v3d_key *key;
 585         struct v3d_fs_key *fs_key;
 586         struct v3d_vs_key *vs_key;
 587
 588         /* Live ranges of temps. */
 589         int *temp_start, *temp_end;
 590         bool live_intervals_valid;
 591
 592         uint32_t *uniform_data;
 593         enum quniform_contents *uniform_contents;
 594         uint32_t uniform_array_size;
 595         uint32_t num_uniforms;
 596         uint32_t num_outputs;
 597         uint32_t output_position_index;
 598         nir_variable *output_color_var[4];
 599         uint32_t output_point_size_index;
 600         uint32_t output_sample_mask_index;
 601
 602         struct qreg undef;
 603         uint32_t num_temps;
 604
 605         struct vir_cursor cursor;
 606         struct list_head blocks;
 607         int next_block_index;
 608         struct qblock *cur_block;
 609         struct qblock *loop_cont_block;
 610         struct qblock *loop_break_block;
 611
 612         uint64_t *qpu_insts;
 613         uint32_t qpu_inst_count;
 614         uint32_t qpu_inst_size;
 615
 616         /* For the FS, the number of varying inputs not counting the
 617          * point/line varyings payload
 618          */
 619         uint32_t num_inputs;
 620
 621         /**
 622          * Number of inputs from num_inputs remaining to be queued to the read
 623          * FIFO in the VS/CS.
 624          */
 625         uint32_t num_inputs_remaining;
 626
 627         /* Number of inputs currently in the read FIFO for the VS/CS */
 628         uint32_t num_inputs_in_fifo;
 629
 630         /** Next offset in the VPM to read from in the VS/CS */
 631         uint32_t vpm_read_offset;
 632
 633         uint32_t program_id;
 634         uint32_t variant_id;
 635
 636         /* Set to compile program in in 1x, 2x, or 4x threaded mode, where
 637          * SIG_THREAD_SWITCH is used to hide texturing latency at the cost of
 638          * limiting ourselves to the part of the physical reg space.
 639          *
 640          * On V3D 3.x, 2x or 4x divide the physical reg space by 2x or 4x.  On
 641          * V3D 4.x, all shaders are 2x threaded, and 4x only divides the
 642          * physical reg space in half.
 643          */
 644         uint8_t threads;
 645         struct qinst *last_thrsw;
 646         bool last_thrsw_at_top_level;
 647
 648         bool failed;
 649 };
 650
 651 struct v3d_uniform_list {
 652         enum quniform_contents *contents;
 653         uint32_t *data;
 654         uint32_t count;
 655 };
 656
 657 struct v3d_prog_data {
 658         struct v3d_uniform_list uniforms;
 659
 660         struct v3d_ubo_range *ubo_ranges;
 661         uint32_t num_ubo_ranges;
 662         uint32_t ubo_size;
 663         uint32_t spill_size;
 664
 665         uint8_t num_inputs;
 666         uint8_t threads;
 667
 668         /* For threads > 1, whether the program should be dispatched in the
 669          * after-final-THRSW state.
 670          */
 671         bool single_seg;
 672 };
 673
 674 struct v3d_vs_prog_data {
 675         struct v3d_prog_data base;
 676
 677         bool uses_iid, uses_vid;
 678
 679         /* Number of components read from each vertex attribute. */
 680         uint8_t vattr_sizes[32];
 681
 682         /* Total number of components read, for the shader state record. */
 683         uint32_t vpm_input_size;
 684
 685         /* Total number of components written, for the shader state record. */
 686         uint32_t vpm_output_size;
 687
 688         /* Set if there should be separate VPM segments for input and output.
 689          * If unset, vpm_input_size will be 0.
 690          */
 691         bool separate_segments;
 692
 693         /* Value to be programmed in VCM_CACHE_SIZE. */
 694         uint8_t vcm_cache_size;
 695 };
 696
 697 struct v3d_fs_prog_data {
 698         struct v3d_prog_data base;
 699
 700         struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
 701
 702         /* Array of flat shade flags.
 703          *
 704          * Each entry is only 24 bits (high 8 bits 0), to match the hardware
 705          * packet layout.
 706          */
 707         uint32_t flat_shade_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
 708
 709         uint32_t noperspective_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
 710
 711         uint32_t centroid_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
 712
 713         bool writes_z;
 714         bool discard;
 715         bool uses_center_w;
 716 };
 717
 718 /* Special nir_load_input intrinsic index for loading the current TLB
 719  * destination color.
 720  */
 721 #define V3D_NIR_TLB_COLOR_READ_INPUT            2000000000
 722
 723 #define V3D_NIR_MS_MASK_OUTPUT                  2000000000
 724
 725 extern const nir_shader_compiler_options v3d_nir_options;
 726
 727 const struct v3d_compiler *v3d_compiler_init(const struct v3d_device_info *devinfo);
 728 void v3d_compiler_free(const struct v3d_compiler *compiler);
 729 void v3d_optimize_nir(struct nir_shader *s);
 730
 731 uint64_t *v3d_compile(const struct v3d_compiler *compiler,
 732                       struct v3d_key *key,
 733                       struct v3d_prog_data **prog_data,
 734                       nir_shader *s,
 735                       void (*debug_output)(const char *msg,
 736                                            void *debug_output_data),
 737                       void *debug_output_data,
 738                       int program_id, int variant_id,
 739                       uint32_t *final_assembly_size);
 740
 741 void v3d_nir_to_vir(struct v3d_compile *c);
 742
 743 void vir_compile_destroy(struct v3d_compile *c);
 744 const char *vir_get_stage_name(struct v3d_compile *c);
 745 struct qblock *vir_new_block(struct v3d_compile *c);
 746 void vir_set_emit_block(struct v3d_compile *c, struct qblock *block);
 747 void vir_link_blocks(struct qblock *predecessor, struct qblock *successor);
 748 struct qblock *vir_entry_block(struct v3d_compile *c);
 749 struct qblock *vir_exit_block(struct v3d_compile *c);
 750 struct qinst *vir_add_inst(enum v3d_qpu_add_op op, struct qreg dst,
 751                            struct qreg src0, struct qreg src1);
 752 struct qinst *vir_mul_inst(enum v3d_qpu_mul_op op, struct qreg dst,
 753                            struct qreg src0, struct qreg src1);
 754 struct qinst *vir_branch_inst(enum v3d_qpu_branch_cond cond, struct qreg src0);
 755 void vir_remove_instruction(struct v3d_compile *c, struct qinst *qinst);
 756 struct qreg vir_uniform(struct v3d_compile *c,
 757                         enum quniform_contents contents,
 758                         uint32_t data);
 759 void vir_schedule_instructions(struct v3d_compile *c);
 760 struct v3d_qpu_instr v3d_qpu_nop(void);
 761
 762 struct qreg vir_emit_def(struct v3d_compile *c, struct qinst *inst);
 763 struct qinst *vir_emit_nondef(struct v3d_compile *c, struct qinst *inst);
 764 void vir_set_cond(struct qinst *inst, enum v3d_qpu_cond cond);
 765 void vir_set_pf(struct qinst *inst, enum v3d_qpu_pf pf);
 766 void vir_set_uf(struct qinst *inst, enum v3d_qpu_uf uf);
 767 void vir_set_unpack(struct qinst *inst, int src,
 768                     enum v3d_qpu_input_unpack unpack);
 769
 770 struct qreg vir_get_temp(struct v3d_compile *c);
 771 void vir_emit_last_thrsw(struct v3d_compile *c);
 772 void vir_calculate_live_intervals(struct v3d_compile *c);
 773 bool vir_has_implicit_uniform(struct qinst *inst);
 774 int vir_get_implicit_uniform_src(struct qinst *inst);
 775 int vir_get_non_sideband_nsrc(struct qinst *inst);
 776 int vir_get_nsrc(struct qinst *inst);
 777 bool vir_has_side_effects(struct v3d_compile *c, struct qinst *inst);
 778 bool vir_get_add_op(struct qinst *inst, enum v3d_qpu_add_op *op);
 779 bool vir_get_mul_op(struct qinst *inst, enum v3d_qpu_mul_op *op);
 780 bool vir_is_raw_mov(struct qinst *inst);
 781 bool vir_is_tex(struct qinst *inst);
 782 bool vir_is_add(struct qinst *inst);
 783 bool vir_is_mul(struct qinst *inst);
 784 bool vir_is_float_input(struct qinst *inst);
 785 bool vir_writes_r3(const struct v3d_device_info *devinfo, struct qinst *inst);
 786 bool vir_writes_r4(const struct v3d_device_info *devinfo, struct qinst *inst);
 787 struct qreg vir_follow_movs(struct v3d_compile *c, struct qreg reg);
 788 uint8_t vir_channels_written(struct qinst *inst);
 789 struct qreg ntq_get_src(struct v3d_compile *c, nir_src src, int i);
 790 void ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
 791                     struct qreg result);
 792 void vir_emit_thrsw(struct v3d_compile *c);
 793
 794 void vir_dump(struct v3d_compile *c);
 795 void vir_dump_inst(struct v3d_compile *c, struct qinst *inst);
 796 void vir_dump_uniform(enum quniform_contents contents, uint32_t data);
 797
 798 void vir_validate(struct v3d_compile *c);
 799
 800 void vir_optimize(struct v3d_compile *c);
 801 bool vir_opt_algebraic(struct v3d_compile *c);
 802 bool vir_opt_constant_folding(struct v3d_compile *c);
 803 bool vir_opt_copy_propagate(struct v3d_compile *c);
 804 bool vir_opt_dead_code(struct v3d_compile *c);
 805 bool vir_opt_peephole_sf(struct v3d_compile *c);
 806 bool vir_opt_small_immediates(struct v3d_compile *c);
 807 bool vir_opt_vpm(struct v3d_compile *c);
 808 void v3d_nir_lower_blend(nir_shader *s, struct v3d_compile *c);
 809 void v3d_nir_lower_io(nir_shader *s, struct v3d_compile *c);
 810 void v3d_nir_lower_txf_ms(nir_shader *s, struct v3d_compile *c);
 811 void v3d_nir_lower_image_load_store(nir_shader *s);
 812 void vir_lower_uniforms(struct v3d_compile *c);
 813
 814 void v3d33_vir_vpm_read_setup(struct v3d_compile *c, int num_components);
 815 void v3d33_vir_vpm_write_setup(struct v3d_compile *c);
 816 void v3d33_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr);
 817 void v3d40_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr);
 818 void v3d40_vir_emit_image_load_store(struct v3d_compile *c,
 819                                      nir_intrinsic_instr *instr);
 820
 821 void v3d_vir_to_qpu(struct v3d_compile *c, struct qpu_reg *temp_registers);
 822 uint32_t v3d_qpu_schedule_instructions(struct v3d_compile *c);
 823 void qpu_validate(struct v3d_compile *c);
 824 struct qpu_reg *v3d_register_allocate(struct v3d_compile *c, bool *spilled);
 825 bool vir_init_reg_sets(struct v3d_compiler *compiler);
 826
 827 bool v3d_gl_format_is_return_32(GLenum format);
 828
 829 void vir_PF(struct v3d_compile *c, struct qreg src, enum v3d_qpu_pf pf);
 830
 831 static inline bool
 832 quniform_contents_is_texture_p0(enum quniform_contents contents)
 833 {
 834         return (contents >= QUNIFORM_TEXTURE_CONFIG_P0_0 &&
 835                 contents < (QUNIFORM_TEXTURE_CONFIG_P0_0 +
 836                             V3D_MAX_TEXTURE_SAMPLERS));
 837 }
 838
 839 static inline struct qreg
 840 vir_uniform_ui(struct v3d_compile *c, uint32_t ui)
 841 {
 842         return vir_uniform(c, QUNIFORM_CONSTANT, ui);
 843 }
 844
 845 static inline struct qreg
 846 vir_uniform_f(struct v3d_compile *c, float f)
 847 {
 848         return vir_uniform(c, QUNIFORM_CONSTANT, fui(f));
 849 }
 850
 851 #define VIR_ALU0(name, vir_inst, op)                                     \
 852 static inline struct qreg                                                \
 853 vir_##name(struct v3d_compile *c)                                        \
 854 {                                                                        \
 855         return vir_emit_def(c, vir_inst(op, c->undef,                    \
 856                                         c->undef, c->undef));            \
 857 }                                                                        \
 858 static inline struct qinst *                                             \
 859 vir_##name##_dest(struct v3d_compile *c, struct qreg dest)               \
 860 {                                                                        \
 861         return vir_emit_nondef(c, vir_inst(op, dest,                     \
 862                                            c->undef, c->undef));         \
 863 }
 864
 865 #define VIR_ALU1(name, vir_inst, op)                                     \
 866 static inline struct qreg                                                \
 867 vir_##name(struct v3d_compile *c, struct qreg a)                         \
 868 {                                                                        \
 869         return vir_emit_def(c, vir_inst(op, c->undef,                    \
 870                                         a, c->undef));                   \
 871 }                                                                        \
 872 static inline struct qinst *                                             \
 873 vir_##name##_dest(struct v3d_compile *c, struct qreg dest,               \
 874                   struct qreg a)                                         \
 875 {                                                                        \
 876         return vir_emit_nondef(c, vir_inst(op, dest, a,          \
 877                                            c->undef));                   \
 878 }
 879
 880 #define VIR_ALU2(name, vir_inst, op)                                       \
 881 static inline struct qreg                                                \
 882 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b)          \
 883 {                                                                        \
 884         return vir_emit_def(c, vir_inst(op, c->undef, a, b));    \
 885 }                                                                        \
 886 static inline struct qinst *                                             \
 887 vir_##name##_dest(struct v3d_compile *c, struct qreg dest,               \
 888                   struct qreg a, struct qreg b)                          \
 889 {                                                                        \
 890         return vir_emit_nondef(c, vir_inst(op, dest, a, b));     \
 891 }
 892
 893 #define VIR_NODST_0(name, vir_inst, op)                                 \
 894 static inline struct qinst *                                            \
 895 vir_##name(struct v3d_compile *c)                                       \
 896 {                                                                       \
 897         return vir_emit_nondef(c, vir_inst(op, c->undef,                \
 898                                            c->undef, c->undef));        \
 899 }
 900
 901 #define VIR_NODST_1(name, vir_inst, op)                                               \
 902 static inline struct qinst *                                            \
 903 vir_##name(struct v3d_compile *c, struct qreg a)                        \
 904 {                                                                       \
 905         return vir_emit_nondef(c, vir_inst(op, c->undef,        \
 906                                            a, c->undef));               \
 907 }
 908
 909 #define VIR_NODST_2(name, vir_inst, op)                                               \
 910 static inline struct qinst *                                            \
 911 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b)         \
 912 {                                                                       \
 913         return vir_emit_nondef(c, vir_inst(op, c->undef,                \
 914                                            a, b));                      \
 915 }
 916
 917 #define VIR_SFU(name)                                                      \
 918 static inline struct qreg                                                \
 919 vir_##name(struct v3d_compile *c, struct qreg a)                         \
 920 {                                                                        \
 921         if (c->devinfo->ver >= 41) {                                     \
 922                 return vir_emit_def(c, vir_add_inst(V3D_QPU_A_##name,    \
 923                                                     c->undef,            \
 924                                                     a, c->undef));       \
 925         } else {                                                         \
 926                 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_##name), a); \
 927                 return vir_FMOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4)); \
 928         }                                                                \
 929 }                                                                        \
 930 static inline struct qinst *                                             \
 931 vir_##name##_dest(struct v3d_compile *c, struct qreg dest,               \
 932                   struct qreg a)                                         \
 933 {                                                                        \
 934         if (c->devinfo->ver >= 41) {                                     \
 935                 return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_##name, \
 936                                                        dest,             \
 937                                                        a, c->undef));    \
 938         } else {                                                         \
 939                 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_##name), a); \
 940                 return vir_FMOV_dest(c, dest, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4)); \
 941         }                                                                \
 942 }
 943
 944 #define VIR_A_ALU2(name) VIR_ALU2(name, vir_add_inst, V3D_QPU_A_##name)
 945 #define VIR_M_ALU2(name) VIR_ALU2(name, vir_mul_inst, V3D_QPU_M_##name)
 946 #define VIR_A_ALU1(name) VIR_ALU1(name, vir_add_inst, V3D_QPU_A_##name)
 947 #define VIR_M_ALU1(name) VIR_ALU1(name, vir_mul_inst, V3D_QPU_M_##name)
 948 #define VIR_A_ALU0(name) VIR_ALU0(name, vir_add_inst, V3D_QPU_A_##name)
 949 #define VIR_M_ALU0(name) VIR_ALU0(name, vir_mul_inst, V3D_QPU_M_##name)
 950 #define VIR_A_NODST_2(name) VIR_NODST_2(name, vir_add_inst, V3D_QPU_A_##name)
 951 #define VIR_M_NODST_2(name) VIR_NODST_2(name, vir_mul_inst, V3D_QPU_M_##name)
 952 #define VIR_A_NODST_1(name) VIR_NODST_1(name, vir_add_inst, V3D_QPU_A_##name)
 953 #define VIR_M_NODST_1(name) VIR_NODST_1(name, vir_mul_inst, V3D_QPU_M_##name)
 954 #define VIR_A_NODST_0(name) VIR_NODST_0(name, vir_add_inst, V3D_QPU_A_##name)
 955
 956 VIR_A_ALU2(FADD)
 957 VIR_A_ALU2(VFPACK)
 958 VIR_A_ALU2(FSUB)
 959 VIR_A_ALU2(FMIN)
 960 VIR_A_ALU2(FMAX)
 961
 962 VIR_A_ALU2(ADD)
 963 VIR_A_ALU2(SUB)
 964 VIR_A_ALU2(SHL)
 965 VIR_A_ALU2(SHR)
 966 VIR_A_ALU2(ASR)
 967 VIR_A_ALU2(ROR)
 968 VIR_A_ALU2(MIN)
 969 VIR_A_ALU2(MAX)
 970 VIR_A_ALU2(UMIN)
 971 VIR_A_ALU2(UMAX)
 972 VIR_A_ALU2(AND)
 973 VIR_A_ALU2(OR)
 974 VIR_A_ALU2(XOR)
 975 VIR_A_ALU2(VADD)
 976 VIR_A_ALU2(VSUB)
 977 VIR_A_NODST_2(STVPMV)
 978 VIR_A_ALU1(NOT)
 979 VIR_A_ALU1(NEG)
 980 VIR_A_ALU1(FLAPUSH)
 981 VIR_A_ALU1(FLBPUSH)
 982 VIR_A_ALU1(FLPOP)
 983 VIR_A_ALU1(SETMSF)
 984 VIR_A_ALU1(SETREVF)
 985 VIR_A_ALU0(TIDX)
 986 VIR_A_ALU0(EIDX)
 987 VIR_A_ALU1(LDVPMV_IN)
 988 VIR_A_ALU1(LDVPMV_OUT)
 989 VIR_A_ALU0(TMUWT)
 990
 991 VIR_A_ALU0(FXCD)
 992 VIR_A_ALU0(XCD)
 993 VIR_A_ALU0(FYCD)
 994 VIR_A_ALU0(YCD)
 995 VIR_A_ALU0(MSF)
 996 VIR_A_ALU0(REVF)
 997 VIR_A_NODST_1(VPMSETUP)
 998 VIR_A_NODST_0(VPMWT)
 999 VIR_A_ALU2(FCMP)
1000 VIR_A_ALU2(VFMAX)
1001
1002 VIR_A_ALU1(FROUND)
1003 VIR_A_ALU1(FTOIN)
1004 VIR_A_ALU1(FTRUNC)
1005 VIR_A_ALU1(FTOIZ)
1006 VIR_A_ALU1(FFLOOR)
1007 VIR_A_ALU1(FTOUZ)
1008 VIR_A_ALU1(FCEIL)
1009 VIR_A_ALU1(FTOC)
1010
1011 VIR_A_ALU1(FDX)
1012 VIR_A_ALU1(FDY)
1013
1014 VIR_A_ALU1(ITOF)
1015 VIR_A_ALU1(CLZ)
1016 VIR_A_ALU1(UTOF)
1017
1018 VIR_M_ALU2(UMUL24)
1019 VIR_M_ALU2(FMUL)
1020 VIR_M_ALU2(SMUL24)
1021 VIR_M_NODST_2(MULTOP)
1022
1023 VIR_M_ALU1(MOV)
1024 VIR_M_ALU1(FMOV)
1025
1026 VIR_SFU(RECIP)
1027 VIR_SFU(RSQRT)
1028 VIR_SFU(EXP)
1029 VIR_SFU(LOG)
1030 VIR_SFU(SIN)
1031 VIR_SFU(RSQRT2)
1032
1033 static inline struct qinst *
1034 vir_MOV_cond(struct v3d_compile *c, enum v3d_qpu_cond cond,
1035              struct qreg dest, struct qreg src)
1036 {
1037         struct qinst *mov = vir_MOV_dest(c, dest, src);
1038         vir_set_cond(mov, cond);
1039         return mov;
1040 }
1041
1042 static inline struct qreg
1043 vir_SEL(struct v3d_compile *c, enum v3d_qpu_cond cond,
1044         struct qreg src0, struct qreg src1)
1045 {
1046         struct qreg t = vir_get_temp(c);
1047         vir_MOV_dest(c, t, src1);
1048         vir_MOV_cond(c, cond, t, src0);
1049         return t;
1050 }
1051
1052 static inline struct qinst *
1053 vir_NOP(struct v3d_compile *c)
1054 {
1055         return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_NOP,
1056                                                c->undef, c->undef, c->undef));
1057 }
1058
1059 static inline struct qreg
1060 vir_LDTMU(struct v3d_compile *c)
1061 {
1062         if (c->devinfo->ver >= 41) {
1063                 struct qinst *ldtmu = vir_add_inst(V3D_QPU_A_NOP, c->undef,
1064                                                    c->undef, c->undef);
1065                 ldtmu->qpu.sig.ldtmu = true;
1066
1067                 return vir_emit_def(c, ldtmu);
1068         } else {
1069                 vir_NOP(c)->qpu.sig.ldtmu = true;
1070                 return vir_MOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4));
1071         }
1072 }
1073
1074 static inline struct qreg
1075 vir_UMUL(struct v3d_compile *c, struct qreg src0, struct qreg src1)
1076 {
1077         vir_MULTOP(c, src0, src1);
1078         return vir_UMUL24(c, src0, src1);
1079 }
1080
1081 /*
1082 static inline struct qreg
1083 vir_LOAD_IMM(struct v3d_compile *c, uint32_t val)
1084 {
1085         return vir_emit_def(c, vir_inst(QOP_LOAD_IMM, c->undef,
1086                                         vir_reg(QFILE_LOAD_IMM, val), c->undef));
1087 }
1088
1089 static inline struct qreg
1090 vir_LOAD_IMM_U2(struct v3d_compile *c, uint32_t val)
1091 {
1092         return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_U2, c->undef,
1093                                         vir_reg(QFILE_LOAD_IMM, val),
1094                                         c->undef));
1095 }
1096 static inline struct qreg
1097 vir_LOAD_IMM_I2(struct v3d_compile *c, uint32_t val)
1098 {
1099         return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_I2, c->undef,
1100                                         vir_reg(QFILE_LOAD_IMM, val),
1101                                         c->undef));
1102 }
1103 */
1104
1105 static inline struct qinst *
1106 vir_BRANCH(struct v3d_compile *c, enum v3d_qpu_branch_cond cond)
1107 {
1108         /* The actual uniform_data value will be set at scheduling time */
1109         return vir_emit_nondef(c, vir_branch_inst(cond, vir_uniform_ui(c, 0)));
1110 }
1111
1112 #define vir_for_each_block(block, c)                                    \
1113         list_for_each_entry(struct qblock, block, &c->blocks, link)
1114
1115 #define vir_for_each_block_rev(block, c)                                \
1116         list_for_each_entry_rev(struct qblock, block, &c->blocks, link)
1117
1118 /* Loop over the non-NULL members of the successors array. */
1119 #define vir_for_each_successor(succ, block)                             \
1120         for (struct qblock *succ = block->successors[0];                \
1121              succ != NULL;                                              \
1122              succ = (succ == block->successors[1] ? NULL :              \
1123                      block->successors[1]))
1124
1125 #define vir_for_each_inst(inst, block)                                  \
1126         list_for_each_entry(struct qinst, inst, &block->instructions, link)
1127
1128 #define vir_for_each_inst_rev(inst, block)                                  \
1129         list_for_each_entry_rev(struct qinst, inst, &block->instructions, link)
1130
1131 #define vir_for_each_inst_safe(inst, block)                             \
1132         list_for_each_entry_safe(struct qinst, inst, &block->instructions, link)
1133
1134 #define vir_for_each_inst_inorder(inst, c)                              \
1135         vir_for_each_block(_block, c)                                   \
1136                 vir_for_each_inst(inst, _block)
1137
1138 #endif /* V3D_COMPILER_H */