src/broadcom/compiler/v3d_compiler.h

   1 /*
   2  * Copyright © 2016 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef V3D_COMPILER_H
  25 #define V3D_COMPILER_H
  26
  27 #include <assert.h>
  28 #include <stdio.h>
  29 #include <stdlib.h>
  30 #include <stdbool.h>
  31 #include <stdint.h>
  32 #include <string.h>
  33
  34 #include "util/macros.h"
  35 #include "common/v3d_debug.h"
  36 #include "common/v3d_device_info.h"
  37 #include "common/v3d_limits.h"
  38 #include "compiler/nir/nir.h"
  39 #include "util/list.h"
  40 #include "util/u_math.h"
  41
  42 #include "qpu/qpu_instr.h"
  43 #include "pipe/p_state.h"
  44
  45 struct nir_builder;
  46
  47 struct v3d_fs_inputs {
  48         /**
  49          * Array of the meanings of the VPM inputs this shader needs.
  50          *
  51          * It doesn't include those that aren't part of the VPM, like
  52          * point/line coordinates.
  53          */
  54         struct v3d_varying_slot *input_slots;
  55         uint32_t num_inputs;
  56 };
  57
  58 enum qfile {
  59         /** An unused source or destination register. */
  60         QFILE_NULL,
  61
  62         /** A physical register, such as the W coordinate payload. */
  63         QFILE_REG,
  64         /** One of the regsiters for fixed function interactions. */
  65         QFILE_MAGIC,
  66
  67         /**
  68          *  A virtual register, that will be allocated to actual accumulator
  69          * or physical registers later.
  70          */
  71         QFILE_TEMP,
  72         QFILE_UNIF,
  73         QFILE_TLB,
  74         QFILE_TLBU,
  75
  76         /**
  77          * VPM reads use this with an index value to say what part of the VPM
  78          * is being read.
  79          */
  80         QFILE_VPM,
  81
  82         /**
  83          * Stores an immediate value in the index field that will be used
  84          * directly by qpu_load_imm().
  85          */
  86         QFILE_LOAD_IMM,
  87
  88         /**
  89          * Stores an immediate value in the index field that can be turned
  90          * into a small immediate field by qpu_encode_small_immediate().
  91          */
  92         QFILE_SMALL_IMM,
  93 };
  94
  95 /**
  96  * A reference to a QPU register or a virtual temp register.
  97  */
  98 struct qreg {
  99         enum qfile file;
 100         uint32_t index;
 101 };
 102
 103 static inline struct qreg vir_reg(enum qfile file, uint32_t index)
 104 {
 105         return (struct qreg){file, index};
 106 }
 107
 108 /**
 109  * A reference to an actual register at the QPU level, for register
 110  * allocation.
 111  */
 112 struct qpu_reg {
 113         bool magic;
 114         bool smimm;
 115         int index;
 116 };
 117
 118 struct qinst {
 119         /** Entry in qblock->instructions */
 120         struct list_head link;
 121
 122         /**
 123          * The instruction being wrapped.  Its condition codes, pack flags,
 124          * signals, etc. will all be used, with just the register references
 125          * being replaced by the contents of qinst->dst and qinst->src[].
 126          */
 127         struct v3d_qpu_instr qpu;
 128
 129         /* Pre-register-allocation references to src/dst registers */
 130         struct qreg dst;
 131         struct qreg src[3];
 132         bool cond_is_exec_mask;
 133         bool has_implicit_uniform;
 134         bool is_last_thrsw;
 135
 136         /* After vir_to_qpu.c: If instr reads a uniform, which uniform from
 137          * the uncompiled stream it is.
 138          */
 139         int uniform;
 140 };
 141
 142 enum quniform_contents {
 143         /**
 144          * Indicates that a constant 32-bit value is copied from the program's
 145          * uniform contents.
 146          */
 147         QUNIFORM_CONSTANT,
 148         /**
 149          * Indicates that the program's uniform contents are used as an index
 150          * into the GL uniform storage.
 151          */
 152         QUNIFORM_UNIFORM,
 153
 154         /** @{
 155          * Scaling factors from clip coordinates to relative to the viewport
 156          * center.
 157          *
 158          * This is used by the coordinate and vertex shaders to produce the
 159          * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
 160          * point offsets from the viewport ccenter.
 161          */
 162         QUNIFORM_VIEWPORT_X_SCALE,
 163         QUNIFORM_VIEWPORT_Y_SCALE,
 164         /** @} */
 165
 166         QUNIFORM_VIEWPORT_Z_OFFSET,
 167         QUNIFORM_VIEWPORT_Z_SCALE,
 168
 169         QUNIFORM_USER_CLIP_PLANE,
 170
 171         /**
 172          * A reference to a V3D 3.x texture config parameter 0 uniform.
 173          *
 174          * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
 175          * defines texture type, miplevels, and such.  It will be found as a
 176          * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
 177          */
 178         QUNIFORM_TEXTURE_CONFIG_P0_0,
 179         QUNIFORM_TEXTURE_CONFIG_P0_1,
 180         QUNIFORM_TEXTURE_CONFIG_P0_2,
 181         QUNIFORM_TEXTURE_CONFIG_P0_3,
 182         QUNIFORM_TEXTURE_CONFIG_P0_4,
 183         QUNIFORM_TEXTURE_CONFIG_P0_5,
 184         QUNIFORM_TEXTURE_CONFIG_P0_6,
 185         QUNIFORM_TEXTURE_CONFIG_P0_7,
 186         QUNIFORM_TEXTURE_CONFIG_P0_8,
 187         QUNIFORM_TEXTURE_CONFIG_P0_9,
 188         QUNIFORM_TEXTURE_CONFIG_P0_10,
 189         QUNIFORM_TEXTURE_CONFIG_P0_11,
 190         QUNIFORM_TEXTURE_CONFIG_P0_12,
 191         QUNIFORM_TEXTURE_CONFIG_P0_13,
 192         QUNIFORM_TEXTURE_CONFIG_P0_14,
 193         QUNIFORM_TEXTURE_CONFIG_P0_15,
 194         QUNIFORM_TEXTURE_CONFIG_P0_16,
 195         QUNIFORM_TEXTURE_CONFIG_P0_17,
 196         QUNIFORM_TEXTURE_CONFIG_P0_18,
 197         QUNIFORM_TEXTURE_CONFIG_P0_19,
 198         QUNIFORM_TEXTURE_CONFIG_P0_20,
 199         QUNIFORM_TEXTURE_CONFIG_P0_21,
 200         QUNIFORM_TEXTURE_CONFIG_P0_22,
 201         QUNIFORM_TEXTURE_CONFIG_P0_23,
 202         QUNIFORM_TEXTURE_CONFIG_P0_24,
 203         QUNIFORM_TEXTURE_CONFIG_P0_25,
 204         QUNIFORM_TEXTURE_CONFIG_P0_26,
 205         QUNIFORM_TEXTURE_CONFIG_P0_27,
 206         QUNIFORM_TEXTURE_CONFIG_P0_28,
 207         QUNIFORM_TEXTURE_CONFIG_P0_29,
 208         QUNIFORM_TEXTURE_CONFIG_P0_30,
 209         QUNIFORM_TEXTURE_CONFIG_P0_31,
 210         QUNIFORM_TEXTURE_CONFIG_P0_32,
 211
 212         /**
 213          * A reference to a V3D 3.x texture config parameter 1 uniform.
 214          *
 215          * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
 216          * has the pointer to the indirect texture state.  Our data[] field
 217          * will have a packed p1 value, but the address field will be just
 218          * which texture unit's texture should be referenced.
 219          */
 220         QUNIFORM_TEXTURE_CONFIG_P1,
 221
 222         /* A V3D 4.x texture config parameter.  The high 8 bits will be
 223          * which texture or sampler is being sampled, and the driver must
 224          * replace the address field with the appropriate address.
 225          */
 226         QUNIFORM_TMU_CONFIG_P0,
 227         QUNIFORM_TMU_CONFIG_P1,
 228
 229         QUNIFORM_IMAGE_TMU_CONFIG_P0,
 230
 231         QUNIFORM_TEXTURE_FIRST_LEVEL,
 232
 233         QUNIFORM_TEXTURE_WIDTH,
 234         QUNIFORM_TEXTURE_HEIGHT,
 235         QUNIFORM_TEXTURE_DEPTH,
 236         QUNIFORM_TEXTURE_ARRAY_SIZE,
 237         QUNIFORM_TEXTURE_LEVELS,
 238
 239         QUNIFORM_UBO_ADDR,
 240
 241         QUNIFORM_TEXRECT_SCALE_X,
 242         QUNIFORM_TEXRECT_SCALE_Y,
 243
 244         /* Returns the base offset of the SSBO given by the data value. */
 245         QUNIFORM_SSBO_OFFSET,
 246
 247         /* Returns the size of the SSBO given by the data value. */
 248         QUNIFORM_GET_BUFFER_SIZE,
 249
 250         /* Sizes (in pixels) of a shader image given by the data value. */
 251         QUNIFORM_IMAGE_WIDTH,
 252         QUNIFORM_IMAGE_HEIGHT,
 253         QUNIFORM_IMAGE_DEPTH,
 254         QUNIFORM_IMAGE_ARRAY_SIZE,
 255
 256         QUNIFORM_ALPHA_REF,
 257
 258         /* Number of workgroups passed to glDispatchCompute in the dimension
 259          * selected by the data value.
 260          */
 261         QUNIFORM_NUM_WORK_GROUPS,
 262
 263         /**
 264          * Returns the the offset of the scratch buffer for register spilling.
 265          */
 266         QUNIFORM_SPILL_OFFSET,
 267         QUNIFORM_SPILL_SIZE_PER_THREAD,
 268
 269         /**
 270          * Returns the offset of the shared memory for compute shaders.
 271          *
 272          * This will be accessed using TMU general memory operations, so the
 273          * L2T cache will effectively be the shared memory area.
 274          */
 275         QUNIFORM_SHARED_OFFSET,
 276 };
 277
 278 static inline uint32_t v3d_tmu_config_data_create(uint32_t unit, uint32_t value)
 279 {
 280         return unit << 24 | value;
 281 }
 282
 283 static inline uint32_t v3d_tmu_config_data_get_unit(uint32_t data)
 284 {
 285         return data >> 24;
 286 }
 287
 288 static inline uint32_t v3d_tmu_config_data_get_value(uint32_t data)
 289 {
 290         return data & 0xffffff;
 291 }
 292
 293 struct v3d_varying_slot {
 294         uint8_t slot_and_component;
 295 };
 296
 297 static inline struct v3d_varying_slot
 298 v3d_slot_from_slot_and_component(uint8_t slot, uint8_t component)
 299 {
 300         assert(slot < 255 / 4);
 301         return (struct v3d_varying_slot){ (slot << 2) + component };
 302 }
 303
 304 static inline uint8_t v3d_slot_get_slot(struct v3d_varying_slot slot)
 305 {
 306         return slot.slot_and_component >> 2;
 307 }
 308
 309 static inline uint8_t v3d_slot_get_component(struct v3d_varying_slot slot)
 310 {
 311         return slot.slot_and_component & 3;
 312 }
 313
 314 struct v3d_ubo_range {
 315         /**
 316          * offset in bytes from the start of the ubo where this range is
 317          * uploaded.
 318          *
 319          * Only set once used is set.
 320          */
 321         uint32_t dst_offset;
 322
 323         /**
 324          * offset in bytes from the start of the gallium uniforms where the
 325          * data comes from.
 326          */
 327         uint32_t src_offset;
 328
 329         /** size in bytes of this ubo range */
 330         uint32_t size;
 331 };
 332
 333 struct v3d_key {
 334         void *shader_state;
 335         struct {
 336                 uint8_t swizzle[4];
 337                 uint8_t return_size;
 338                 uint8_t return_channels;
 339                 bool clamp_s:1;
 340                 bool clamp_t:1;
 341                 bool clamp_r:1;
 342         } tex[V3D_MAX_TEXTURE_SAMPLERS];
 343         uint8_t ucp_enables;
 344 };
 345
 346 struct v3d_fs_key {
 347         struct v3d_key base;
 348         bool depth_enabled;
 349         bool is_points;
 350         bool is_lines;
 351         bool alpha_test;
 352         bool point_coord_upper_left;
 353         bool light_twoside;
 354         bool msaa;
 355         bool sample_coverage;
 356         bool sample_alpha_to_coverage;
 357         bool sample_alpha_to_one;
 358         bool clamp_color;
 359         bool shade_model_flat;
 360         uint8_t nr_cbufs;
 361         uint8_t swap_color_rb;
 362         /* Mask of which render targets need to be written as 32-bit floats */
 363         uint8_t f32_color_rb;
 364         /* Masks of which render targets need to be written as ints/uints.
 365          * Used by gallium to work around lost information in TGSI.
 366          */
 367         uint8_t int_color_rb;
 368         uint8_t uint_color_rb;
 369         uint8_t alpha_test_func;
 370         uint8_t logicop_func;
 371         uint32_t point_sprite_mask;
 372
 373         struct pipe_rt_blend_state blend;
 374 };
 375
 376 struct v3d_vs_key {
 377         struct v3d_key base;
 378
 379         struct v3d_varying_slot fs_inputs[V3D_MAX_FS_INPUTS];
 380         uint8_t num_fs_inputs;
 381
 382         bool is_coord;
 383         bool per_vertex_point_size;
 384         bool clamp_color;
 385 };
 386
 387 /** A basic block of VIR intructions. */
 388 struct qblock {
 389         struct list_head link;
 390
 391         struct list_head instructions;
 392
 393         struct set *predecessors;
 394         struct qblock *successors[2];
 395
 396         int index;
 397
 398         /* Instruction IPs for the first and last instruction of the block.
 399          * Set by qpu_schedule.c.
 400          */
 401         uint32_t start_qpu_ip;
 402         uint32_t end_qpu_ip;
 403
 404         /* Instruction IP for the branch instruction of the block.  Set by
 405          * qpu_schedule.c.
 406          */
 407         uint32_t branch_qpu_ip;
 408
 409         /** Offset within the uniform stream at the start of the block. */
 410         uint32_t start_uniform;
 411         /** Offset within the uniform stream of the branch instruction */
 412         uint32_t branch_uniform;
 413
 414         /** @{ used by v3d_vir_live_variables.c */
 415         BITSET_WORD *def;
 416         BITSET_WORD *use;
 417         BITSET_WORD *live_in;
 418         BITSET_WORD *live_out;
 419         int start_ip, end_ip;
 420         /** @} */
 421 };
 422
 423 /** Which util/list.h add mode we should use when inserting an instruction. */
 424 enum vir_cursor_mode {
 425         vir_cursor_add,
 426         vir_cursor_addtail,
 427 };
 428
 429 /**
 430  * Tracking structure for where new instructions should be inserted.  Create
 431  * with one of the vir_after_inst()-style helper functions.
 432  *
 433  * This does not protect against removal of the block or instruction, so we
 434  * have an assert in instruction removal to try to catch it.
 435  */
 436 struct vir_cursor {
 437         enum vir_cursor_mode mode;
 438         struct list_head *link;
 439 };
 440
 441 static inline struct vir_cursor
 442 vir_before_inst(struct qinst *inst)
 443 {
 444         return (struct vir_cursor){ vir_cursor_addtail, &inst->link };
 445 }
 446
 447 static inline struct vir_cursor
 448 vir_after_inst(struct qinst *inst)
 449 {
 450         return (struct vir_cursor){ vir_cursor_add, &inst->link };
 451 }
 452
 453 static inline struct vir_cursor
 454 vir_before_block(struct qblock *block)
 455 {
 456         return (struct vir_cursor){ vir_cursor_add, &block->instructions };
 457 }
 458
 459 static inline struct vir_cursor
 460 vir_after_block(struct qblock *block)
 461 {
 462         return (struct vir_cursor){ vir_cursor_addtail, &block->instructions };
 463 }
 464
 465 /**
 466  * Compiler state saved across compiler invocations, for any expensive global
 467  * setup.
 468  */
 469 struct v3d_compiler {
 470         const struct v3d_device_info *devinfo;
 471         struct ra_regs *regs;
 472         unsigned int reg_class_phys[3];
 473         unsigned int reg_class_phys_or_acc[3];
 474 };
 475
 476 struct v3d_compile {
 477         const struct v3d_device_info *devinfo;
 478         nir_shader *s;
 479         nir_function_impl *impl;
 480         struct exec_list *cf_node_list;
 481         const struct v3d_compiler *compiler;
 482
 483         void (*debug_output)(const char *msg,
 484                              void *debug_output_data);
 485         void *debug_output_data;
 486
 487         /**
 488          * Mapping from nir_register * or nir_ssa_def * to array of struct
 489          * qreg for the values.
 490          */
 491         struct hash_table *def_ht;
 492
 493         /* For each temp, the instruction generating its value. */
 494         struct qinst **defs;
 495         uint32_t defs_array_size;
 496
 497         /**
 498          * Inputs to the shader, arranged by TGSI declaration order.
 499          *
 500          * Not all fragment shader QFILE_VARY reads are present in this array.
 501          */
 502         struct qreg *inputs;
 503         struct qreg *outputs;
 504         bool msaa_per_sample_output;
 505         struct qreg color_reads[V3D_MAX_SAMPLES];
 506         struct qreg sample_colors[V3D_MAX_SAMPLES];
 507         uint32_t inputs_array_size;
 508         uint32_t outputs_array_size;
 509         uint32_t uniforms_array_size;
 510
 511         /* Booleans for whether the corresponding QFILE_VARY[i] is
 512          * flat-shaded.  This includes gl_FragColor flat-shading, which is
 513          * customized based on the shademodel_flat shader key.
 514          */
 515         uint32_t flat_shade_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
 516
 517         uint32_t noperspective_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
 518
 519         uint32_t centroid_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
 520
 521         bool uses_center_w;
 522
 523         struct v3d_ubo_range *ubo_ranges;
 524         bool *ubo_range_used;
 525         uint32_t ubo_ranges_array_size;
 526         /** Number of uniform areas tracked in ubo_ranges. */
 527         uint32_t num_ubo_ranges;
 528         uint32_t next_ubo_dst_offset;
 529
 530         /* State for whether we're executing on each channel currently.  0 if
 531          * yes, otherwise a block number + 1 that the channel jumped to.
 532          */
 533         struct qreg execute;
 534
 535         struct qreg line_x, point_x, point_y;
 536
 537         /**
 538          * Instance ID, which comes in before the vertex attribute payload if
 539          * the shader record requests it.
 540          */
 541         struct qreg iid;
 542
 543         /**
 544          * Vertex ID, which comes in before the vertex attribute payload
 545          * (after Instance ID) if the shader record requests it.
 546          */
 547         struct qreg vid;
 548
 549         /* Fragment shader payload regs. */
 550         struct qreg payload_w, payload_w_centroid, payload_z;
 551
 552         struct qreg cs_payload[2];
 553         struct qreg cs_shared_offset;
 554         int local_invocation_index_bits;
 555
 556         uint8_t vattr_sizes[V3D_MAX_VS_INPUTS / 4];
 557         uint32_t num_vpm_writes;
 558
 559         /* Size in bytes of registers that have been spilled. This is how much
 560          * space needs to be available in the spill BO per thread per QPU.
 561          */
 562         uint32_t spill_size;
 563         /* Shader-db stats */
 564         uint32_t spills, fills, loops;
 565         /**
 566          * Register spilling's per-thread base address, shared between each
 567          * spill/fill's addressing calculations.
 568          */
 569         struct qreg spill_base;
 570         /* Bit vector of which temps may be spilled */
 571         BITSET_WORD *spillable;
 572
 573         /**
 574          * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
 575          *
 576          * This includes those that aren't part of the VPM varyings, like
 577          * point/line coordinates.
 578          */
 579         struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
 580
 581         /**
 582          * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
 583          * of the output is.  Used to emit from the VS in the order that the
 584          * FS needs.
 585          */
 586         struct v3d_varying_slot *output_slots;
 587
 588         struct pipe_shader_state *shader_state;
 589         struct v3d_key *key;
 590         struct v3d_fs_key *fs_key;
 591         struct v3d_vs_key *vs_key;
 592
 593         /* Live ranges of temps. */
 594         int *temp_start, *temp_end;
 595         bool live_intervals_valid;
 596
 597         uint32_t *uniform_data;
 598         enum quniform_contents *uniform_contents;
 599         uint32_t uniform_array_size;
 600         uint32_t num_uniforms;
 601         uint32_t num_outputs;
 602         uint32_t output_position_index;
 603         nir_variable *output_color_var[4];
 604         uint32_t output_point_size_index;
 605         uint32_t output_sample_mask_index;
 606
 607         struct qreg undef;
 608         uint32_t num_temps;
 609
 610         struct vir_cursor cursor;
 611         struct list_head blocks;
 612         int next_block_index;
 613         struct qblock *cur_block;
 614         struct qblock *loop_cont_block;
 615         struct qblock *loop_break_block;
 616
 617         uint64_t *qpu_insts;
 618         uint32_t qpu_inst_count;
 619         uint32_t qpu_inst_size;
 620
 621         /* For the FS, the number of varying inputs not counting the
 622          * point/line varyings payload
 623          */
 624         uint32_t num_inputs;
 625
 626         /**
 627          * Number of inputs from num_inputs remaining to be queued to the read
 628          * FIFO in the VS/CS.
 629          */
 630         uint32_t num_inputs_remaining;
 631
 632         /* Number of inputs currently in the read FIFO for the VS/CS */
 633         uint32_t num_inputs_in_fifo;
 634
 635         /** Next offset in the VPM to read from in the VS/CS */
 636         uint32_t vpm_read_offset;
 637
 638         uint32_t program_id;
 639         uint32_t variant_id;
 640
 641         /* Set to compile program in in 1x, 2x, or 4x threaded mode, where
 642          * SIG_THREAD_SWITCH is used to hide texturing latency at the cost of
 643          * limiting ourselves to the part of the physical reg space.
 644          *
 645          * On V3D 3.x, 2x or 4x divide the physical reg space by 2x or 4x.  On
 646          * V3D 4.x, all shaders are 2x threaded, and 4x only divides the
 647          * physical reg space in half.
 648          */
 649         uint8_t threads;
 650         struct qinst *last_thrsw;
 651         bool last_thrsw_at_top_level;
 652
 653         bool failed;
 654 };
 655
 656 struct v3d_uniform_list {
 657         enum quniform_contents *contents;
 658         uint32_t *data;
 659         uint32_t count;
 660 };
 661
 662 struct v3d_prog_data {
 663         struct v3d_uniform_list uniforms;
 664
 665         struct v3d_ubo_range *ubo_ranges;
 666         uint32_t num_ubo_ranges;
 667         uint32_t ubo_size;
 668         uint32_t spill_size;
 669
 670         uint8_t num_inputs;
 671         uint8_t threads;
 672
 673         /* For threads > 1, whether the program should be dispatched in the
 674          * after-final-THRSW state.
 675          */
 676         bool single_seg;
 677 };
 678
 679 struct v3d_vs_prog_data {
 680         struct v3d_prog_data base;
 681
 682         bool uses_iid, uses_vid;
 683
 684         /* Number of components read from each vertex attribute. */
 685         uint8_t vattr_sizes[V3D_MAX_VS_INPUTS / 4];
 686
 687         /* Total number of components read, for the shader state record. */
 688         uint32_t vpm_input_size;
 689
 690         /* Total number of components written, for the shader state record. */
 691         uint32_t vpm_output_size;
 692
 693         /* Set if there should be separate VPM segments for input and output.
 694          * If unset, vpm_input_size will be 0.
 695          */
 696         bool separate_segments;
 697
 698         /* Value to be programmed in VCM_CACHE_SIZE. */
 699         uint8_t vcm_cache_size;
 700 };
 701
 702 struct v3d_fs_prog_data {
 703         struct v3d_prog_data base;
 704
 705         struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
 706
 707         /* Array of flat shade flags.
 708          *
 709          * Each entry is only 24 bits (high 8 bits 0), to match the hardware
 710          * packet layout.
 711          */
 712         uint32_t flat_shade_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
 713
 714         uint32_t noperspective_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
 715
 716         uint32_t centroid_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
 717
 718         bool writes_z;
 719         bool discard;
 720         bool uses_center_w;
 721 };
 722
 723 /* Special nir_load_input intrinsic index for loading the current TLB
 724  * destination color.
 725  */
 726 #define V3D_NIR_TLB_COLOR_READ_INPUT            2000000000
 727
 728 #define V3D_NIR_MS_MASK_OUTPUT                  2000000000
 729
 730 extern const nir_shader_compiler_options v3d_nir_options;
 731
 732 const struct v3d_compiler *v3d_compiler_init(const struct v3d_device_info *devinfo);
 733 void v3d_compiler_free(const struct v3d_compiler *compiler);
 734 void v3d_optimize_nir(struct nir_shader *s);
 735
 736 uint64_t *v3d_compile(const struct v3d_compiler *compiler,
 737                       struct v3d_key *key,
 738                       struct v3d_prog_data **prog_data,
 739                       nir_shader *s,
 740                       void (*debug_output)(const char *msg,
 741                                            void *debug_output_data),
 742                       void *debug_output_data,
 743                       int program_id, int variant_id,
 744                       uint32_t *final_assembly_size);
 745
 746 void v3d_nir_to_vir(struct v3d_compile *c);
 747
 748 void vir_compile_destroy(struct v3d_compile *c);
 749 const char *vir_get_stage_name(struct v3d_compile *c);
 750 struct qblock *vir_new_block(struct v3d_compile *c);
 751 void vir_set_emit_block(struct v3d_compile *c, struct qblock *block);
 752 void vir_link_blocks(struct qblock *predecessor, struct qblock *successor);
 753 struct qblock *vir_entry_block(struct v3d_compile *c);
 754 struct qblock *vir_exit_block(struct v3d_compile *c);
 755 struct qinst *vir_add_inst(enum v3d_qpu_add_op op, struct qreg dst,
 756                            struct qreg src0, struct qreg src1);
 757 struct qinst *vir_mul_inst(enum v3d_qpu_mul_op op, struct qreg dst,
 758                            struct qreg src0, struct qreg src1);
 759 struct qinst *vir_branch_inst(enum v3d_qpu_branch_cond cond, struct qreg src0);
 760 void vir_remove_instruction(struct v3d_compile *c, struct qinst *qinst);
 761 struct qreg vir_uniform(struct v3d_compile *c,
 762                         enum quniform_contents contents,
 763                         uint32_t data);
 764 void vir_schedule_instructions(struct v3d_compile *c);
 765 struct v3d_qpu_instr v3d_qpu_nop(void);
 766
 767 struct qreg vir_emit_def(struct v3d_compile *c, struct qinst *inst);
 768 struct qinst *vir_emit_nondef(struct v3d_compile *c, struct qinst *inst);
 769 void vir_set_cond(struct qinst *inst, enum v3d_qpu_cond cond);
 770 void vir_set_pf(struct qinst *inst, enum v3d_qpu_pf pf);
 771 void vir_set_uf(struct qinst *inst, enum v3d_qpu_uf uf);
 772 void vir_set_unpack(struct qinst *inst, int src,
 773                     enum v3d_qpu_input_unpack unpack);
 774
 775 struct qreg vir_get_temp(struct v3d_compile *c);
 776 void vir_emit_last_thrsw(struct v3d_compile *c);
 777 void vir_calculate_live_intervals(struct v3d_compile *c);
 778 bool vir_has_implicit_uniform(struct qinst *inst);
 779 int vir_get_implicit_uniform_src(struct qinst *inst);
 780 int vir_get_non_sideband_nsrc(struct qinst *inst);
 781 int vir_get_nsrc(struct qinst *inst);
 782 bool vir_has_side_effects(struct v3d_compile *c, struct qinst *inst);
 783 bool vir_get_add_op(struct qinst *inst, enum v3d_qpu_add_op *op);
 784 bool vir_get_mul_op(struct qinst *inst, enum v3d_qpu_mul_op *op);
 785 bool vir_is_raw_mov(struct qinst *inst);
 786 bool vir_is_tex(struct qinst *inst);
 787 bool vir_is_add(struct qinst *inst);
 788 bool vir_is_mul(struct qinst *inst);
 789 bool vir_is_float_input(struct qinst *inst);
 790 bool vir_writes_r3(const struct v3d_device_info *devinfo, struct qinst *inst);
 791 bool vir_writes_r4(const struct v3d_device_info *devinfo, struct qinst *inst);
 792 struct qreg vir_follow_movs(struct v3d_compile *c, struct qreg reg);
 793 uint8_t vir_channels_written(struct qinst *inst);
 794 struct qreg ntq_get_src(struct v3d_compile *c, nir_src src, int i);
 795 void ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
 796                     struct qreg result);
 797 void vir_emit_thrsw(struct v3d_compile *c);
 798
 799 void vir_dump(struct v3d_compile *c);
 800 void vir_dump_inst(struct v3d_compile *c, struct qinst *inst);
 801 void vir_dump_uniform(enum quniform_contents contents, uint32_t data);
 802
 803 void vir_validate(struct v3d_compile *c);
 804
 805 void vir_optimize(struct v3d_compile *c);
 806 bool vir_opt_algebraic(struct v3d_compile *c);
 807 bool vir_opt_constant_folding(struct v3d_compile *c);
 808 bool vir_opt_copy_propagate(struct v3d_compile *c);
 809 bool vir_opt_dead_code(struct v3d_compile *c);
 810 bool vir_opt_peephole_sf(struct v3d_compile *c);
 811 bool vir_opt_small_immediates(struct v3d_compile *c);
 812 bool vir_opt_vpm(struct v3d_compile *c);
 813 void v3d_nir_lower_blend(nir_shader *s, struct v3d_compile *c);
 814 void v3d_nir_lower_io(nir_shader *s, struct v3d_compile *c);
 815 void v3d_nir_lower_txf_ms(nir_shader *s, struct v3d_compile *c);
 816 void v3d_nir_lower_image_load_store(nir_shader *s);
 817 void vir_lower_uniforms(struct v3d_compile *c);
 818
 819 void v3d33_vir_vpm_read_setup(struct v3d_compile *c, int num_components);
 820 void v3d33_vir_vpm_write_setup(struct v3d_compile *c);
 821 void v3d33_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr);
 822 void v3d40_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr);
 823 void v3d40_vir_emit_image_load_store(struct v3d_compile *c,
 824                                      nir_intrinsic_instr *instr);
 825
 826 void v3d_vir_to_qpu(struct v3d_compile *c, struct qpu_reg *temp_registers);
 827 uint32_t v3d_qpu_schedule_instructions(struct v3d_compile *c);
 828 void qpu_validate(struct v3d_compile *c);
 829 struct qpu_reg *v3d_register_allocate(struct v3d_compile *c, bool *spilled);
 830 bool vir_init_reg_sets(struct v3d_compiler *compiler);
 831
 832 bool v3d_gl_format_is_return_32(GLenum format);
 833
 834 void vir_PF(struct v3d_compile *c, struct qreg src, enum v3d_qpu_pf pf);
 835
 836 static inline bool
 837 quniform_contents_is_texture_p0(enum quniform_contents contents)
 838 {
 839         return (contents >= QUNIFORM_TEXTURE_CONFIG_P0_0 &&
 840                 contents < (QUNIFORM_TEXTURE_CONFIG_P0_0 +
 841                             V3D_MAX_TEXTURE_SAMPLERS));
 842 }
 843
 844 static inline struct qreg
 845 vir_uniform_ui(struct v3d_compile *c, uint32_t ui)
 846 {
 847         return vir_uniform(c, QUNIFORM_CONSTANT, ui);
 848 }
 849
 850 static inline struct qreg
 851 vir_uniform_f(struct v3d_compile *c, float f)
 852 {
 853         return vir_uniform(c, QUNIFORM_CONSTANT, fui(f));
 854 }
 855
 856 #define VIR_ALU0(name, vir_inst, op)                                     \
 857 static inline struct qreg                                                \
 858 vir_##name(struct v3d_compile *c)                                        \
 859 {                                                                        \
 860         return vir_emit_def(c, vir_inst(op, c->undef,                    \
 861                                         c->undef, c->undef));            \
 862 }                                                                        \
 863 static inline struct qinst *                                             \
 864 vir_##name##_dest(struct v3d_compile *c, struct qreg dest)               \
 865 {                                                                        \
 866         return vir_emit_nondef(c, vir_inst(op, dest,                     \
 867                                            c->undef, c->undef));         \
 868 }
 869
 870 #define VIR_ALU1(name, vir_inst, op)                                     \
 871 static inline struct qreg                                                \
 872 vir_##name(struct v3d_compile *c, struct qreg a)                         \
 873 {                                                                        \
 874         return vir_emit_def(c, vir_inst(op, c->undef,                    \
 875                                         a, c->undef));                   \
 876 }                                                                        \
 877 static inline struct qinst *                                             \
 878 vir_##name##_dest(struct v3d_compile *c, struct qreg dest,               \
 879                   struct qreg a)                                         \
 880 {                                                                        \
 881         return vir_emit_nondef(c, vir_inst(op, dest, a,          \
 882                                            c->undef));                   \
 883 }
 884
 885 #define VIR_ALU2(name, vir_inst, op)                                       \
 886 static inline struct qreg                                                \
 887 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b)          \
 888 {                                                                        \
 889         return vir_emit_def(c, vir_inst(op, c->undef, a, b));    \
 890 }                                                                        \
 891 static inline struct qinst *                                             \
 892 vir_##name##_dest(struct v3d_compile *c, struct qreg dest,               \
 893                   struct qreg a, struct qreg b)                          \
 894 {                                                                        \
 895         return vir_emit_nondef(c, vir_inst(op, dest, a, b));     \
 896 }
 897
 898 #define VIR_NODST_0(name, vir_inst, op)                                 \
 899 static inline struct qinst *                                            \
 900 vir_##name(struct v3d_compile *c)                                       \
 901 {                                                                       \
 902         return vir_emit_nondef(c, vir_inst(op, c->undef,                \
 903                                            c->undef, c->undef));        \
 904 }
 905
 906 #define VIR_NODST_1(name, vir_inst, op)                                               \
 907 static inline struct qinst *                                            \
 908 vir_##name(struct v3d_compile *c, struct qreg a)                        \
 909 {                                                                       \
 910         return vir_emit_nondef(c, vir_inst(op, c->undef,        \
 911                                            a, c->undef));               \
 912 }
 913
 914 #define VIR_NODST_2(name, vir_inst, op)                                               \
 915 static inline struct qinst *                                            \
 916 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b)         \
 917 {                                                                       \
 918         return vir_emit_nondef(c, vir_inst(op, c->undef,                \
 919                                            a, b));                      \
 920 }
 921
 922 #define VIR_SFU(name)                                                      \
 923 static inline struct qreg                                                \
 924 vir_##name(struct v3d_compile *c, struct qreg a)                         \
 925 {                                                                        \
 926         if (c->devinfo->ver >= 41) {                                     \
 927                 return vir_emit_def(c, vir_add_inst(V3D_QPU_A_##name,    \
 928                                                     c->undef,            \
 929                                                     a, c->undef));       \
 930         } else {                                                         \
 931                 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_##name), a); \
 932                 return vir_FMOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4)); \
 933         }                                                                \
 934 }                                                                        \
 935 static inline struct qinst *                                             \
 936 vir_##name##_dest(struct v3d_compile *c, struct qreg dest,               \
 937                   struct qreg a)                                         \
 938 {                                                                        \
 939         if (c->devinfo->ver >= 41) {                                     \
 940                 return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_##name, \
 941                                                        dest,             \
 942                                                        a, c->undef));    \
 943         } else {                                                         \
 944                 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_##name), a); \
 945                 return vir_FMOV_dest(c, dest, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4)); \
 946         }                                                                \
 947 }
 948
 949 #define VIR_A_ALU2(name) VIR_ALU2(name, vir_add_inst, V3D_QPU_A_##name)
 950 #define VIR_M_ALU2(name) VIR_ALU2(name, vir_mul_inst, V3D_QPU_M_##name)
 951 #define VIR_A_ALU1(name) VIR_ALU1(name, vir_add_inst, V3D_QPU_A_##name)
 952 #define VIR_M_ALU1(name) VIR_ALU1(name, vir_mul_inst, V3D_QPU_M_##name)
 953 #define VIR_A_ALU0(name) VIR_ALU0(name, vir_add_inst, V3D_QPU_A_##name)
 954 #define VIR_M_ALU0(name) VIR_ALU0(name, vir_mul_inst, V3D_QPU_M_##name)
 955 #define VIR_A_NODST_2(name) VIR_NODST_2(name, vir_add_inst, V3D_QPU_A_##name)
 956 #define VIR_M_NODST_2(name) VIR_NODST_2(name, vir_mul_inst, V3D_QPU_M_##name)
 957 #define VIR_A_NODST_1(name) VIR_NODST_1(name, vir_add_inst, V3D_QPU_A_##name)
 958 #define VIR_M_NODST_1(name) VIR_NODST_1(name, vir_mul_inst, V3D_QPU_M_##name)
 959 #define VIR_A_NODST_0(name) VIR_NODST_0(name, vir_add_inst, V3D_QPU_A_##name)
 960
 961 VIR_A_ALU2(FADD)
 962 VIR_A_ALU2(VFPACK)
 963 VIR_A_ALU2(FSUB)
 964 VIR_A_ALU2(FMIN)
 965 VIR_A_ALU2(FMAX)
 966
 967 VIR_A_ALU2(ADD)
 968 VIR_A_ALU2(SUB)
 969 VIR_A_ALU2(SHL)
 970 VIR_A_ALU2(SHR)
 971 VIR_A_ALU2(ASR)
 972 VIR_A_ALU2(ROR)
 973 VIR_A_ALU2(MIN)
 974 VIR_A_ALU2(MAX)
 975 VIR_A_ALU2(UMIN)
 976 VIR_A_ALU2(UMAX)
 977 VIR_A_ALU2(AND)
 978 VIR_A_ALU2(OR)
 979 VIR_A_ALU2(XOR)
 980 VIR_A_ALU2(VADD)
 981 VIR_A_ALU2(VSUB)
 982 VIR_A_NODST_2(STVPMV)
 983 VIR_A_ALU1(NOT)
 984 VIR_A_ALU1(NEG)
 985 VIR_A_ALU1(FLAPUSH)
 986 VIR_A_ALU1(FLBPUSH)
 987 VIR_A_ALU1(FLPOP)
 988 VIR_A_ALU1(SETMSF)
 989 VIR_A_ALU1(SETREVF)
 990 VIR_A_ALU0(TIDX)
 991 VIR_A_ALU0(EIDX)
 992 VIR_A_ALU1(LDVPMV_IN)
 993 VIR_A_ALU1(LDVPMV_OUT)
 994 VIR_A_ALU0(TMUWT)
 995
 996 VIR_A_ALU0(FXCD)
 997 VIR_A_ALU0(XCD)
 998 VIR_A_ALU0(FYCD)
 999 VIR_A_ALU0(YCD)
1000 VIR_A_ALU0(MSF)
1001 VIR_A_ALU0(REVF)
1002 VIR_A_ALU0(BARRIERID)
1003 VIR_A_NODST_1(VPMSETUP)
1004 VIR_A_NODST_0(VPMWT)
1005 VIR_A_ALU2(FCMP)
1006 VIR_A_ALU2(VFMAX)
1007
1008 VIR_A_ALU1(FROUND)
1009 VIR_A_ALU1(FTOIN)
1010 VIR_A_ALU1(FTRUNC)
1011 VIR_A_ALU1(FTOIZ)
1012 VIR_A_ALU1(FFLOOR)
1013 VIR_A_ALU1(FTOUZ)
1014 VIR_A_ALU1(FCEIL)
1015 VIR_A_ALU1(FTOC)
1016
1017 VIR_A_ALU1(FDX)
1018 VIR_A_ALU1(FDY)
1019
1020 VIR_A_ALU1(ITOF)
1021 VIR_A_ALU1(CLZ)
1022 VIR_A_ALU1(UTOF)
1023
1024 VIR_M_ALU2(UMUL24)
1025 VIR_M_ALU2(FMUL)
1026 VIR_M_ALU2(SMUL24)
1027 VIR_M_NODST_2(MULTOP)
1028
1029 VIR_M_ALU1(MOV)
1030 VIR_M_ALU1(FMOV)
1031
1032 VIR_SFU(RECIP)
1033 VIR_SFU(RSQRT)
1034 VIR_SFU(EXP)
1035 VIR_SFU(LOG)
1036 VIR_SFU(SIN)
1037 VIR_SFU(RSQRT2)
1038
1039 static inline struct qinst *
1040 vir_MOV_cond(struct v3d_compile *c, enum v3d_qpu_cond cond,
1041              struct qreg dest, struct qreg src)
1042 {
1043         struct qinst *mov = vir_MOV_dest(c, dest, src);
1044         vir_set_cond(mov, cond);
1045         return mov;
1046 }
1047
1048 static inline struct qreg
1049 vir_SEL(struct v3d_compile *c, enum v3d_qpu_cond cond,
1050         struct qreg src0, struct qreg src1)
1051 {
1052         struct qreg t = vir_get_temp(c);
1053         vir_MOV_dest(c, t, src1);
1054         vir_MOV_cond(c, cond, t, src0);
1055         return t;
1056 }
1057
1058 static inline struct qinst *
1059 vir_NOP(struct v3d_compile *c)
1060 {
1061         return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_NOP,
1062                                                c->undef, c->undef, c->undef));
1063 }
1064
1065 static inline struct qreg
1066 vir_LDTMU(struct v3d_compile *c)
1067 {
1068         if (c->devinfo->ver >= 41) {
1069                 struct qinst *ldtmu = vir_add_inst(V3D_QPU_A_NOP, c->undef,
1070                                                    c->undef, c->undef);
1071                 ldtmu->qpu.sig.ldtmu = true;
1072
1073                 return vir_emit_def(c, ldtmu);
1074         } else {
1075                 vir_NOP(c)->qpu.sig.ldtmu = true;
1076                 return vir_MOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4));
1077         }
1078 }
1079
1080 static inline struct qreg
1081 vir_UMUL(struct v3d_compile *c, struct qreg src0, struct qreg src1)
1082 {
1083         vir_MULTOP(c, src0, src1);
1084         return vir_UMUL24(c, src0, src1);
1085 }
1086
1087 /*
1088 static inline struct qreg
1089 vir_LOAD_IMM(struct v3d_compile *c, uint32_t val)
1090 {
1091         return vir_emit_def(c, vir_inst(QOP_LOAD_IMM, c->undef,
1092                                         vir_reg(QFILE_LOAD_IMM, val), c->undef));
1093 }
1094
1095 static inline struct qreg
1096 vir_LOAD_IMM_U2(struct v3d_compile *c, uint32_t val)
1097 {
1098         return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_U2, c->undef,
1099                                         vir_reg(QFILE_LOAD_IMM, val),
1100                                         c->undef));
1101 }
1102 static inline struct qreg
1103 vir_LOAD_IMM_I2(struct v3d_compile *c, uint32_t val)
1104 {
1105         return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_I2, c->undef,
1106                                         vir_reg(QFILE_LOAD_IMM, val),
1107                                         c->undef));
1108 }
1109 */
1110
1111 static inline struct qinst *
1112 vir_BRANCH(struct v3d_compile *c, enum v3d_qpu_branch_cond cond)
1113 {
1114         /* The actual uniform_data value will be set at scheduling time */
1115         return vir_emit_nondef(c, vir_branch_inst(cond, vir_uniform_ui(c, 0)));
1116 }
1117
1118 #define vir_for_each_block(block, c)                                    \
1119         list_for_each_entry(struct qblock, block, &c->blocks, link)
1120
1121 #define vir_for_each_block_rev(block, c)                                \
1122         list_for_each_entry_rev(struct qblock, block, &c->blocks, link)
1123
1124 /* Loop over the non-NULL members of the successors array. */
1125 #define vir_for_each_successor(succ, block)                             \
1126         for (struct qblock *succ = block->successors[0];                \
1127              succ != NULL;                                              \
1128              succ = (succ == block->successors[1] ? NULL :              \
1129                      block->successors[1]))
1130
1131 #define vir_for_each_inst(inst, block)                                  \
1132         list_for_each_entry(struct qinst, inst, &block->instructions, link)
1133
1134 #define vir_for_each_inst_rev(inst, block)                                  \
1135         list_for_each_entry_rev(struct qinst, inst, &block->instructions, link)
1136
1137 #define vir_for_each_inst_safe(inst, block)                             \
1138         list_for_each_entry_safe(struct qinst, inst, &block->instructions, link)
1139
1140 #define vir_for_each_inst_inorder(inst, c)                              \
1141         vir_for_each_block(_block, c)                                   \
1142                 vir_for_each_inst(inst, _block)
1143
1144 #endif /* V3D_COMPILER_H */