src/broadcom/compiler/v3d_compiler.h

   1 /*
   2  * Copyright © 2016 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef V3D_COMPILER_H
  25 #define V3D_COMPILER_H
  26
  27 #include <assert.h>
  28 #include <stdio.h>
  29 #include <stdlib.h>
  30 #include <stdbool.h>
  31 #include <stdint.h>
  32 #include <string.h>
  33
  34 #include "util/macros.h"
  35 #include "common/v3d_debug.h"
  36 #include "common/v3d_device_info.h"
  37 #include "compiler/nir/nir.h"
  38 #include "util/list.h"
  39 #include "util/u_math.h"
  40
  41 #include "qpu/qpu_instr.h"
  42 #include "pipe/p_state.h"
  43
  44 #define V3D_MAX_TEXTURE_SAMPLERS 32
  45 #define V3D_MAX_SAMPLES 4
  46 #define V3D_MAX_FS_INPUTS 64
  47 #define V3D_MAX_VS_INPUTS 64
  48
  49 struct nir_builder;
  50
  51 struct v3d_fs_inputs {
  52         /**
  53          * Array of the meanings of the VPM inputs this shader needs.
  54          *
  55          * It doesn't include those that aren't part of the VPM, like
  56          * point/line coordinates.
  57          */
  58         struct v3d_varying_slot *input_slots;
  59         uint32_t num_inputs;
  60 };
  61
  62 enum qfile {
  63         /** An unused source or destination register. */
  64         QFILE_NULL,
  65
  66         /** A physical register, such as the W coordinate payload. */
  67         QFILE_REG,
  68         /** One of the regsiters for fixed function interactions. */
  69         QFILE_MAGIC,
  70
  71         /**
  72          *  A virtual register, that will be allocated to actual accumulator
  73          * or physical registers later.
  74          */
  75         QFILE_TEMP,
  76         QFILE_UNIF,
  77         QFILE_TLB,
  78         QFILE_TLBU,
  79
  80         /**
  81          * VPM reads use this with an index value to say what part of the VPM
  82          * is being read.
  83          */
  84         QFILE_VPM,
  85
  86         /**
  87          * Stores an immediate value in the index field that will be used
  88          * directly by qpu_load_imm().
  89          */
  90         QFILE_LOAD_IMM,
  91
  92         /**
  93          * Stores an immediate value in the index field that can be turned
  94          * into a small immediate field by qpu_encode_small_immediate().
  95          */
  96         QFILE_SMALL_IMM,
  97 };
  98
  99 /**
 100  * A reference to a QPU register or a virtual temp register.
 101  */
 102 struct qreg {
 103         enum qfile file;
 104         uint32_t index;
 105 };
 106
 107 static inline struct qreg vir_reg(enum qfile file, uint32_t index)
 108 {
 109         return (struct qreg){file, index};
 110 }
 111
 112 /**
 113  * A reference to an actual register at the QPU level, for register
 114  * allocation.
 115  */
 116 struct qpu_reg {
 117         bool magic;
 118         bool smimm;
 119         int index;
 120 };
 121
 122 struct qinst {
 123         /** Entry in qblock->instructions */
 124         struct list_head link;
 125
 126         /**
 127          * The instruction being wrapped.  Its condition codes, pack flags,
 128          * signals, etc. will all be used, with just the register references
 129          * being replaced by the contents of qinst->dst and qinst->src[].
 130          */
 131         struct v3d_qpu_instr qpu;
 132
 133         /* Pre-register-allocation references to src/dst registers */
 134         struct qreg dst;
 135         struct qreg src[3];
 136         bool cond_is_exec_mask;
 137         bool has_implicit_uniform;
 138         bool is_last_thrsw;
 139
 140         /* After vir_to_qpu.c: If instr reads a uniform, which uniform from
 141          * the uncompiled stream it is.
 142          */
 143         int uniform;
 144 };
 145
 146 enum quniform_contents {
 147         /**
 148          * Indicates that a constant 32-bit value is copied from the program's
 149          * uniform contents.
 150          */
 151         QUNIFORM_CONSTANT,
 152         /**
 153          * Indicates that the program's uniform contents are used as an index
 154          * into the GL uniform storage.
 155          */
 156         QUNIFORM_UNIFORM,
 157
 158         /** @{
 159          * Scaling factors from clip coordinates to relative to the viewport
 160          * center.
 161          *
 162          * This is used by the coordinate and vertex shaders to produce the
 163          * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
 164          * point offsets from the viewport ccenter.
 165          */
 166         QUNIFORM_VIEWPORT_X_SCALE,
 167         QUNIFORM_VIEWPORT_Y_SCALE,
 168         /** @} */
 169
 170         QUNIFORM_VIEWPORT_Z_OFFSET,
 171         QUNIFORM_VIEWPORT_Z_SCALE,
 172
 173         QUNIFORM_USER_CLIP_PLANE,
 174
 175         /**
 176          * A reference to a V3D 3.x texture config parameter 0 uniform.
 177          *
 178          * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
 179          * defines texture type, miplevels, and such.  It will be found as a
 180          * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
 181          */
 182         QUNIFORM_TEXTURE_CONFIG_P0_0,
 183         QUNIFORM_TEXTURE_CONFIG_P0_1,
 184         QUNIFORM_TEXTURE_CONFIG_P0_2,
 185         QUNIFORM_TEXTURE_CONFIG_P0_3,
 186         QUNIFORM_TEXTURE_CONFIG_P0_4,
 187         QUNIFORM_TEXTURE_CONFIG_P0_5,
 188         QUNIFORM_TEXTURE_CONFIG_P0_6,
 189         QUNIFORM_TEXTURE_CONFIG_P0_7,
 190         QUNIFORM_TEXTURE_CONFIG_P0_8,
 191         QUNIFORM_TEXTURE_CONFIG_P0_9,
 192         QUNIFORM_TEXTURE_CONFIG_P0_10,
 193         QUNIFORM_TEXTURE_CONFIG_P0_11,
 194         QUNIFORM_TEXTURE_CONFIG_P0_12,
 195         QUNIFORM_TEXTURE_CONFIG_P0_13,
 196         QUNIFORM_TEXTURE_CONFIG_P0_14,
 197         QUNIFORM_TEXTURE_CONFIG_P0_15,
 198         QUNIFORM_TEXTURE_CONFIG_P0_16,
 199         QUNIFORM_TEXTURE_CONFIG_P0_17,
 200         QUNIFORM_TEXTURE_CONFIG_P0_18,
 201         QUNIFORM_TEXTURE_CONFIG_P0_19,
 202         QUNIFORM_TEXTURE_CONFIG_P0_20,
 203         QUNIFORM_TEXTURE_CONFIG_P0_21,
 204         QUNIFORM_TEXTURE_CONFIG_P0_22,
 205         QUNIFORM_TEXTURE_CONFIG_P0_23,
 206         QUNIFORM_TEXTURE_CONFIG_P0_24,
 207         QUNIFORM_TEXTURE_CONFIG_P0_25,
 208         QUNIFORM_TEXTURE_CONFIG_P0_26,
 209         QUNIFORM_TEXTURE_CONFIG_P0_27,
 210         QUNIFORM_TEXTURE_CONFIG_P0_28,
 211         QUNIFORM_TEXTURE_CONFIG_P0_29,
 212         QUNIFORM_TEXTURE_CONFIG_P0_30,
 213         QUNIFORM_TEXTURE_CONFIG_P0_31,
 214         QUNIFORM_TEXTURE_CONFIG_P0_32,
 215
 216         /**
 217          * A reference to a V3D 3.x texture config parameter 1 uniform.
 218          *
 219          * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
 220          * has the pointer to the indirect texture state.  Our data[] field
 221          * will have a packed p1 value, but the address field will be just
 222          * which texture unit's texture should be referenced.
 223          */
 224         QUNIFORM_TEXTURE_CONFIG_P1,
 225
 226         /* A V3D 4.x texture config parameter.  The high 8 bits will be
 227          * which texture or sampler is being sampled, and the driver must
 228          * replace the address field with the appropriate address.
 229          */
 230         QUNIFORM_TMU_CONFIG_P0,
 231         QUNIFORM_TMU_CONFIG_P1,
 232
 233         QUNIFORM_IMAGE_TMU_CONFIG_P0,
 234
 235         QUNIFORM_TEXTURE_FIRST_LEVEL,
 236
 237         QUNIFORM_TEXTURE_WIDTH,
 238         QUNIFORM_TEXTURE_HEIGHT,
 239         QUNIFORM_TEXTURE_DEPTH,
 240         QUNIFORM_TEXTURE_ARRAY_SIZE,
 241         QUNIFORM_TEXTURE_LEVELS,
 242
 243         QUNIFORM_UBO_ADDR,
 244
 245         QUNIFORM_TEXRECT_SCALE_X,
 246         QUNIFORM_TEXRECT_SCALE_Y,
 247
 248         /* Returns the base offset of the SSBO given by the data value. */
 249         QUNIFORM_SSBO_OFFSET,
 250
 251         /* Returns the size of the SSBO given by the data value. */
 252         QUNIFORM_GET_BUFFER_SIZE,
 253
 254         /* Sizes (in pixels) of a shader image given by the data value. */
 255         QUNIFORM_IMAGE_WIDTH,
 256         QUNIFORM_IMAGE_HEIGHT,
 257         QUNIFORM_IMAGE_DEPTH,
 258         QUNIFORM_IMAGE_ARRAY_SIZE,
 259
 260         QUNIFORM_ALPHA_REF,
 261
 262         /* Number of workgroups passed to glDispatchCompute in the dimension
 263          * selected by the data value.
 264          */
 265         QUNIFORM_NUM_WORK_GROUPS,
 266
 267         /**
 268          * Returns the the offset of the scratch buffer for register spilling.
 269          */
 270         QUNIFORM_SPILL_OFFSET,
 271         QUNIFORM_SPILL_SIZE_PER_THREAD,
 272
 273         /**
 274          * Returns the offset of the shared memory for compute shaders.
 275          *
 276          * This will be accessed using TMU general memory operations, so the
 277          * L2T cache will effectively be the shared memory area.
 278          */
 279         QUNIFORM_SHARED_OFFSET,
 280 };
 281
 282 static inline uint32_t v3d_tmu_config_data_create(uint32_t unit, uint32_t value)
 283 {
 284         return unit << 24 | value;
 285 }
 286
 287 static inline uint32_t v3d_tmu_config_data_get_unit(uint32_t data)
 288 {
 289         return data >> 24;
 290 }
 291
 292 static inline uint32_t v3d_tmu_config_data_get_value(uint32_t data)
 293 {
 294         return data & 0xffffff;
 295 }
 296
 297 struct v3d_varying_slot {
 298         uint8_t slot_and_component;
 299 };
 300
 301 static inline struct v3d_varying_slot
 302 v3d_slot_from_slot_and_component(uint8_t slot, uint8_t component)
 303 {
 304         assert(slot < 255 / 4);
 305         return (struct v3d_varying_slot){ (slot << 2) + component };
 306 }
 307
 308 static inline uint8_t v3d_slot_get_slot(struct v3d_varying_slot slot)
 309 {
 310         return slot.slot_and_component >> 2;
 311 }
 312
 313 static inline uint8_t v3d_slot_get_component(struct v3d_varying_slot slot)
 314 {
 315         return slot.slot_and_component & 3;
 316 }
 317
 318 struct v3d_ubo_range {
 319         /**
 320          * offset in bytes from the start of the ubo where this range is
 321          * uploaded.
 322          *
 323          * Only set once used is set.
 324          */
 325         uint32_t dst_offset;
 326
 327         /**
 328          * offset in bytes from the start of the gallium uniforms where the
 329          * data comes from.
 330          */
 331         uint32_t src_offset;
 332
 333         /** size in bytes of this ubo range */
 334         uint32_t size;
 335 };
 336
 337 struct v3d_key {
 338         void *shader_state;
 339         struct {
 340                 uint8_t swizzle[4];
 341                 uint8_t return_size;
 342                 uint8_t return_channels;
 343                 bool clamp_s:1;
 344                 bool clamp_t:1;
 345                 bool clamp_r:1;
 346         } tex[V3D_MAX_TEXTURE_SAMPLERS];
 347         uint8_t ucp_enables;
 348 };
 349
 350 struct v3d_fs_key {
 351         struct v3d_key base;
 352         bool depth_enabled;
 353         bool is_points;
 354         bool is_lines;
 355         bool alpha_test;
 356         bool point_coord_upper_left;
 357         bool light_twoside;
 358         bool msaa;
 359         bool sample_coverage;
 360         bool sample_alpha_to_coverage;
 361         bool sample_alpha_to_one;
 362         bool clamp_color;
 363         bool shade_model_flat;
 364         uint8_t nr_cbufs;
 365         uint8_t swap_color_rb;
 366         /* Mask of which render targets need to be written as 32-bit floats */
 367         uint8_t f32_color_rb;
 368         /* Masks of which render targets need to be written as ints/uints.
 369          * Used by gallium to work around lost information in TGSI.
 370          */
 371         uint8_t int_color_rb;
 372         uint8_t uint_color_rb;
 373         uint8_t alpha_test_func;
 374         uint8_t logicop_func;
 375         uint32_t point_sprite_mask;
 376
 377         struct pipe_rt_blend_state blend;
 378 };
 379
 380 struct v3d_vs_key {
 381         struct v3d_key base;
 382
 383         struct v3d_varying_slot fs_inputs[V3D_MAX_FS_INPUTS];
 384         uint8_t num_fs_inputs;
 385
 386         bool is_coord;
 387         bool per_vertex_point_size;
 388         bool clamp_color;
 389 };
 390
 391 /** A basic block of VIR intructions. */
 392 struct qblock {
 393         struct list_head link;
 394
 395         struct list_head instructions;
 396
 397         struct set *predecessors;
 398         struct qblock *successors[2];
 399
 400         int index;
 401
 402         /* Instruction IPs for the first and last instruction of the block.
 403          * Set by qpu_schedule.c.
 404          */
 405         uint32_t start_qpu_ip;
 406         uint32_t end_qpu_ip;
 407
 408         /* Instruction IP for the branch instruction of the block.  Set by
 409          * qpu_schedule.c.
 410          */
 411         uint32_t branch_qpu_ip;
 412
 413         /** Offset within the uniform stream at the start of the block. */
 414         uint32_t start_uniform;
 415         /** Offset within the uniform stream of the branch instruction */
 416         uint32_t branch_uniform;
 417
 418         /** @{ used by v3d_vir_live_variables.c */
 419         BITSET_WORD *def;
 420         BITSET_WORD *use;
 421         BITSET_WORD *live_in;
 422         BITSET_WORD *live_out;
 423         int start_ip, end_ip;
 424         /** @} */
 425 };
 426
 427 /** Which util/list.h add mode we should use when inserting an instruction. */
 428 enum vir_cursor_mode {
 429         vir_cursor_add,
 430         vir_cursor_addtail,
 431 };
 432
 433 /**
 434  * Tracking structure for where new instructions should be inserted.  Create
 435  * with one of the vir_after_inst()-style helper functions.
 436  *
 437  * This does not protect against removal of the block or instruction, so we
 438  * have an assert in instruction removal to try to catch it.
 439  */
 440 struct vir_cursor {
 441         enum vir_cursor_mode mode;
 442         struct list_head *link;
 443 };
 444
 445 static inline struct vir_cursor
 446 vir_before_inst(struct qinst *inst)
 447 {
 448         return (struct vir_cursor){ vir_cursor_addtail, &inst->link };
 449 }
 450
 451 static inline struct vir_cursor
 452 vir_after_inst(struct qinst *inst)
 453 {
 454         return (struct vir_cursor){ vir_cursor_add, &inst->link };
 455 }
 456
 457 static inline struct vir_cursor
 458 vir_before_block(struct qblock *block)
 459 {
 460         return (struct vir_cursor){ vir_cursor_add, &block->instructions };
 461 }
 462
 463 static inline struct vir_cursor
 464 vir_after_block(struct qblock *block)
 465 {
 466         return (struct vir_cursor){ vir_cursor_addtail, &block->instructions };
 467 }
 468
 469 /**
 470  * Compiler state saved across compiler invocations, for any expensive global
 471  * setup.
 472  */
 473 struct v3d_compiler {
 474         const struct v3d_device_info *devinfo;
 475         struct ra_regs *regs;
 476         unsigned int reg_class_phys[3];
 477         unsigned int reg_class_phys_or_acc[3];
 478 };
 479
 480 struct v3d_compile {
 481         const struct v3d_device_info *devinfo;
 482         nir_shader *s;
 483         nir_function_impl *impl;
 484         struct exec_list *cf_node_list;
 485         const struct v3d_compiler *compiler;
 486
 487         void (*debug_output)(const char *msg,
 488                              void *debug_output_data);
 489         void *debug_output_data;
 490
 491         /**
 492          * Mapping from nir_register * or nir_ssa_def * to array of struct
 493          * qreg for the values.
 494          */
 495         struct hash_table *def_ht;
 496
 497         /* For each temp, the instruction generating its value. */
 498         struct qinst **defs;
 499         uint32_t defs_array_size;
 500
 501         /**
 502          * Inputs to the shader, arranged by TGSI declaration order.
 503          *
 504          * Not all fragment shader QFILE_VARY reads are present in this array.
 505          */
 506         struct qreg *inputs;
 507         struct qreg *outputs;
 508         bool msaa_per_sample_output;
 509         struct qreg color_reads[V3D_MAX_SAMPLES];
 510         struct qreg sample_colors[V3D_MAX_SAMPLES];
 511         uint32_t inputs_array_size;
 512         uint32_t outputs_array_size;
 513         uint32_t uniforms_array_size;
 514
 515         /* Booleans for whether the corresponding QFILE_VARY[i] is
 516          * flat-shaded.  This includes gl_FragColor flat-shading, which is
 517          * customized based on the shademodel_flat shader key.
 518          */
 519         uint32_t flat_shade_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
 520
 521         uint32_t noperspective_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
 522
 523         uint32_t centroid_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
 524
 525         bool uses_center_w;
 526
 527         struct v3d_ubo_range *ubo_ranges;
 528         bool *ubo_range_used;
 529         uint32_t ubo_ranges_array_size;
 530         /** Number of uniform areas tracked in ubo_ranges. */
 531         uint32_t num_ubo_ranges;
 532         uint32_t next_ubo_dst_offset;
 533
 534         /* State for whether we're executing on each channel currently.  0 if
 535          * yes, otherwise a block number + 1 that the channel jumped to.
 536          */
 537         struct qreg execute;
 538
 539         struct qreg line_x, point_x, point_y;
 540
 541         /**
 542          * Instance ID, which comes in before the vertex attribute payload if
 543          * the shader record requests it.
 544          */
 545         struct qreg iid;
 546
 547         /**
 548          * Vertex ID, which comes in before the vertex attribute payload
 549          * (after Instance ID) if the shader record requests it.
 550          */
 551         struct qreg vid;
 552
 553         /* Fragment shader payload regs. */
 554         struct qreg payload_w, payload_w_centroid, payload_z;
 555
 556         struct qreg cs_payload[2];
 557         struct qreg cs_shared_offset;
 558         int local_invocation_index_bits;
 559
 560         uint8_t vattr_sizes[V3D_MAX_VS_INPUTS];
 561         uint32_t num_vpm_writes;
 562
 563         /* Size in bytes of registers that have been spilled. This is how much
 564          * space needs to be available in the spill BO per thread per QPU.
 565          */
 566         uint32_t spill_size;
 567         /* Shader-db stats */
 568         uint32_t spills, fills, loops;
 569         /**
 570          * Register spilling's per-thread base address, shared between each
 571          * spill/fill's addressing calculations.
 572          */
 573         struct qreg spill_base;
 574         /* Bit vector of which temps may be spilled */
 575         BITSET_WORD *spillable;
 576
 577         /**
 578          * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
 579          *
 580          * This includes those that aren't part of the VPM varyings, like
 581          * point/line coordinates.
 582          */
 583         struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
 584
 585         /**
 586          * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
 587          * of the output is.  Used to emit from the VS in the order that the
 588          * FS needs.
 589          */
 590         struct v3d_varying_slot *output_slots;
 591
 592         struct pipe_shader_state *shader_state;
 593         struct v3d_key *key;
 594         struct v3d_fs_key *fs_key;
 595         struct v3d_vs_key *vs_key;
 596
 597         /* Live ranges of temps. */
 598         int *temp_start, *temp_end;
 599         bool live_intervals_valid;
 600
 601         uint32_t *uniform_data;
 602         enum quniform_contents *uniform_contents;
 603         uint32_t uniform_array_size;
 604         uint32_t num_uniforms;
 605         uint32_t num_outputs;
 606         uint32_t output_position_index;
 607         nir_variable *output_color_var[4];
 608         uint32_t output_point_size_index;
 609         uint32_t output_sample_mask_index;
 610
 611         struct qreg undef;
 612         uint32_t num_temps;
 613
 614         struct vir_cursor cursor;
 615         struct list_head blocks;
 616         int next_block_index;
 617         struct qblock *cur_block;
 618         struct qblock *loop_cont_block;
 619         struct qblock *loop_break_block;
 620
 621         uint64_t *qpu_insts;
 622         uint32_t qpu_inst_count;
 623         uint32_t qpu_inst_size;
 624
 625         /* For the FS, the number of varying inputs not counting the
 626          * point/line varyings payload
 627          */
 628         uint32_t num_inputs;
 629
 630         /**
 631          * Number of inputs from num_inputs remaining to be queued to the read
 632          * FIFO in the VS/CS.
 633          */
 634         uint32_t num_inputs_remaining;
 635
 636         /* Number of inputs currently in the read FIFO for the VS/CS */
 637         uint32_t num_inputs_in_fifo;
 638
 639         /** Next offset in the VPM to read from in the VS/CS */
 640         uint32_t vpm_read_offset;
 641
 642         uint32_t program_id;
 643         uint32_t variant_id;
 644
 645         /* Set to compile program in in 1x, 2x, or 4x threaded mode, where
 646          * SIG_THREAD_SWITCH is used to hide texturing latency at the cost of
 647          * limiting ourselves to the part of the physical reg space.
 648          *
 649          * On V3D 3.x, 2x or 4x divide the physical reg space by 2x or 4x.  On
 650          * V3D 4.x, all shaders are 2x threaded, and 4x only divides the
 651          * physical reg space in half.
 652          */
 653         uint8_t threads;
 654         struct qinst *last_thrsw;
 655         bool last_thrsw_at_top_level;
 656
 657         bool failed;
 658 };
 659
 660 struct v3d_uniform_list {
 661         enum quniform_contents *contents;
 662         uint32_t *data;
 663         uint32_t count;
 664 };
 665
 666 struct v3d_prog_data {
 667         struct v3d_uniform_list uniforms;
 668
 669         struct v3d_ubo_range *ubo_ranges;
 670         uint32_t num_ubo_ranges;
 671         uint32_t ubo_size;
 672         uint32_t spill_size;
 673
 674         uint8_t num_inputs;
 675         uint8_t threads;
 676
 677         /* For threads > 1, whether the program should be dispatched in the
 678          * after-final-THRSW state.
 679          */
 680         bool single_seg;
 681 };
 682
 683 struct v3d_vs_prog_data {
 684         struct v3d_prog_data base;
 685
 686         bool uses_iid, uses_vid;
 687
 688         /* Number of components read from each vertex attribute. */
 689         uint8_t vattr_sizes[32];
 690
 691         /* Total number of components read, for the shader state record. */
 692         uint32_t vpm_input_size;
 693
 694         /* Total number of components written, for the shader state record. */
 695         uint32_t vpm_output_size;
 696
 697         /* Set if there should be separate VPM segments for input and output.
 698          * If unset, vpm_input_size will be 0.
 699          */
 700         bool separate_segments;
 701
 702         /* Value to be programmed in VCM_CACHE_SIZE. */
 703         uint8_t vcm_cache_size;
 704 };
 705
 706 struct v3d_fs_prog_data {
 707         struct v3d_prog_data base;
 708
 709         struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
 710
 711         /* Array of flat shade flags.
 712          *
 713          * Each entry is only 24 bits (high 8 bits 0), to match the hardware
 714          * packet layout.
 715          */
 716         uint32_t flat_shade_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
 717
 718         uint32_t noperspective_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
 719
 720         uint32_t centroid_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
 721
 722         bool writes_z;
 723         bool discard;
 724         bool uses_center_w;
 725 };
 726
 727 /* Special nir_load_input intrinsic index for loading the current TLB
 728  * destination color.
 729  */
 730 #define V3D_NIR_TLB_COLOR_READ_INPUT            2000000000
 731
 732 #define V3D_NIR_MS_MASK_OUTPUT                  2000000000
 733
 734 extern const nir_shader_compiler_options v3d_nir_options;
 735
 736 const struct v3d_compiler *v3d_compiler_init(const struct v3d_device_info *devinfo);
 737 void v3d_compiler_free(const struct v3d_compiler *compiler);
 738 void v3d_optimize_nir(struct nir_shader *s);
 739
 740 uint64_t *v3d_compile(const struct v3d_compiler *compiler,
 741                       struct v3d_key *key,
 742                       struct v3d_prog_data **prog_data,
 743                       nir_shader *s,
 744                       void (*debug_output)(const char *msg,
 745                                            void *debug_output_data),
 746                       void *debug_output_data,
 747                       int program_id, int variant_id,
 748                       uint32_t *final_assembly_size);
 749
 750 void v3d_nir_to_vir(struct v3d_compile *c);
 751
 752 void vir_compile_destroy(struct v3d_compile *c);
 753 const char *vir_get_stage_name(struct v3d_compile *c);
 754 struct qblock *vir_new_block(struct v3d_compile *c);
 755 void vir_set_emit_block(struct v3d_compile *c, struct qblock *block);
 756 void vir_link_blocks(struct qblock *predecessor, struct qblock *successor);
 757 struct qblock *vir_entry_block(struct v3d_compile *c);
 758 struct qblock *vir_exit_block(struct v3d_compile *c);
 759 struct qinst *vir_add_inst(enum v3d_qpu_add_op op, struct qreg dst,
 760                            struct qreg src0, struct qreg src1);
 761 struct qinst *vir_mul_inst(enum v3d_qpu_mul_op op, struct qreg dst,
 762                            struct qreg src0, struct qreg src1);
 763 struct qinst *vir_branch_inst(enum v3d_qpu_branch_cond cond, struct qreg src0);
 764 void vir_remove_instruction(struct v3d_compile *c, struct qinst *qinst);
 765 struct qreg vir_uniform(struct v3d_compile *c,
 766                         enum quniform_contents contents,
 767                         uint32_t data);
 768 void vir_schedule_instructions(struct v3d_compile *c);
 769 struct v3d_qpu_instr v3d_qpu_nop(void);
 770
 771 struct qreg vir_emit_def(struct v3d_compile *c, struct qinst *inst);
 772 struct qinst *vir_emit_nondef(struct v3d_compile *c, struct qinst *inst);
 773 void vir_set_cond(struct qinst *inst, enum v3d_qpu_cond cond);
 774 void vir_set_pf(struct qinst *inst, enum v3d_qpu_pf pf);
 775 void vir_set_uf(struct qinst *inst, enum v3d_qpu_uf uf);
 776 void vir_set_unpack(struct qinst *inst, int src,
 777                     enum v3d_qpu_input_unpack unpack);
 778
 779 struct qreg vir_get_temp(struct v3d_compile *c);
 780 void vir_emit_last_thrsw(struct v3d_compile *c);
 781 void vir_calculate_live_intervals(struct v3d_compile *c);
 782 bool vir_has_implicit_uniform(struct qinst *inst);
 783 int vir_get_implicit_uniform_src(struct qinst *inst);
 784 int vir_get_non_sideband_nsrc(struct qinst *inst);
 785 int vir_get_nsrc(struct qinst *inst);
 786 bool vir_has_side_effects(struct v3d_compile *c, struct qinst *inst);
 787 bool vir_get_add_op(struct qinst *inst, enum v3d_qpu_add_op *op);
 788 bool vir_get_mul_op(struct qinst *inst, enum v3d_qpu_mul_op *op);
 789 bool vir_is_raw_mov(struct qinst *inst);
 790 bool vir_is_tex(struct qinst *inst);
 791 bool vir_is_add(struct qinst *inst);
 792 bool vir_is_mul(struct qinst *inst);
 793 bool vir_is_float_input(struct qinst *inst);
 794 bool vir_writes_r3(const struct v3d_device_info *devinfo, struct qinst *inst);
 795 bool vir_writes_r4(const struct v3d_device_info *devinfo, struct qinst *inst);
 796 struct qreg vir_follow_movs(struct v3d_compile *c, struct qreg reg);
 797 uint8_t vir_channels_written(struct qinst *inst);
 798 struct qreg ntq_get_src(struct v3d_compile *c, nir_src src, int i);
 799 void ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
 800                     struct qreg result);
 801 void vir_emit_thrsw(struct v3d_compile *c);
 802
 803 void vir_dump(struct v3d_compile *c);
 804 void vir_dump_inst(struct v3d_compile *c, struct qinst *inst);
 805 void vir_dump_uniform(enum quniform_contents contents, uint32_t data);
 806
 807 void vir_validate(struct v3d_compile *c);
 808
 809 void vir_optimize(struct v3d_compile *c);
 810 bool vir_opt_algebraic(struct v3d_compile *c);
 811 bool vir_opt_constant_folding(struct v3d_compile *c);
 812 bool vir_opt_copy_propagate(struct v3d_compile *c);
 813 bool vir_opt_dead_code(struct v3d_compile *c);
 814 bool vir_opt_peephole_sf(struct v3d_compile *c);
 815 bool vir_opt_small_immediates(struct v3d_compile *c);
 816 bool vir_opt_vpm(struct v3d_compile *c);
 817 void v3d_nir_lower_blend(nir_shader *s, struct v3d_compile *c);
 818 void v3d_nir_lower_io(nir_shader *s, struct v3d_compile *c);
 819 void v3d_nir_lower_txf_ms(nir_shader *s, struct v3d_compile *c);
 820 void v3d_nir_lower_image_load_store(nir_shader *s);
 821 void vir_lower_uniforms(struct v3d_compile *c);
 822
 823 void v3d33_vir_vpm_read_setup(struct v3d_compile *c, int num_components);
 824 void v3d33_vir_vpm_write_setup(struct v3d_compile *c);
 825 void v3d33_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr);
 826 void v3d40_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr);
 827 void v3d40_vir_emit_image_load_store(struct v3d_compile *c,
 828                                      nir_intrinsic_instr *instr);
 829
 830 void v3d_vir_to_qpu(struct v3d_compile *c, struct qpu_reg *temp_registers);
 831 uint32_t v3d_qpu_schedule_instructions(struct v3d_compile *c);
 832 void qpu_validate(struct v3d_compile *c);
 833 struct qpu_reg *v3d_register_allocate(struct v3d_compile *c, bool *spilled);
 834 bool vir_init_reg_sets(struct v3d_compiler *compiler);
 835
 836 bool v3d_gl_format_is_return_32(GLenum format);
 837
 838 void vir_PF(struct v3d_compile *c, struct qreg src, enum v3d_qpu_pf pf);
 839
 840 static inline bool
 841 quniform_contents_is_texture_p0(enum quniform_contents contents)
 842 {
 843         return (contents >= QUNIFORM_TEXTURE_CONFIG_P0_0 &&
 844                 contents < (QUNIFORM_TEXTURE_CONFIG_P0_0 +
 845                             V3D_MAX_TEXTURE_SAMPLERS));
 846 }
 847
 848 static inline struct qreg
 849 vir_uniform_ui(struct v3d_compile *c, uint32_t ui)
 850 {
 851         return vir_uniform(c, QUNIFORM_CONSTANT, ui);
 852 }
 853
 854 static inline struct qreg
 855 vir_uniform_f(struct v3d_compile *c, float f)
 856 {
 857         return vir_uniform(c, QUNIFORM_CONSTANT, fui(f));
 858 }
 859
 860 #define VIR_ALU0(name, vir_inst, op)                                     \
 861 static inline struct qreg                                                \
 862 vir_##name(struct v3d_compile *c)                                        \
 863 {                                                                        \
 864         return vir_emit_def(c, vir_inst(op, c->undef,                    \
 865                                         c->undef, c->undef));            \
 866 }                                                                        \
 867 static inline struct qinst *                                             \
 868 vir_##name##_dest(struct v3d_compile *c, struct qreg dest)               \
 869 {                                                                        \
 870         return vir_emit_nondef(c, vir_inst(op, dest,                     \
 871                                            c->undef, c->undef));         \
 872 }
 873
 874 #define VIR_ALU1(name, vir_inst, op)                                     \
 875 static inline struct qreg                                                \
 876 vir_##name(struct v3d_compile *c, struct qreg a)                         \
 877 {                                                                        \
 878         return vir_emit_def(c, vir_inst(op, c->undef,                    \
 879                                         a, c->undef));                   \
 880 }                                                                        \
 881 static inline struct qinst *                                             \
 882 vir_##name##_dest(struct v3d_compile *c, struct qreg dest,               \
 883                   struct qreg a)                                         \
 884 {                                                                        \
 885         return vir_emit_nondef(c, vir_inst(op, dest, a,          \
 886                                            c->undef));                   \
 887 }
 888
 889 #define VIR_ALU2(name, vir_inst, op)                                       \
 890 static inline struct qreg                                                \
 891 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b)          \
 892 {                                                                        \
 893         return vir_emit_def(c, vir_inst(op, c->undef, a, b));    \
 894 }                                                                        \
 895 static inline struct qinst *                                             \
 896 vir_##name##_dest(struct v3d_compile *c, struct qreg dest,               \
 897                   struct qreg a, struct qreg b)                          \
 898 {                                                                        \
 899         return vir_emit_nondef(c, vir_inst(op, dest, a, b));     \
 900 }
 901
 902 #define VIR_NODST_0(name, vir_inst, op)                                 \
 903 static inline struct qinst *                                            \
 904 vir_##name(struct v3d_compile *c)                                       \
 905 {                                                                       \
 906         return vir_emit_nondef(c, vir_inst(op, c->undef,                \
 907                                            c->undef, c->undef));        \
 908 }
 909
 910 #define VIR_NODST_1(name, vir_inst, op)                                               \
 911 static inline struct qinst *                                            \
 912 vir_##name(struct v3d_compile *c, struct qreg a)                        \
 913 {                                                                       \
 914         return vir_emit_nondef(c, vir_inst(op, c->undef,        \
 915                                            a, c->undef));               \
 916 }
 917
 918 #define VIR_NODST_2(name, vir_inst, op)                                               \
 919 static inline struct qinst *                                            \
 920 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b)         \
 921 {                                                                       \
 922         return vir_emit_nondef(c, vir_inst(op, c->undef,                \
 923                                            a, b));                      \
 924 }
 925
 926 #define VIR_SFU(name)                                                      \
 927 static inline struct qreg                                                \
 928 vir_##name(struct v3d_compile *c, struct qreg a)                         \
 929 {                                                                        \
 930         if (c->devinfo->ver >= 41) {                                     \
 931                 return vir_emit_def(c, vir_add_inst(V3D_QPU_A_##name,    \
 932                                                     c->undef,            \
 933                                                     a, c->undef));       \
 934         } else {                                                         \
 935                 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_##name), a); \
 936                 return vir_FMOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4)); \
 937         }                                                                \
 938 }                                                                        \
 939 static inline struct qinst *                                             \
 940 vir_##name##_dest(struct v3d_compile *c, struct qreg dest,               \
 941                   struct qreg a)                                         \
 942 {                                                                        \
 943         if (c->devinfo->ver >= 41) {                                     \
 944                 return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_##name, \
 945                                                        dest,             \
 946                                                        a, c->undef));    \
 947         } else {                                                         \
 948                 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_##name), a); \
 949                 return vir_FMOV_dest(c, dest, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4)); \
 950         }                                                                \
 951 }
 952
 953 #define VIR_A_ALU2(name) VIR_ALU2(name, vir_add_inst, V3D_QPU_A_##name)
 954 #define VIR_M_ALU2(name) VIR_ALU2(name, vir_mul_inst, V3D_QPU_M_##name)
 955 #define VIR_A_ALU1(name) VIR_ALU1(name, vir_add_inst, V3D_QPU_A_##name)
 956 #define VIR_M_ALU1(name) VIR_ALU1(name, vir_mul_inst, V3D_QPU_M_##name)
 957 #define VIR_A_ALU0(name) VIR_ALU0(name, vir_add_inst, V3D_QPU_A_##name)
 958 #define VIR_M_ALU0(name) VIR_ALU0(name, vir_mul_inst, V3D_QPU_M_##name)
 959 #define VIR_A_NODST_2(name) VIR_NODST_2(name, vir_add_inst, V3D_QPU_A_##name)
 960 #define VIR_M_NODST_2(name) VIR_NODST_2(name, vir_mul_inst, V3D_QPU_M_##name)
 961 #define VIR_A_NODST_1(name) VIR_NODST_1(name, vir_add_inst, V3D_QPU_A_##name)
 962 #define VIR_M_NODST_1(name) VIR_NODST_1(name, vir_mul_inst, V3D_QPU_M_##name)
 963 #define VIR_A_NODST_0(name) VIR_NODST_0(name, vir_add_inst, V3D_QPU_A_##name)
 964
 965 VIR_A_ALU2(FADD)
 966 VIR_A_ALU2(VFPACK)
 967 VIR_A_ALU2(FSUB)
 968 VIR_A_ALU2(FMIN)
 969 VIR_A_ALU2(FMAX)
 970
 971 VIR_A_ALU2(ADD)
 972 VIR_A_ALU2(SUB)
 973 VIR_A_ALU2(SHL)
 974 VIR_A_ALU2(SHR)
 975 VIR_A_ALU2(ASR)
 976 VIR_A_ALU2(ROR)
 977 VIR_A_ALU2(MIN)
 978 VIR_A_ALU2(MAX)
 979 VIR_A_ALU2(UMIN)
 980 VIR_A_ALU2(UMAX)
 981 VIR_A_ALU2(AND)
 982 VIR_A_ALU2(OR)
 983 VIR_A_ALU2(XOR)
 984 VIR_A_ALU2(VADD)
 985 VIR_A_ALU2(VSUB)
 986 VIR_A_NODST_2(STVPMV)
 987 VIR_A_ALU1(NOT)
 988 VIR_A_ALU1(NEG)
 989 VIR_A_ALU1(FLAPUSH)
 990 VIR_A_ALU1(FLBPUSH)
 991 VIR_A_ALU1(FLPOP)
 992 VIR_A_ALU1(SETMSF)
 993 VIR_A_ALU1(SETREVF)
 994 VIR_A_ALU0(TIDX)
 995 VIR_A_ALU0(EIDX)
 996 VIR_A_ALU1(LDVPMV_IN)
 997 VIR_A_ALU1(LDVPMV_OUT)
 998 VIR_A_ALU0(TMUWT)
 999
1000 VIR_A_ALU0(FXCD)
1001 VIR_A_ALU0(XCD)
1002 VIR_A_ALU0(FYCD)
1003 VIR_A_ALU0(YCD)
1004 VIR_A_ALU0(MSF)
1005 VIR_A_ALU0(REVF)
1006 VIR_A_NODST_1(VPMSETUP)
1007 VIR_A_NODST_0(VPMWT)
1008 VIR_A_ALU2(FCMP)
1009 VIR_A_ALU2(VFMAX)
1010
1011 VIR_A_ALU1(FROUND)
1012 VIR_A_ALU1(FTOIN)
1013 VIR_A_ALU1(FTRUNC)
1014 VIR_A_ALU1(FTOIZ)
1015 VIR_A_ALU1(FFLOOR)
1016 VIR_A_ALU1(FTOUZ)
1017 VIR_A_ALU1(FCEIL)
1018 VIR_A_ALU1(FTOC)
1019
1020 VIR_A_ALU1(FDX)
1021 VIR_A_ALU1(FDY)
1022
1023 VIR_A_ALU1(ITOF)
1024 VIR_A_ALU1(CLZ)
1025 VIR_A_ALU1(UTOF)
1026
1027 VIR_M_ALU2(UMUL24)
1028 VIR_M_ALU2(FMUL)
1029 VIR_M_ALU2(SMUL24)
1030 VIR_M_NODST_2(MULTOP)
1031
1032 VIR_M_ALU1(MOV)
1033 VIR_M_ALU1(FMOV)
1034
1035 VIR_SFU(RECIP)
1036 VIR_SFU(RSQRT)
1037 VIR_SFU(EXP)
1038 VIR_SFU(LOG)
1039 VIR_SFU(SIN)
1040 VIR_SFU(RSQRT2)
1041
1042 static inline struct qinst *
1043 vir_MOV_cond(struct v3d_compile *c, enum v3d_qpu_cond cond,
1044              struct qreg dest, struct qreg src)
1045 {
1046         struct qinst *mov = vir_MOV_dest(c, dest, src);
1047         vir_set_cond(mov, cond);
1048         return mov;
1049 }
1050
1051 static inline struct qreg
1052 vir_SEL(struct v3d_compile *c, enum v3d_qpu_cond cond,
1053         struct qreg src0, struct qreg src1)
1054 {
1055         struct qreg t = vir_get_temp(c);
1056         vir_MOV_dest(c, t, src1);
1057         vir_MOV_cond(c, cond, t, src0);
1058         return t;
1059 }
1060
1061 static inline struct qinst *
1062 vir_NOP(struct v3d_compile *c)
1063 {
1064         return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_NOP,
1065                                                c->undef, c->undef, c->undef));
1066 }
1067
1068 static inline struct qreg
1069 vir_LDTMU(struct v3d_compile *c)
1070 {
1071         if (c->devinfo->ver >= 41) {
1072                 struct qinst *ldtmu = vir_add_inst(V3D_QPU_A_NOP, c->undef,
1073                                                    c->undef, c->undef);
1074                 ldtmu->qpu.sig.ldtmu = true;
1075
1076                 return vir_emit_def(c, ldtmu);
1077         } else {
1078                 vir_NOP(c)->qpu.sig.ldtmu = true;
1079                 return vir_MOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4));
1080         }
1081 }
1082
1083 static inline struct qreg
1084 vir_UMUL(struct v3d_compile *c, struct qreg src0, struct qreg src1)
1085 {
1086         vir_MULTOP(c, src0, src1);
1087         return vir_UMUL24(c, src0, src1);
1088 }
1089
1090 /*
1091 static inline struct qreg
1092 vir_LOAD_IMM(struct v3d_compile *c, uint32_t val)
1093 {
1094         return vir_emit_def(c, vir_inst(QOP_LOAD_IMM, c->undef,
1095                                         vir_reg(QFILE_LOAD_IMM, val), c->undef));
1096 }
1097
1098 static inline struct qreg
1099 vir_LOAD_IMM_U2(struct v3d_compile *c, uint32_t val)
1100 {
1101         return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_U2, c->undef,
1102                                         vir_reg(QFILE_LOAD_IMM, val),
1103                                         c->undef));
1104 }
1105 static inline struct qreg
1106 vir_LOAD_IMM_I2(struct v3d_compile *c, uint32_t val)
1107 {
1108         return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_I2, c->undef,
1109                                         vir_reg(QFILE_LOAD_IMM, val),
1110                                         c->undef));
1111 }
1112 */
1113
1114 static inline struct qinst *
1115 vir_BRANCH(struct v3d_compile *c, enum v3d_qpu_branch_cond cond)
1116 {
1117         /* The actual uniform_data value will be set at scheduling time */
1118         return vir_emit_nondef(c, vir_branch_inst(cond, vir_uniform_ui(c, 0)));
1119 }
1120
1121 #define vir_for_each_block(block, c)                                    \
1122         list_for_each_entry(struct qblock, block, &c->blocks, link)
1123
1124 #define vir_for_each_block_rev(block, c)                                \
1125         list_for_each_entry_rev(struct qblock, block, &c->blocks, link)
1126
1127 /* Loop over the non-NULL members of the successors array. */
1128 #define vir_for_each_successor(succ, block)                             \
1129         for (struct qblock *succ = block->successors[0];                \
1130              succ != NULL;                                              \
1131              succ = (succ == block->successors[1] ? NULL :              \
1132                      block->successors[1]))
1133
1134 #define vir_for_each_inst(inst, block)                                  \
1135         list_for_each_entry(struct qinst, inst, &block->instructions, link)
1136
1137 #define vir_for_each_inst_rev(inst, block)                                  \
1138         list_for_each_entry_rev(struct qinst, inst, &block->instructions, link)
1139
1140 #define vir_for_each_inst_safe(inst, block)                             \
1141         list_for_each_entry_safe(struct qinst, inst, &block->instructions, link)
1142
1143 #define vir_for_each_inst_inorder(inst, c)                              \
1144         vir_for_each_block(_block, c)                                   \
1145                 vir_for_each_inst(inst, _block)
1146
1147 #endif /* V3D_COMPILER_H */