src/broadcom/compiler/v3d_compiler.h

   1 /*
   2  * Copyright © 2016 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef V3D_COMPILER_H
  25 #define V3D_COMPILER_H
  26
  27 #include <assert.h>
  28 #include <stdio.h>
  29 #include <stdlib.h>
  30 #include <stdbool.h>
  31 #include <stdint.h>
  32 #include <string.h>
  33
  34 #include "util/macros.h"
  35 #include "common/v3d_debug.h"
  36 #include "compiler/nir/nir.h"
  37 #include "util/list.h"
  38 #include "util/u_math.h"
  39
  40 #include "qpu/qpu_instr.h"
  41 #include "pipe/p_state.h"
  42
  43 #define V3D_MAX_TEXTURE_SAMPLERS 32
  44 #define V3D_MAX_SAMPLES 4
  45 #define V3D_MAX_FS_INPUTS 64
  46 #define V3D_MAX_VS_INPUTS 64
  47
  48 struct nir_builder;
  49
  50 struct v3d_fs_inputs {
  51         /**
  52          * Array of the meanings of the VPM inputs this shader needs.
  53          *
  54          * It doesn't include those that aren't part of the VPM, like
  55          * point/line coordinates.
  56          */
  57         struct v3d_varying_slot *input_slots;
  58         uint32_t num_inputs;
  59 };
  60
  61 enum qfile {
  62         /** An unused source or destination register. */
  63         QFILE_NULL,
  64
  65         /** A physical register, such as the W coordinate payload. */
  66         QFILE_REG,
  67         /** One of the regsiters for fixed function interactions. */
  68         QFILE_MAGIC,
  69
  70         /**
  71          *  A virtual register, that will be allocated to actual accumulator
  72          * or physical registers later.
  73          */
  74         QFILE_TEMP,
  75         QFILE_VARY,
  76         QFILE_UNIF,
  77         QFILE_TLB,
  78         QFILE_TLBU,
  79
  80         /**
  81          * VPM reads use this with an index value to say what part of the VPM
  82          * is being read.
  83          */
  84         QFILE_VPM,
  85
  86         /**
  87          * Stores an immediate value in the index field that will be used
  88          * directly by qpu_load_imm().
  89          */
  90         QFILE_LOAD_IMM,
  91
  92         /**
  93          * Stores an immediate value in the index field that can be turned
  94          * into a small immediate field by qpu_encode_small_immediate().
  95          */
  96         QFILE_SMALL_IMM,
  97 };
  98
  99 /**
 100  * A reference to a QPU register or a virtual temp register.
 101  */
 102 struct qreg {
 103         enum qfile file;
 104         uint32_t index;
 105 };
 106
 107 static inline struct qreg vir_reg(enum qfile file, uint32_t index)
 108 {
 109         return (struct qreg){file, index};
 110 }
 111
 112 /**
 113  * A reference to an actual register at the QPU level, for register
 114  * allocation.
 115  */
 116 struct qpu_reg {
 117         bool magic;
 118         int index;
 119 };
 120
 121 struct qinst {
 122         /** Entry in qblock->instructions */
 123         struct list_head link;
 124
 125         /**
 126          * The instruction being wrapped.  Its condition codes, pack flags,
 127          * signals, etc. will all be used, with just the register references
 128          * being replaced by the contents of qinst->dst and qinst->src[].
 129          */
 130         struct v3d_qpu_instr qpu;
 131
 132         /* Pre-register-allocation references to src/dst registers */
 133         struct qreg dst;
 134         struct qreg src[3];
 135         bool cond_is_exec_mask;
 136         bool has_implicit_uniform;
 137         bool is_last_thrsw;
 138
 139         /* After vir_to_qpu.c: If instr reads a uniform, which uniform from
 140          * the uncompiled stream it is.
 141          */
 142         int uniform;
 143 };
 144
 145 enum quniform_contents {
 146         /**
 147          * Indicates that a constant 32-bit value is copied from the program's
 148          * uniform contents.
 149          */
 150         QUNIFORM_CONSTANT,
 151         /**
 152          * Indicates that the program's uniform contents are used as an index
 153          * into the GL uniform storage.
 154          */
 155         QUNIFORM_UNIFORM,
 156
 157         /** @{
 158          * Scaling factors from clip coordinates to relative to the viewport
 159          * center.
 160          *
 161          * This is used by the coordinate and vertex shaders to produce the
 162          * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
 163          * point offsets from the viewport ccenter.
 164          */
 165         QUNIFORM_VIEWPORT_X_SCALE,
 166         QUNIFORM_VIEWPORT_Y_SCALE,
 167         /** @} */
 168
 169         QUNIFORM_VIEWPORT_Z_OFFSET,
 170         QUNIFORM_VIEWPORT_Z_SCALE,
 171
 172         QUNIFORM_USER_CLIP_PLANE,
 173
 174         /**
 175          * A reference to a texture config parameter 0 uniform.
 176          *
 177          * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
 178          * defines texture type, miplevels, and such.  It will be found as a
 179          * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
 180          */
 181         QUNIFORM_TEXTURE_CONFIG_P0_0,
 182         QUNIFORM_TEXTURE_CONFIG_P0_1,
 183         QUNIFORM_TEXTURE_CONFIG_P0_2,
 184         QUNIFORM_TEXTURE_CONFIG_P0_3,
 185         QUNIFORM_TEXTURE_CONFIG_P0_4,
 186         QUNIFORM_TEXTURE_CONFIG_P0_5,
 187         QUNIFORM_TEXTURE_CONFIG_P0_6,
 188         QUNIFORM_TEXTURE_CONFIG_P0_7,
 189         QUNIFORM_TEXTURE_CONFIG_P0_8,
 190         QUNIFORM_TEXTURE_CONFIG_P0_9,
 191         QUNIFORM_TEXTURE_CONFIG_P0_10,
 192         QUNIFORM_TEXTURE_CONFIG_P0_11,
 193         QUNIFORM_TEXTURE_CONFIG_P0_12,
 194         QUNIFORM_TEXTURE_CONFIG_P0_13,
 195         QUNIFORM_TEXTURE_CONFIG_P0_14,
 196         QUNIFORM_TEXTURE_CONFIG_P0_15,
 197         QUNIFORM_TEXTURE_CONFIG_P0_16,
 198         QUNIFORM_TEXTURE_CONFIG_P0_17,
 199         QUNIFORM_TEXTURE_CONFIG_P0_18,
 200         QUNIFORM_TEXTURE_CONFIG_P0_19,
 201         QUNIFORM_TEXTURE_CONFIG_P0_20,
 202         QUNIFORM_TEXTURE_CONFIG_P0_21,
 203         QUNIFORM_TEXTURE_CONFIG_P0_22,
 204         QUNIFORM_TEXTURE_CONFIG_P0_23,
 205         QUNIFORM_TEXTURE_CONFIG_P0_24,
 206         QUNIFORM_TEXTURE_CONFIG_P0_25,
 207         QUNIFORM_TEXTURE_CONFIG_P0_26,
 208         QUNIFORM_TEXTURE_CONFIG_P0_27,
 209         QUNIFORM_TEXTURE_CONFIG_P0_28,
 210         QUNIFORM_TEXTURE_CONFIG_P0_29,
 211         QUNIFORM_TEXTURE_CONFIG_P0_30,
 212         QUNIFORM_TEXTURE_CONFIG_P0_31,
 213         QUNIFORM_TEXTURE_CONFIG_P0_32,
 214
 215         /**
 216          * A reference to a texture config parameter 1 uniform.
 217          *
 218          * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
 219          * has the pointer to the indirect texture state.  Our data[] field
 220          * will have a packed p1 value, but the address field will be just
 221          * which texture unit's texture should be referenced.
 222          */
 223         QUNIFORM_TEXTURE_CONFIG_P1,
 224
 225         QUNIFORM_TEXTURE_FIRST_LEVEL,
 226
 227         QUNIFORM_TEXTURE_WIDTH,
 228         QUNIFORM_TEXTURE_HEIGHT,
 229         QUNIFORM_TEXTURE_DEPTH,
 230         QUNIFORM_TEXTURE_ARRAY_SIZE,
 231         QUNIFORM_TEXTURE_LEVELS,
 232
 233         QUNIFORM_UBO_ADDR,
 234
 235         QUNIFORM_TEXRECT_SCALE_X,
 236         QUNIFORM_TEXRECT_SCALE_Y,
 237
 238         QUNIFORM_TEXTURE_BORDER_COLOR,
 239
 240         QUNIFORM_STENCIL,
 241
 242         QUNIFORM_ALPHA_REF,
 243         QUNIFORM_SAMPLE_MASK,
 244 };
 245
 246 struct v3d_varying_slot {
 247         uint8_t slot_and_component;
 248 };
 249
 250 static inline struct v3d_varying_slot
 251 v3d_slot_from_slot_and_component(uint8_t slot, uint8_t component)
 252 {
 253         assert(slot < 255 / 4);
 254         return (struct v3d_varying_slot){ (slot << 2) + component };
 255 }
 256
 257 static inline uint8_t v3d_slot_get_slot(struct v3d_varying_slot slot)
 258 {
 259         return slot.slot_and_component >> 2;
 260 }
 261
 262 static inline uint8_t v3d_slot_get_component(struct v3d_varying_slot slot)
 263 {
 264         return slot.slot_and_component & 3;
 265 }
 266
 267 struct v3d_ubo_range {
 268         /**
 269          * offset in bytes from the start of the ubo where this range is
 270          * uploaded.
 271          *
 272          * Only set once used is set.
 273          */
 274         uint32_t dst_offset;
 275
 276         /**
 277          * offset in bytes from the start of the gallium uniforms where the
 278          * data comes from.
 279          */
 280         uint32_t src_offset;
 281
 282         /** size in bytes of this ubo range */
 283         uint32_t size;
 284 };
 285
 286 struct v3d_key {
 287         void *shader_state;
 288         struct {
 289                 uint8_t swizzle[4];
 290                 uint8_t return_size;
 291                 uint8_t return_channels;
 292                 union {
 293                         struct {
 294                                 unsigned compare_mode:1;
 295                                 unsigned compare_func:3;
 296                                 bool clamp_s:1;
 297                                 bool clamp_t:1;
 298                                 bool clamp_r:1;
 299                         };
 300                         struct {
 301                                 uint16_t msaa_width, msaa_height;
 302                         };
 303                 };
 304         } tex[V3D_MAX_TEXTURE_SAMPLERS];
 305         uint8_t ucp_enables;
 306 };
 307
 308 struct v3d_fs_key {
 309         struct v3d_key base;
 310         bool depth_enabled;
 311         bool is_points;
 312         bool is_lines;
 313         bool alpha_test;
 314         bool point_coord_upper_left;
 315         bool light_twoside;
 316         bool msaa;
 317         bool sample_coverage;
 318         bool sample_alpha_to_coverage;
 319         bool sample_alpha_to_one;
 320         bool clamp_color;
 321         bool shade_model_flat;
 322         uint8_t nr_cbufs;
 323         uint8_t swap_color_rb;
 324         /* Mask of which render targets need to be written as 32-bit floats */
 325         uint8_t f32_color_rb;
 326         uint8_t alpha_test_func;
 327         uint8_t logicop_func;
 328         uint32_t point_sprite_mask;
 329
 330         struct pipe_rt_blend_state blend;
 331 };
 332
 333 struct v3d_vs_key {
 334         struct v3d_key base;
 335
 336         struct v3d_varying_slot fs_inputs[V3D_MAX_FS_INPUTS];
 337         uint8_t num_fs_inputs;
 338
 339         bool is_coord;
 340         bool per_vertex_point_size;
 341         bool clamp_color;
 342 };
 343
 344 /** A basic block of VIR intructions. */
 345 struct qblock {
 346         struct list_head link;
 347
 348         struct list_head instructions;
 349
 350         struct set *predecessors;
 351         struct qblock *successors[2];
 352
 353         int index;
 354
 355         /* Instruction IPs for the first and last instruction of the block.
 356          * Set by qpu_schedule.c.
 357          */
 358         uint32_t start_qpu_ip;
 359         uint32_t end_qpu_ip;
 360
 361         /* Instruction IP for the branch instruction of the block.  Set by
 362          * qpu_schedule.c.
 363          */
 364         uint32_t branch_qpu_ip;
 365
 366         /** Offset within the uniform stream at the start of the block. */
 367         uint32_t start_uniform;
 368         /** Offset within the uniform stream of the branch instruction */
 369         uint32_t branch_uniform;
 370
 371         /** @{ used by v3d_vir_live_variables.c */
 372         BITSET_WORD *def;
 373         BITSET_WORD *use;
 374         BITSET_WORD *live_in;
 375         BITSET_WORD *live_out;
 376         int start_ip, end_ip;
 377         /** @} */
 378 };
 379
 380 /**
 381  * Compiler state saved across compiler invocations, for any expensive global
 382  * setup.
 383  */
 384 struct v3d_compiler {
 385         const struct v3d_device_info *devinfo;
 386         struct ra_regs *regs;
 387         unsigned int reg_class_phys[3];
 388         unsigned int reg_class_phys_or_acc[3];
 389 };
 390
 391 struct v3d_compile {
 392         const struct v3d_device_info *devinfo;
 393         nir_shader *s;
 394         nir_function_impl *impl;
 395         struct exec_list *cf_node_list;
 396         const struct v3d_compiler *compiler;
 397
 398         /**
 399          * Mapping from nir_register * or nir_ssa_def * to array of struct
 400          * qreg for the values.
 401          */
 402         struct hash_table *def_ht;
 403
 404         /* For each temp, the instruction generating its value. */
 405         struct qinst **defs;
 406         uint32_t defs_array_size;
 407
 408         /**
 409          * Inputs to the shader, arranged by TGSI declaration order.
 410          *
 411          * Not all fragment shader QFILE_VARY reads are present in this array.
 412          */
 413         struct qreg *inputs;
 414         struct qreg *outputs;
 415         bool msaa_per_sample_output;
 416         struct qreg color_reads[V3D_MAX_SAMPLES];
 417         struct qreg sample_colors[V3D_MAX_SAMPLES];
 418         uint32_t inputs_array_size;
 419         uint32_t outputs_array_size;
 420         uint32_t uniforms_array_size;
 421
 422         /* Booleans for whether the corresponding QFILE_VARY[i] is
 423          * flat-shaded.  This includes gl_FragColor flat-shading, which is
 424          * customized based on the shademodel_flat shader key.
 425          */
 426         uint32_t flat_shade_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
 427
 428         struct v3d_ubo_range *ubo_ranges;
 429         bool *ubo_range_used;
 430         uint32_t ubo_ranges_array_size;
 431         /** Number of uniform areas tracked in ubo_ranges. */
 432         uint32_t num_ubo_ranges;
 433         uint32_t next_ubo_dst_offset;
 434
 435         /* State for whether we're executing on each channel currently.  0 if
 436          * yes, otherwise a block number + 1 that the channel jumped to.
 437          */
 438         struct qreg execute;
 439
 440         struct qreg line_x, point_x, point_y;
 441
 442         /**
 443          * Instance ID, which comes in before the vertex attribute payload if
 444          * the shader record requests it.
 445          */
 446         struct qreg iid;
 447
 448         /**
 449          * Vertex ID, which comes in before the vertex attribute payload
 450          * (after Instance ID) if the shader record requests it.
 451          */
 452         struct qreg vid;
 453
 454         /* Fragment shader payload regs. */
 455         struct qreg payload_w, payload_w_centroid, payload_z;
 456
 457         uint8_t vattr_sizes[V3D_MAX_VS_INPUTS];
 458         uint32_t num_vpm_writes;
 459
 460         /**
 461          * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
 462          *
 463          * This includes those that aren't part of the VPM varyings, like
 464          * point/line coordinates.
 465          */
 466         struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
 467
 468         /**
 469          * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
 470          * of the output is.  Used to emit from the VS in the order that the
 471          * FS needs.
 472          */
 473         struct v3d_varying_slot *output_slots;
 474
 475         struct pipe_shader_state *shader_state;
 476         struct v3d_key *key;
 477         struct v3d_fs_key *fs_key;
 478         struct v3d_vs_key *vs_key;
 479
 480         /* Live ranges of temps. */
 481         int *temp_start, *temp_end;
 482
 483         uint32_t *uniform_data;
 484         enum quniform_contents *uniform_contents;
 485         uint32_t uniform_array_size;
 486         uint32_t num_uniforms;
 487         uint32_t num_outputs;
 488         uint32_t output_position_index;
 489         nir_variable *output_color_var[4];
 490         uint32_t output_point_size_index;
 491         uint32_t output_sample_mask_index;
 492
 493         struct qreg undef;
 494         uint32_t num_temps;
 495
 496         struct list_head blocks;
 497         int next_block_index;
 498         struct qblock *cur_block;
 499         struct qblock *loop_cont_block;
 500         struct qblock *loop_break_block;
 501
 502         uint64_t *qpu_insts;
 503         uint32_t qpu_inst_count;
 504         uint32_t qpu_inst_size;
 505
 506         /* For the FS, the number of varying inputs not counting the
 507          * point/line varyings payload
 508          */
 509         uint32_t num_inputs;
 510
 511         /**
 512          * Number of inputs from num_inputs remaining to be queued to the read
 513          * FIFO in the VS/CS.
 514          */
 515         uint32_t num_inputs_remaining;
 516
 517         /* Number of inputs currently in the read FIFO for the VS/CS */
 518         uint32_t num_inputs_in_fifo;
 519
 520         /** Next offset in the VPM to read from in the VS/CS */
 521         uint32_t vpm_read_offset;
 522
 523         uint32_t program_id;
 524         uint32_t variant_id;
 525
 526         /* Set to compile program in in 1x, 2x, or 4x threaded mode, where
 527          * SIG_THREAD_SWITCH is used to hide texturing latency at the cost of
 528          * limiting ourselves to the part of the physical reg space.
 529          *
 530          * On V3D 3.x, 2x or 4x divide the physical reg space by 2x or 4x.  On
 531          * V3D 4.x, all shaders are 2x threaded, and 4x only divides the
 532          * physical reg space in half.
 533          */
 534         uint8_t threads;
 535         struct qinst *last_thrsw;
 536         bool last_thrsw_at_top_level;
 537
 538         bool failed;
 539 };
 540
 541 struct v3d_uniform_list {
 542         enum quniform_contents *contents;
 543         uint32_t *data;
 544         uint32_t count;
 545 };
 546
 547 struct v3d_prog_data {
 548         struct v3d_uniform_list uniforms;
 549
 550         struct v3d_ubo_range *ubo_ranges;
 551         uint32_t num_ubo_ranges;
 552         uint32_t ubo_size;
 553
 554         uint8_t num_inputs;
 555         uint8_t threads;
 556
 557         /* For threads > 1, whether the program should be dispatched in the
 558          * after-final-THRSW state.
 559          */
 560         bool single_seg;
 561 };
 562
 563 struct v3d_vs_prog_data {
 564         struct v3d_prog_data base;
 565
 566         bool uses_iid, uses_vid;
 567
 568         /* Number of components read from each vertex attribute. */
 569         uint8_t vattr_sizes[32];
 570
 571         /* Total number of components read, for the shader state record. */
 572         uint32_t vpm_input_size;
 573
 574         /* Total number of components written, for the shader state record. */
 575         uint32_t vpm_output_size;
 576 };
 577
 578 struct v3d_fs_prog_data {
 579         struct v3d_prog_data base;
 580
 581         struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
 582
 583         /* Array of flat shade flags.
 584          *
 585          * Each entry is only 24 bits (high 8 bits 0), to match the hardware
 586          * packet layout.
 587          */
 588         uint32_t flat_shade_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
 589
 590         bool writes_z;
 591         bool discard;
 592 };
 593
 594 /* Special nir_load_input intrinsic index for loading the current TLB
 595  * destination color.
 596  */
 597 #define V3D_NIR_TLB_COLOR_READ_INPUT            2000000000
 598
 599 #define V3D_NIR_MS_MASK_OUTPUT                  2000000000
 600
 601 extern const nir_shader_compiler_options v3d_nir_options;
 602
 603 const struct v3d_compiler *v3d_compiler_init(const struct v3d_device_info *devinfo);
 604 void v3d_compiler_free(const struct v3d_compiler *compiler);
 605 void v3d_optimize_nir(struct nir_shader *s);
 606
 607 uint64_t *v3d_compile_vs(const struct v3d_compiler *compiler,
 608                          struct v3d_vs_key *key,
 609                          struct v3d_vs_prog_data *prog_data,
 610                          nir_shader *s,
 611                          int program_id, int variant_id,
 612                          uint32_t *final_assembly_size);
 613
 614 uint64_t *v3d_compile_fs(const struct v3d_compiler *compiler,
 615                          struct v3d_fs_key *key,
 616                          struct v3d_fs_prog_data *prog_data,
 617                          nir_shader *s,
 618                          int program_id, int variant_id,
 619                          uint32_t *final_assembly_size);
 620
 621 void v3d_nir_to_vir(struct v3d_compile *c);
 622
 623 void vir_compile_destroy(struct v3d_compile *c);
 624 const char *vir_get_stage_name(struct v3d_compile *c);
 625 struct qblock *vir_new_block(struct v3d_compile *c);
 626 void vir_set_emit_block(struct v3d_compile *c, struct qblock *block);
 627 void vir_link_blocks(struct qblock *predecessor, struct qblock *successor);
 628 struct qblock *vir_entry_block(struct v3d_compile *c);
 629 struct qblock *vir_exit_block(struct v3d_compile *c);
 630 struct qinst *vir_add_inst(enum v3d_qpu_add_op op, struct qreg dst,
 631                            struct qreg src0, struct qreg src1);
 632 struct qinst *vir_mul_inst(enum v3d_qpu_mul_op op, struct qreg dst,
 633                            struct qreg src0, struct qreg src1);
 634 struct qinst *vir_branch_inst(enum v3d_qpu_branch_cond cond, struct qreg src0);
 635 void vir_remove_instruction(struct v3d_compile *c, struct qinst *qinst);
 636 struct qreg vir_uniform(struct v3d_compile *c,
 637                         enum quniform_contents contents,
 638                         uint32_t data);
 639 void vir_schedule_instructions(struct v3d_compile *c);
 640 struct v3d_qpu_instr v3d_qpu_nop(void);
 641
 642 struct qreg vir_emit_def(struct v3d_compile *c, struct qinst *inst);
 643 struct qinst *vir_emit_nondef(struct v3d_compile *c, struct qinst *inst);
 644 void vir_set_cond(struct qinst *inst, enum v3d_qpu_cond cond);
 645 void vir_set_pf(struct qinst *inst, enum v3d_qpu_pf pf);
 646 void vir_set_unpack(struct qinst *inst, int src,
 647                     enum v3d_qpu_input_unpack unpack);
 648
 649 struct qreg vir_get_temp(struct v3d_compile *c);
 650 void vir_calculate_live_intervals(struct v3d_compile *c);
 651 bool vir_has_implicit_uniform(struct qinst *inst);
 652 int vir_get_implicit_uniform_src(struct qinst *inst);
 653 int vir_get_non_sideband_nsrc(struct qinst *inst);
 654 int vir_get_nsrc(struct qinst *inst);
 655 bool vir_has_side_effects(struct v3d_compile *c, struct qinst *inst);
 656 bool vir_get_add_op(struct qinst *inst, enum v3d_qpu_add_op *op);
 657 bool vir_get_mul_op(struct qinst *inst, enum v3d_qpu_mul_op *op);
 658 bool vir_is_raw_mov(struct qinst *inst);
 659 bool vir_is_tex(struct qinst *inst);
 660 bool vir_is_add(struct qinst *inst);
 661 bool vir_is_mul(struct qinst *inst);
 662 bool vir_is_float_input(struct qinst *inst);
 663 bool vir_depends_on_flags(struct qinst *inst);
 664 bool vir_writes_r3(const struct v3d_device_info *devinfo, struct qinst *inst);
 665 bool vir_writes_r4(const struct v3d_device_info *devinfo, struct qinst *inst);
 666 struct qreg vir_follow_movs(struct v3d_compile *c, struct qreg reg);
 667 uint8_t vir_channels_written(struct qinst *inst);
 668
 669 void vir_dump(struct v3d_compile *c);
 670 void vir_dump_inst(struct v3d_compile *c, struct qinst *inst);
 671
 672 void vir_validate(struct v3d_compile *c);
 673
 674 void vir_optimize(struct v3d_compile *c);
 675 bool vir_opt_algebraic(struct v3d_compile *c);
 676 bool vir_opt_constant_folding(struct v3d_compile *c);
 677 bool vir_opt_copy_propagate(struct v3d_compile *c);
 678 bool vir_opt_dead_code(struct v3d_compile *c);
 679 bool vir_opt_peephole_sf(struct v3d_compile *c);
 680 bool vir_opt_small_immediates(struct v3d_compile *c);
 681 bool vir_opt_vpm(struct v3d_compile *c);
 682 void v3d_nir_lower_blend(nir_shader *s, struct v3d_compile *c);
 683 void v3d_nir_lower_io(nir_shader *s, struct v3d_compile *c);
 684 void v3d_nir_lower_txf_ms(nir_shader *s, struct v3d_compile *c);
 685 void vir_lower_uniforms(struct v3d_compile *c);
 686
 687 void v3d33_vir_vpm_read_setup(struct v3d_compile *c, int num_components);
 688 void v3d33_vir_vpm_write_setup(struct v3d_compile *c);
 689
 690 void v3d_vir_to_qpu(struct v3d_compile *c, struct qpu_reg *temp_registers);
 691 uint32_t v3d_qpu_schedule_instructions(struct v3d_compile *c);
 692 void qpu_validate(struct v3d_compile *c);
 693 struct qpu_reg *v3d_register_allocate(struct v3d_compile *c);
 694 bool vir_init_reg_sets(struct v3d_compiler *compiler);
 695
 696 void vir_PF(struct v3d_compile *c, struct qreg src, enum v3d_qpu_pf pf);
 697
 698 static inline bool
 699 quniform_contents_is_texture_p0(enum quniform_contents contents)
 700 {
 701         return (contents >= QUNIFORM_TEXTURE_CONFIG_P0_0 &&
 702                 contents < (QUNIFORM_TEXTURE_CONFIG_P0_0 +
 703                             V3D_MAX_TEXTURE_SAMPLERS));
 704 }
 705
 706 static inline struct qreg
 707 vir_uniform_ui(struct v3d_compile *c, uint32_t ui)
 708 {
 709         return vir_uniform(c, QUNIFORM_CONSTANT, ui);
 710 }
 711
 712 static inline struct qreg
 713 vir_uniform_f(struct v3d_compile *c, float f)
 714 {
 715         return vir_uniform(c, QUNIFORM_CONSTANT, fui(f));
 716 }
 717
 718 #define VIR_ALU0(name, vir_inst, op)                                     \
 719 static inline struct qreg                                                \
 720 vir_##name(struct v3d_compile *c)                                        \
 721 {                                                                        \
 722         return vir_emit_def(c, vir_inst(op, c->undef,                    \
 723                                         c->undef, c->undef));            \
 724 }                                                                        \
 725 static inline struct qinst *                                             \
 726 vir_##name##_dest(struct v3d_compile *c, struct qreg dest)               \
 727 {                                                                        \
 728         return vir_emit_nondef(c, vir_inst(op, dest,                     \
 729                                            c->undef, c->undef));         \
 730 }
 731
 732 #define VIR_ALU1(name, vir_inst, op)                                     \
 733 static inline struct qreg                                                \
 734 vir_##name(struct v3d_compile *c, struct qreg a)                         \
 735 {                                                                        \
 736         return vir_emit_def(c, vir_inst(op, c->undef,                    \
 737                                         a, c->undef));                   \
 738 }                                                                        \
 739 static inline struct qinst *                                             \
 740 vir_##name##_dest(struct v3d_compile *c, struct qreg dest,               \
 741                   struct qreg a)                                         \
 742 {                                                                        \
 743         return vir_emit_nondef(c, vir_inst(op, dest, a,          \
 744                                            c->undef));                   \
 745 }
 746
 747 #define VIR_ALU2(name, vir_inst, op)                                       \
 748 static inline struct qreg                                                \
 749 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b)          \
 750 {                                                                        \
 751         return vir_emit_def(c, vir_inst(op, c->undef, a, b));    \
 752 }                                                                        \
 753 static inline struct qinst *                                             \
 754 vir_##name##_dest(struct v3d_compile *c, struct qreg dest,               \
 755                   struct qreg a, struct qreg b)                          \
 756 {                                                                        \
 757         return vir_emit_nondef(c, vir_inst(op, dest, a, b));     \
 758 }
 759
 760 #define VIR_NODST_0(name, vir_inst, op)                                 \
 761 static inline struct qinst *                                            \
 762 vir_##name(struct v3d_compile *c)                                       \
 763 {                                                                       \
 764         return vir_emit_nondef(c, vir_inst(op, c->undef,                \
 765                                            c->undef, c->undef));        \
 766 }
 767
 768 #define VIR_NODST_1(name, vir_inst, op)                                               \
 769 static inline struct qinst *                                            \
 770 vir_##name(struct v3d_compile *c, struct qreg a)                        \
 771 {                                                                       \
 772         return vir_emit_nondef(c, vir_inst(op, c->undef,        \
 773                                            a, c->undef));               \
 774 }
 775
 776 #define VIR_NODST_2(name, vir_inst, op)                                               \
 777 static inline struct qinst *                                            \
 778 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b)         \
 779 {                                                                       \
 780         return vir_emit_nondef(c, vir_inst(op, c->undef,                \
 781                                            a, b));                      \
 782 }
 783
 784 #define VIR_A_ALU2(name) VIR_ALU2(name, vir_add_inst, V3D_QPU_A_##name)
 785 #define VIR_M_ALU2(name) VIR_ALU2(name, vir_mul_inst, V3D_QPU_M_##name)
 786 #define VIR_A_ALU1(name) VIR_ALU1(name, vir_add_inst, V3D_QPU_A_##name)
 787 #define VIR_M_ALU1(name) VIR_ALU1(name, vir_mul_inst, V3D_QPU_M_##name)
 788 #define VIR_A_ALU0(name) VIR_ALU0(name, vir_add_inst, V3D_QPU_A_##name)
 789 #define VIR_M_ALU0(name) VIR_ALU0(name, vir_mul_inst, V3D_QPU_M_##name)
 790 #define VIR_A_NODST_2(name) VIR_NODST_2(name, vir_add_inst, V3D_QPU_A_##name)
 791 #define VIR_M_NODST_2(name) VIR_NODST_2(name, vir_mul_inst, V3D_QPU_M_##name)
 792 #define VIR_A_NODST_1(name) VIR_NODST_1(name, vir_add_inst, V3D_QPU_A_##name)
 793 #define VIR_M_NODST_1(name) VIR_NODST_1(name, vir_mul_inst, V3D_QPU_M_##name)
 794 #define VIR_A_NODST_0(name) VIR_NODST_0(name, vir_add_inst, V3D_QPU_A_##name)
 795
 796 VIR_A_ALU2(FADD)
 797 VIR_A_ALU2(VFPACK)
 798 VIR_A_ALU2(FSUB)
 799 VIR_A_ALU2(FMIN)
 800 VIR_A_ALU2(FMAX)
 801
 802 VIR_A_ALU2(ADD)
 803 VIR_A_ALU2(SUB)
 804 VIR_A_ALU2(SHL)
 805 VIR_A_ALU2(SHR)
 806 VIR_A_ALU2(ASR)
 807 VIR_A_ALU2(ROR)
 808 VIR_A_ALU2(MIN)
 809 VIR_A_ALU2(MAX)
 810 VIR_A_ALU2(UMIN)
 811 VIR_A_ALU2(UMAX)
 812 VIR_A_ALU2(AND)
 813 VIR_A_ALU2(OR)
 814 VIR_A_ALU2(XOR)
 815 VIR_A_ALU2(VADD)
 816 VIR_A_ALU2(VSUB)
 817 VIR_A_ALU2(STVPMV)
 818 VIR_A_ALU1(NOT)
 819 VIR_A_ALU1(NEG)
 820 VIR_A_ALU1(FLAPUSH)
 821 VIR_A_ALU1(FLBPUSH)
 822 VIR_A_ALU1(FLBPOP)
 823 VIR_A_ALU1(SETMSF)
 824 VIR_A_ALU1(SETREVF)
 825 VIR_A_ALU1(TIDX)
 826 VIR_A_ALU1(EIDX)
 827 VIR_A_ALU1(LDVPMV_IN)
 828 VIR_A_ALU1(LDVPMV_OUT)
 829
 830 VIR_A_ALU0(FXCD)
 831 VIR_A_ALU0(XCD)
 832 VIR_A_ALU0(FYCD)
 833 VIR_A_ALU0(YCD)
 834 VIR_A_ALU0(MSF)
 835 VIR_A_ALU0(REVF)
 836 VIR_A_NODST_1(VPMSETUP)
 837 VIR_A_NODST_0(VPMWT)
 838 VIR_A_ALU2(FCMP)
 839 VIR_A_ALU2(VFMAX)
 840
 841 VIR_A_ALU1(FROUND)
 842 VIR_A_ALU1(FTOIN)
 843 VIR_A_ALU1(FTRUNC)
 844 VIR_A_ALU1(FTOIZ)
 845 VIR_A_ALU1(FFLOOR)
 846 VIR_A_ALU1(FTOUZ)
 847 VIR_A_ALU1(FCEIL)
 848 VIR_A_ALU1(FTOC)
 849
 850 VIR_A_ALU1(FDX)
 851 VIR_A_ALU1(FDY)
 852
 853 VIR_A_ALU1(ITOF)
 854 VIR_A_ALU1(CLZ)
 855 VIR_A_ALU1(UTOF)
 856
 857 VIR_M_ALU2(UMUL24)
 858 VIR_M_ALU2(FMUL)
 859 VIR_M_ALU2(SMUL24)
 860 VIR_M_NODST_2(MULTOP)
 861
 862 VIR_M_ALU1(MOV)
 863 VIR_M_ALU1(FMOV)
 864
 865 static inline struct qinst *
 866 vir_MOV_cond(struct v3d_compile *c, enum v3d_qpu_cond cond,
 867              struct qreg dest, struct qreg src)
 868 {
 869         struct qinst *mov = vir_MOV_dest(c, dest, src);
 870         vir_set_cond(mov, cond);
 871         return mov;
 872 }
 873
 874 static inline struct qreg
 875 vir_SEL(struct v3d_compile *c, enum v3d_qpu_cond cond,
 876         struct qreg src0, struct qreg src1)
 877 {
 878         struct qreg t = vir_get_temp(c);
 879         vir_MOV_dest(c, t, src1);
 880         vir_MOV_cond(c, cond, t, src0);
 881         return t;
 882 }
 883
 884 static inline struct qinst *
 885 vir_NOP(struct v3d_compile *c)
 886 {
 887         return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_NOP,
 888                                                c->undef, c->undef, c->undef));
 889 }
 890 /*
 891 static inline struct qreg
 892 vir_LOAD_IMM(struct v3d_compile *c, uint32_t val)
 893 {
 894         return vir_emit_def(c, vir_inst(QOP_LOAD_IMM, c->undef,
 895                                         vir_reg(QFILE_LOAD_IMM, val), c->undef));
 896 }
 897
 898 static inline struct qreg
 899 vir_LOAD_IMM_U2(struct v3d_compile *c, uint32_t val)
 900 {
 901         return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_U2, c->undef,
 902                                         vir_reg(QFILE_LOAD_IMM, val),
 903                                         c->undef));
 904 }
 905 static inline struct qreg
 906 vir_LOAD_IMM_I2(struct v3d_compile *c, uint32_t val)
 907 {
 908         return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_I2, c->undef,
 909                                         vir_reg(QFILE_LOAD_IMM, val),
 910                                         c->undef));
 911 }
 912 */
 913
 914 static inline struct qinst *
 915 vir_BRANCH(struct v3d_compile *c, enum v3d_qpu_cond cond)
 916 {
 917         /* The actual uniform_data value will be set at scheduling time */
 918         return vir_emit_nondef(c, vir_branch_inst(cond, vir_uniform_ui(c, 0)));
 919 }
 920
 921 #define vir_for_each_block(block, c)                                    \
 922         list_for_each_entry(struct qblock, block, &c->blocks, link)
 923
 924 #define vir_for_each_block_rev(block, c)                                \
 925         list_for_each_entry_rev(struct qblock, block, &c->blocks, link)
 926
 927 /* Loop over the non-NULL members of the successors array. */
 928 #define vir_for_each_successor(succ, block)                             \
 929         for (struct qblock *succ = block->successors[0];                \
 930              succ != NULL;                                              \
 931              succ = (succ == block->successors[1] ? NULL :              \
 932                      block->successors[1]))
 933
 934 #define vir_for_each_inst(inst, block)                                  \
 935         list_for_each_entry(struct qinst, inst, &block->instructions, link)
 936
 937 #define vir_for_each_inst_rev(inst, block)                                  \
 938         list_for_each_entry_rev(struct qinst, inst, &block->instructions, link)
 939
 940 #define vir_for_each_inst_safe(inst, block)                             \
 941         list_for_each_entry_safe(struct qinst, inst, &block->instructions, link)
 942
 943 #define vir_for_each_inst_inorder(inst, c)                              \
 944         vir_for_each_block(_block, c)                                   \
 945                 vir_for_each_inst(inst, _block)
 946
 947 #endif /* V3D_COMPILER_H */