2 * Copyright © 2016 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef V3D_COMPILER_H
25 #define V3D_COMPILER_H
34 #include "util/macros.h"
35 #include "common/v3d_debug.h"
36 #include "common/v3d_device_info.h"
37 #include "common/v3d_limits.h"
38 #include "compiler/nir/nir.h"
39 #include "util/list.h"
40 #include "util/u_math.h"
42 #include "qpu/qpu_instr.h"
43 #include "pipe/p_state.h"
47 struct v3d_fs_inputs
{
49 * Array of the meanings of the VPM inputs this shader needs.
51 * It doesn't include those that aren't part of the VPM, like
52 * point/line coordinates.
54 struct v3d_varying_slot
*input_slots
;
59 /** An unused source or destination register. */
62 /** A physical register, such as the W coordinate payload. */
64 /** One of the regsiters for fixed function interactions. */
68 * A virtual register, that will be allocated to actual accumulator
69 * or physical registers later.
77 * VPM reads use this with an index value to say what part of the VPM
83 * Stores an immediate value in the index field that will be used
84 * directly by qpu_load_imm().
89 * Stores an immediate value in the index field that can be turned
90 * into a small immediate field by qpu_encode_small_immediate().
96 * A reference to a QPU register or a virtual temp register.
103 static inline struct qreg
vir_reg(enum qfile file
, uint32_t index
)
105 return (struct qreg
){file
, index
};
109 * A reference to an actual register at the QPU level, for register
119 /** Entry in qblock->instructions */
120 struct list_head link
;
123 * The instruction being wrapped. Its condition codes, pack flags,
124 * signals, etc. will all be used, with just the register references
125 * being replaced by the contents of qinst->dst and qinst->src[].
127 struct v3d_qpu_instr qpu
;
129 /* Pre-register-allocation references to src/dst registers */
132 bool cond_is_exec_mask
;
133 bool has_implicit_uniform
;
136 /* After vir_to_qpu.c: If instr reads a uniform, which uniform from
137 * the uncompiled stream it is.
142 enum quniform_contents
{
144 * Indicates that a constant 32-bit value is copied from the program's
149 * Indicates that the program's uniform contents are used as an index
150 * into the GL uniform storage.
155 * Scaling factors from clip coordinates to relative to the viewport
158 * This is used by the coordinate and vertex shaders to produce the
159 * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
160 * point offsets from the viewport ccenter.
162 QUNIFORM_VIEWPORT_X_SCALE
,
163 QUNIFORM_VIEWPORT_Y_SCALE
,
166 QUNIFORM_VIEWPORT_Z_OFFSET
,
167 QUNIFORM_VIEWPORT_Z_SCALE
,
169 QUNIFORM_USER_CLIP_PLANE
,
172 * A reference to a V3D 3.x texture config parameter 0 uniform.
174 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
175 * defines texture type, miplevels, and such. It will be found as a
176 * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
178 QUNIFORM_TEXTURE_CONFIG_P0_0
,
179 QUNIFORM_TEXTURE_CONFIG_P0_1
,
180 QUNIFORM_TEXTURE_CONFIG_P0_2
,
181 QUNIFORM_TEXTURE_CONFIG_P0_3
,
182 QUNIFORM_TEXTURE_CONFIG_P0_4
,
183 QUNIFORM_TEXTURE_CONFIG_P0_5
,
184 QUNIFORM_TEXTURE_CONFIG_P0_6
,
185 QUNIFORM_TEXTURE_CONFIG_P0_7
,
186 QUNIFORM_TEXTURE_CONFIG_P0_8
,
187 QUNIFORM_TEXTURE_CONFIG_P0_9
,
188 QUNIFORM_TEXTURE_CONFIG_P0_10
,
189 QUNIFORM_TEXTURE_CONFIG_P0_11
,
190 QUNIFORM_TEXTURE_CONFIG_P0_12
,
191 QUNIFORM_TEXTURE_CONFIG_P0_13
,
192 QUNIFORM_TEXTURE_CONFIG_P0_14
,
193 QUNIFORM_TEXTURE_CONFIG_P0_15
,
194 QUNIFORM_TEXTURE_CONFIG_P0_16
,
195 QUNIFORM_TEXTURE_CONFIG_P0_17
,
196 QUNIFORM_TEXTURE_CONFIG_P0_18
,
197 QUNIFORM_TEXTURE_CONFIG_P0_19
,
198 QUNIFORM_TEXTURE_CONFIG_P0_20
,
199 QUNIFORM_TEXTURE_CONFIG_P0_21
,
200 QUNIFORM_TEXTURE_CONFIG_P0_22
,
201 QUNIFORM_TEXTURE_CONFIG_P0_23
,
202 QUNIFORM_TEXTURE_CONFIG_P0_24
,
203 QUNIFORM_TEXTURE_CONFIG_P0_25
,
204 QUNIFORM_TEXTURE_CONFIG_P0_26
,
205 QUNIFORM_TEXTURE_CONFIG_P0_27
,
206 QUNIFORM_TEXTURE_CONFIG_P0_28
,
207 QUNIFORM_TEXTURE_CONFIG_P0_29
,
208 QUNIFORM_TEXTURE_CONFIG_P0_30
,
209 QUNIFORM_TEXTURE_CONFIG_P0_31
,
210 QUNIFORM_TEXTURE_CONFIG_P0_32
,
213 * A reference to a V3D 3.x texture config parameter 1 uniform.
215 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
216 * has the pointer to the indirect texture state. Our data[] field
217 * will have a packed p1 value, but the address field will be just
218 * which texture unit's texture should be referenced.
220 QUNIFORM_TEXTURE_CONFIG_P1
,
222 /* A V3D 4.x texture config parameter. The high 8 bits will be
223 * which texture or sampler is being sampled, and the driver must
224 * replace the address field with the appropriate address.
226 QUNIFORM_TMU_CONFIG_P0
,
227 QUNIFORM_TMU_CONFIG_P1
,
229 QUNIFORM_IMAGE_TMU_CONFIG_P0
,
231 QUNIFORM_TEXTURE_FIRST_LEVEL
,
233 QUNIFORM_TEXTURE_WIDTH
,
234 QUNIFORM_TEXTURE_HEIGHT
,
235 QUNIFORM_TEXTURE_DEPTH
,
236 QUNIFORM_TEXTURE_ARRAY_SIZE
,
237 QUNIFORM_TEXTURE_LEVELS
,
241 QUNIFORM_TEXRECT_SCALE_X
,
242 QUNIFORM_TEXRECT_SCALE_Y
,
244 /* Returns the base offset of the SSBO given by the data value. */
245 QUNIFORM_SSBO_OFFSET
,
247 /* Returns the size of the SSBO given by the data value. */
248 QUNIFORM_GET_BUFFER_SIZE
,
250 /* Sizes (in pixels) of a shader image given by the data value. */
251 QUNIFORM_IMAGE_WIDTH
,
252 QUNIFORM_IMAGE_HEIGHT
,
253 QUNIFORM_IMAGE_DEPTH
,
254 QUNIFORM_IMAGE_ARRAY_SIZE
,
258 /* Number of workgroups passed to glDispatchCompute in the dimension
259 * selected by the data value.
261 QUNIFORM_NUM_WORK_GROUPS
,
264 * Returns the the offset of the scratch buffer for register spilling.
266 QUNIFORM_SPILL_OFFSET
,
267 QUNIFORM_SPILL_SIZE_PER_THREAD
,
270 * Returns the offset of the shared memory for compute shaders.
272 * This will be accessed using TMU general memory operations, so the
273 * L2T cache will effectively be the shared memory area.
275 QUNIFORM_SHARED_OFFSET
,
278 static inline uint32_t v3d_tmu_config_data_create(uint32_t unit
, uint32_t value
)
280 return unit
<< 24 | value
;
283 static inline uint32_t v3d_tmu_config_data_get_unit(uint32_t data
)
288 static inline uint32_t v3d_tmu_config_data_get_value(uint32_t data
)
290 return data
& 0xffffff;
293 struct v3d_varying_slot
{
294 uint8_t slot_and_component
;
297 static inline struct v3d_varying_slot
298 v3d_slot_from_slot_and_component(uint8_t slot
, uint8_t component
)
300 assert(slot
< 255 / 4);
301 return (struct v3d_varying_slot
){ (slot
<< 2) + component
};
304 static inline uint8_t v3d_slot_get_slot(struct v3d_varying_slot slot
)
306 return slot
.slot_and_component
>> 2;
309 static inline uint8_t v3d_slot_get_component(struct v3d_varying_slot slot
)
311 return slot
.slot_and_component
& 3;
314 struct v3d_ubo_range
{
316 * offset in bytes from the start of the ubo where this range is
319 * Only set once used is set.
324 * offset in bytes from the start of the gallium uniforms where the
329 /** size in bytes of this ubo range */
338 uint8_t return_channels
;
342 } tex
[V3D_MAX_TEXTURE_SAMPLERS
];
352 bool point_coord_upper_left
;
355 bool sample_coverage
;
356 bool sample_alpha_to_coverage
;
357 bool sample_alpha_to_one
;
359 bool shade_model_flat
;
360 /* Mask of which color render targets are present. */
362 uint8_t swap_color_rb
;
363 /* Mask of which render targets need to be written as 32-bit floats */
364 uint8_t f32_color_rb
;
365 /* Masks of which render targets need to be written as ints/uints.
366 * Used by gallium to work around lost information in TGSI.
368 uint8_t int_color_rb
;
369 uint8_t uint_color_rb
;
370 uint8_t alpha_test_func
;
371 uint8_t logicop_func
;
372 uint32_t point_sprite_mask
;
374 struct pipe_rt_blend_state blend
;
380 struct v3d_varying_slot fs_inputs
[V3D_MAX_FS_INPUTS
];
381 uint8_t num_fs_inputs
;
384 bool per_vertex_point_size
;
388 /** A basic block of VIR intructions. */
390 struct list_head link
;
392 struct list_head instructions
;
394 struct set
*predecessors
;
395 struct qblock
*successors
[2];
399 /* Instruction IPs for the first and last instruction of the block.
400 * Set by qpu_schedule.c.
402 uint32_t start_qpu_ip
;
405 /* Instruction IP for the branch instruction of the block. Set by
408 uint32_t branch_qpu_ip
;
410 /** Offset within the uniform stream at the start of the block. */
411 uint32_t start_uniform
;
412 /** Offset within the uniform stream of the branch instruction */
413 uint32_t branch_uniform
;
415 /** @{ used by v3d_vir_live_variables.c */
418 BITSET_WORD
*live_in
;
419 BITSET_WORD
*live_out
;
420 int start_ip
, end_ip
;
424 /** Which util/list.h add mode we should use when inserting an instruction. */
425 enum vir_cursor_mode
{
431 * Tracking structure for where new instructions should be inserted. Create
432 * with one of the vir_after_inst()-style helper functions.
434 * This does not protect against removal of the block or instruction, so we
435 * have an assert in instruction removal to try to catch it.
438 enum vir_cursor_mode mode
;
439 struct list_head
*link
;
442 static inline struct vir_cursor
443 vir_before_inst(struct qinst
*inst
)
445 return (struct vir_cursor
){ vir_cursor_addtail
, &inst
->link
};
448 static inline struct vir_cursor
449 vir_after_inst(struct qinst
*inst
)
451 return (struct vir_cursor
){ vir_cursor_add
, &inst
->link
};
454 static inline struct vir_cursor
455 vir_before_block(struct qblock
*block
)
457 return (struct vir_cursor
){ vir_cursor_add
, &block
->instructions
};
460 static inline struct vir_cursor
461 vir_after_block(struct qblock
*block
)
463 return (struct vir_cursor
){ vir_cursor_addtail
, &block
->instructions
};
467 * Compiler state saved across compiler invocations, for any expensive global
470 struct v3d_compiler
{
471 const struct v3d_device_info
*devinfo
;
472 struct ra_regs
*regs
;
473 unsigned int reg_class_phys
[3];
474 unsigned int reg_class_phys_or_acc
[3];
478 const struct v3d_device_info
*devinfo
;
480 nir_function_impl
*impl
;
481 struct exec_list
*cf_node_list
;
482 const struct v3d_compiler
*compiler
;
484 void (*debug_output
)(const char *msg
,
485 void *debug_output_data
);
486 void *debug_output_data
;
489 * Mapping from nir_register * or nir_ssa_def * to array of struct
490 * qreg for the values.
492 struct hash_table
*def_ht
;
494 /* For each temp, the instruction generating its value. */
496 uint32_t defs_array_size
;
499 * Inputs to the shader, arranged by TGSI declaration order.
501 * Not all fragment shader QFILE_VARY reads are present in this array.
504 struct qreg
*outputs
;
505 bool msaa_per_sample_output
;
506 struct qreg color_reads
[V3D_MAX_SAMPLES
];
507 struct qreg sample_colors
[V3D_MAX_SAMPLES
];
508 uint32_t inputs_array_size
;
509 uint32_t outputs_array_size
;
510 uint32_t uniforms_array_size
;
512 /* Booleans for whether the corresponding QFILE_VARY[i] is
513 * flat-shaded. This includes gl_FragColor flat-shading, which is
514 * customized based on the shademodel_flat shader key.
516 uint32_t flat_shade_flags
[BITSET_WORDS(V3D_MAX_FS_INPUTS
)];
518 uint32_t noperspective_flags
[BITSET_WORDS(V3D_MAX_FS_INPUTS
)];
520 uint32_t centroid_flags
[BITSET_WORDS(V3D_MAX_FS_INPUTS
)];
525 struct v3d_ubo_range
*ubo_ranges
;
526 bool *ubo_range_used
;
527 uint32_t ubo_ranges_array_size
;
528 /** Number of uniform areas tracked in ubo_ranges. */
529 uint32_t num_ubo_ranges
;
530 uint32_t next_ubo_dst_offset
;
532 /* State for whether we're executing on each channel currently. 0 if
533 * yes, otherwise a block number + 1 that the channel jumped to.
537 struct qreg line_x
, point_x
, point_y
;
540 * Instance ID, which comes in before the vertex attribute payload if
541 * the shader record requests it.
546 * Vertex ID, which comes in before the vertex attribute payload
547 * (after Instance ID) if the shader record requests it.
551 /* Fragment shader payload regs. */
552 struct qreg payload_w
, payload_w_centroid
, payload_z
;
554 struct qreg cs_payload
[2];
555 struct qreg cs_shared_offset
;
556 int local_invocation_index_bits
;
558 uint8_t vattr_sizes
[V3D_MAX_VS_INPUTS
/ 4];
559 uint32_t num_vpm_writes
;
561 /* Size in bytes of registers that have been spilled. This is how much
562 * space needs to be available in the spill BO per thread per QPU.
565 /* Shader-db stats */
566 uint32_t spills
, fills
, loops
;
568 * Register spilling's per-thread base address, shared between each
569 * spill/fill's addressing calculations.
571 struct qreg spill_base
;
572 /* Bit vector of which temps may be spilled */
573 BITSET_WORD
*spillable
;
576 * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
578 * This includes those that aren't part of the VPM varyings, like
579 * point/line coordinates.
581 struct v3d_varying_slot input_slots
[V3D_MAX_FS_INPUTS
];
584 * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
585 * of the output is. Used to emit from the VS in the order that the
588 struct v3d_varying_slot
*output_slots
;
590 struct pipe_shader_state
*shader_state
;
592 struct v3d_fs_key
*fs_key
;
593 struct v3d_vs_key
*vs_key
;
595 /* Live ranges of temps. */
596 int *temp_start
, *temp_end
;
597 bool live_intervals_valid
;
599 uint32_t *uniform_data
;
600 enum quniform_contents
*uniform_contents
;
601 uint32_t uniform_array_size
;
602 uint32_t num_uniforms
;
603 uint32_t num_outputs
;
604 uint32_t output_position_index
;
605 nir_variable
*output_color_var
[4];
606 uint32_t output_point_size_index
;
607 uint32_t output_sample_mask_index
;
612 struct vir_cursor cursor
;
613 struct list_head blocks
;
614 int next_block_index
;
615 struct qblock
*cur_block
;
616 struct qblock
*loop_cont_block
;
617 struct qblock
*loop_break_block
;
620 uint32_t qpu_inst_count
;
621 uint32_t qpu_inst_size
;
623 /* For the FS, the number of varying inputs not counting the
624 * point/line varyings payload
629 * Number of inputs from num_inputs remaining to be queued to the read
632 uint32_t num_inputs_remaining
;
634 /* Number of inputs currently in the read FIFO for the VS/CS */
635 uint32_t num_inputs_in_fifo
;
637 /** Next offset in the VPM to read from in the VS/CS */
638 uint32_t vpm_read_offset
;
643 /* Set to compile program in in 1x, 2x, or 4x threaded mode, where
644 * SIG_THREAD_SWITCH is used to hide texturing latency at the cost of
645 * limiting ourselves to the part of the physical reg space.
647 * On V3D 3.x, 2x or 4x divide the physical reg space by 2x or 4x. On
648 * V3D 4.x, all shaders are 2x threaded, and 4x only divides the
649 * physical reg space in half.
652 struct qinst
*last_thrsw
;
653 bool last_thrsw_at_top_level
;
658 struct v3d_uniform_list
{
659 enum quniform_contents
*contents
;
664 struct v3d_prog_data
{
665 struct v3d_uniform_list uniforms
;
667 struct v3d_ubo_range
*ubo_ranges
;
668 uint32_t num_ubo_ranges
;
675 /* For threads > 1, whether the program should be dispatched in the
676 * after-final-THRSW state.
681 struct v3d_vs_prog_data
{
682 struct v3d_prog_data base
;
684 bool uses_iid
, uses_vid
;
686 /* Number of components read from each vertex attribute. */
687 uint8_t vattr_sizes
[V3D_MAX_VS_INPUTS
/ 4];
689 /* Total number of components read, for the shader state record. */
690 uint32_t vpm_input_size
;
692 /* Total number of components written, for the shader state record. */
693 uint32_t vpm_output_size
;
695 /* Set if there should be separate VPM segments for input and output.
696 * If unset, vpm_input_size will be 0.
698 bool separate_segments
;
700 /* Value to be programmed in VCM_CACHE_SIZE. */
701 uint8_t vcm_cache_size
;
704 struct v3d_fs_prog_data
{
705 struct v3d_prog_data base
;
707 struct v3d_varying_slot input_slots
[V3D_MAX_FS_INPUTS
];
709 /* Array of flat shade flags.
711 * Each entry is only 24 bits (high 8 bits 0), to match the hardware
714 uint32_t flat_shade_flags
[((V3D_MAX_FS_INPUTS
- 1) / 24) + 1];
716 uint32_t noperspective_flags
[((V3D_MAX_FS_INPUTS
- 1) / 24) + 1];
718 uint32_t centroid_flags
[((V3D_MAX_FS_INPUTS
- 1) / 24) + 1];
725 /* Special nir_load_input intrinsic index for loading the current TLB
728 #define V3D_NIR_TLB_COLOR_READ_INPUT 2000000000
730 #define V3D_NIR_MS_MASK_OUTPUT 2000000000
732 extern const nir_shader_compiler_options v3d_nir_options
;
734 const struct v3d_compiler
*v3d_compiler_init(const struct v3d_device_info
*devinfo
);
735 void v3d_compiler_free(const struct v3d_compiler
*compiler
);
736 void v3d_optimize_nir(struct nir_shader
*s
);
738 uint64_t *v3d_compile(const struct v3d_compiler
*compiler
,
740 struct v3d_prog_data
**prog_data
,
742 void (*debug_output
)(const char *msg
,
743 void *debug_output_data
),
744 void *debug_output_data
,
745 int program_id
, int variant_id
,
746 uint32_t *final_assembly_size
);
748 void v3d_nir_to_vir(struct v3d_compile
*c
);
750 void vir_compile_destroy(struct v3d_compile
*c
);
751 const char *vir_get_stage_name(struct v3d_compile
*c
);
752 struct qblock
*vir_new_block(struct v3d_compile
*c
);
753 void vir_set_emit_block(struct v3d_compile
*c
, struct qblock
*block
);
754 void vir_link_blocks(struct qblock
*predecessor
, struct qblock
*successor
);
755 struct qblock
*vir_entry_block(struct v3d_compile
*c
);
756 struct qblock
*vir_exit_block(struct v3d_compile
*c
);
757 struct qinst
*vir_add_inst(enum v3d_qpu_add_op op
, struct qreg dst
,
758 struct qreg src0
, struct qreg src1
);
759 struct qinst
*vir_mul_inst(enum v3d_qpu_mul_op op
, struct qreg dst
,
760 struct qreg src0
, struct qreg src1
);
761 struct qinst
*vir_branch_inst(enum v3d_qpu_branch_cond cond
, struct qreg src0
);
762 void vir_remove_instruction(struct v3d_compile
*c
, struct qinst
*qinst
);
763 struct qreg
vir_uniform(struct v3d_compile
*c
,
764 enum quniform_contents contents
,
766 void vir_schedule_instructions(struct v3d_compile
*c
);
767 struct v3d_qpu_instr
v3d_qpu_nop(void);
769 struct qreg
vir_emit_def(struct v3d_compile
*c
, struct qinst
*inst
);
770 struct qinst
*vir_emit_nondef(struct v3d_compile
*c
, struct qinst
*inst
);
771 void vir_set_cond(struct qinst
*inst
, enum v3d_qpu_cond cond
);
772 void vir_set_pf(struct qinst
*inst
, enum v3d_qpu_pf pf
);
773 void vir_set_uf(struct qinst
*inst
, enum v3d_qpu_uf uf
);
774 void vir_set_unpack(struct qinst
*inst
, int src
,
775 enum v3d_qpu_input_unpack unpack
);
777 struct qreg
vir_get_temp(struct v3d_compile
*c
);
778 void vir_emit_last_thrsw(struct v3d_compile
*c
);
779 void vir_calculate_live_intervals(struct v3d_compile
*c
);
780 bool vir_has_implicit_uniform(struct qinst
*inst
);
781 int vir_get_implicit_uniform_src(struct qinst
*inst
);
782 int vir_get_non_sideband_nsrc(struct qinst
*inst
);
783 int vir_get_nsrc(struct qinst
*inst
);
784 bool vir_has_side_effects(struct v3d_compile
*c
, struct qinst
*inst
);
785 bool vir_get_add_op(struct qinst
*inst
, enum v3d_qpu_add_op
*op
);
786 bool vir_get_mul_op(struct qinst
*inst
, enum v3d_qpu_mul_op
*op
);
787 bool vir_is_raw_mov(struct qinst
*inst
);
788 bool vir_is_tex(struct qinst
*inst
);
789 bool vir_is_add(struct qinst
*inst
);
790 bool vir_is_mul(struct qinst
*inst
);
791 bool vir_writes_r3(const struct v3d_device_info
*devinfo
, struct qinst
*inst
);
792 bool vir_writes_r4(const struct v3d_device_info
*devinfo
, struct qinst
*inst
);
793 struct qreg
vir_follow_movs(struct v3d_compile
*c
, struct qreg reg
);
794 uint8_t vir_channels_written(struct qinst
*inst
);
795 struct qreg
ntq_get_src(struct v3d_compile
*c
, nir_src src
, int i
);
796 void ntq_store_dest(struct v3d_compile
*c
, nir_dest
*dest
, int chan
,
798 void vir_emit_thrsw(struct v3d_compile
*c
);
800 void vir_dump(struct v3d_compile
*c
);
801 void vir_dump_inst(struct v3d_compile
*c
, struct qinst
*inst
);
802 void vir_dump_uniform(enum quniform_contents contents
, uint32_t data
);
804 void vir_validate(struct v3d_compile
*c
);
806 void vir_optimize(struct v3d_compile
*c
);
807 bool vir_opt_algebraic(struct v3d_compile
*c
);
808 bool vir_opt_constant_folding(struct v3d_compile
*c
);
809 bool vir_opt_copy_propagate(struct v3d_compile
*c
);
810 bool vir_opt_dead_code(struct v3d_compile
*c
);
811 bool vir_opt_peephole_sf(struct v3d_compile
*c
);
812 bool vir_opt_small_immediates(struct v3d_compile
*c
);
813 bool vir_opt_vpm(struct v3d_compile
*c
);
814 void v3d_nir_lower_blend(nir_shader
*s
, struct v3d_compile
*c
);
815 void v3d_nir_lower_io(nir_shader
*s
, struct v3d_compile
*c
);
816 void v3d_nir_lower_txf_ms(nir_shader
*s
, struct v3d_compile
*c
);
817 void v3d_nir_lower_image_load_store(nir_shader
*s
);
818 void vir_lower_uniforms(struct v3d_compile
*c
);
820 void v3d33_vir_vpm_read_setup(struct v3d_compile
*c
, int num_components
);
821 void v3d33_vir_vpm_write_setup(struct v3d_compile
*c
);
822 void v3d33_vir_emit_tex(struct v3d_compile
*c
, nir_tex_instr
*instr
);
823 void v3d40_vir_emit_tex(struct v3d_compile
*c
, nir_tex_instr
*instr
);
824 void v3d40_vir_emit_image_load_store(struct v3d_compile
*c
,
825 nir_intrinsic_instr
*instr
);
827 void v3d_vir_to_qpu(struct v3d_compile
*c
, struct qpu_reg
*temp_registers
);
828 uint32_t v3d_qpu_schedule_instructions(struct v3d_compile
*c
);
829 void qpu_validate(struct v3d_compile
*c
);
830 struct qpu_reg
*v3d_register_allocate(struct v3d_compile
*c
, bool *spilled
);
831 bool vir_init_reg_sets(struct v3d_compiler
*compiler
);
833 bool v3d_gl_format_is_return_32(GLenum format
);
835 void vir_PF(struct v3d_compile
*c
, struct qreg src
, enum v3d_qpu_pf pf
);
838 quniform_contents_is_texture_p0(enum quniform_contents contents
)
840 return (contents
>= QUNIFORM_TEXTURE_CONFIG_P0_0
&&
841 contents
< (QUNIFORM_TEXTURE_CONFIG_P0_0
+
842 V3D_MAX_TEXTURE_SAMPLERS
));
845 static inline struct qreg
846 vir_uniform_ui(struct v3d_compile
*c
, uint32_t ui
)
848 return vir_uniform(c
, QUNIFORM_CONSTANT
, ui
);
851 static inline struct qreg
852 vir_uniform_f(struct v3d_compile
*c
, float f
)
854 return vir_uniform(c
, QUNIFORM_CONSTANT
, fui(f
));
857 #define VIR_ALU0(name, vir_inst, op) \
858 static inline struct qreg \
859 vir_##name(struct v3d_compile *c) \
861 return vir_emit_def(c, vir_inst(op, c->undef, \
862 c->undef, c->undef)); \
864 static inline struct qinst * \
865 vir_##name##_dest(struct v3d_compile *c, struct qreg dest) \
867 return vir_emit_nondef(c, vir_inst(op, dest, \
868 c->undef, c->undef)); \
871 #define VIR_ALU1(name, vir_inst, op) \
872 static inline struct qreg \
873 vir_##name(struct v3d_compile *c, struct qreg a) \
875 return vir_emit_def(c, vir_inst(op, c->undef, \
878 static inline struct qinst * \
879 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
882 return vir_emit_nondef(c, vir_inst(op, dest, a, \
886 #define VIR_ALU2(name, vir_inst, op) \
887 static inline struct qreg \
888 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b) \
890 return vir_emit_def(c, vir_inst(op, c->undef, a, b)); \
892 static inline struct qinst * \
893 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
894 struct qreg a, struct qreg b) \
896 return vir_emit_nondef(c, vir_inst(op, dest, a, b)); \
899 #define VIR_NODST_0(name, vir_inst, op) \
900 static inline struct qinst * \
901 vir_##name(struct v3d_compile *c) \
903 return vir_emit_nondef(c, vir_inst(op, c->undef, \
904 c->undef, c->undef)); \
907 #define VIR_NODST_1(name, vir_inst, op) \
908 static inline struct qinst * \
909 vir_##name(struct v3d_compile *c, struct qreg a) \
911 return vir_emit_nondef(c, vir_inst(op, c->undef, \
915 #define VIR_NODST_2(name, vir_inst, op) \
916 static inline struct qinst * \
917 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b) \
919 return vir_emit_nondef(c, vir_inst(op, c->undef, \
923 #define VIR_SFU(name) \
924 static inline struct qreg \
925 vir_##name(struct v3d_compile *c, struct qreg a) \
927 if (c->devinfo->ver >= 41) { \
928 return vir_emit_def(c, vir_add_inst(V3D_QPU_A_##name, \
932 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_##name), a); \
933 return vir_FMOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4)); \
936 static inline struct qinst * \
937 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
940 if (c->devinfo->ver >= 41) { \
941 return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_##name, \
945 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_##name), a); \
946 return vir_FMOV_dest(c, dest, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4)); \
950 #define VIR_A_ALU2(name) VIR_ALU2(name, vir_add_inst, V3D_QPU_A_##name)
951 #define VIR_M_ALU2(name) VIR_ALU2(name, vir_mul_inst, V3D_QPU_M_##name)
952 #define VIR_A_ALU1(name) VIR_ALU1(name, vir_add_inst, V3D_QPU_A_##name)
953 #define VIR_M_ALU1(name) VIR_ALU1(name, vir_mul_inst, V3D_QPU_M_##name)
954 #define VIR_A_ALU0(name) VIR_ALU0(name, vir_add_inst, V3D_QPU_A_##name)
955 #define VIR_M_ALU0(name) VIR_ALU0(name, vir_mul_inst, V3D_QPU_M_##name)
956 #define VIR_A_NODST_2(name) VIR_NODST_2(name, vir_add_inst, V3D_QPU_A_##name)
957 #define VIR_M_NODST_2(name) VIR_NODST_2(name, vir_mul_inst, V3D_QPU_M_##name)
958 #define VIR_A_NODST_1(name) VIR_NODST_1(name, vir_add_inst, V3D_QPU_A_##name)
959 #define VIR_M_NODST_1(name) VIR_NODST_1(name, vir_mul_inst, V3D_QPU_M_##name)
960 #define VIR_A_NODST_0(name) VIR_NODST_0(name, vir_add_inst, V3D_QPU_A_##name)
983 VIR_A_NODST_2(STVPMV
)
993 VIR_A_ALU1(LDVPMV_IN
)
994 VIR_A_ALU1(LDVPMV_OUT
)
1003 VIR_A_ALU0(BARRIERID
)
1004 VIR_A_NODST_1(VPMSETUP
)
1005 VIR_A_NODST_0(VPMWT
)
1028 VIR_M_NODST_2(MULTOP
)
1040 static inline struct qinst
*
1041 vir_MOV_cond(struct v3d_compile
*c
, enum v3d_qpu_cond cond
,
1042 struct qreg dest
, struct qreg src
)
1044 struct qinst
*mov
= vir_MOV_dest(c
, dest
, src
);
1045 vir_set_cond(mov
, cond
);
1049 static inline struct qreg
1050 vir_SEL(struct v3d_compile
*c
, enum v3d_qpu_cond cond
,
1051 struct qreg src0
, struct qreg src1
)
1053 struct qreg t
= vir_get_temp(c
);
1054 vir_MOV_dest(c
, t
, src1
);
1055 vir_MOV_cond(c
, cond
, t
, src0
);
1059 static inline struct qinst
*
1060 vir_NOP(struct v3d_compile
*c
)
1062 return vir_emit_nondef(c
, vir_add_inst(V3D_QPU_A_NOP
,
1063 c
->undef
, c
->undef
, c
->undef
));
1066 static inline struct qreg
1067 vir_LDTMU(struct v3d_compile
*c
)
1069 if (c
->devinfo
->ver
>= 41) {
1070 struct qinst
*ldtmu
= vir_add_inst(V3D_QPU_A_NOP
, c
->undef
,
1071 c
->undef
, c
->undef
);
1072 ldtmu
->qpu
.sig
.ldtmu
= true;
1074 return vir_emit_def(c
, ldtmu
);
1076 vir_NOP(c
)->qpu
.sig
.ldtmu
= true;
1077 return vir_MOV(c
, vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_R4
));
1081 static inline struct qreg
1082 vir_UMUL(struct v3d_compile
*c
, struct qreg src0
, struct qreg src1
)
1084 vir_MULTOP(c
, src0
, src1
);
1085 return vir_UMUL24(c
, src0
, src1
);
1089 static inline struct qreg
1090 vir_LOAD_IMM(struct v3d_compile *c, uint32_t val)
1092 return vir_emit_def(c, vir_inst(QOP_LOAD_IMM, c->undef,
1093 vir_reg(QFILE_LOAD_IMM, val), c->undef));
1096 static inline struct qreg
1097 vir_LOAD_IMM_U2(struct v3d_compile *c, uint32_t val)
1099 return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_U2, c->undef,
1100 vir_reg(QFILE_LOAD_IMM, val),
1103 static inline struct qreg
1104 vir_LOAD_IMM_I2(struct v3d_compile *c, uint32_t val)
1106 return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_I2, c->undef,
1107 vir_reg(QFILE_LOAD_IMM, val),
1112 static inline struct qinst
*
1113 vir_BRANCH(struct v3d_compile
*c
, enum v3d_qpu_branch_cond cond
)
1115 /* The actual uniform_data value will be set at scheduling time */
1116 return vir_emit_nondef(c
, vir_branch_inst(cond
, vir_uniform_ui(c
, 0)));
1119 #define vir_for_each_block(block, c) \
1120 list_for_each_entry(struct qblock, block, &c->blocks, link)
1122 #define vir_for_each_block_rev(block, c) \
1123 list_for_each_entry_rev(struct qblock, block, &c->blocks, link)
1125 /* Loop over the non-NULL members of the successors array. */
1126 #define vir_for_each_successor(succ, block) \
1127 for (struct qblock *succ = block->successors[0]; \
1129 succ = (succ == block->successors[1] ? NULL : \
1130 block->successors[1]))
1132 #define vir_for_each_inst(inst, block) \
1133 list_for_each_entry(struct qinst, inst, &block->instructions, link)
1135 #define vir_for_each_inst_rev(inst, block) \
1136 list_for_each_entry_rev(struct qinst, inst, &block->instructions, link)
1138 #define vir_for_each_inst_safe(inst, block) \
1139 list_for_each_entry_safe(struct qinst, inst, &block->instructions, link)
1141 #define vir_for_each_inst_inorder(inst, c) \
1142 vir_for_each_block(_block, c) \
1143 vir_for_each_inst(inst, _block)
1145 #endif /* V3D_COMPILER_H */