2 * Copyright © 2016 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef V3D_COMPILER_H
25 #define V3D_COMPILER_H
34 #include "util/macros.h"
35 #include "common/v3d_debug.h"
36 #include "common/v3d_device_info.h"
37 #include "compiler/nir/nir.h"
38 #include "util/list.h"
39 #include "util/u_math.h"
41 #include "qpu/qpu_instr.h"
42 #include "pipe/p_state.h"
44 #define V3D_MAX_TEXTURE_SAMPLERS 32
45 #define V3D_MAX_SAMPLES 4
46 #define V3D_MAX_FS_INPUTS 64
47 #define V3D_MAX_VS_INPUTS 64
51 struct v3d_fs_inputs
{
53 * Array of the meanings of the VPM inputs this shader needs.
55 * It doesn't include those that aren't part of the VPM, like
56 * point/line coordinates.
58 struct v3d_varying_slot
*input_slots
;
63 /** An unused source or destination register. */
66 /** A physical register, such as the W coordinate payload. */
68 /** One of the regsiters for fixed function interactions. */
72 * A virtual register, that will be allocated to actual accumulator
73 * or physical registers later.
81 * VPM reads use this with an index value to say what part of the VPM
87 * Stores an immediate value in the index field that will be used
88 * directly by qpu_load_imm().
93 * Stores an immediate value in the index field that can be turned
94 * into a small immediate field by qpu_encode_small_immediate().
100 * A reference to a QPU register or a virtual temp register.
107 static inline struct qreg
vir_reg(enum qfile file
, uint32_t index
)
109 return (struct qreg
){file
, index
};
113 * A reference to an actual register at the QPU level, for register
123 /** Entry in qblock->instructions */
124 struct list_head link
;
127 * The instruction being wrapped. Its condition codes, pack flags,
128 * signals, etc. will all be used, with just the register references
129 * being replaced by the contents of qinst->dst and qinst->src[].
131 struct v3d_qpu_instr qpu
;
133 /* Pre-register-allocation references to src/dst registers */
136 bool cond_is_exec_mask
;
137 bool has_implicit_uniform
;
140 /* After vir_to_qpu.c: If instr reads a uniform, which uniform from
141 * the uncompiled stream it is.
146 enum quniform_contents
{
148 * Indicates that a constant 32-bit value is copied from the program's
153 * Indicates that the program's uniform contents are used as an index
154 * into the GL uniform storage.
159 * Scaling factors from clip coordinates to relative to the viewport
162 * This is used by the coordinate and vertex shaders to produce the
163 * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
164 * point offsets from the viewport ccenter.
166 QUNIFORM_VIEWPORT_X_SCALE
,
167 QUNIFORM_VIEWPORT_Y_SCALE
,
170 QUNIFORM_VIEWPORT_Z_OFFSET
,
171 QUNIFORM_VIEWPORT_Z_SCALE
,
173 QUNIFORM_USER_CLIP_PLANE
,
176 * A reference to a V3D 3.x texture config parameter 0 uniform.
178 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
179 * defines texture type, miplevels, and such. It will be found as a
180 * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
182 QUNIFORM_TEXTURE_CONFIG_P0_0
,
183 QUNIFORM_TEXTURE_CONFIG_P0_1
,
184 QUNIFORM_TEXTURE_CONFIG_P0_2
,
185 QUNIFORM_TEXTURE_CONFIG_P0_3
,
186 QUNIFORM_TEXTURE_CONFIG_P0_4
,
187 QUNIFORM_TEXTURE_CONFIG_P0_5
,
188 QUNIFORM_TEXTURE_CONFIG_P0_6
,
189 QUNIFORM_TEXTURE_CONFIG_P0_7
,
190 QUNIFORM_TEXTURE_CONFIG_P0_8
,
191 QUNIFORM_TEXTURE_CONFIG_P0_9
,
192 QUNIFORM_TEXTURE_CONFIG_P0_10
,
193 QUNIFORM_TEXTURE_CONFIG_P0_11
,
194 QUNIFORM_TEXTURE_CONFIG_P0_12
,
195 QUNIFORM_TEXTURE_CONFIG_P0_13
,
196 QUNIFORM_TEXTURE_CONFIG_P0_14
,
197 QUNIFORM_TEXTURE_CONFIG_P0_15
,
198 QUNIFORM_TEXTURE_CONFIG_P0_16
,
199 QUNIFORM_TEXTURE_CONFIG_P0_17
,
200 QUNIFORM_TEXTURE_CONFIG_P0_18
,
201 QUNIFORM_TEXTURE_CONFIG_P0_19
,
202 QUNIFORM_TEXTURE_CONFIG_P0_20
,
203 QUNIFORM_TEXTURE_CONFIG_P0_21
,
204 QUNIFORM_TEXTURE_CONFIG_P0_22
,
205 QUNIFORM_TEXTURE_CONFIG_P0_23
,
206 QUNIFORM_TEXTURE_CONFIG_P0_24
,
207 QUNIFORM_TEXTURE_CONFIG_P0_25
,
208 QUNIFORM_TEXTURE_CONFIG_P0_26
,
209 QUNIFORM_TEXTURE_CONFIG_P0_27
,
210 QUNIFORM_TEXTURE_CONFIG_P0_28
,
211 QUNIFORM_TEXTURE_CONFIG_P0_29
,
212 QUNIFORM_TEXTURE_CONFIG_P0_30
,
213 QUNIFORM_TEXTURE_CONFIG_P0_31
,
214 QUNIFORM_TEXTURE_CONFIG_P0_32
,
217 * A reference to a V3D 3.x texture config parameter 1 uniform.
219 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
220 * has the pointer to the indirect texture state. Our data[] field
221 * will have a packed p1 value, but the address field will be just
222 * which texture unit's texture should be referenced.
224 QUNIFORM_TEXTURE_CONFIG_P1
,
226 /* A V3D 4.x texture config parameter. The high 8 bits will be
227 * which texture or sampler is being sampled, and the driver must
228 * replace the address field with the appropriate address.
230 QUNIFORM_TMU_CONFIG_P0
,
231 QUNIFORM_TMU_CONFIG_P1
,
233 QUNIFORM_TEXTURE_FIRST_LEVEL
,
235 QUNIFORM_TEXTURE_WIDTH
,
236 QUNIFORM_TEXTURE_HEIGHT
,
237 QUNIFORM_TEXTURE_DEPTH
,
238 QUNIFORM_TEXTURE_ARRAY_SIZE
,
239 QUNIFORM_TEXTURE_LEVELS
,
243 QUNIFORM_TEXRECT_SCALE_X
,
244 QUNIFORM_TEXRECT_SCALE_Y
,
249 * Returns the the offset of the scratch buffer for register spilling.
251 QUNIFORM_SPILL_OFFSET
,
252 QUNIFORM_SPILL_SIZE_PER_THREAD
,
255 static inline uint32_t v3d_tmu_config_data_create(uint32_t unit
, uint32_t value
)
257 return unit
<< 24 | value
;
260 static inline uint32_t v3d_tmu_config_data_get_unit(uint32_t data
)
265 static inline uint32_t v3d_tmu_config_data_get_value(uint32_t data
)
267 return data
& 0xffffff;
270 struct v3d_varying_slot
{
271 uint8_t slot_and_component
;
274 static inline struct v3d_varying_slot
275 v3d_slot_from_slot_and_component(uint8_t slot
, uint8_t component
)
277 assert(slot
< 255 / 4);
278 return (struct v3d_varying_slot
){ (slot
<< 2) + component
};
281 static inline uint8_t v3d_slot_get_slot(struct v3d_varying_slot slot
)
283 return slot
.slot_and_component
>> 2;
286 static inline uint8_t v3d_slot_get_component(struct v3d_varying_slot slot
)
288 return slot
.slot_and_component
& 3;
291 struct v3d_ubo_range
{
293 * offset in bytes from the start of the ubo where this range is
296 * Only set once used is set.
301 * offset in bytes from the start of the gallium uniforms where the
306 /** size in bytes of this ubo range */
315 uint8_t return_channels
;
319 } tex
[V3D_MAX_TEXTURE_SAMPLERS
];
329 bool point_coord_upper_left
;
332 bool sample_coverage
;
333 bool sample_alpha_to_coverage
;
334 bool sample_alpha_to_one
;
336 bool shade_model_flat
;
338 uint8_t swap_color_rb
;
339 /* Mask of which render targets need to be written as 32-bit floats */
340 uint8_t f32_color_rb
;
341 /* Masks of which render targets need to be written as ints/uints.
342 * Used by gallium to work around lost information in TGSI.
344 uint8_t int_color_rb
;
345 uint8_t uint_color_rb
;
346 uint8_t alpha_test_func
;
347 uint8_t logicop_func
;
348 uint32_t point_sprite_mask
;
350 struct pipe_rt_blend_state blend
;
356 struct v3d_varying_slot fs_inputs
[V3D_MAX_FS_INPUTS
];
357 uint8_t num_fs_inputs
;
360 bool per_vertex_point_size
;
364 /** A basic block of VIR intructions. */
366 struct list_head link
;
368 struct list_head instructions
;
370 struct set
*predecessors
;
371 struct qblock
*successors
[2];
375 /* Instruction IPs for the first and last instruction of the block.
376 * Set by qpu_schedule.c.
378 uint32_t start_qpu_ip
;
381 /* Instruction IP for the branch instruction of the block. Set by
384 uint32_t branch_qpu_ip
;
386 /** Offset within the uniform stream at the start of the block. */
387 uint32_t start_uniform
;
388 /** Offset within the uniform stream of the branch instruction */
389 uint32_t branch_uniform
;
391 /** @{ used by v3d_vir_live_variables.c */
394 BITSET_WORD
*live_in
;
395 BITSET_WORD
*live_out
;
396 int start_ip
, end_ip
;
400 /** Which util/list.h add mode we should use when inserting an instruction. */
401 enum vir_cursor_mode
{
407 * Tracking structure for where new instructions should be inserted. Create
408 * with one of the vir_after_inst()-style helper functions.
410 * This does not protect against removal of the block or instruction, so we
411 * have an assert in instruction removal to try to catch it.
414 enum vir_cursor_mode mode
;
415 struct list_head
*link
;
418 static inline struct vir_cursor
419 vir_before_inst(struct qinst
*inst
)
421 return (struct vir_cursor
){ vir_cursor_addtail
, &inst
->link
};
424 static inline struct vir_cursor
425 vir_after_inst(struct qinst
*inst
)
427 return (struct vir_cursor
){ vir_cursor_add
, &inst
->link
};
430 static inline struct vir_cursor
431 vir_before_block(struct qblock
*block
)
433 return (struct vir_cursor
){ vir_cursor_add
, &block
->instructions
};
436 static inline struct vir_cursor
437 vir_after_block(struct qblock
*block
)
439 return (struct vir_cursor
){ vir_cursor_addtail
, &block
->instructions
};
443 * Compiler state saved across compiler invocations, for any expensive global
446 struct v3d_compiler
{
447 const struct v3d_device_info
*devinfo
;
448 struct ra_regs
*regs
;
449 unsigned int reg_class_phys
[3];
450 unsigned int reg_class_phys_or_acc
[3];
454 const struct v3d_device_info
*devinfo
;
456 nir_function_impl
*impl
;
457 struct exec_list
*cf_node_list
;
458 const struct v3d_compiler
*compiler
;
460 void (*debug_output
)(const char *msg
,
461 void *debug_output_data
);
462 void *debug_output_data
;
465 * Mapping from nir_register * or nir_ssa_def * to array of struct
466 * qreg for the values.
468 struct hash_table
*def_ht
;
470 /* For each temp, the instruction generating its value. */
472 uint32_t defs_array_size
;
475 * Inputs to the shader, arranged by TGSI declaration order.
477 * Not all fragment shader QFILE_VARY reads are present in this array.
480 struct qreg
*outputs
;
481 bool msaa_per_sample_output
;
482 struct qreg color_reads
[V3D_MAX_SAMPLES
];
483 struct qreg sample_colors
[V3D_MAX_SAMPLES
];
484 uint32_t inputs_array_size
;
485 uint32_t outputs_array_size
;
486 uint32_t uniforms_array_size
;
488 /* Booleans for whether the corresponding QFILE_VARY[i] is
489 * flat-shaded. This includes gl_FragColor flat-shading, which is
490 * customized based on the shademodel_flat shader key.
492 uint32_t flat_shade_flags
[BITSET_WORDS(V3D_MAX_FS_INPUTS
)];
494 uint32_t noperspective_flags
[BITSET_WORDS(V3D_MAX_FS_INPUTS
)];
496 uint32_t centroid_flags
[BITSET_WORDS(V3D_MAX_FS_INPUTS
)];
500 struct v3d_ubo_range
*ubo_ranges
;
501 bool *ubo_range_used
;
502 uint32_t ubo_ranges_array_size
;
503 /** Number of uniform areas tracked in ubo_ranges. */
504 uint32_t num_ubo_ranges
;
505 uint32_t next_ubo_dst_offset
;
507 /* State for whether we're executing on each channel currently. 0 if
508 * yes, otherwise a block number + 1 that the channel jumped to.
512 struct qreg line_x
, point_x
, point_y
;
515 * Instance ID, which comes in before the vertex attribute payload if
516 * the shader record requests it.
521 * Vertex ID, which comes in before the vertex attribute payload
522 * (after Instance ID) if the shader record requests it.
526 /* Fragment shader payload regs. */
527 struct qreg payload_w
, payload_w_centroid
, payload_z
;
529 uint8_t vattr_sizes
[V3D_MAX_VS_INPUTS
];
530 uint32_t num_vpm_writes
;
532 /* Size in bytes of registers that have been spilled. This is how much
533 * space needs to be available in the spill BO per thread per QPU.
536 /* Shader-db stats */
537 uint32_t spills
, fills
, loops
;
539 * Register spilling's per-thread base address, shared between each
540 * spill/fill's addressing calculations.
542 struct qreg spill_base
;
543 /* Bit vector of which temps may be spilled */
544 BITSET_WORD
*spillable
;
547 * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
549 * This includes those that aren't part of the VPM varyings, like
550 * point/line coordinates.
552 struct v3d_varying_slot input_slots
[V3D_MAX_FS_INPUTS
];
555 * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
556 * of the output is. Used to emit from the VS in the order that the
559 struct v3d_varying_slot
*output_slots
;
561 struct pipe_shader_state
*shader_state
;
563 struct v3d_fs_key
*fs_key
;
564 struct v3d_vs_key
*vs_key
;
566 /* Live ranges of temps. */
567 int *temp_start
, *temp_end
;
568 bool live_intervals_valid
;
570 uint32_t *uniform_data
;
571 enum quniform_contents
*uniform_contents
;
572 uint32_t uniform_array_size
;
573 uint32_t num_uniforms
;
574 uint32_t num_outputs
;
575 uint32_t output_position_index
;
576 nir_variable
*output_color_var
[4];
577 uint32_t output_point_size_index
;
578 uint32_t output_sample_mask_index
;
583 struct vir_cursor cursor
;
584 struct list_head blocks
;
585 int next_block_index
;
586 struct qblock
*cur_block
;
587 struct qblock
*loop_cont_block
;
588 struct qblock
*loop_break_block
;
591 uint32_t qpu_inst_count
;
592 uint32_t qpu_inst_size
;
594 /* For the FS, the number of varying inputs not counting the
595 * point/line varyings payload
600 * Number of inputs from num_inputs remaining to be queued to the read
603 uint32_t num_inputs_remaining
;
605 /* Number of inputs currently in the read FIFO for the VS/CS */
606 uint32_t num_inputs_in_fifo
;
608 /** Next offset in the VPM to read from in the VS/CS */
609 uint32_t vpm_read_offset
;
614 /* Set to compile program in in 1x, 2x, or 4x threaded mode, where
615 * SIG_THREAD_SWITCH is used to hide texturing latency at the cost of
616 * limiting ourselves to the part of the physical reg space.
618 * On V3D 3.x, 2x or 4x divide the physical reg space by 2x or 4x. On
619 * V3D 4.x, all shaders are 2x threaded, and 4x only divides the
620 * physical reg space in half.
623 struct qinst
*last_thrsw
;
624 bool last_thrsw_at_top_level
;
629 struct v3d_uniform_list
{
630 enum quniform_contents
*contents
;
635 struct v3d_prog_data
{
636 struct v3d_uniform_list uniforms
;
638 struct v3d_ubo_range
*ubo_ranges
;
639 uint32_t num_ubo_ranges
;
646 /* For threads > 1, whether the program should be dispatched in the
647 * after-final-THRSW state.
652 struct v3d_vs_prog_data
{
653 struct v3d_prog_data base
;
655 bool uses_iid
, uses_vid
;
657 /* Number of components read from each vertex attribute. */
658 uint8_t vattr_sizes
[32];
660 /* Total number of components read, for the shader state record. */
661 uint32_t vpm_input_size
;
663 /* Total number of components written, for the shader state record. */
664 uint32_t vpm_output_size
;
666 /* Set if there should be separate VPM segments for input and output.
667 * If unset, vpm_input_size will be 0.
669 bool separate_segments
;
671 /* Value to be programmed in VCM_CACHE_SIZE. */
672 uint8_t vcm_cache_size
;
675 struct v3d_fs_prog_data
{
676 struct v3d_prog_data base
;
678 struct v3d_varying_slot input_slots
[V3D_MAX_FS_INPUTS
];
680 /* Array of flat shade flags.
682 * Each entry is only 24 bits (high 8 bits 0), to match the hardware
685 uint32_t flat_shade_flags
[((V3D_MAX_FS_INPUTS
- 1) / 24) + 1];
687 uint32_t noperspective_flags
[((V3D_MAX_FS_INPUTS
- 1) / 24) + 1];
689 uint32_t centroid_flags
[((V3D_MAX_FS_INPUTS
- 1) / 24) + 1];
696 /* Special nir_load_input intrinsic index for loading the current TLB
699 #define V3D_NIR_TLB_COLOR_READ_INPUT 2000000000
701 #define V3D_NIR_MS_MASK_OUTPUT 2000000000
703 extern const nir_shader_compiler_options v3d_nir_options
;
705 const struct v3d_compiler
*v3d_compiler_init(const struct v3d_device_info
*devinfo
);
706 void v3d_compiler_free(const struct v3d_compiler
*compiler
);
707 void v3d_optimize_nir(struct nir_shader
*s
);
709 uint64_t *v3d_compile(const struct v3d_compiler
*compiler
,
711 struct v3d_prog_data
**prog_data
,
713 void (*debug_output
)(const char *msg
,
714 void *debug_output_data
),
715 void *debug_output_data
,
716 int program_id
, int variant_id
,
717 uint32_t *final_assembly_size
);
719 void v3d_nir_to_vir(struct v3d_compile
*c
);
721 void vir_compile_destroy(struct v3d_compile
*c
);
722 const char *vir_get_stage_name(struct v3d_compile
*c
);
723 struct qblock
*vir_new_block(struct v3d_compile
*c
);
724 void vir_set_emit_block(struct v3d_compile
*c
, struct qblock
*block
);
725 void vir_link_blocks(struct qblock
*predecessor
, struct qblock
*successor
);
726 struct qblock
*vir_entry_block(struct v3d_compile
*c
);
727 struct qblock
*vir_exit_block(struct v3d_compile
*c
);
728 struct qinst
*vir_add_inst(enum v3d_qpu_add_op op
, struct qreg dst
,
729 struct qreg src0
, struct qreg src1
);
730 struct qinst
*vir_mul_inst(enum v3d_qpu_mul_op op
, struct qreg dst
,
731 struct qreg src0
, struct qreg src1
);
732 struct qinst
*vir_branch_inst(enum v3d_qpu_branch_cond cond
, struct qreg src0
);
733 void vir_remove_instruction(struct v3d_compile
*c
, struct qinst
*qinst
);
734 struct qreg
vir_uniform(struct v3d_compile
*c
,
735 enum quniform_contents contents
,
737 void vir_schedule_instructions(struct v3d_compile
*c
);
738 struct v3d_qpu_instr
v3d_qpu_nop(void);
740 struct qreg
vir_emit_def(struct v3d_compile
*c
, struct qinst
*inst
);
741 struct qinst
*vir_emit_nondef(struct v3d_compile
*c
, struct qinst
*inst
);
742 void vir_set_cond(struct qinst
*inst
, enum v3d_qpu_cond cond
);
743 void vir_set_pf(struct qinst
*inst
, enum v3d_qpu_pf pf
);
744 void vir_set_uf(struct qinst
*inst
, enum v3d_qpu_uf uf
);
745 void vir_set_unpack(struct qinst
*inst
, int src
,
746 enum v3d_qpu_input_unpack unpack
);
748 struct qreg
vir_get_temp(struct v3d_compile
*c
);
749 void vir_emit_last_thrsw(struct v3d_compile
*c
);
750 void vir_calculate_live_intervals(struct v3d_compile
*c
);
751 bool vir_has_implicit_uniform(struct qinst
*inst
);
752 int vir_get_implicit_uniform_src(struct qinst
*inst
);
753 int vir_get_non_sideband_nsrc(struct qinst
*inst
);
754 int vir_get_nsrc(struct qinst
*inst
);
755 bool vir_has_side_effects(struct v3d_compile
*c
, struct qinst
*inst
);
756 bool vir_get_add_op(struct qinst
*inst
, enum v3d_qpu_add_op
*op
);
757 bool vir_get_mul_op(struct qinst
*inst
, enum v3d_qpu_mul_op
*op
);
758 bool vir_is_raw_mov(struct qinst
*inst
);
759 bool vir_is_tex(struct qinst
*inst
);
760 bool vir_is_add(struct qinst
*inst
);
761 bool vir_is_mul(struct qinst
*inst
);
762 bool vir_is_float_input(struct qinst
*inst
);
763 bool vir_writes_r3(const struct v3d_device_info
*devinfo
, struct qinst
*inst
);
764 bool vir_writes_r4(const struct v3d_device_info
*devinfo
, struct qinst
*inst
);
765 struct qreg
vir_follow_movs(struct v3d_compile
*c
, struct qreg reg
);
766 uint8_t vir_channels_written(struct qinst
*inst
);
767 struct qreg
ntq_get_src(struct v3d_compile
*c
, nir_src src
, int i
);
768 void ntq_store_dest(struct v3d_compile
*c
, nir_dest
*dest
, int chan
,
770 void vir_emit_thrsw(struct v3d_compile
*c
);
772 void vir_dump(struct v3d_compile
*c
);
773 void vir_dump_inst(struct v3d_compile
*c
, struct qinst
*inst
);
774 void vir_dump_uniform(enum quniform_contents contents
, uint32_t data
);
776 void vir_validate(struct v3d_compile
*c
);
778 void vir_optimize(struct v3d_compile
*c
);
779 bool vir_opt_algebraic(struct v3d_compile
*c
);
780 bool vir_opt_constant_folding(struct v3d_compile
*c
);
781 bool vir_opt_copy_propagate(struct v3d_compile
*c
);
782 bool vir_opt_dead_code(struct v3d_compile
*c
);
783 bool vir_opt_peephole_sf(struct v3d_compile
*c
);
784 bool vir_opt_small_immediates(struct v3d_compile
*c
);
785 bool vir_opt_vpm(struct v3d_compile
*c
);
786 void v3d_nir_lower_blend(nir_shader
*s
, struct v3d_compile
*c
);
787 void v3d_nir_lower_io(nir_shader
*s
, struct v3d_compile
*c
);
788 void v3d_nir_lower_txf_ms(nir_shader
*s
, struct v3d_compile
*c
);
789 void vir_lower_uniforms(struct v3d_compile
*c
);
791 void v3d33_vir_vpm_read_setup(struct v3d_compile
*c
, int num_components
);
792 void v3d33_vir_vpm_write_setup(struct v3d_compile
*c
);
793 void v3d33_vir_emit_tex(struct v3d_compile
*c
, nir_tex_instr
*instr
);
794 void v3d40_vir_emit_tex(struct v3d_compile
*c
, nir_tex_instr
*instr
);
796 void v3d_vir_to_qpu(struct v3d_compile
*c
, struct qpu_reg
*temp_registers
);
797 uint32_t v3d_qpu_schedule_instructions(struct v3d_compile
*c
);
798 void qpu_validate(struct v3d_compile
*c
);
799 struct qpu_reg
*v3d_register_allocate(struct v3d_compile
*c
, bool *spilled
);
800 bool vir_init_reg_sets(struct v3d_compiler
*compiler
);
802 void vir_PF(struct v3d_compile
*c
, struct qreg src
, enum v3d_qpu_pf pf
);
805 quniform_contents_is_texture_p0(enum quniform_contents contents
)
807 return (contents
>= QUNIFORM_TEXTURE_CONFIG_P0_0
&&
808 contents
< (QUNIFORM_TEXTURE_CONFIG_P0_0
+
809 V3D_MAX_TEXTURE_SAMPLERS
));
812 static inline struct qreg
813 vir_uniform_ui(struct v3d_compile
*c
, uint32_t ui
)
815 return vir_uniform(c
, QUNIFORM_CONSTANT
, ui
);
818 static inline struct qreg
819 vir_uniform_f(struct v3d_compile
*c
, float f
)
821 return vir_uniform(c
, QUNIFORM_CONSTANT
, fui(f
));
824 #define VIR_ALU0(name, vir_inst, op) \
825 static inline struct qreg \
826 vir_##name(struct v3d_compile *c) \
828 return vir_emit_def(c, vir_inst(op, c->undef, \
829 c->undef, c->undef)); \
831 static inline struct qinst * \
832 vir_##name##_dest(struct v3d_compile *c, struct qreg dest) \
834 return vir_emit_nondef(c, vir_inst(op, dest, \
835 c->undef, c->undef)); \
838 #define VIR_ALU1(name, vir_inst, op) \
839 static inline struct qreg \
840 vir_##name(struct v3d_compile *c, struct qreg a) \
842 return vir_emit_def(c, vir_inst(op, c->undef, \
845 static inline struct qinst * \
846 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
849 return vir_emit_nondef(c, vir_inst(op, dest, a, \
853 #define VIR_ALU2(name, vir_inst, op) \
854 static inline struct qreg \
855 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b) \
857 return vir_emit_def(c, vir_inst(op, c->undef, a, b)); \
859 static inline struct qinst * \
860 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
861 struct qreg a, struct qreg b) \
863 return vir_emit_nondef(c, vir_inst(op, dest, a, b)); \
866 #define VIR_NODST_0(name, vir_inst, op) \
867 static inline struct qinst * \
868 vir_##name(struct v3d_compile *c) \
870 return vir_emit_nondef(c, vir_inst(op, c->undef, \
871 c->undef, c->undef)); \
874 #define VIR_NODST_1(name, vir_inst, op) \
875 static inline struct qinst * \
876 vir_##name(struct v3d_compile *c, struct qreg a) \
878 return vir_emit_nondef(c, vir_inst(op, c->undef, \
882 #define VIR_NODST_2(name, vir_inst, op) \
883 static inline struct qinst * \
884 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b) \
886 return vir_emit_nondef(c, vir_inst(op, c->undef, \
890 #define VIR_SFU(name) \
891 static inline struct qreg \
892 vir_##name(struct v3d_compile *c, struct qreg a) \
894 if (c->devinfo->ver >= 41) { \
895 return vir_emit_def(c, vir_add_inst(V3D_QPU_A_##name, \
899 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_##name), a); \
900 return vir_FMOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4)); \
903 static inline struct qinst * \
904 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
907 if (c->devinfo->ver >= 41) { \
908 return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_##name, \
912 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_##name), a); \
913 return vir_FMOV_dest(c, dest, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4)); \
917 #define VIR_A_ALU2(name) VIR_ALU2(name, vir_add_inst, V3D_QPU_A_##name)
918 #define VIR_M_ALU2(name) VIR_ALU2(name, vir_mul_inst, V3D_QPU_M_##name)
919 #define VIR_A_ALU1(name) VIR_ALU1(name, vir_add_inst, V3D_QPU_A_##name)
920 #define VIR_M_ALU1(name) VIR_ALU1(name, vir_mul_inst, V3D_QPU_M_##name)
921 #define VIR_A_ALU0(name) VIR_ALU0(name, vir_add_inst, V3D_QPU_A_##name)
922 #define VIR_M_ALU0(name) VIR_ALU0(name, vir_mul_inst, V3D_QPU_M_##name)
923 #define VIR_A_NODST_2(name) VIR_NODST_2(name, vir_add_inst, V3D_QPU_A_##name)
924 #define VIR_M_NODST_2(name) VIR_NODST_2(name, vir_mul_inst, V3D_QPU_M_##name)
925 #define VIR_A_NODST_1(name) VIR_NODST_1(name, vir_add_inst, V3D_QPU_A_##name)
926 #define VIR_M_NODST_1(name) VIR_NODST_1(name, vir_mul_inst, V3D_QPU_M_##name)
927 #define VIR_A_NODST_0(name) VIR_NODST_0(name, vir_add_inst, V3D_QPU_A_##name)
950 VIR_A_NODST_2(STVPMV
)
960 VIR_A_ALU1(LDVPMV_IN
)
961 VIR_A_ALU1(LDVPMV_OUT
)
970 VIR_A_NODST_1(VPMSETUP
)
994 VIR_M_NODST_2(MULTOP
)
1006 static inline struct qinst
*
1007 vir_MOV_cond(struct v3d_compile
*c
, enum v3d_qpu_cond cond
,
1008 struct qreg dest
, struct qreg src
)
1010 struct qinst
*mov
= vir_MOV_dest(c
, dest
, src
);
1011 vir_set_cond(mov
, cond
);
1015 static inline struct qreg
1016 vir_SEL(struct v3d_compile
*c
, enum v3d_qpu_cond cond
,
1017 struct qreg src0
, struct qreg src1
)
1019 struct qreg t
= vir_get_temp(c
);
1020 vir_MOV_dest(c
, t
, src1
);
1021 vir_MOV_cond(c
, cond
, t
, src0
);
1025 static inline struct qinst
*
1026 vir_NOP(struct v3d_compile
*c
)
1028 return vir_emit_nondef(c
, vir_add_inst(V3D_QPU_A_NOP
,
1029 c
->undef
, c
->undef
, c
->undef
));
1032 static inline struct qreg
1033 vir_LDTMU(struct v3d_compile
*c
)
1035 if (c
->devinfo
->ver
>= 41) {
1036 struct qinst
*ldtmu
= vir_add_inst(V3D_QPU_A_NOP
, c
->undef
,
1037 c
->undef
, c
->undef
);
1038 ldtmu
->qpu
.sig
.ldtmu
= true;
1040 return vir_emit_def(c
, ldtmu
);
1042 vir_NOP(c
)->qpu
.sig
.ldtmu
= true;
1043 return vir_MOV(c
, vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_R4
));
1047 static inline struct qreg
1048 vir_UMUL(struct v3d_compile
*c
, struct qreg src0
, struct qreg src1
)
1050 vir_MULTOP(c
, src0
, src1
);
1051 return vir_UMUL24(c
, src0
, src1
);
1055 static inline struct qreg
1056 vir_LOAD_IMM(struct v3d_compile *c, uint32_t val)
1058 return vir_emit_def(c, vir_inst(QOP_LOAD_IMM, c->undef,
1059 vir_reg(QFILE_LOAD_IMM, val), c->undef));
1062 static inline struct qreg
1063 vir_LOAD_IMM_U2(struct v3d_compile *c, uint32_t val)
1065 return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_U2, c->undef,
1066 vir_reg(QFILE_LOAD_IMM, val),
1069 static inline struct qreg
1070 vir_LOAD_IMM_I2(struct v3d_compile *c, uint32_t val)
1072 return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_I2, c->undef,
1073 vir_reg(QFILE_LOAD_IMM, val),
1078 static inline struct qinst
*
1079 vir_BRANCH(struct v3d_compile
*c
, enum v3d_qpu_branch_cond cond
)
1081 /* The actual uniform_data value will be set at scheduling time */
1082 return vir_emit_nondef(c
, vir_branch_inst(cond
, vir_uniform_ui(c
, 0)));
1085 #define vir_for_each_block(block, c) \
1086 list_for_each_entry(struct qblock, block, &c->blocks, link)
1088 #define vir_for_each_block_rev(block, c) \
1089 list_for_each_entry_rev(struct qblock, block, &c->blocks, link)
1091 /* Loop over the non-NULL members of the successors array. */
1092 #define vir_for_each_successor(succ, block) \
1093 for (struct qblock *succ = block->successors[0]; \
1095 succ = (succ == block->successors[1] ? NULL : \
1096 block->successors[1]))
1098 #define vir_for_each_inst(inst, block) \
1099 list_for_each_entry(struct qinst, inst, &block->instructions, link)
1101 #define vir_for_each_inst_rev(inst, block) \
1102 list_for_each_entry_rev(struct qinst, inst, &block->instructions, link)
1104 #define vir_for_each_inst_safe(inst, block) \
1105 list_for_each_entry_safe(struct qinst, inst, &block->instructions, link)
1107 #define vir_for_each_inst_inorder(inst, c) \
1108 vir_for_each_block(_block, c) \
1109 vir_for_each_inst(inst, _block)
1111 #endif /* V3D_COMPILER_H */