src/broadcom/compiler/v3d_compiler.h

   1 /*
   2  * Copyright © 2016 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef V3D_COMPILER_H
  25 #define V3D_COMPILER_H
  26
  27 #include <assert.h>
  28 #include <stdio.h>
  29 #include <stdlib.h>
  30 #include <stdbool.h>
  31 #include <stdint.h>
  32 #include <string.h>
  33
  34 #include "util/macros.h"
  35 #include "common/v3d_debug.h"
  36 #include "compiler/nir/nir.h"
  37 #include "util/list.h"
  38 #include "util/u_math.h"
  39
  40 #include "qpu/qpu_instr.h"
  41 #include "pipe/p_state.h"
  42
  43 #define V3D_MAX_TEXTURE_SAMPLERS 32
  44 #define V3D_MAX_SAMPLES 4
  45 #define V3D_MAX_FS_INPUTS 64
  46 #define V3D_MAX_VS_INPUTS 64
  47
  48 struct nir_builder;
  49
  50 struct v3d_fs_inputs {
  51         /**
  52          * Array of the meanings of the VPM inputs this shader needs.
  53          *
  54          * It doesn't include those that aren't part of the VPM, like
  55          * point/line coordinates.
  56          */
  57         struct v3d_varying_slot *input_slots;
  58         uint32_t num_inputs;
  59 };
  60
  61 enum qfile {
  62         /** An unused source or destination register. */
  63         QFILE_NULL,
  64
  65         /** A physical register, such as the W coordinate payload. */
  66         QFILE_REG,
  67         /** One of the regsiters for fixed function interactions. */
  68         QFILE_MAGIC,
  69
  70         /**
  71          *  A virtual register, that will be allocated to actual accumulator
  72          * or physical registers later.
  73          */
  74         QFILE_TEMP,
  75         QFILE_VARY,
  76         QFILE_UNIF,
  77         QFILE_TLB,
  78         QFILE_TLBU,
  79
  80         /**
  81          * VPM reads use this with an index value to say what part of the VPM
  82          * is being read.
  83          */
  84         QFILE_VPM,
  85
  86         /**
  87          * Stores an immediate value in the index field that will be used
  88          * directly by qpu_load_imm().
  89          */
  90         QFILE_LOAD_IMM,
  91
  92         /**
  93          * Stores an immediate value in the index field that can be turned
  94          * into a small immediate field by qpu_encode_small_immediate().
  95          */
  96         QFILE_SMALL_IMM,
  97 };
  98
  99 /**
 100  * A reference to a QPU register or a virtual temp register.
 101  */
 102 struct qreg {
 103         enum qfile file;
 104         uint32_t index;
 105 };
 106
 107 static inline struct qreg vir_reg(enum qfile file, uint32_t index)
 108 {
 109         return (struct qreg){file, index};
 110 }
 111
 112 /**
 113  * A reference to an actual register at the QPU level, for register
 114  * allocation.
 115  */
 116 struct qpu_reg {
 117         bool magic;
 118         int index;
 119 };
 120
 121 struct qinst {
 122         /** Entry in qblock->instructions */
 123         struct list_head link;
 124
 125         /**
 126          * The instruction being wrapped.  Its condition codes, pack flags,
 127          * signals, etc. will all be used, with just the register references
 128          * being replaced by the contents of qinst->dst and qinst->src[].
 129          */
 130         struct v3d_qpu_instr qpu;
 131
 132         /* Pre-register-allocation references to src/dst registers */
 133         struct qreg dst;
 134         struct qreg src[3];
 135         bool cond_is_exec_mask;
 136         bool has_implicit_uniform;
 137
 138         /* After vir_to_qpu.c: If instr reads a uniform, which uniform from
 139          * the uncompiled stream it is.
 140          */
 141         int uniform;
 142 };
 143
 144 enum quniform_contents {
 145         /**
 146          * Indicates that a constant 32-bit value is copied from the program's
 147          * uniform contents.
 148          */
 149         QUNIFORM_CONSTANT,
 150         /**
 151          * Indicates that the program's uniform contents are used as an index
 152          * into the GL uniform storage.
 153          */
 154         QUNIFORM_UNIFORM,
 155
 156         /** @{
 157          * Scaling factors from clip coordinates to relative to the viewport
 158          * center.
 159          *
 160          * This is used by the coordinate and vertex shaders to produce the
 161          * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
 162          * point offsets from the viewport ccenter.
 163          */
 164         QUNIFORM_VIEWPORT_X_SCALE,
 165         QUNIFORM_VIEWPORT_Y_SCALE,
 166         /** @} */
 167
 168         QUNIFORM_VIEWPORT_Z_OFFSET,
 169         QUNIFORM_VIEWPORT_Z_SCALE,
 170
 171         QUNIFORM_USER_CLIP_PLANE,
 172
 173         /**
 174          * A reference to a texture config parameter 0 uniform.
 175          *
 176          * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
 177          * defines texture type, miplevels, and such.  It will be found as a
 178          * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
 179          */
 180         QUNIFORM_TEXTURE_CONFIG_P0_0,
 181         QUNIFORM_TEXTURE_CONFIG_P0_1,
 182         QUNIFORM_TEXTURE_CONFIG_P0_2,
 183         QUNIFORM_TEXTURE_CONFIG_P0_3,
 184         QUNIFORM_TEXTURE_CONFIG_P0_4,
 185         QUNIFORM_TEXTURE_CONFIG_P0_5,
 186         QUNIFORM_TEXTURE_CONFIG_P0_6,
 187         QUNIFORM_TEXTURE_CONFIG_P0_7,
 188         QUNIFORM_TEXTURE_CONFIG_P0_8,
 189         QUNIFORM_TEXTURE_CONFIG_P0_9,
 190         QUNIFORM_TEXTURE_CONFIG_P0_10,
 191         QUNIFORM_TEXTURE_CONFIG_P0_11,
 192         QUNIFORM_TEXTURE_CONFIG_P0_12,
 193         QUNIFORM_TEXTURE_CONFIG_P0_13,
 194         QUNIFORM_TEXTURE_CONFIG_P0_14,
 195         QUNIFORM_TEXTURE_CONFIG_P0_15,
 196         QUNIFORM_TEXTURE_CONFIG_P0_16,
 197         QUNIFORM_TEXTURE_CONFIG_P0_17,
 198         QUNIFORM_TEXTURE_CONFIG_P0_18,
 199         QUNIFORM_TEXTURE_CONFIG_P0_19,
 200         QUNIFORM_TEXTURE_CONFIG_P0_20,
 201         QUNIFORM_TEXTURE_CONFIG_P0_21,
 202         QUNIFORM_TEXTURE_CONFIG_P0_22,
 203         QUNIFORM_TEXTURE_CONFIG_P0_23,
 204         QUNIFORM_TEXTURE_CONFIG_P0_24,
 205         QUNIFORM_TEXTURE_CONFIG_P0_25,
 206         QUNIFORM_TEXTURE_CONFIG_P0_26,
 207         QUNIFORM_TEXTURE_CONFIG_P0_27,
 208         QUNIFORM_TEXTURE_CONFIG_P0_28,
 209         QUNIFORM_TEXTURE_CONFIG_P0_29,
 210         QUNIFORM_TEXTURE_CONFIG_P0_30,
 211         QUNIFORM_TEXTURE_CONFIG_P0_31,
 212         QUNIFORM_TEXTURE_CONFIG_P0_32,
 213
 214         /**
 215          * A reference to a texture config parameter 1 uniform.
 216          *
 217          * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
 218          * defines texture width, height, filters, and wrap modes.  It will be
 219          * found as a parameter to the second QOP_TEX_[STRB] instruction in a
 220          * sequence.
 221          */
 222         QUNIFORM_TEXTURE_CONFIG_P1,
 223
 224         QUNIFORM_TEXTURE_FIRST_LEVEL,
 225
 226         QUNIFORM_TEXTURE_WIDTH,
 227         QUNIFORM_TEXTURE_HEIGHT,
 228         QUNIFORM_TEXTURE_DEPTH,
 229         QUNIFORM_TEXTURE_ARRAY_SIZE,
 230         QUNIFORM_TEXTURE_LEVELS,
 231
 232         QUNIFORM_TEXTURE_MSAA_ADDR,
 233
 234         QUNIFORM_UBO_ADDR,
 235
 236         QUNIFORM_TEXRECT_SCALE_X,
 237         QUNIFORM_TEXRECT_SCALE_Y,
 238
 239         QUNIFORM_TEXTURE_BORDER_COLOR,
 240
 241         QUNIFORM_STENCIL,
 242
 243         QUNIFORM_ALPHA_REF,
 244         QUNIFORM_SAMPLE_MASK,
 245 };
 246
 247 struct v3d_varying_slot {
 248         uint8_t slot_and_component;
 249 };
 250
 251 static inline struct v3d_varying_slot
 252 v3d_slot_from_slot_and_component(uint8_t slot, uint8_t component)
 253 {
 254         assert(slot < 255 / 4);
 255         return (struct v3d_varying_slot){ (slot << 2) + component };
 256 }
 257
 258 static inline uint8_t v3d_slot_get_slot(struct v3d_varying_slot slot)
 259 {
 260         return slot.slot_and_component >> 2;
 261 }
 262
 263 static inline uint8_t v3d_slot_get_component(struct v3d_varying_slot slot)
 264 {
 265         return slot.slot_and_component & 3;
 266 }
 267
 268 struct v3d_ubo_range {
 269         /**
 270          * offset in bytes from the start of the ubo where this range is
 271          * uploaded.
 272          *
 273          * Only set once used is set.
 274          */
 275         uint32_t dst_offset;
 276
 277         /**
 278          * offset in bytes from the start of the gallium uniforms where the
 279          * data comes from.
 280          */
 281         uint32_t src_offset;
 282
 283         /** size in bytes of this ubo range */
 284         uint32_t size;
 285 };
 286
 287 struct v3d_key {
 288         void *shader_state;
 289         struct {
 290                 uint8_t swizzle[4];
 291                 uint8_t return_size;
 292                 uint8_t return_channels;
 293                 union {
 294                         struct {
 295                                 unsigned compare_mode:1;
 296                                 unsigned compare_func:3;
 297                                 bool clamp_s:1;
 298                                 bool clamp_t:1;
 299                                 bool clamp_r:1;
 300                         };
 301                         struct {
 302                                 uint16_t msaa_width, msaa_height;
 303                         };
 304                 };
 305         } tex[V3D_MAX_TEXTURE_SAMPLERS];
 306         uint8_t ucp_enables;
 307 };
 308
 309 struct v3d_fs_key {
 310         struct v3d_key base;
 311         bool depth_enabled;
 312         bool is_points;
 313         bool is_lines;
 314         bool alpha_test;
 315         bool point_coord_upper_left;
 316         bool light_twoside;
 317         bool msaa;
 318         bool sample_coverage;
 319         bool sample_alpha_to_coverage;
 320         bool sample_alpha_to_one;
 321         bool clamp_color;
 322         uint8_t nr_cbufs;
 323         uint8_t swap_color_rb;
 324         /* Mask of which render targets need to be written as 32-bit floats */
 325         uint8_t f32_color_rb;
 326         uint8_t alpha_test_func;
 327         uint8_t logicop_func;
 328         uint32_t point_sprite_mask;
 329
 330         struct pipe_rt_blend_state blend;
 331 };
 332
 333 struct v3d_vs_key {
 334         struct v3d_key base;
 335
 336         struct v3d_varying_slot fs_inputs[V3D_MAX_FS_INPUTS];
 337         uint8_t num_fs_inputs;
 338
 339         bool is_coord;
 340         bool per_vertex_point_size;
 341         bool clamp_color;
 342 };
 343
 344 /** A basic block of VIR intructions. */
 345 struct qblock {
 346         struct list_head link;
 347
 348         struct list_head instructions;
 349
 350         struct set *predecessors;
 351         struct qblock *successors[2];
 352
 353         int index;
 354
 355         /* Instruction IPs for the first and last instruction of the block.
 356          * Set by qpu_schedule.c.
 357          */
 358         uint32_t start_qpu_ip;
 359         uint32_t end_qpu_ip;
 360
 361         /* Instruction IP for the branch instruction of the block.  Set by
 362          * qpu_schedule.c.
 363          */
 364         uint32_t branch_qpu_ip;
 365
 366         /** Offset within the uniform stream at the start of the block. */
 367         uint32_t start_uniform;
 368         /** Offset within the uniform stream of the branch instruction */
 369         uint32_t branch_uniform;
 370
 371         /** @{ used by v3d_vir_live_variables.c */
 372         BITSET_WORD *def;
 373         BITSET_WORD *use;
 374         BITSET_WORD *live_in;
 375         BITSET_WORD *live_out;
 376         int start_ip, end_ip;
 377         /** @} */
 378 };
 379
 380 /**
 381  * Compiler state saved across compiler invocations, for any expensive global
 382  * setup.
 383  */
 384 struct v3d_compiler {
 385         const struct v3d_device_info *devinfo;
 386         struct ra_regs *regs;
 387         unsigned int reg_class[3];
 388 };
 389
 390 struct v3d_compile {
 391         const struct v3d_device_info *devinfo;
 392         nir_shader *s;
 393         nir_function_impl *impl;
 394         struct exec_list *cf_node_list;
 395         const struct v3d_compiler *compiler;
 396
 397         /**
 398          * Mapping from nir_register * or nir_ssa_def * to array of struct
 399          * qreg for the values.
 400          */
 401         struct hash_table *def_ht;
 402
 403         /* For each temp, the instruction generating its value. */
 404         struct qinst **defs;
 405         uint32_t defs_array_size;
 406
 407         /**
 408          * Inputs to the shader, arranged by TGSI declaration order.
 409          *
 410          * Not all fragment shader QFILE_VARY reads are present in this array.
 411          */
 412         struct qreg *inputs;
 413         struct qreg *outputs;
 414         bool msaa_per_sample_output;
 415         struct qreg color_reads[V3D_MAX_SAMPLES];
 416         struct qreg sample_colors[V3D_MAX_SAMPLES];
 417         uint32_t inputs_array_size;
 418         uint32_t outputs_array_size;
 419         uint32_t uniforms_array_size;
 420
 421         /* Booleans for whether the corresponding QFILE_VARY[i] is
 422          * flat-shaded.  This doesn't count gl_FragColor flat-shading, which is
 423          * controlled by shader->color_inputs and rasterizer->flatshade in the
 424          * gallium driver.
 425          */
 426         BITSET_WORD flat_shade_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
 427
 428         /* Booleans for whether the corresponding QFILE_VARY[i] uses the
 429          * default glShadeModel() behavior.
 430          */
 431         BITSET_WORD shade_model_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
 432
 433         struct v3d_ubo_range *ubo_ranges;
 434         bool *ubo_range_used;
 435         uint32_t ubo_ranges_array_size;
 436         /** Number of uniform areas tracked in ubo_ranges. */
 437         uint32_t num_ubo_ranges;
 438         uint32_t next_ubo_dst_offset;
 439
 440         /* State for whether we're executing on each channel currently.  0 if
 441          * yes, otherwise a block number + 1 that the channel jumped to.
 442          */
 443         struct qreg execute;
 444
 445         struct qreg line_x, point_x, point_y;
 446
 447         /**
 448          * Instance ID, which comes in before the vertex attribute payload if
 449          * the shader record requests it.
 450          */
 451         struct qreg iid;
 452
 453         /**
 454          * Vertex ID, which comes in before the vertex attribute payload
 455          * (after Instance ID) if the shader record requests it.
 456          */
 457         struct qreg vid;
 458
 459         /* Fragment shader payload regs. */
 460         struct qreg payload_w, payload_w_centroid, payload_z;
 461
 462         uint8_t vattr_sizes[V3D_MAX_VS_INPUTS];
 463         uint32_t num_vpm_writes;
 464
 465         /**
 466          * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
 467          *
 468          * This includes those that aren't part of the VPM varyings, like
 469          * point/line coordinates.
 470          */
 471         struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
 472
 473         /**
 474          * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
 475          * of the output is.  Used to emit from the VS in the order that the
 476          * FS needs.
 477          */
 478         struct v3d_varying_slot *output_slots;
 479
 480         struct pipe_shader_state *shader_state;
 481         struct v3d_key *key;
 482         struct v3d_fs_key *fs_key;
 483         struct v3d_vs_key *vs_key;
 484
 485         /* Live ranges of temps. */
 486         int *temp_start, *temp_end;
 487
 488         uint32_t *uniform_data;
 489         enum quniform_contents *uniform_contents;
 490         uint32_t uniform_array_size;
 491         uint32_t num_uniforms;
 492         uint32_t num_outputs;
 493         uint32_t output_position_index;
 494         nir_variable *output_color_var[4];
 495         uint32_t output_point_size_index;
 496         uint32_t output_sample_mask_index;
 497
 498         struct qreg undef;
 499         uint32_t num_temps;
 500
 501         struct list_head blocks;
 502         int next_block_index;
 503         struct qblock *cur_block;
 504         struct qblock *loop_cont_block;
 505         struct qblock *loop_break_block;
 506
 507         uint64_t *qpu_insts;
 508         uint32_t qpu_inst_count;
 509         uint32_t qpu_inst_size;
 510
 511         /* For the FS, the number of varying inputs not counting the
 512          * point/line varyings payload
 513          */
 514         uint32_t num_inputs;
 515
 516         /**
 517          * Number of inputs from num_inputs remaining to be queued to the read
 518          * FIFO in the VS/CS.
 519          */
 520         uint32_t num_inputs_remaining;
 521
 522         /* Number of inputs currently in the read FIFO for the VS/CS */
 523         uint32_t num_inputs_in_fifo;
 524
 525         /** Next offset in the VPM to read from in the VS/CS */
 526         uint32_t vpm_read_offset;
 527
 528         uint32_t program_id;
 529         uint32_t variant_id;
 530
 531         /* Set to compile program in threaded FS mode, where SIG_THREAD_SWITCH
 532          * is used to hide texturing latency at the cost of limiting ourselves
 533          * to the bottom half of physical reg space.
 534          */
 535         bool fs_threaded;
 536
 537         bool last_thrsw_at_top_level;
 538
 539         bool failed;
 540 };
 541
 542 struct v3d_uniform_list {
 543         enum quniform_contents *contents;
 544         uint32_t *data;
 545         uint32_t count;
 546 };
 547
 548 struct v3d_prog_data {
 549         struct v3d_uniform_list uniforms;
 550
 551         struct v3d_ubo_range *ubo_ranges;
 552         uint32_t num_ubo_ranges;
 553         uint32_t ubo_size;
 554
 555         uint8_t num_inputs;
 556
 557 };
 558
 559 struct v3d_vs_prog_data {
 560         struct v3d_prog_data base;
 561
 562         bool uses_iid, uses_vid;
 563
 564         /* Number of components read from each vertex attribute. */
 565         uint8_t vattr_sizes[32];
 566
 567         /* Total number of components read, for the shader state record. */
 568         uint32_t vpm_input_size;
 569
 570         /* Total number of components written, for the shader state record. */
 571         uint32_t vpm_output_size;
 572 };
 573
 574 struct v3d_fs_prog_data {
 575         struct v3d_prog_data base;
 576
 577         struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
 578
 579         /* Bitmask for whether the corresponding input is flat-shaded,
 580          * independent of rasterizer (gl_FragColor) flat-shading.
 581          */
 582         BITSET_WORD flat_shade_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
 583         /* Bitmask for whether the corresponding input uses the default
 584          * glShadeModel() behavior.
 585          */
 586         BITSET_WORD shade_model_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
 587
 588         bool writes_z;
 589         bool discard;
 590 };
 591
 592 /* Special nir_load_input intrinsic index for loading the current TLB
 593  * destination color.
 594  */
 595 #define V3D_NIR_TLB_COLOR_READ_INPUT            2000000000
 596
 597 #define V3D_NIR_MS_MASK_OUTPUT                  2000000000
 598
 599 extern const nir_shader_compiler_options v3d_nir_options;
 600
 601 const struct v3d_compiler *v3d_compiler_init(const struct v3d_device_info *devinfo);
 602 void v3d_compiler_free(const struct v3d_compiler *compiler);
 603 void v3d_optimize_nir(struct nir_shader *s);
 604
 605 uint64_t *v3d_compile_vs(const struct v3d_compiler *compiler,
 606                          struct v3d_vs_key *key,
 607                          struct v3d_vs_prog_data *prog_data,
 608                          nir_shader *s,
 609                          int program_id, int variant_id,
 610                          uint32_t *final_assembly_size);
 611
 612 uint64_t *v3d_compile_fs(const struct v3d_compiler *compiler,
 613                          struct v3d_fs_key *key,
 614                          struct v3d_fs_prog_data *prog_data,
 615                          nir_shader *s,
 616                          int program_id, int variant_id,
 617                          uint32_t *final_assembly_size);
 618
 619 void v3d_nir_to_vir(struct v3d_compile *c);
 620
 621 void vir_compile_destroy(struct v3d_compile *c);
 622 const char *vir_get_stage_name(struct v3d_compile *c);
 623 struct qblock *vir_new_block(struct v3d_compile *c);
 624 void vir_set_emit_block(struct v3d_compile *c, struct qblock *block);
 625 void vir_link_blocks(struct qblock *predecessor, struct qblock *successor);
 626 struct qblock *vir_entry_block(struct v3d_compile *c);
 627 struct qblock *vir_exit_block(struct v3d_compile *c);
 628 struct qinst *vir_add_inst(enum v3d_qpu_add_op op, struct qreg dst,
 629                            struct qreg src0, struct qreg src1);
 630 struct qinst *vir_mul_inst(enum v3d_qpu_mul_op op, struct qreg dst,
 631                            struct qreg src0, struct qreg src1);
 632 struct qinst *vir_branch_inst(enum v3d_qpu_branch_cond cond, struct qreg src0);
 633 void vir_remove_instruction(struct v3d_compile *c, struct qinst *qinst);
 634 struct qreg vir_uniform(struct v3d_compile *c,
 635                         enum quniform_contents contents,
 636                         uint32_t data);
 637 void vir_schedule_instructions(struct v3d_compile *c);
 638 struct v3d_qpu_instr v3d_qpu_nop(void);
 639
 640 struct qreg vir_emit_def(struct v3d_compile *c, struct qinst *inst);
 641 struct qinst *vir_emit_nondef(struct v3d_compile *c, struct qinst *inst);
 642 void vir_set_cond(struct qinst *inst, enum v3d_qpu_cond cond);
 643 void vir_set_pf(struct qinst *inst, enum v3d_qpu_pf pf);
 644 void vir_set_unpack(struct qinst *inst, int src,
 645                     enum v3d_qpu_input_unpack unpack);
 646
 647 struct qreg vir_get_temp(struct v3d_compile *c);
 648 void vir_calculate_live_intervals(struct v3d_compile *c);
 649 bool vir_has_implicit_uniform(struct qinst *inst);
 650 int vir_get_implicit_uniform_src(struct qinst *inst);
 651 int vir_get_non_sideband_nsrc(struct qinst *inst);
 652 int vir_get_nsrc(struct qinst *inst);
 653 bool vir_has_side_effects(struct v3d_compile *c, struct qinst *inst);
 654 bool vir_get_add_op(struct qinst *inst, enum v3d_qpu_add_op *op);
 655 bool vir_get_mul_op(struct qinst *inst, enum v3d_qpu_mul_op *op);
 656 bool vir_is_raw_mov(struct qinst *inst);
 657 bool vir_is_tex(struct qinst *inst);
 658 bool vir_is_add(struct qinst *inst);
 659 bool vir_is_mul(struct qinst *inst);
 660 bool vir_is_float_input(struct qinst *inst);
 661 bool vir_depends_on_flags(struct qinst *inst);
 662 bool vir_writes_r3(struct qinst *inst);
 663 bool vir_writes_r4(struct qinst *inst);
 664 struct qreg vir_follow_movs(struct v3d_compile *c, struct qreg reg);
 665 uint8_t vir_channels_written(struct qinst *inst);
 666
 667 void vir_dump(struct v3d_compile *c);
 668 void vir_dump_inst(struct v3d_compile *c, struct qinst *inst);
 669
 670 void vir_validate(struct v3d_compile *c);
 671
 672 void vir_optimize(struct v3d_compile *c);
 673 bool vir_opt_algebraic(struct v3d_compile *c);
 674 bool vir_opt_constant_folding(struct v3d_compile *c);
 675 bool vir_opt_copy_propagate(struct v3d_compile *c);
 676 bool vir_opt_dead_code(struct v3d_compile *c);
 677 bool vir_opt_peephole_sf(struct v3d_compile *c);
 678 bool vir_opt_small_immediates(struct v3d_compile *c);
 679 bool vir_opt_vpm(struct v3d_compile *c);
 680 void v3d_nir_lower_blend(nir_shader *s, struct v3d_compile *c);
 681 void v3d_nir_lower_io(nir_shader *s, struct v3d_compile *c);
 682 void v3d_nir_lower_txf_ms(nir_shader *s, struct v3d_compile *c);
 683 void vir_lower_uniforms(struct v3d_compile *c);
 684
 685 void v3d_vir_to_qpu(struct v3d_compile *c);
 686 uint32_t v3d_qpu_schedule_instructions(struct v3d_compile *c);
 687 void qpu_validate(struct v3d_compile *c);
 688 struct qpu_reg *v3d_register_allocate(struct v3d_compile *c);
 689 bool vir_init_reg_sets(struct v3d_compiler *compiler);
 690
 691 void vir_PF(struct v3d_compile *c, struct qreg src, enum v3d_qpu_pf pf);
 692
 693 static inline bool
 694 quniform_contents_is_texture_p0(enum quniform_contents contents)
 695 {
 696         return (contents >= QUNIFORM_TEXTURE_CONFIG_P0_0 &&
 697                 contents < (QUNIFORM_TEXTURE_CONFIG_P0_0 +
 698                             V3D_MAX_TEXTURE_SAMPLERS));
 699 }
 700
 701 static inline struct qreg
 702 vir_uniform_ui(struct v3d_compile *c, uint32_t ui)
 703 {
 704         return vir_uniform(c, QUNIFORM_CONSTANT, ui);
 705 }
 706
 707 static inline struct qreg
 708 vir_uniform_f(struct v3d_compile *c, float f)
 709 {
 710         return vir_uniform(c, QUNIFORM_CONSTANT, fui(f));
 711 }
 712
 713 #define VIR_ALU0(name, vir_inst, op)                                     \
 714 static inline struct qreg                                                \
 715 vir_##name(struct v3d_compile *c)                                        \
 716 {                                                                        \
 717         return vir_emit_def(c, vir_inst(op, c->undef,                    \
 718                                         c->undef, c->undef));            \
 719 }                                                                        \
 720 static inline struct qinst *                                             \
 721 vir_##name##_dest(struct v3d_compile *c, struct qreg dest)               \
 722 {                                                                        \
 723         return vir_emit_nondef(c, vir_inst(op, dest,                     \
 724                                            c->undef, c->undef));         \
 725 }
 726
 727 #define VIR_ALU1(name, vir_inst, op)                                     \
 728 static inline struct qreg                                                \
 729 vir_##name(struct v3d_compile *c, struct qreg a)                         \
 730 {                                                                        \
 731         return vir_emit_def(c, vir_inst(op, c->undef,                    \
 732                                         a, c->undef));                   \
 733 }                                                                        \
 734 static inline struct qinst *                                             \
 735 vir_##name##_dest(struct v3d_compile *c, struct qreg dest,               \
 736                   struct qreg a)                                         \
 737 {                                                                        \
 738         return vir_emit_nondef(c, vir_inst(op, dest, a,          \
 739                                            c->undef));                   \
 740 }
 741
 742 #define VIR_ALU2(name, vir_inst, op)                                       \
 743 static inline struct qreg                                                \
 744 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b)          \
 745 {                                                                        \
 746         return vir_emit_def(c, vir_inst(op, c->undef, a, b));    \
 747 }                                                                        \
 748 static inline struct qinst *                                             \
 749 vir_##name##_dest(struct v3d_compile *c, struct qreg dest,               \
 750                   struct qreg a, struct qreg b)                          \
 751 {                                                                        \
 752         return vir_emit_nondef(c, vir_inst(op, dest, a, b));     \
 753 }
 754
 755 #define VIR_NODST_1(name, vir_inst, op)                                               \
 756 static inline struct qinst *                                            \
 757 vir_##name(struct v3d_compile *c, struct qreg a)                        \
 758 {                                                                       \
 759         return vir_emit_nondef(c, vir_inst(op, c->undef,        \
 760                                            a, c->undef));               \
 761 }
 762
 763 #define VIR_NODST_2(name, vir_inst, op)                                               \
 764 static inline struct qinst *                                            \
 765 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b)         \
 766 {                                                                       \
 767         return vir_emit_nondef(c, vir_inst(op, c->undef,                \
 768                                            a, b));                      \
 769 }
 770
 771 #define VIR_A_ALU2(name) VIR_ALU2(name, vir_add_inst, V3D_QPU_A_##name)
 772 #define VIR_M_ALU2(name) VIR_ALU2(name, vir_mul_inst, V3D_QPU_M_##name)
 773 #define VIR_A_ALU1(name) VIR_ALU1(name, vir_add_inst, V3D_QPU_A_##name)
 774 #define VIR_M_ALU1(name) VIR_ALU1(name, vir_mul_inst, V3D_QPU_M_##name)
 775 #define VIR_A_ALU0(name) VIR_ALU0(name, vir_add_inst, V3D_QPU_A_##name)
 776 #define VIR_M_ALU0(name) VIR_ALU0(name, vir_mul_inst, V3D_QPU_M_##name)
 777 #define VIR_A_NODST_2(name) VIR_NODST_2(name, vir_add_inst, V3D_QPU_A_##name)
 778 #define VIR_M_NODST_2(name) VIR_NODST_2(name, vir_mul_inst, V3D_QPU_M_##name)
 779 #define VIR_A_NODST_1(name) VIR_NODST_1(name, vir_add_inst, V3D_QPU_A_##name)
 780 #define VIR_M_NODST_1(name) VIR_NODST_1(name, vir_mul_inst, V3D_QPU_M_##name)
 781
 782 VIR_A_ALU2(FADD)
 783 VIR_A_ALU2(VFPACK)
 784 VIR_A_ALU2(FSUB)
 785 VIR_A_ALU2(FMIN)
 786 VIR_A_ALU2(FMAX)
 787
 788 VIR_A_ALU2(ADD)
 789 VIR_A_ALU2(SUB)
 790 VIR_A_ALU2(SHL)
 791 VIR_A_ALU2(SHR)
 792 VIR_A_ALU2(ASR)
 793 VIR_A_ALU2(ROR)
 794 VIR_A_ALU2(MIN)
 795 VIR_A_ALU2(MAX)
 796 VIR_A_ALU2(UMIN)
 797 VIR_A_ALU2(UMAX)
 798 VIR_A_ALU2(AND)
 799 VIR_A_ALU2(OR)
 800 VIR_A_ALU2(XOR)
 801 VIR_A_ALU2(VADD)
 802 VIR_A_ALU2(VSUB)
 803 VIR_A_ALU1(NOT)
 804 VIR_A_ALU1(NEG)
 805 VIR_A_ALU1(FLAPUSH)
 806 VIR_A_ALU1(FLBPUSH)
 807 VIR_A_ALU1(FLBPOP)
 808 VIR_A_ALU1(SETMSF)
 809 VIR_A_ALU1(SETREVF)
 810 VIR_A_ALU1(TIDX)
 811 VIR_A_ALU1(EIDX)
 812
 813 VIR_A_ALU0(FXCD)
 814 VIR_A_ALU0(XCD)
 815 VIR_A_ALU0(FYCD)
 816 VIR_A_ALU0(YCD)
 817 VIR_A_ALU0(MSF)
 818 VIR_A_ALU0(REVF)
 819 VIR_A_NODST_1(VPMSETUP)
 820 VIR_A_ALU2(FCMP)
 821 VIR_A_ALU2(VFMAX)
 822
 823 VIR_A_ALU1(FROUND)
 824 VIR_A_ALU1(FTOIN)
 825 VIR_A_ALU1(FTRUNC)
 826 VIR_A_ALU1(FTOIZ)
 827 VIR_A_ALU1(FFLOOR)
 828 VIR_A_ALU1(FTOUZ)
 829 VIR_A_ALU1(FCEIL)
 830 VIR_A_ALU1(FTOC)
 831
 832 VIR_A_ALU1(FDX)
 833 VIR_A_ALU1(FDY)
 834
 835 VIR_A_ALU1(ITOF)
 836 VIR_A_ALU1(CLZ)
 837 VIR_A_ALU1(UTOF)
 838
 839 VIR_M_ALU2(UMUL24)
 840 VIR_M_ALU2(FMUL)
 841 VIR_M_ALU2(SMUL24)
 842 VIR_M_NODST_2(MULTOP)
 843
 844 VIR_M_ALU1(MOV)
 845 VIR_M_ALU1(FMOV)
 846
 847 static inline struct qinst *
 848 vir_MOV_cond(struct v3d_compile *c, enum v3d_qpu_cond cond,
 849              struct qreg dest, struct qreg src)
 850 {
 851         struct qinst *mov = vir_MOV_dest(c, dest, src);
 852         vir_set_cond(mov, cond);
 853         return mov;
 854 }
 855
 856 static inline struct qreg
 857 vir_SEL(struct v3d_compile *c, enum v3d_qpu_cond cond,
 858         struct qreg src0, struct qreg src1)
 859 {
 860         struct qreg t = vir_get_temp(c);
 861         vir_MOV_dest(c, t, src1);
 862         vir_MOV_cond(c, cond, t, src0);
 863         return t;
 864 }
 865
 866 static inline void
 867 vir_VPM_WRITE(struct v3d_compile *c, struct qreg val)
 868 {
 869         vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM), val);
 870 }
 871
 872 static inline struct qinst *
 873 vir_NOP(struct v3d_compile *c)
 874 {
 875         return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_NOP,
 876                                                c->undef, c->undef, c->undef));
 877 }
 878 /*
 879 static inline struct qreg
 880 vir_LOAD_IMM(struct v3d_compile *c, uint32_t val)
 881 {
 882         return vir_emit_def(c, vir_inst(QOP_LOAD_IMM, c->undef,
 883                                         vir_reg(QFILE_LOAD_IMM, val), c->undef));
 884 }
 885
 886 static inline struct qreg
 887 vir_LOAD_IMM_U2(struct v3d_compile *c, uint32_t val)
 888 {
 889         return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_U2, c->undef,
 890                                         vir_reg(QFILE_LOAD_IMM, val),
 891                                         c->undef));
 892 }
 893 static inline struct qreg
 894 vir_LOAD_IMM_I2(struct v3d_compile *c, uint32_t val)
 895 {
 896         return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_I2, c->undef,
 897                                         vir_reg(QFILE_LOAD_IMM, val),
 898                                         c->undef));
 899 }
 900 */
 901
 902 static inline struct qinst *
 903 vir_BRANCH(struct v3d_compile *c, enum v3d_qpu_cond cond)
 904 {
 905         /* The actual uniform_data value will be set at scheduling time */
 906         return vir_emit_nondef(c, vir_branch_inst(cond, vir_uniform_ui(c, 0)));
 907 }
 908
 909 #define vir_for_each_block(block, c)                                    \
 910         list_for_each_entry(struct qblock, block, &c->blocks, link)
 911
 912 #define vir_for_each_block_rev(block, c)                                \
 913         list_for_each_entry_rev(struct qblock, block, &c->blocks, link)
 914
 915 /* Loop over the non-NULL members of the successors array. */
 916 #define vir_for_each_successor(succ, block)                             \
 917         for (struct qblock *succ = block->successors[0];                \
 918              succ != NULL;                                              \
 919              succ = (succ == block->successors[1] ? NULL :              \
 920                      block->successors[1]))
 921
 922 #define vir_for_each_inst(inst, block)                                  \
 923         list_for_each_entry(struct qinst, inst, &block->instructions, link)
 924
 925 #define vir_for_each_inst_rev(inst, block)                                  \
 926         list_for_each_entry_rev(struct qinst, inst, &block->instructions, link)
 927
 928 #define vir_for_each_inst_safe(inst, block)                             \
 929         list_for_each_entry_safe(struct qinst, inst, &block->instructions, link)
 930
 931 #define vir_for_each_inst_inorder(inst, c)                              \
 932         vir_for_each_block(_block, c)                                   \
 933                 vir_for_each_inst(inst, _block)
 934
 935 #endif /* V3D_COMPILER_H */