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[mesa.git] / src / broadcom / compiler / vir.c
1 /*
2 * Copyright © 2016-2017 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "broadcom/common/v3d_device_info.h"
25 #include "v3d_compiler.h"
26 #include "util/u_prim.h"
27 #include "compiler/nir/nir_schedule.h"
28
29 int
30 vir_get_nsrc(struct qinst *inst)
31 {
32 switch (inst->qpu.type) {
33 case V3D_QPU_INSTR_TYPE_BRANCH:
34 return 0;
35 case V3D_QPU_INSTR_TYPE_ALU:
36 if (inst->qpu.alu.add.op != V3D_QPU_A_NOP)
37 return v3d_qpu_add_op_num_src(inst->qpu.alu.add.op);
38 else
39 return v3d_qpu_mul_op_num_src(inst->qpu.alu.mul.op);
40 }
41
42 return 0;
43 }
44
45 /**
46 * Returns whether the instruction has any side effects that must be
47 * preserved.
48 */
49 bool
50 vir_has_side_effects(struct v3d_compile *c, struct qinst *inst)
51 {
52 switch (inst->qpu.type) {
53 case V3D_QPU_INSTR_TYPE_BRANCH:
54 return true;
55 case V3D_QPU_INSTR_TYPE_ALU:
56 switch (inst->qpu.alu.add.op) {
57 case V3D_QPU_A_SETREVF:
58 case V3D_QPU_A_SETMSF:
59 case V3D_QPU_A_VPMSETUP:
60 case V3D_QPU_A_STVPMV:
61 case V3D_QPU_A_STVPMD:
62 case V3D_QPU_A_STVPMP:
63 case V3D_QPU_A_VPMWT:
64 case V3D_QPU_A_TMUWT:
65 return true;
66 default:
67 break;
68 }
69
70 switch (inst->qpu.alu.mul.op) {
71 case V3D_QPU_M_MULTOP:
72 return true;
73 default:
74 break;
75 }
76 }
77
78 if (inst->qpu.sig.ldtmu ||
79 inst->qpu.sig.ldvary ||
80 inst->qpu.sig.ldtlbu ||
81 inst->qpu.sig.ldtlb ||
82 inst->qpu.sig.wrtmuc ||
83 inst->qpu.sig.thrsw) {
84 return true;
85 }
86
87 return false;
88 }
89
90 bool
91 vir_is_raw_mov(struct qinst *inst)
92 {
93 if (inst->qpu.type != V3D_QPU_INSTR_TYPE_ALU ||
94 (inst->qpu.alu.mul.op != V3D_QPU_M_FMOV &&
95 inst->qpu.alu.mul.op != V3D_QPU_M_MOV)) {
96 return false;
97 }
98
99 if (inst->qpu.alu.add.output_pack != V3D_QPU_PACK_NONE ||
100 inst->qpu.alu.mul.output_pack != V3D_QPU_PACK_NONE) {
101 return false;
102 }
103
104 if (inst->qpu.alu.add.a_unpack != V3D_QPU_UNPACK_NONE ||
105 inst->qpu.alu.add.b_unpack != V3D_QPU_UNPACK_NONE ||
106 inst->qpu.alu.mul.a_unpack != V3D_QPU_UNPACK_NONE ||
107 inst->qpu.alu.mul.b_unpack != V3D_QPU_UNPACK_NONE) {
108 return false;
109 }
110
111 if (inst->qpu.flags.ac != V3D_QPU_COND_NONE ||
112 inst->qpu.flags.mc != V3D_QPU_COND_NONE)
113 return false;
114
115 return true;
116 }
117
118 bool
119 vir_is_add(struct qinst *inst)
120 {
121 return (inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU &&
122 inst->qpu.alu.add.op != V3D_QPU_A_NOP);
123 }
124
125 bool
126 vir_is_mul(struct qinst *inst)
127 {
128 return (inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU &&
129 inst->qpu.alu.mul.op != V3D_QPU_M_NOP);
130 }
131
132 bool
133 vir_is_tex(struct qinst *inst)
134 {
135 if (inst->dst.file == QFILE_MAGIC)
136 return v3d_qpu_magic_waddr_is_tmu(inst->dst.index);
137
138 if (inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU &&
139 inst->qpu.alu.add.op == V3D_QPU_A_TMUWT) {
140 return true;
141 }
142
143 return false;
144 }
145
146 bool
147 vir_writes_r3(const struct v3d_device_info *devinfo, struct qinst *inst)
148 {
149 for (int i = 0; i < vir_get_nsrc(inst); i++) {
150 switch (inst->src[i].file) {
151 case QFILE_VPM:
152 return true;
153 default:
154 break;
155 }
156 }
157
158 if (devinfo->ver < 41 && (inst->qpu.sig.ldvary ||
159 inst->qpu.sig.ldtlb ||
160 inst->qpu.sig.ldtlbu ||
161 inst->qpu.sig.ldvpm)) {
162 return true;
163 }
164
165 return false;
166 }
167
168 bool
169 vir_writes_r4(const struct v3d_device_info *devinfo, struct qinst *inst)
170 {
171 switch (inst->dst.file) {
172 case QFILE_MAGIC:
173 switch (inst->dst.index) {
174 case V3D_QPU_WADDR_RECIP:
175 case V3D_QPU_WADDR_RSQRT:
176 case V3D_QPU_WADDR_EXP:
177 case V3D_QPU_WADDR_LOG:
178 case V3D_QPU_WADDR_SIN:
179 return true;
180 }
181 break;
182 default:
183 break;
184 }
185
186 if (devinfo->ver < 41 && inst->qpu.sig.ldtmu)
187 return true;
188
189 return false;
190 }
191
192 void
193 vir_set_unpack(struct qinst *inst, int src,
194 enum v3d_qpu_input_unpack unpack)
195 {
196 assert(src == 0 || src == 1);
197
198 if (vir_is_add(inst)) {
199 if (src == 0)
200 inst->qpu.alu.add.a_unpack = unpack;
201 else
202 inst->qpu.alu.add.b_unpack = unpack;
203 } else {
204 assert(vir_is_mul(inst));
205 if (src == 0)
206 inst->qpu.alu.mul.a_unpack = unpack;
207 else
208 inst->qpu.alu.mul.b_unpack = unpack;
209 }
210 }
211
212 void
213 vir_set_cond(struct qinst *inst, enum v3d_qpu_cond cond)
214 {
215 if (vir_is_add(inst)) {
216 inst->qpu.flags.ac = cond;
217 } else {
218 assert(vir_is_mul(inst));
219 inst->qpu.flags.mc = cond;
220 }
221 }
222
223 void
224 vir_set_pf(struct qinst *inst, enum v3d_qpu_pf pf)
225 {
226 if (vir_is_add(inst)) {
227 inst->qpu.flags.apf = pf;
228 } else {
229 assert(vir_is_mul(inst));
230 inst->qpu.flags.mpf = pf;
231 }
232 }
233
234 void
235 vir_set_uf(struct qinst *inst, enum v3d_qpu_uf uf)
236 {
237 if (vir_is_add(inst)) {
238 inst->qpu.flags.auf = uf;
239 } else {
240 assert(vir_is_mul(inst));
241 inst->qpu.flags.muf = uf;
242 }
243 }
244
245 #if 0
246 uint8_t
247 vir_channels_written(struct qinst *inst)
248 {
249 if (vir_is_mul(inst)) {
250 switch (inst->dst.pack) {
251 case QPU_PACK_MUL_NOP:
252 case QPU_PACK_MUL_8888:
253 return 0xf;
254 case QPU_PACK_MUL_8A:
255 return 0x1;
256 case QPU_PACK_MUL_8B:
257 return 0x2;
258 case QPU_PACK_MUL_8C:
259 return 0x4;
260 case QPU_PACK_MUL_8D:
261 return 0x8;
262 }
263 } else {
264 switch (inst->dst.pack) {
265 case QPU_PACK_A_NOP:
266 case QPU_PACK_A_8888:
267 case QPU_PACK_A_8888_SAT:
268 case QPU_PACK_A_32_SAT:
269 return 0xf;
270 case QPU_PACK_A_8A:
271 case QPU_PACK_A_8A_SAT:
272 return 0x1;
273 case QPU_PACK_A_8B:
274 case QPU_PACK_A_8B_SAT:
275 return 0x2;
276 case QPU_PACK_A_8C:
277 case QPU_PACK_A_8C_SAT:
278 return 0x4;
279 case QPU_PACK_A_8D:
280 case QPU_PACK_A_8D_SAT:
281 return 0x8;
282 case QPU_PACK_A_16A:
283 case QPU_PACK_A_16A_SAT:
284 return 0x3;
285 case QPU_PACK_A_16B:
286 case QPU_PACK_A_16B_SAT:
287 return 0xc;
288 }
289 }
290 unreachable("Bad pack field");
291 }
292 #endif
293
294 struct qreg
295 vir_get_temp(struct v3d_compile *c)
296 {
297 struct qreg reg;
298
299 reg.file = QFILE_TEMP;
300 reg.index = c->num_temps++;
301
302 if (c->num_temps > c->defs_array_size) {
303 uint32_t old_size = c->defs_array_size;
304 c->defs_array_size = MAX2(old_size * 2, 16);
305
306 c->defs = reralloc(c, c->defs, struct qinst *,
307 c->defs_array_size);
308 memset(&c->defs[old_size], 0,
309 sizeof(c->defs[0]) * (c->defs_array_size - old_size));
310
311 c->spillable = reralloc(c, c->spillable,
312 BITSET_WORD,
313 BITSET_WORDS(c->defs_array_size));
314 for (int i = old_size; i < c->defs_array_size; i++)
315 BITSET_SET(c->spillable, i);
316 }
317
318 return reg;
319 }
320
321 struct qinst *
322 vir_add_inst(enum v3d_qpu_add_op op, struct qreg dst, struct qreg src0, struct qreg src1)
323 {
324 struct qinst *inst = calloc(1, sizeof(*inst));
325
326 inst->qpu = v3d_qpu_nop();
327 inst->qpu.alu.add.op = op;
328
329 inst->dst = dst;
330 inst->src[0] = src0;
331 inst->src[1] = src1;
332 inst->uniform = ~0;
333
334 return inst;
335 }
336
337 struct qinst *
338 vir_mul_inst(enum v3d_qpu_mul_op op, struct qreg dst, struct qreg src0, struct qreg src1)
339 {
340 struct qinst *inst = calloc(1, sizeof(*inst));
341
342 inst->qpu = v3d_qpu_nop();
343 inst->qpu.alu.mul.op = op;
344
345 inst->dst = dst;
346 inst->src[0] = src0;
347 inst->src[1] = src1;
348 inst->uniform = ~0;
349
350 return inst;
351 }
352
353 struct qinst *
354 vir_branch_inst(struct v3d_compile *c, enum v3d_qpu_branch_cond cond)
355 {
356 struct qinst *inst = calloc(1, sizeof(*inst));
357
358 inst->qpu = v3d_qpu_nop();
359 inst->qpu.type = V3D_QPU_INSTR_TYPE_BRANCH;
360 inst->qpu.branch.cond = cond;
361 inst->qpu.branch.msfign = V3D_QPU_MSFIGN_NONE;
362 inst->qpu.branch.bdi = V3D_QPU_BRANCH_DEST_REL;
363 inst->qpu.branch.ub = true;
364 inst->qpu.branch.bdu = V3D_QPU_BRANCH_DEST_REL;
365
366 inst->dst = vir_nop_reg();
367 inst->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT, 0);
368
369 return inst;
370 }
371
372 static void
373 vir_emit(struct v3d_compile *c, struct qinst *inst)
374 {
375 switch (c->cursor.mode) {
376 case vir_cursor_add:
377 list_add(&inst->link, c->cursor.link);
378 break;
379 case vir_cursor_addtail:
380 list_addtail(&inst->link, c->cursor.link);
381 break;
382 }
383
384 c->cursor = vir_after_inst(inst);
385 c->live_intervals_valid = false;
386 }
387
388 /* Updates inst to write to a new temporary, emits it, and notes the def. */
389 struct qreg
390 vir_emit_def(struct v3d_compile *c, struct qinst *inst)
391 {
392 assert(inst->dst.file == QFILE_NULL);
393
394 /* If we're emitting an instruction that's a def, it had better be
395 * writing a register.
396 */
397 if (inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU) {
398 assert(inst->qpu.alu.add.op == V3D_QPU_A_NOP ||
399 v3d_qpu_add_op_has_dst(inst->qpu.alu.add.op));
400 assert(inst->qpu.alu.mul.op == V3D_QPU_M_NOP ||
401 v3d_qpu_mul_op_has_dst(inst->qpu.alu.mul.op));
402 }
403
404 inst->dst = vir_get_temp(c);
405
406 if (inst->dst.file == QFILE_TEMP)
407 c->defs[inst->dst.index] = inst;
408
409 vir_emit(c, inst);
410
411 return inst->dst;
412 }
413
414 struct qinst *
415 vir_emit_nondef(struct v3d_compile *c, struct qinst *inst)
416 {
417 if (inst->dst.file == QFILE_TEMP)
418 c->defs[inst->dst.index] = NULL;
419
420 vir_emit(c, inst);
421
422 return inst;
423 }
424
425 struct qblock *
426 vir_new_block(struct v3d_compile *c)
427 {
428 struct qblock *block = rzalloc(c, struct qblock);
429
430 list_inithead(&block->instructions);
431
432 block->predecessors = _mesa_set_create(block,
433 _mesa_hash_pointer,
434 _mesa_key_pointer_equal);
435
436 block->index = c->next_block_index++;
437
438 return block;
439 }
440
441 void
442 vir_set_emit_block(struct v3d_compile *c, struct qblock *block)
443 {
444 c->cur_block = block;
445 c->cursor = vir_after_block(block);
446 list_addtail(&block->link, &c->blocks);
447 }
448
449 struct qblock *
450 vir_entry_block(struct v3d_compile *c)
451 {
452 return list_first_entry(&c->blocks, struct qblock, link);
453 }
454
455 struct qblock *
456 vir_exit_block(struct v3d_compile *c)
457 {
458 return list_last_entry(&c->blocks, struct qblock, link);
459 }
460
461 void
462 vir_link_blocks(struct qblock *predecessor, struct qblock *successor)
463 {
464 _mesa_set_add(successor->predecessors, predecessor);
465 if (predecessor->successors[0]) {
466 assert(!predecessor->successors[1]);
467 predecessor->successors[1] = successor;
468 } else {
469 predecessor->successors[0] = successor;
470 }
471 }
472
473 const struct v3d_compiler *
474 v3d_compiler_init(const struct v3d_device_info *devinfo)
475 {
476 struct v3d_compiler *compiler = rzalloc(NULL, struct v3d_compiler);
477 if (!compiler)
478 return NULL;
479
480 compiler->devinfo = devinfo;
481
482 if (!vir_init_reg_sets(compiler)) {
483 ralloc_free(compiler);
484 return NULL;
485 }
486
487 return compiler;
488 }
489
490 void
491 v3d_compiler_free(const struct v3d_compiler *compiler)
492 {
493 ralloc_free((void *)compiler);
494 }
495
496 static struct v3d_compile *
497 vir_compile_init(const struct v3d_compiler *compiler,
498 struct v3d_key *key,
499 nir_shader *s,
500 void (*debug_output)(const char *msg,
501 void *debug_output_data),
502 void *debug_output_data,
503 int program_id, int variant_id)
504 {
505 struct v3d_compile *c = rzalloc(NULL, struct v3d_compile);
506
507 c->compiler = compiler;
508 c->devinfo = compiler->devinfo;
509 c->key = key;
510 c->program_id = program_id;
511 c->variant_id = variant_id;
512 c->threads = 4;
513 c->debug_output = debug_output;
514 c->debug_output_data = debug_output_data;
515
516 s = nir_shader_clone(c, s);
517 c->s = s;
518
519 list_inithead(&c->blocks);
520 vir_set_emit_block(c, vir_new_block(c));
521
522 c->output_position_index = -1;
523 c->output_sample_mask_index = -1;
524
525 c->def_ht = _mesa_hash_table_create(c, _mesa_hash_pointer,
526 _mesa_key_pointer_equal);
527
528 return c;
529 }
530
531 static int
532 type_size_vec4(const struct glsl_type *type, bool bindless)
533 {
534 return glsl_count_attribute_slots(type, false);
535 }
536
537 static void
538 v3d_lower_nir(struct v3d_compile *c)
539 {
540 struct nir_lower_tex_options tex_options = {
541 .lower_txd = true,
542 .lower_tg4_broadcom_swizzle = true,
543
544 .lower_rect = false, /* XXX: Use this on V3D 3.x */
545 .lower_txp = ~0,
546 /* Apply swizzles to all samplers. */
547 .swizzle_result = ~0,
548 };
549
550 /* Lower the format swizzle and (for 32-bit returns)
551 * ARB_texture_swizzle-style swizzle.
552 */
553 for (int i = 0; i < ARRAY_SIZE(c->key->tex); i++) {
554 for (int j = 0; j < 4; j++)
555 tex_options.swizzles[i][j] = c->key->tex[i].swizzle[j];
556
557 if (c->key->tex[i].clamp_s)
558 tex_options.saturate_s |= 1 << i;
559 if (c->key->tex[i].clamp_t)
560 tex_options.saturate_t |= 1 << i;
561 if (c->key->tex[i].clamp_r)
562 tex_options.saturate_r |= 1 << i;
563 if (c->key->tex[i].return_size == 16) {
564 tex_options.lower_tex_packing[i] =
565 nir_lower_tex_packing_16;
566 }
567 }
568
569 /* CS textures may not have return_size reflecting the shadow state. */
570 nir_foreach_variable(var, &c->s->uniforms) {
571 const struct glsl_type *type = glsl_without_array(var->type);
572 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
573
574 if (!glsl_type_is_sampler(type) ||
575 !glsl_sampler_type_is_shadow(type))
576 continue;
577
578 for (int i = 0; i < array_len; i++) {
579 tex_options.lower_tex_packing[var->data.binding + i] =
580 nir_lower_tex_packing_16;
581 }
582 }
583
584 NIR_PASS_V(c->s, nir_lower_tex, &tex_options);
585 NIR_PASS_V(c->s, nir_lower_system_values);
586
587 NIR_PASS_V(c->s, nir_lower_vars_to_scratch,
588 nir_var_function_temp,
589 0,
590 glsl_get_natural_size_align_bytes);
591 NIR_PASS_V(c->s, v3d_nir_lower_scratch);
592 }
593
594 static void
595 v3d_set_prog_data_uniforms(struct v3d_compile *c,
596 struct v3d_prog_data *prog_data)
597 {
598 int count = c->num_uniforms;
599 struct v3d_uniform_list *ulist = &prog_data->uniforms;
600
601 ulist->count = count;
602 ulist->data = ralloc_array(prog_data, uint32_t, count);
603 memcpy(ulist->data, c->uniform_data,
604 count * sizeof(*ulist->data));
605 ulist->contents = ralloc_array(prog_data, enum quniform_contents, count);
606 memcpy(ulist->contents, c->uniform_contents,
607 count * sizeof(*ulist->contents));
608 }
609
610 static void
611 v3d_vs_set_prog_data(struct v3d_compile *c,
612 struct v3d_vs_prog_data *prog_data)
613 {
614 /* The vertex data gets format converted by the VPM so that
615 * each attribute channel takes up a VPM column. Precompute
616 * the sizes for the shader record.
617 */
618 for (int i = 0; i < ARRAY_SIZE(prog_data->vattr_sizes); i++) {
619 prog_data->vattr_sizes[i] = c->vattr_sizes[i];
620 prog_data->vpm_input_size += c->vattr_sizes[i];
621 }
622
623 prog_data->uses_vid = (c->s->info.system_values_read &
624 (1ull << SYSTEM_VALUE_VERTEX_ID));
625 prog_data->uses_iid = (c->s->info.system_values_read &
626 (1ull << SYSTEM_VALUE_INSTANCE_ID));
627
628 if (prog_data->uses_vid)
629 prog_data->vpm_input_size++;
630 if (prog_data->uses_iid)
631 prog_data->vpm_input_size++;
632
633 /* Input/output segment size are in sectors (8 rows of 32 bits per
634 * channel).
635 */
636 prog_data->vpm_input_size = align(prog_data->vpm_input_size, 8) / 8;
637 prog_data->vpm_output_size = align(c->vpm_output_size, 8) / 8;
638
639 /* Set us up for shared input/output segments. This is apparently
640 * necessary for our VCM setup to avoid varying corruption.
641 */
642 prog_data->separate_segments = false;
643 prog_data->vpm_output_size = MAX2(prog_data->vpm_output_size,
644 prog_data->vpm_input_size);
645 prog_data->vpm_input_size = 0;
646
647 /* Compute VCM cache size. We set up our program to take up less than
648 * half of the VPM, so that any set of bin and render programs won't
649 * run out of space. We need space for at least one input segment,
650 * and then allocate the rest to output segments (one for the current
651 * program, the rest to VCM). The valid range of the VCM cache size
652 * field is 1-4 16-vertex batches, but GFXH-1744 limits us to 2-4
653 * batches.
654 */
655 assert(c->devinfo->vpm_size);
656 int sector_size = V3D_CHANNELS * sizeof(uint32_t) * 8;
657 int vpm_size_in_sectors = c->devinfo->vpm_size / sector_size;
658 int half_vpm = vpm_size_in_sectors / 2;
659 int vpm_output_sectors = half_vpm - prog_data->vpm_input_size;
660 int vpm_output_batches = vpm_output_sectors / prog_data->vpm_output_size;
661 assert(vpm_output_batches >= 2);
662 prog_data->vcm_cache_size = CLAMP(vpm_output_batches - 1, 2, 4);
663 }
664
665 static void
666 v3d_gs_set_prog_data(struct v3d_compile *c,
667 struct v3d_gs_prog_data *prog_data)
668 {
669 prog_data->num_inputs = c->num_inputs;
670 memcpy(prog_data->input_slots, c->input_slots,
671 c->num_inputs * sizeof(*c->input_slots));
672
673 /* gl_PrimitiveIdIn is written by the GBG into the first word of the
674 * VPM output header automatically and the shader will overwrite
675 * it after reading it if necessary, so it doesn't add to the VPM
676 * size requirements.
677 */
678 prog_data->uses_pid = (c->s->info.system_values_read &
679 (1ull << SYSTEM_VALUE_PRIMITIVE_ID));
680
681 /* Output segment size is in sectors (8 rows of 32 bits per channel) */
682 prog_data->vpm_output_size = align(c->vpm_output_size, 8) / 8;
683
684 /* Compute SIMD dispatch width and update VPM output size accordingly
685 * to ensure we can fit our program in memory. Available widths are
686 * 16, 8, 4, 1.
687 *
688 * Notice that at draw time we will have to consider VPM memory
689 * requirements from other stages and choose a smaller dispatch
690 * width if needed to fit the program in VPM memory.
691 */
692 prog_data->simd_width = 16;
693 while ((prog_data->simd_width > 1 && prog_data->vpm_output_size > 16) ||
694 prog_data->simd_width == 2) {
695 prog_data->simd_width >>= 1;
696 prog_data->vpm_output_size =
697 align(prog_data->vpm_output_size, 2) / 2;
698 }
699 assert(prog_data->vpm_output_size <= 16);
700 assert(prog_data->simd_width != 2);
701
702 prog_data->out_prim_type = c->s->info.gs.output_primitive;
703 prog_data->num_invocations = c->s->info.gs.invocations;
704 }
705
706 static void
707 v3d_set_fs_prog_data_inputs(struct v3d_compile *c,
708 struct v3d_fs_prog_data *prog_data)
709 {
710 prog_data->num_inputs = c->num_inputs;
711 memcpy(prog_data->input_slots, c->input_slots,
712 c->num_inputs * sizeof(*c->input_slots));
713
714 STATIC_ASSERT(ARRAY_SIZE(prog_data->flat_shade_flags) >
715 (V3D_MAX_FS_INPUTS - 1) / 24);
716 for (int i = 0; i < V3D_MAX_FS_INPUTS; i++) {
717 if (BITSET_TEST(c->flat_shade_flags, i))
718 prog_data->flat_shade_flags[i / 24] |= 1 << (i % 24);
719
720 if (BITSET_TEST(c->noperspective_flags, i))
721 prog_data->noperspective_flags[i / 24] |= 1 << (i % 24);
722
723 if (BITSET_TEST(c->centroid_flags, i))
724 prog_data->centroid_flags[i / 24] |= 1 << (i % 24);
725 }
726 }
727
728 static void
729 v3d_fs_set_prog_data(struct v3d_compile *c,
730 struct v3d_fs_prog_data *prog_data)
731 {
732 v3d_set_fs_prog_data_inputs(c, prog_data);
733 prog_data->writes_z = c->writes_z;
734 prog_data->disable_ez = !c->s->info.fs.early_fragment_tests;
735 prog_data->uses_center_w = c->uses_center_w;
736 prog_data->uses_implicit_point_line_varyings =
737 c->uses_implicit_point_line_varyings;
738 prog_data->lock_scoreboard_on_first_thrsw =
739 c->lock_scoreboard_on_first_thrsw;
740 }
741
742 static void
743 v3d_cs_set_prog_data(struct v3d_compile *c,
744 struct v3d_compute_prog_data *prog_data)
745 {
746 prog_data->shared_size = c->s->info.cs.shared_size;
747 }
748
749 static void
750 v3d_set_prog_data(struct v3d_compile *c,
751 struct v3d_prog_data *prog_data)
752 {
753 prog_data->threads = c->threads;
754 prog_data->single_seg = !c->last_thrsw;
755 prog_data->spill_size = c->spill_size;
756 prog_data->tmu_dirty_rcl = c->tmu_dirty_rcl;
757
758 v3d_set_prog_data_uniforms(c, prog_data);
759
760 switch (c->s->info.stage) {
761 case MESA_SHADER_VERTEX:
762 v3d_vs_set_prog_data(c, (struct v3d_vs_prog_data *)prog_data);
763 break;
764 case MESA_SHADER_GEOMETRY:
765 v3d_gs_set_prog_data(c, (struct v3d_gs_prog_data *)prog_data);
766 break;
767 case MESA_SHADER_FRAGMENT:
768 v3d_fs_set_prog_data(c, (struct v3d_fs_prog_data *)prog_data);
769 break;
770 case MESA_SHADER_COMPUTE:
771 v3d_cs_set_prog_data(c, (struct v3d_compute_prog_data *)prog_data);
772 break;
773 default:
774 unreachable("unsupported shader stage");
775 }
776 }
777
778 static uint64_t *
779 v3d_return_qpu_insts(struct v3d_compile *c, uint32_t *final_assembly_size)
780 {
781 *final_assembly_size = c->qpu_inst_count * sizeof(uint64_t);
782
783 uint64_t *qpu_insts = malloc(*final_assembly_size);
784 if (!qpu_insts)
785 return NULL;
786
787 memcpy(qpu_insts, c->qpu_insts, *final_assembly_size);
788
789 vir_compile_destroy(c);
790
791 return qpu_insts;
792 }
793
794 static void
795 v3d_nir_lower_vs_early(struct v3d_compile *c)
796 {
797 /* Split our I/O vars and dead code eliminate the unused
798 * components.
799 */
800 NIR_PASS_V(c->s, nir_lower_io_to_scalar_early,
801 nir_var_shader_in | nir_var_shader_out);
802 uint64_t used_outputs[4] = {0};
803 for (int i = 0; i < c->vs_key->num_used_outputs; i++) {
804 int slot = v3d_slot_get_slot(c->vs_key->used_outputs[i]);
805 int comp = v3d_slot_get_component(c->vs_key->used_outputs[i]);
806 used_outputs[comp] |= 1ull << slot;
807 }
808 NIR_PASS_V(c->s, nir_remove_unused_io_vars,
809 &c->s->outputs, used_outputs, NULL); /* demotes to globals */
810 NIR_PASS_V(c->s, nir_lower_global_vars_to_local);
811 v3d_optimize_nir(c->s);
812 NIR_PASS_V(c->s, nir_remove_dead_variables, nir_var_shader_in, NULL);
813
814 /* This must go before nir_lower_io */
815 if (c->vs_key->per_vertex_point_size)
816 NIR_PASS_V(c->s, nir_lower_point_size, 1.0f, 0.0f);
817
818 NIR_PASS_V(c->s, nir_lower_io, nir_var_shader_in | nir_var_shader_out,
819 type_size_vec4,
820 (nir_lower_io_options)0);
821 /* clean up nir_lower_io's deref_var remains */
822 NIR_PASS_V(c->s, nir_opt_dce);
823 }
824
825 static void
826 v3d_nir_lower_gs_early(struct v3d_compile *c)
827 {
828 /* Split our I/O vars and dead code eliminate the unused
829 * components.
830 */
831 NIR_PASS_V(c->s, nir_lower_io_to_scalar_early,
832 nir_var_shader_in | nir_var_shader_out);
833 uint64_t used_outputs[4] = {0};
834 for (int i = 0; i < c->gs_key->num_used_outputs; i++) {
835 int slot = v3d_slot_get_slot(c->gs_key->used_outputs[i]);
836 int comp = v3d_slot_get_component(c->gs_key->used_outputs[i]);
837 used_outputs[comp] |= 1ull << slot;
838 }
839 NIR_PASS_V(c->s, nir_remove_unused_io_vars,
840 &c->s->outputs, used_outputs, NULL); /* demotes to globals */
841 NIR_PASS_V(c->s, nir_lower_global_vars_to_local);
842 v3d_optimize_nir(c->s);
843 NIR_PASS_V(c->s, nir_remove_dead_variables, nir_var_shader_in, NULL);
844
845 /* This must go before nir_lower_io */
846 if (c->gs_key->per_vertex_point_size)
847 NIR_PASS_V(c->s, nir_lower_point_size, 1.0f, 0.0f);
848
849 NIR_PASS_V(c->s, nir_lower_io, nir_var_shader_in | nir_var_shader_out,
850 type_size_vec4,
851 (nir_lower_io_options)0);
852 /* clean up nir_lower_io's deref_var remains */
853 NIR_PASS_V(c->s, nir_opt_dce);
854 }
855
856 static void
857 v3d_fixup_fs_output_types(struct v3d_compile *c)
858 {
859 nir_foreach_variable(var, &c->s->outputs) {
860 uint32_t mask = 0;
861
862 switch (var->data.location) {
863 case FRAG_RESULT_COLOR:
864 mask = ~0;
865 break;
866 case FRAG_RESULT_DATA0:
867 case FRAG_RESULT_DATA1:
868 case FRAG_RESULT_DATA2:
869 case FRAG_RESULT_DATA3:
870 mask = 1 << (var->data.location - FRAG_RESULT_DATA0);
871 break;
872 }
873
874 if (c->fs_key->int_color_rb & mask) {
875 var->type =
876 glsl_vector_type(GLSL_TYPE_INT,
877 glsl_get_components(var->type));
878 } else if (c->fs_key->uint_color_rb & mask) {
879 var->type =
880 glsl_vector_type(GLSL_TYPE_UINT,
881 glsl_get_components(var->type));
882 }
883 }
884 }
885
886 static void
887 v3d_nir_lower_fs_early(struct v3d_compile *c)
888 {
889 if (c->fs_key->int_color_rb || c->fs_key->uint_color_rb)
890 v3d_fixup_fs_output_types(c);
891
892 NIR_PASS_V(c->s, v3d_nir_lower_logic_ops, c);
893
894 if (c->fs_key->line_smoothing) {
895 v3d_nir_lower_line_smooth(c->s);
896 NIR_PASS_V(c->s, nir_lower_global_vars_to_local);
897 /* The lowering pass can introduce new sysval reads */
898 nir_shader_gather_info(c->s, nir_shader_get_entrypoint(c->s));
899 }
900
901 /* If the shader has no non-TLB side effects, we can promote it to
902 * enabling early_fragment_tests even if the user didn't.
903 */
904 if (!(c->s->info.num_images ||
905 c->s->info.num_ssbos)) {
906 c->s->info.fs.early_fragment_tests = true;
907 }
908 }
909
910 static void
911 v3d_nir_lower_gs_late(struct v3d_compile *c)
912 {
913 if (c->key->ucp_enables) {
914 NIR_PASS_V(c->s, nir_lower_clip_gs, c->key->ucp_enables,
915 false, NULL);
916 }
917
918 /* Note: GS output scalarizing must happen after nir_lower_clip_gs. */
919 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_out);
920 }
921
922 static void
923 v3d_nir_lower_vs_late(struct v3d_compile *c)
924 {
925 if (c->vs_key->clamp_color)
926 NIR_PASS_V(c->s, nir_lower_clamp_color_outputs);
927
928 if (c->key->ucp_enables) {
929 NIR_PASS_V(c->s, nir_lower_clip_vs, c->key->ucp_enables,
930 false, false, NULL);
931 NIR_PASS_V(c->s, nir_lower_io_to_scalar,
932 nir_var_shader_out);
933 }
934
935 /* Note: VS output scalarizing must happen after nir_lower_clip_vs. */
936 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_out);
937 }
938
939 static void
940 v3d_nir_lower_fs_late(struct v3d_compile *c)
941 {
942 if (c->fs_key->light_twoside)
943 NIR_PASS_V(c->s, nir_lower_two_sided_color, true);
944
945 if (c->fs_key->clamp_color)
946 NIR_PASS_V(c->s, nir_lower_clamp_color_outputs);
947
948 if (c->fs_key->alpha_test) {
949 NIR_PASS_V(c->s, nir_lower_alpha_test,
950 c->fs_key->alpha_test_func,
951 false, NULL);
952 }
953
954 if (c->key->ucp_enables)
955 NIR_PASS_V(c->s, nir_lower_clip_fs, c->key->ucp_enables,
956 false);
957
958 /* Note: FS input scalarizing must happen after
959 * nir_lower_two_sided_color, which only handles a vec4 at a time.
960 */
961 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_in);
962 }
963
964 static uint32_t
965 vir_get_max_temps(struct v3d_compile *c)
966 {
967 int max_ip = 0;
968 vir_for_each_inst_inorder(inst, c)
969 max_ip++;
970
971 uint32_t *pressure = rzalloc_array(NULL, uint32_t, max_ip);
972
973 for (int t = 0; t < c->num_temps; t++) {
974 for (int i = c->temp_start[t]; (i < c->temp_end[t] &&
975 i < max_ip); i++) {
976 if (i > max_ip)
977 break;
978 pressure[i]++;
979 }
980 }
981
982 uint32_t max_temps = 0;
983 for (int i = 0; i < max_ip; i++)
984 max_temps = MAX2(max_temps, pressure[i]);
985
986 ralloc_free(pressure);
987
988 return max_temps;
989 }
990
991 uint64_t *v3d_compile(const struct v3d_compiler *compiler,
992 struct v3d_key *key,
993 struct v3d_prog_data **out_prog_data,
994 nir_shader *s,
995 void (*debug_output)(const char *msg,
996 void *debug_output_data),
997 void *debug_output_data,
998 int program_id, int variant_id,
999 uint32_t *final_assembly_size)
1000 {
1001 struct v3d_prog_data *prog_data;
1002 struct v3d_compile *c = vir_compile_init(compiler, key, s,
1003 debug_output, debug_output_data,
1004 program_id, variant_id);
1005
1006 switch (c->s->info.stage) {
1007 case MESA_SHADER_VERTEX:
1008 c->vs_key = (struct v3d_vs_key *)key;
1009 prog_data = rzalloc_size(NULL, sizeof(struct v3d_vs_prog_data));
1010 break;
1011 case MESA_SHADER_GEOMETRY:
1012 c->gs_key = (struct v3d_gs_key *)key;
1013 prog_data = rzalloc_size(NULL, sizeof(struct v3d_gs_prog_data));
1014 break;
1015 case MESA_SHADER_FRAGMENT:
1016 c->fs_key = (struct v3d_fs_key *)key;
1017 prog_data = rzalloc_size(NULL, sizeof(struct v3d_fs_prog_data));
1018 break;
1019 case MESA_SHADER_COMPUTE:
1020 prog_data = rzalloc_size(NULL,
1021 sizeof(struct v3d_compute_prog_data));
1022 break;
1023 default:
1024 unreachable("unsupported shader stage");
1025 }
1026
1027
1028 switch (c->s->info.stage) {
1029 case MESA_SHADER_VERTEX:
1030 v3d_nir_lower_vs_early(c);
1031 break;
1032 case MESA_SHADER_GEOMETRY:
1033 v3d_nir_lower_gs_early(c);
1034 break;
1035 case MESA_SHADER_FRAGMENT:
1036 v3d_nir_lower_fs_early(c);
1037 break;
1038 default:
1039 break;
1040 }
1041
1042 v3d_lower_nir(c);
1043
1044 switch (c->s->info.stage) {
1045 case MESA_SHADER_VERTEX:
1046 v3d_nir_lower_vs_late(c);
1047 break;
1048 case MESA_SHADER_GEOMETRY:
1049 v3d_nir_lower_gs_late(c);
1050 break;
1051 case MESA_SHADER_FRAGMENT:
1052 v3d_nir_lower_fs_late(c);
1053 break;
1054 default:
1055 break;
1056 }
1057
1058 NIR_PASS_V(c->s, v3d_nir_lower_io, c);
1059 NIR_PASS_V(c->s, v3d_nir_lower_txf_ms, c);
1060 NIR_PASS_V(c->s, v3d_nir_lower_image_load_store);
1061 NIR_PASS_V(c->s, nir_lower_idiv, nir_lower_idiv_fast);
1062
1063 v3d_optimize_nir(c->s);
1064
1065 /* Do late algebraic optimization to turn add(a, neg(b)) back into
1066 * subs, then the mandatory cleanup after algebraic. Note that it may
1067 * produce fnegs, and if so then we need to keep running to squash
1068 * fneg(fneg(a)).
1069 */
1070 bool more_late_algebraic = true;
1071 while (more_late_algebraic) {
1072 more_late_algebraic = false;
1073 NIR_PASS(more_late_algebraic, c->s, nir_opt_algebraic_late);
1074 NIR_PASS_V(c->s, nir_opt_constant_folding);
1075 NIR_PASS_V(c->s, nir_copy_prop);
1076 NIR_PASS_V(c->s, nir_opt_dce);
1077 NIR_PASS_V(c->s, nir_opt_cse);
1078 }
1079
1080 NIR_PASS_V(c->s, nir_lower_bool_to_int32);
1081 NIR_PASS_V(c->s, nir_convert_from_ssa, true);
1082
1083 static const struct nir_schedule_options schedule_options = {
1084 /* Schedule for about half our register space, to enable more
1085 * shaders to hit 4 threads.
1086 */
1087 .threshold = 24,
1088
1089 /* Vertex shaders share the same memory for inputs and outputs,
1090 * fragement and geometry shaders do not.
1091 */
1092 .stages_with_shared_io_memory =
1093 (((1 << MESA_ALL_SHADER_STAGES) - 1) &
1094 ~((1 << MESA_SHADER_FRAGMENT) |
1095 (1 << MESA_SHADER_GEOMETRY))),
1096 };
1097 NIR_PASS_V(c->s, nir_schedule, &schedule_options);
1098
1099 v3d_nir_to_vir(c);
1100
1101 v3d_set_prog_data(c, prog_data);
1102
1103 *out_prog_data = prog_data;
1104
1105 char *shaderdb;
1106 int ret = asprintf(&shaderdb,
1107 "%s shader: %d inst, %d threads, %d loops, "
1108 "%d uniforms, %d max-temps, %d:%d spills:fills, "
1109 "%d sfu-stalls, %d inst-and-stalls",
1110 vir_get_stage_name(c),
1111 c->qpu_inst_count,
1112 c->threads,
1113 c->loops,
1114 c->num_uniforms,
1115 vir_get_max_temps(c),
1116 c->spills,
1117 c->fills,
1118 c->qpu_inst_stalled_count,
1119 c->qpu_inst_count + c->qpu_inst_stalled_count);
1120 if (ret >= 0) {
1121 if (V3D_DEBUG & V3D_DEBUG_SHADERDB)
1122 fprintf(stderr, "SHADER-DB: %s\n", shaderdb);
1123
1124 c->debug_output(shaderdb, c->debug_output_data);
1125 free(shaderdb);
1126 }
1127
1128 return v3d_return_qpu_insts(c, final_assembly_size);
1129 }
1130
1131 void
1132 vir_remove_instruction(struct v3d_compile *c, struct qinst *qinst)
1133 {
1134 if (qinst->dst.file == QFILE_TEMP)
1135 c->defs[qinst->dst.index] = NULL;
1136
1137 assert(&qinst->link != c->cursor.link);
1138
1139 list_del(&qinst->link);
1140 free(qinst);
1141
1142 c->live_intervals_valid = false;
1143 }
1144
1145 struct qreg
1146 vir_follow_movs(struct v3d_compile *c, struct qreg reg)
1147 {
1148 /* XXX
1149 int pack = reg.pack;
1150
1151 while (reg.file == QFILE_TEMP &&
1152 c->defs[reg.index] &&
1153 (c->defs[reg.index]->op == QOP_MOV ||
1154 c->defs[reg.index]->op == QOP_FMOV) &&
1155 !c->defs[reg.index]->dst.pack &&
1156 !c->defs[reg.index]->src[0].pack) {
1157 reg = c->defs[reg.index]->src[0];
1158 }
1159
1160 reg.pack = pack;
1161 */
1162 return reg;
1163 }
1164
1165 void
1166 vir_compile_destroy(struct v3d_compile *c)
1167 {
1168 /* Defuse the assert that we aren't removing the cursor's instruction.
1169 */
1170 c->cursor.link = NULL;
1171
1172 vir_for_each_block(block, c) {
1173 while (!list_is_empty(&block->instructions)) {
1174 struct qinst *qinst =
1175 list_first_entry(&block->instructions,
1176 struct qinst, link);
1177 vir_remove_instruction(c, qinst);
1178 }
1179 }
1180
1181 ralloc_free(c);
1182 }
1183
1184 uint32_t
1185 vir_get_uniform_index(struct v3d_compile *c,
1186 enum quniform_contents contents,
1187 uint32_t data)
1188 {
1189 for (int i = 0; i < c->num_uniforms; i++) {
1190 if (c->uniform_contents[i] == contents &&
1191 c->uniform_data[i] == data) {
1192 return i;
1193 }
1194 }
1195
1196 uint32_t uniform = c->num_uniforms++;
1197
1198 if (uniform >= c->uniform_array_size) {
1199 c->uniform_array_size = MAX2(MAX2(16, uniform + 1),
1200 c->uniform_array_size * 2);
1201
1202 c->uniform_data = reralloc(c, c->uniform_data,
1203 uint32_t,
1204 c->uniform_array_size);
1205 c->uniform_contents = reralloc(c, c->uniform_contents,
1206 enum quniform_contents,
1207 c->uniform_array_size);
1208 }
1209
1210 c->uniform_contents[uniform] = contents;
1211 c->uniform_data[uniform] = data;
1212
1213 return uniform;
1214 }
1215
1216 struct qreg
1217 vir_uniform(struct v3d_compile *c,
1218 enum quniform_contents contents,
1219 uint32_t data)
1220 {
1221 struct qinst *inst = vir_NOP(c);
1222 inst->qpu.sig.ldunif = true;
1223 inst->uniform = vir_get_uniform_index(c, contents, data);
1224 inst->dst = vir_get_temp(c);
1225 c->defs[inst->dst.index] = inst;
1226 return inst->dst;
1227 }
1228
1229 #define OPTPASS(func) \
1230 do { \
1231 bool stage_progress = func(c); \
1232 if (stage_progress) { \
1233 progress = true; \
1234 if (print_opt_debug) { \
1235 fprintf(stderr, \
1236 "VIR opt pass %2d: %s progress\n", \
1237 pass, #func); \
1238 } \
1239 /*XXX vir_validate(c);*/ \
1240 } \
1241 } while (0)
1242
1243 void
1244 vir_optimize(struct v3d_compile *c)
1245 {
1246 bool print_opt_debug = false;
1247 int pass = 1;
1248
1249 while (true) {
1250 bool progress = false;
1251
1252 OPTPASS(vir_opt_copy_propagate);
1253 OPTPASS(vir_opt_redundant_flags);
1254 OPTPASS(vir_opt_dead_code);
1255 OPTPASS(vir_opt_small_immediates);
1256
1257 if (!progress)
1258 break;
1259
1260 pass++;
1261 }
1262 }
1263
1264 const char *
1265 vir_get_stage_name(struct v3d_compile *c)
1266 {
1267 if (c->vs_key && c->vs_key->is_coord)
1268 return "MESA_SHADER_VERTEX_BIN";
1269 else if (c->gs_key && c->gs_key->is_coord)
1270 return "MESA_SHADER_GEOMETRY_BIN";
1271 else
1272 return gl_shader_stage_name(c->s->info.stage);
1273 }