2 * Copyright © 2016-2017 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "broadcom/common/v3d_device_info.h"
25 #include "v3d_compiler.h"
26 #include "util/u_prim.h"
27 #include "compiler/nir/nir_schedule.h"
30 vir_get_nsrc(struct qinst
*inst
)
32 switch (inst
->qpu
.type
) {
33 case V3D_QPU_INSTR_TYPE_BRANCH
:
35 case V3D_QPU_INSTR_TYPE_ALU
:
36 if (inst
->qpu
.alu
.add
.op
!= V3D_QPU_A_NOP
)
37 return v3d_qpu_add_op_num_src(inst
->qpu
.alu
.add
.op
);
39 return v3d_qpu_mul_op_num_src(inst
->qpu
.alu
.mul
.op
);
46 * Returns whether the instruction has any side effects that must be
50 vir_has_side_effects(struct v3d_compile
*c
, struct qinst
*inst
)
52 switch (inst
->qpu
.type
) {
53 case V3D_QPU_INSTR_TYPE_BRANCH
:
55 case V3D_QPU_INSTR_TYPE_ALU
:
56 switch (inst
->qpu
.alu
.add
.op
) {
57 case V3D_QPU_A_SETREVF
:
58 case V3D_QPU_A_SETMSF
:
59 case V3D_QPU_A_VPMSETUP
:
60 case V3D_QPU_A_STVPMV
:
61 case V3D_QPU_A_STVPMD
:
62 case V3D_QPU_A_STVPMP
:
70 switch (inst
->qpu
.alu
.mul
.op
) {
71 case V3D_QPU_M_MULTOP
:
78 if (inst
->qpu
.sig
.ldtmu
||
79 inst
->qpu
.sig
.ldvary
||
80 inst
->qpu
.sig
.ldtlbu
||
81 inst
->qpu
.sig
.ldtlb
||
82 inst
->qpu
.sig
.wrtmuc
||
83 inst
->qpu
.sig
.thrsw
) {
91 vir_is_raw_mov(struct qinst
*inst
)
93 if (inst
->qpu
.type
!= V3D_QPU_INSTR_TYPE_ALU
||
94 (inst
->qpu
.alu
.mul
.op
!= V3D_QPU_M_FMOV
&&
95 inst
->qpu
.alu
.mul
.op
!= V3D_QPU_M_MOV
)) {
99 if (inst
->qpu
.alu
.add
.output_pack
!= V3D_QPU_PACK_NONE
||
100 inst
->qpu
.alu
.mul
.output_pack
!= V3D_QPU_PACK_NONE
) {
104 if (inst
->qpu
.alu
.add
.a_unpack
!= V3D_QPU_UNPACK_NONE
||
105 inst
->qpu
.alu
.add
.b_unpack
!= V3D_QPU_UNPACK_NONE
||
106 inst
->qpu
.alu
.mul
.a_unpack
!= V3D_QPU_UNPACK_NONE
||
107 inst
->qpu
.alu
.mul
.b_unpack
!= V3D_QPU_UNPACK_NONE
) {
111 if (inst
->qpu
.flags
.ac
!= V3D_QPU_COND_NONE
||
112 inst
->qpu
.flags
.mc
!= V3D_QPU_COND_NONE
)
119 vir_is_add(struct qinst
*inst
)
121 return (inst
->qpu
.type
== V3D_QPU_INSTR_TYPE_ALU
&&
122 inst
->qpu
.alu
.add
.op
!= V3D_QPU_A_NOP
);
126 vir_is_mul(struct qinst
*inst
)
128 return (inst
->qpu
.type
== V3D_QPU_INSTR_TYPE_ALU
&&
129 inst
->qpu
.alu
.mul
.op
!= V3D_QPU_M_NOP
);
133 vir_is_tex(struct qinst
*inst
)
135 if (inst
->dst
.file
== QFILE_MAGIC
)
136 return v3d_qpu_magic_waddr_is_tmu(inst
->dst
.index
);
138 if (inst
->qpu
.type
== V3D_QPU_INSTR_TYPE_ALU
&&
139 inst
->qpu
.alu
.add
.op
== V3D_QPU_A_TMUWT
) {
147 vir_writes_r3(const struct v3d_device_info
*devinfo
, struct qinst
*inst
)
149 for (int i
= 0; i
< vir_get_nsrc(inst
); i
++) {
150 switch (inst
->src
[i
].file
) {
158 if (devinfo
->ver
< 41 && (inst
->qpu
.sig
.ldvary
||
159 inst
->qpu
.sig
.ldtlb
||
160 inst
->qpu
.sig
.ldtlbu
||
161 inst
->qpu
.sig
.ldvpm
)) {
169 vir_writes_r4(const struct v3d_device_info
*devinfo
, struct qinst
*inst
)
171 switch (inst
->dst
.file
) {
173 switch (inst
->dst
.index
) {
174 case V3D_QPU_WADDR_RECIP
:
175 case V3D_QPU_WADDR_RSQRT
:
176 case V3D_QPU_WADDR_EXP
:
177 case V3D_QPU_WADDR_LOG
:
178 case V3D_QPU_WADDR_SIN
:
186 if (devinfo
->ver
< 41 && inst
->qpu
.sig
.ldtmu
)
193 vir_set_unpack(struct qinst
*inst
, int src
,
194 enum v3d_qpu_input_unpack unpack
)
196 assert(src
== 0 || src
== 1);
198 if (vir_is_add(inst
)) {
200 inst
->qpu
.alu
.add
.a_unpack
= unpack
;
202 inst
->qpu
.alu
.add
.b_unpack
= unpack
;
204 assert(vir_is_mul(inst
));
206 inst
->qpu
.alu
.mul
.a_unpack
= unpack
;
208 inst
->qpu
.alu
.mul
.b_unpack
= unpack
;
213 vir_set_cond(struct qinst
*inst
, enum v3d_qpu_cond cond
)
215 if (vir_is_add(inst
)) {
216 inst
->qpu
.flags
.ac
= cond
;
218 assert(vir_is_mul(inst
));
219 inst
->qpu
.flags
.mc
= cond
;
224 vir_set_pf(struct qinst
*inst
, enum v3d_qpu_pf pf
)
226 if (vir_is_add(inst
)) {
227 inst
->qpu
.flags
.apf
= pf
;
229 assert(vir_is_mul(inst
));
230 inst
->qpu
.flags
.mpf
= pf
;
235 vir_set_uf(struct qinst
*inst
, enum v3d_qpu_uf uf
)
237 if (vir_is_add(inst
)) {
238 inst
->qpu
.flags
.auf
= uf
;
240 assert(vir_is_mul(inst
));
241 inst
->qpu
.flags
.muf
= uf
;
247 vir_channels_written(struct qinst
*inst
)
249 if (vir_is_mul(inst
)) {
250 switch (inst
->dst
.pack
) {
251 case QPU_PACK_MUL_NOP
:
252 case QPU_PACK_MUL_8888
:
254 case QPU_PACK_MUL_8A
:
256 case QPU_PACK_MUL_8B
:
258 case QPU_PACK_MUL_8C
:
260 case QPU_PACK_MUL_8D
:
264 switch (inst
->dst
.pack
) {
266 case QPU_PACK_A_8888
:
267 case QPU_PACK_A_8888_SAT
:
268 case QPU_PACK_A_32_SAT
:
271 case QPU_PACK_A_8A_SAT
:
274 case QPU_PACK_A_8B_SAT
:
277 case QPU_PACK_A_8C_SAT
:
280 case QPU_PACK_A_8D_SAT
:
283 case QPU_PACK_A_16A_SAT
:
286 case QPU_PACK_A_16B_SAT
:
290 unreachable("Bad pack field");
295 vir_get_temp(struct v3d_compile
*c
)
299 reg
.file
= QFILE_TEMP
;
300 reg
.index
= c
->num_temps
++;
302 if (c
->num_temps
> c
->defs_array_size
) {
303 uint32_t old_size
= c
->defs_array_size
;
304 c
->defs_array_size
= MAX2(old_size
* 2, 16);
306 c
->defs
= reralloc(c
, c
->defs
, struct qinst
*,
308 memset(&c
->defs
[old_size
], 0,
309 sizeof(c
->defs
[0]) * (c
->defs_array_size
- old_size
));
311 c
->spillable
= reralloc(c
, c
->spillable
,
313 BITSET_WORDS(c
->defs_array_size
));
314 for (int i
= old_size
; i
< c
->defs_array_size
; i
++)
315 BITSET_SET(c
->spillable
, i
);
322 vir_add_inst(enum v3d_qpu_add_op op
, struct qreg dst
, struct qreg src0
, struct qreg src1
)
324 struct qinst
*inst
= calloc(1, sizeof(*inst
));
326 inst
->qpu
= v3d_qpu_nop();
327 inst
->qpu
.alu
.add
.op
= op
;
338 vir_mul_inst(enum v3d_qpu_mul_op op
, struct qreg dst
, struct qreg src0
, struct qreg src1
)
340 struct qinst
*inst
= calloc(1, sizeof(*inst
));
342 inst
->qpu
= v3d_qpu_nop();
343 inst
->qpu
.alu
.mul
.op
= op
;
354 vir_branch_inst(struct v3d_compile
*c
, enum v3d_qpu_branch_cond cond
)
356 struct qinst
*inst
= calloc(1, sizeof(*inst
));
358 inst
->qpu
= v3d_qpu_nop();
359 inst
->qpu
.type
= V3D_QPU_INSTR_TYPE_BRANCH
;
360 inst
->qpu
.branch
.cond
= cond
;
361 inst
->qpu
.branch
.msfign
= V3D_QPU_MSFIGN_NONE
;
362 inst
->qpu
.branch
.bdi
= V3D_QPU_BRANCH_DEST_REL
;
363 inst
->qpu
.branch
.ub
= true;
364 inst
->qpu
.branch
.bdu
= V3D_QPU_BRANCH_DEST_REL
;
366 inst
->dst
= vir_nop_reg();
367 inst
->uniform
= vir_get_uniform_index(c
, QUNIFORM_CONSTANT
, 0);
373 vir_emit(struct v3d_compile
*c
, struct qinst
*inst
)
375 switch (c
->cursor
.mode
) {
377 list_add(&inst
->link
, c
->cursor
.link
);
379 case vir_cursor_addtail
:
380 list_addtail(&inst
->link
, c
->cursor
.link
);
384 c
->cursor
= vir_after_inst(inst
);
385 c
->live_intervals_valid
= false;
388 /* Updates inst to write to a new temporary, emits it, and notes the def. */
390 vir_emit_def(struct v3d_compile
*c
, struct qinst
*inst
)
392 assert(inst
->dst
.file
== QFILE_NULL
);
394 /* If we're emitting an instruction that's a def, it had better be
395 * writing a register.
397 if (inst
->qpu
.type
== V3D_QPU_INSTR_TYPE_ALU
) {
398 assert(inst
->qpu
.alu
.add
.op
== V3D_QPU_A_NOP
||
399 v3d_qpu_add_op_has_dst(inst
->qpu
.alu
.add
.op
));
400 assert(inst
->qpu
.alu
.mul
.op
== V3D_QPU_M_NOP
||
401 v3d_qpu_mul_op_has_dst(inst
->qpu
.alu
.mul
.op
));
404 inst
->dst
= vir_get_temp(c
);
406 if (inst
->dst
.file
== QFILE_TEMP
)
407 c
->defs
[inst
->dst
.index
] = inst
;
415 vir_emit_nondef(struct v3d_compile
*c
, struct qinst
*inst
)
417 if (inst
->dst
.file
== QFILE_TEMP
)
418 c
->defs
[inst
->dst
.index
] = NULL
;
426 vir_new_block(struct v3d_compile
*c
)
428 struct qblock
*block
= rzalloc(c
, struct qblock
);
430 list_inithead(&block
->instructions
);
432 block
->predecessors
= _mesa_set_create(block
,
434 _mesa_key_pointer_equal
);
436 block
->index
= c
->next_block_index
++;
442 vir_set_emit_block(struct v3d_compile
*c
, struct qblock
*block
)
444 c
->cur_block
= block
;
445 c
->cursor
= vir_after_block(block
);
446 list_addtail(&block
->link
, &c
->blocks
);
450 vir_entry_block(struct v3d_compile
*c
)
452 return list_first_entry(&c
->blocks
, struct qblock
, link
);
456 vir_exit_block(struct v3d_compile
*c
)
458 return list_last_entry(&c
->blocks
, struct qblock
, link
);
462 vir_link_blocks(struct qblock
*predecessor
, struct qblock
*successor
)
464 _mesa_set_add(successor
->predecessors
, predecessor
);
465 if (predecessor
->successors
[0]) {
466 assert(!predecessor
->successors
[1]);
467 predecessor
->successors
[1] = successor
;
469 predecessor
->successors
[0] = successor
;
473 const struct v3d_compiler
*
474 v3d_compiler_init(const struct v3d_device_info
*devinfo
)
476 struct v3d_compiler
*compiler
= rzalloc(NULL
, struct v3d_compiler
);
480 compiler
->devinfo
= devinfo
;
482 if (!vir_init_reg_sets(compiler
)) {
483 ralloc_free(compiler
);
491 v3d_compiler_free(const struct v3d_compiler
*compiler
)
493 ralloc_free((void *)compiler
);
496 static struct v3d_compile
*
497 vir_compile_init(const struct v3d_compiler
*compiler
,
500 void (*debug_output
)(const char *msg
,
501 void *debug_output_data
),
502 void *debug_output_data
,
503 int program_id
, int variant_id
)
505 struct v3d_compile
*c
= rzalloc(NULL
, struct v3d_compile
);
507 c
->compiler
= compiler
;
508 c
->devinfo
= compiler
->devinfo
;
510 c
->program_id
= program_id
;
511 c
->variant_id
= variant_id
;
513 c
->debug_output
= debug_output
;
514 c
->debug_output_data
= debug_output_data
;
516 s
= nir_shader_clone(c
, s
);
519 list_inithead(&c
->blocks
);
520 vir_set_emit_block(c
, vir_new_block(c
));
522 c
->output_position_index
= -1;
523 c
->output_sample_mask_index
= -1;
525 c
->def_ht
= _mesa_hash_table_create(c
, _mesa_hash_pointer
,
526 _mesa_key_pointer_equal
);
532 type_size_vec4(const struct glsl_type
*type
, bool bindless
)
534 return glsl_count_attribute_slots(type
, false);
538 v3d_lower_nir(struct v3d_compile
*c
)
540 struct nir_lower_tex_options tex_options
= {
542 .lower_tg4_broadcom_swizzle
= true,
544 .lower_rect
= false, /* XXX: Use this on V3D 3.x */
546 /* Apply swizzles to all samplers. */
547 .swizzle_result
= ~0,
550 /* Lower the format swizzle and (for 32-bit returns)
551 * ARB_texture_swizzle-style swizzle.
553 for (int i
= 0; i
< ARRAY_SIZE(c
->key
->tex
); i
++) {
554 for (int j
= 0; j
< 4; j
++)
555 tex_options
.swizzles
[i
][j
] = c
->key
->tex
[i
].swizzle
[j
];
557 if (c
->key
->tex
[i
].clamp_s
)
558 tex_options
.saturate_s
|= 1 << i
;
559 if (c
->key
->tex
[i
].clamp_t
)
560 tex_options
.saturate_t
|= 1 << i
;
561 if (c
->key
->tex
[i
].clamp_r
)
562 tex_options
.saturate_r
|= 1 << i
;
563 if (c
->key
->tex
[i
].return_size
== 16) {
564 tex_options
.lower_tex_packing
[i
] =
565 nir_lower_tex_packing_16
;
569 /* CS textures may not have return_size reflecting the shadow state. */
570 nir_foreach_variable(var
, &c
->s
->uniforms
) {
571 const struct glsl_type
*type
= glsl_without_array(var
->type
);
572 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
574 if (!glsl_type_is_sampler(type
) ||
575 !glsl_sampler_type_is_shadow(type
))
578 for (int i
= 0; i
< array_len
; i
++) {
579 tex_options
.lower_tex_packing
[var
->data
.binding
+ i
] =
580 nir_lower_tex_packing_16
;
584 NIR_PASS_V(c
->s
, nir_lower_tex
, &tex_options
);
585 NIR_PASS_V(c
->s
, nir_lower_system_values
);
587 NIR_PASS_V(c
->s
, nir_lower_vars_to_scratch
,
588 nir_var_function_temp
,
590 glsl_get_natural_size_align_bytes
);
591 NIR_PASS_V(c
->s
, v3d_nir_lower_scratch
);
595 v3d_set_prog_data_uniforms(struct v3d_compile
*c
,
596 struct v3d_prog_data
*prog_data
)
598 int count
= c
->num_uniforms
;
599 struct v3d_uniform_list
*ulist
= &prog_data
->uniforms
;
601 ulist
->count
= count
;
602 ulist
->data
= ralloc_array(prog_data
, uint32_t, count
);
603 memcpy(ulist
->data
, c
->uniform_data
,
604 count
* sizeof(*ulist
->data
));
605 ulist
->contents
= ralloc_array(prog_data
, enum quniform_contents
, count
);
606 memcpy(ulist
->contents
, c
->uniform_contents
,
607 count
* sizeof(*ulist
->contents
));
611 v3d_vs_set_prog_data(struct v3d_compile
*c
,
612 struct v3d_vs_prog_data
*prog_data
)
614 /* The vertex data gets format converted by the VPM so that
615 * each attribute channel takes up a VPM column. Precompute
616 * the sizes for the shader record.
618 for (int i
= 0; i
< ARRAY_SIZE(prog_data
->vattr_sizes
); i
++) {
619 prog_data
->vattr_sizes
[i
] = c
->vattr_sizes
[i
];
620 prog_data
->vpm_input_size
+= c
->vattr_sizes
[i
];
623 prog_data
->uses_vid
= (c
->s
->info
.system_values_read
&
624 (1ull << SYSTEM_VALUE_VERTEX_ID
));
625 prog_data
->uses_iid
= (c
->s
->info
.system_values_read
&
626 (1ull << SYSTEM_VALUE_INSTANCE_ID
));
628 if (prog_data
->uses_vid
)
629 prog_data
->vpm_input_size
++;
630 if (prog_data
->uses_iid
)
631 prog_data
->vpm_input_size
++;
633 /* Input/output segment size are in sectors (8 rows of 32 bits per
636 prog_data
->vpm_input_size
= align(prog_data
->vpm_input_size
, 8) / 8;
637 prog_data
->vpm_output_size
= align(c
->vpm_output_size
, 8) / 8;
639 /* Set us up for shared input/output segments. This is apparently
640 * necessary for our VCM setup to avoid varying corruption.
642 prog_data
->separate_segments
= false;
643 prog_data
->vpm_output_size
= MAX2(prog_data
->vpm_output_size
,
644 prog_data
->vpm_input_size
);
645 prog_data
->vpm_input_size
= 0;
647 /* Compute VCM cache size. We set up our program to take up less than
648 * half of the VPM, so that any set of bin and render programs won't
649 * run out of space. We need space for at least one input segment,
650 * and then allocate the rest to output segments (one for the current
651 * program, the rest to VCM). The valid range of the VCM cache size
652 * field is 1-4 16-vertex batches, but GFXH-1744 limits us to 2-4
655 assert(c
->devinfo
->vpm_size
);
656 int sector_size
= V3D_CHANNELS
* sizeof(uint32_t) * 8;
657 int vpm_size_in_sectors
= c
->devinfo
->vpm_size
/ sector_size
;
658 int half_vpm
= vpm_size_in_sectors
/ 2;
659 int vpm_output_sectors
= half_vpm
- prog_data
->vpm_input_size
;
660 int vpm_output_batches
= vpm_output_sectors
/ prog_data
->vpm_output_size
;
661 assert(vpm_output_batches
>= 2);
662 prog_data
->vcm_cache_size
= CLAMP(vpm_output_batches
- 1, 2, 4);
666 v3d_gs_set_prog_data(struct v3d_compile
*c
,
667 struct v3d_gs_prog_data
*prog_data
)
669 prog_data
->num_inputs
= c
->num_inputs
;
670 memcpy(prog_data
->input_slots
, c
->input_slots
,
671 c
->num_inputs
* sizeof(*c
->input_slots
));
673 /* gl_PrimitiveIdIn is written by the GBG into the first word of the
674 * VPM output header automatically and the shader will overwrite
675 * it after reading it if necessary, so it doesn't add to the VPM
678 prog_data
->uses_pid
= (c
->s
->info
.system_values_read
&
679 (1ull << SYSTEM_VALUE_PRIMITIVE_ID
));
681 /* Output segment size is in sectors (8 rows of 32 bits per channel) */
682 prog_data
->vpm_output_size
= align(c
->vpm_output_size
, 8) / 8;
684 /* Compute SIMD dispatch width and update VPM output size accordingly
685 * to ensure we can fit our program in memory. Available widths are
688 * Notice that at draw time we will have to consider VPM memory
689 * requirements from other stages and choose a smaller dispatch
690 * width if needed to fit the program in VPM memory.
692 prog_data
->simd_width
= 16;
693 while ((prog_data
->simd_width
> 1 && prog_data
->vpm_output_size
> 16) ||
694 prog_data
->simd_width
== 2) {
695 prog_data
->simd_width
>>= 1;
696 prog_data
->vpm_output_size
=
697 align(prog_data
->vpm_output_size
, 2) / 2;
699 assert(prog_data
->vpm_output_size
<= 16);
700 assert(prog_data
->simd_width
!= 2);
702 prog_data
->out_prim_type
= c
->s
->info
.gs
.output_primitive
;
703 prog_data
->num_invocations
= c
->s
->info
.gs
.invocations
;
707 v3d_set_fs_prog_data_inputs(struct v3d_compile
*c
,
708 struct v3d_fs_prog_data
*prog_data
)
710 prog_data
->num_inputs
= c
->num_inputs
;
711 memcpy(prog_data
->input_slots
, c
->input_slots
,
712 c
->num_inputs
* sizeof(*c
->input_slots
));
714 STATIC_ASSERT(ARRAY_SIZE(prog_data
->flat_shade_flags
) >
715 (V3D_MAX_FS_INPUTS
- 1) / 24);
716 for (int i
= 0; i
< V3D_MAX_FS_INPUTS
; i
++) {
717 if (BITSET_TEST(c
->flat_shade_flags
, i
))
718 prog_data
->flat_shade_flags
[i
/ 24] |= 1 << (i
% 24);
720 if (BITSET_TEST(c
->noperspective_flags
, i
))
721 prog_data
->noperspective_flags
[i
/ 24] |= 1 << (i
% 24);
723 if (BITSET_TEST(c
->centroid_flags
, i
))
724 prog_data
->centroid_flags
[i
/ 24] |= 1 << (i
% 24);
729 v3d_fs_set_prog_data(struct v3d_compile
*c
,
730 struct v3d_fs_prog_data
*prog_data
)
732 v3d_set_fs_prog_data_inputs(c
, prog_data
);
733 prog_data
->writes_z
= c
->writes_z
;
734 prog_data
->disable_ez
= !c
->s
->info
.fs
.early_fragment_tests
;
735 prog_data
->uses_center_w
= c
->uses_center_w
;
736 prog_data
->uses_implicit_point_line_varyings
=
737 c
->uses_implicit_point_line_varyings
;
738 prog_data
->lock_scoreboard_on_first_thrsw
=
739 c
->lock_scoreboard_on_first_thrsw
;
743 v3d_cs_set_prog_data(struct v3d_compile
*c
,
744 struct v3d_compute_prog_data
*prog_data
)
746 prog_data
->shared_size
= c
->s
->info
.cs
.shared_size
;
750 v3d_set_prog_data(struct v3d_compile
*c
,
751 struct v3d_prog_data
*prog_data
)
753 prog_data
->threads
= c
->threads
;
754 prog_data
->single_seg
= !c
->last_thrsw
;
755 prog_data
->spill_size
= c
->spill_size
;
756 prog_data
->tmu_dirty_rcl
= c
->tmu_dirty_rcl
;
758 v3d_set_prog_data_uniforms(c
, prog_data
);
760 switch (c
->s
->info
.stage
) {
761 case MESA_SHADER_VERTEX
:
762 v3d_vs_set_prog_data(c
, (struct v3d_vs_prog_data
*)prog_data
);
764 case MESA_SHADER_GEOMETRY
:
765 v3d_gs_set_prog_data(c
, (struct v3d_gs_prog_data
*)prog_data
);
767 case MESA_SHADER_FRAGMENT
:
768 v3d_fs_set_prog_data(c
, (struct v3d_fs_prog_data
*)prog_data
);
770 case MESA_SHADER_COMPUTE
:
771 v3d_cs_set_prog_data(c
, (struct v3d_compute_prog_data
*)prog_data
);
774 unreachable("unsupported shader stage");
779 v3d_return_qpu_insts(struct v3d_compile
*c
, uint32_t *final_assembly_size
)
781 *final_assembly_size
= c
->qpu_inst_count
* sizeof(uint64_t);
783 uint64_t *qpu_insts
= malloc(*final_assembly_size
);
787 memcpy(qpu_insts
, c
->qpu_insts
, *final_assembly_size
);
789 vir_compile_destroy(c
);
795 v3d_nir_lower_vs_early(struct v3d_compile
*c
)
797 /* Split our I/O vars and dead code eliminate the unused
800 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar_early
,
801 nir_var_shader_in
| nir_var_shader_out
);
802 uint64_t used_outputs
[4] = {0};
803 for (int i
= 0; i
< c
->vs_key
->num_used_outputs
; i
++) {
804 int slot
= v3d_slot_get_slot(c
->vs_key
->used_outputs
[i
]);
805 int comp
= v3d_slot_get_component(c
->vs_key
->used_outputs
[i
]);
806 used_outputs
[comp
] |= 1ull << slot
;
808 NIR_PASS_V(c
->s
, nir_remove_unused_io_vars
,
809 &c
->s
->outputs
, used_outputs
, NULL
); /* demotes to globals */
810 NIR_PASS_V(c
->s
, nir_lower_global_vars_to_local
);
811 v3d_optimize_nir(c
->s
);
812 NIR_PASS_V(c
->s
, nir_remove_dead_variables
, nir_var_shader_in
, NULL
);
814 /* This must go before nir_lower_io */
815 if (c
->vs_key
->per_vertex_point_size
)
816 NIR_PASS_V(c
->s
, nir_lower_point_size
, 1.0f
, 0.0f
);
818 NIR_PASS_V(c
->s
, nir_lower_io
, nir_var_shader_in
| nir_var_shader_out
,
820 (nir_lower_io_options
)0);
821 /* clean up nir_lower_io's deref_var remains */
822 NIR_PASS_V(c
->s
, nir_opt_dce
);
826 v3d_nir_lower_gs_early(struct v3d_compile
*c
)
828 /* Split our I/O vars and dead code eliminate the unused
831 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar_early
,
832 nir_var_shader_in
| nir_var_shader_out
);
833 uint64_t used_outputs
[4] = {0};
834 for (int i
= 0; i
< c
->gs_key
->num_used_outputs
; i
++) {
835 int slot
= v3d_slot_get_slot(c
->gs_key
->used_outputs
[i
]);
836 int comp
= v3d_slot_get_component(c
->gs_key
->used_outputs
[i
]);
837 used_outputs
[comp
] |= 1ull << slot
;
839 NIR_PASS_V(c
->s
, nir_remove_unused_io_vars
,
840 &c
->s
->outputs
, used_outputs
, NULL
); /* demotes to globals */
841 NIR_PASS_V(c
->s
, nir_lower_global_vars_to_local
);
842 v3d_optimize_nir(c
->s
);
843 NIR_PASS_V(c
->s
, nir_remove_dead_variables
, nir_var_shader_in
, NULL
);
845 /* This must go before nir_lower_io */
846 if (c
->gs_key
->per_vertex_point_size
)
847 NIR_PASS_V(c
->s
, nir_lower_point_size
, 1.0f
, 0.0f
);
849 NIR_PASS_V(c
->s
, nir_lower_io
, nir_var_shader_in
| nir_var_shader_out
,
851 (nir_lower_io_options
)0);
852 /* clean up nir_lower_io's deref_var remains */
853 NIR_PASS_V(c
->s
, nir_opt_dce
);
857 v3d_fixup_fs_output_types(struct v3d_compile
*c
)
859 nir_foreach_variable(var
, &c
->s
->outputs
) {
862 switch (var
->data
.location
) {
863 case FRAG_RESULT_COLOR
:
866 case FRAG_RESULT_DATA0
:
867 case FRAG_RESULT_DATA1
:
868 case FRAG_RESULT_DATA2
:
869 case FRAG_RESULT_DATA3
:
870 mask
= 1 << (var
->data
.location
- FRAG_RESULT_DATA0
);
874 if (c
->fs_key
->int_color_rb
& mask
) {
876 glsl_vector_type(GLSL_TYPE_INT
,
877 glsl_get_components(var
->type
));
878 } else if (c
->fs_key
->uint_color_rb
& mask
) {
880 glsl_vector_type(GLSL_TYPE_UINT
,
881 glsl_get_components(var
->type
));
887 v3d_nir_lower_fs_early(struct v3d_compile
*c
)
889 if (c
->fs_key
->int_color_rb
|| c
->fs_key
->uint_color_rb
)
890 v3d_fixup_fs_output_types(c
);
892 NIR_PASS_V(c
->s
, v3d_nir_lower_logic_ops
, c
);
894 if (c
->fs_key
->line_smoothing
) {
895 v3d_nir_lower_line_smooth(c
->s
);
896 NIR_PASS_V(c
->s
, nir_lower_global_vars_to_local
);
897 /* The lowering pass can introduce new sysval reads */
898 nir_shader_gather_info(c
->s
, nir_shader_get_entrypoint(c
->s
));
901 /* If the shader has no non-TLB side effects, we can promote it to
902 * enabling early_fragment_tests even if the user didn't.
904 if (!(c
->s
->info
.num_images
||
905 c
->s
->info
.num_ssbos
)) {
906 c
->s
->info
.fs
.early_fragment_tests
= true;
911 v3d_nir_lower_gs_late(struct v3d_compile
*c
)
913 if (c
->key
->ucp_enables
) {
914 NIR_PASS_V(c
->s
, nir_lower_clip_gs
, c
->key
->ucp_enables
,
918 /* Note: GS output scalarizing must happen after nir_lower_clip_gs. */
919 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar
, nir_var_shader_out
);
923 v3d_nir_lower_vs_late(struct v3d_compile
*c
)
925 if (c
->vs_key
->clamp_color
)
926 NIR_PASS_V(c
->s
, nir_lower_clamp_color_outputs
);
928 if (c
->key
->ucp_enables
) {
929 NIR_PASS_V(c
->s
, nir_lower_clip_vs
, c
->key
->ucp_enables
,
931 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar
,
935 /* Note: VS output scalarizing must happen after nir_lower_clip_vs. */
936 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar
, nir_var_shader_out
);
940 v3d_nir_lower_fs_late(struct v3d_compile
*c
)
942 if (c
->fs_key
->light_twoside
)
943 NIR_PASS_V(c
->s
, nir_lower_two_sided_color
, true);
945 if (c
->fs_key
->clamp_color
)
946 NIR_PASS_V(c
->s
, nir_lower_clamp_color_outputs
);
948 if (c
->fs_key
->alpha_test
) {
949 NIR_PASS_V(c
->s
, nir_lower_alpha_test
,
950 c
->fs_key
->alpha_test_func
,
954 if (c
->key
->ucp_enables
)
955 NIR_PASS_V(c
->s
, nir_lower_clip_fs
, c
->key
->ucp_enables
,
958 /* Note: FS input scalarizing must happen after
959 * nir_lower_two_sided_color, which only handles a vec4 at a time.
961 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar
, nir_var_shader_in
);
965 vir_get_max_temps(struct v3d_compile
*c
)
968 vir_for_each_inst_inorder(inst
, c
)
971 uint32_t *pressure
= rzalloc_array(NULL
, uint32_t, max_ip
);
973 for (int t
= 0; t
< c
->num_temps
; t
++) {
974 for (int i
= c
->temp_start
[t
]; (i
< c
->temp_end
[t
] &&
982 uint32_t max_temps
= 0;
983 for (int i
= 0; i
< max_ip
; i
++)
984 max_temps
= MAX2(max_temps
, pressure
[i
]);
986 ralloc_free(pressure
);
991 enum v3d_dependency_class
{
992 V3D_DEPENDENCY_CLASS_GS_VPM_OUTPUT_0
996 v3d_intrinsic_dependency_cb(nir_intrinsic_instr
*intr
,
997 nir_schedule_dependency
*dep
,
1000 struct v3d_compile
*c
= user_data
;
1002 switch (intr
->intrinsic
) {
1003 case nir_intrinsic_store_output
:
1004 /* Writing to location 0 overwrites the value passed in for
1005 * gl_PrimitiveID on geometry shaders
1007 if (c
->s
->info
.stage
!= MESA_SHADER_GEOMETRY
||
1008 nir_intrinsic_base(intr
) != 0)
1011 nir_const_value
*const_value
=
1012 nir_src_as_const_value(intr
->src
[1]);
1014 if (const_value
== NULL
)
1018 nir_const_value_as_uint(*const_value
,
1019 nir_src_bit_size(intr
->src
[1]));
1023 dep
->klass
= V3D_DEPENDENCY_CLASS_GS_VPM_OUTPUT_0
;
1024 dep
->type
= NIR_SCHEDULE_WRITE_DEPENDENCY
;
1027 case nir_intrinsic_load_primitive_id
:
1028 if (c
->s
->info
.stage
!= MESA_SHADER_GEOMETRY
)
1031 dep
->klass
= V3D_DEPENDENCY_CLASS_GS_VPM_OUTPUT_0
;
1032 dep
->type
= NIR_SCHEDULE_READ_DEPENDENCY
;
1042 uint64_t *v3d_compile(const struct v3d_compiler
*compiler
,
1043 struct v3d_key
*key
,
1044 struct v3d_prog_data
**out_prog_data
,
1046 void (*debug_output
)(const char *msg
,
1047 void *debug_output_data
),
1048 void *debug_output_data
,
1049 int program_id
, int variant_id
,
1050 uint32_t *final_assembly_size
)
1052 struct v3d_prog_data
*prog_data
;
1053 struct v3d_compile
*c
= vir_compile_init(compiler
, key
, s
,
1054 debug_output
, debug_output_data
,
1055 program_id
, variant_id
);
1057 switch (c
->s
->info
.stage
) {
1058 case MESA_SHADER_VERTEX
:
1059 c
->vs_key
= (struct v3d_vs_key
*)key
;
1060 prog_data
= rzalloc_size(NULL
, sizeof(struct v3d_vs_prog_data
));
1062 case MESA_SHADER_GEOMETRY
:
1063 c
->gs_key
= (struct v3d_gs_key
*)key
;
1064 prog_data
= rzalloc_size(NULL
, sizeof(struct v3d_gs_prog_data
));
1066 case MESA_SHADER_FRAGMENT
:
1067 c
->fs_key
= (struct v3d_fs_key
*)key
;
1068 prog_data
= rzalloc_size(NULL
, sizeof(struct v3d_fs_prog_data
));
1070 case MESA_SHADER_COMPUTE
:
1071 prog_data
= rzalloc_size(NULL
,
1072 sizeof(struct v3d_compute_prog_data
));
1075 unreachable("unsupported shader stage");
1079 switch (c
->s
->info
.stage
) {
1080 case MESA_SHADER_VERTEX
:
1081 v3d_nir_lower_vs_early(c
);
1083 case MESA_SHADER_GEOMETRY
:
1084 v3d_nir_lower_gs_early(c
);
1086 case MESA_SHADER_FRAGMENT
:
1087 v3d_nir_lower_fs_early(c
);
1095 switch (c
->s
->info
.stage
) {
1096 case MESA_SHADER_VERTEX
:
1097 v3d_nir_lower_vs_late(c
);
1099 case MESA_SHADER_GEOMETRY
:
1100 v3d_nir_lower_gs_late(c
);
1102 case MESA_SHADER_FRAGMENT
:
1103 v3d_nir_lower_fs_late(c
);
1109 NIR_PASS_V(c
->s
, v3d_nir_lower_io
, c
);
1110 NIR_PASS_V(c
->s
, v3d_nir_lower_txf_ms
, c
);
1111 NIR_PASS_V(c
->s
, v3d_nir_lower_image_load_store
);
1112 NIR_PASS_V(c
->s
, nir_lower_idiv
, nir_lower_idiv_fast
);
1114 v3d_optimize_nir(c
->s
);
1116 /* Do late algebraic optimization to turn add(a, neg(b)) back into
1117 * subs, then the mandatory cleanup after algebraic. Note that it may
1118 * produce fnegs, and if so then we need to keep running to squash
1121 bool more_late_algebraic
= true;
1122 while (more_late_algebraic
) {
1123 more_late_algebraic
= false;
1124 NIR_PASS(more_late_algebraic
, c
->s
, nir_opt_algebraic_late
);
1125 NIR_PASS_V(c
->s
, nir_opt_constant_folding
);
1126 NIR_PASS_V(c
->s
, nir_copy_prop
);
1127 NIR_PASS_V(c
->s
, nir_opt_dce
);
1128 NIR_PASS_V(c
->s
, nir_opt_cse
);
1131 NIR_PASS_V(c
->s
, nir_lower_bool_to_int32
);
1132 NIR_PASS_V(c
->s
, nir_convert_from_ssa
, true);
1134 struct nir_schedule_options schedule_options
= {
1135 /* Schedule for about half our register space, to enable more
1136 * shaders to hit 4 threads.
1140 /* Vertex shaders share the same memory for inputs and outputs,
1141 * fragement and geometry shaders do not.
1143 .stages_with_shared_io_memory
=
1144 (((1 << MESA_ALL_SHADER_STAGES
) - 1) &
1145 ~((1 << MESA_SHADER_FRAGMENT
) |
1146 (1 << MESA_SHADER_GEOMETRY
))),
1148 .intrinsic_cb
= v3d_intrinsic_dependency_cb
,
1149 .intrinsic_cb_data
= c
,
1151 NIR_PASS_V(c
->s
, nir_schedule
, &schedule_options
);
1155 v3d_set_prog_data(c
, prog_data
);
1157 *out_prog_data
= prog_data
;
1160 int ret
= asprintf(&shaderdb
,
1161 "%s shader: %d inst, %d threads, %d loops, "
1162 "%d uniforms, %d max-temps, %d:%d spills:fills, "
1163 "%d sfu-stalls, %d inst-and-stalls",
1164 vir_get_stage_name(c
),
1169 vir_get_max_temps(c
),
1172 c
->qpu_inst_stalled_count
,
1173 c
->qpu_inst_count
+ c
->qpu_inst_stalled_count
);
1175 if (V3D_DEBUG
& V3D_DEBUG_SHADERDB
)
1176 fprintf(stderr
, "SHADER-DB: %s\n", shaderdb
);
1178 c
->debug_output(shaderdb
, c
->debug_output_data
);
1182 return v3d_return_qpu_insts(c
, final_assembly_size
);
1186 vir_remove_instruction(struct v3d_compile
*c
, struct qinst
*qinst
)
1188 if (qinst
->dst
.file
== QFILE_TEMP
)
1189 c
->defs
[qinst
->dst
.index
] = NULL
;
1191 assert(&qinst
->link
!= c
->cursor
.link
);
1193 list_del(&qinst
->link
);
1196 c
->live_intervals_valid
= false;
1200 vir_follow_movs(struct v3d_compile
*c
, struct qreg reg
)
1203 int pack = reg.pack;
1205 while (reg.file == QFILE_TEMP &&
1206 c->defs[reg.index] &&
1207 (c->defs[reg.index]->op == QOP_MOV ||
1208 c->defs[reg.index]->op == QOP_FMOV) &&
1209 !c->defs[reg.index]->dst.pack &&
1210 !c->defs[reg.index]->src[0].pack) {
1211 reg = c->defs[reg.index]->src[0];
1220 vir_compile_destroy(struct v3d_compile
*c
)
1222 /* Defuse the assert that we aren't removing the cursor's instruction.
1224 c
->cursor
.link
= NULL
;
1226 vir_for_each_block(block
, c
) {
1227 while (!list_is_empty(&block
->instructions
)) {
1228 struct qinst
*qinst
=
1229 list_first_entry(&block
->instructions
,
1230 struct qinst
, link
);
1231 vir_remove_instruction(c
, qinst
);
1239 vir_get_uniform_index(struct v3d_compile
*c
,
1240 enum quniform_contents contents
,
1243 for (int i
= 0; i
< c
->num_uniforms
; i
++) {
1244 if (c
->uniform_contents
[i
] == contents
&&
1245 c
->uniform_data
[i
] == data
) {
1250 uint32_t uniform
= c
->num_uniforms
++;
1252 if (uniform
>= c
->uniform_array_size
) {
1253 c
->uniform_array_size
= MAX2(MAX2(16, uniform
+ 1),
1254 c
->uniform_array_size
* 2);
1256 c
->uniform_data
= reralloc(c
, c
->uniform_data
,
1258 c
->uniform_array_size
);
1259 c
->uniform_contents
= reralloc(c
, c
->uniform_contents
,
1260 enum quniform_contents
,
1261 c
->uniform_array_size
);
1264 c
->uniform_contents
[uniform
] = contents
;
1265 c
->uniform_data
[uniform
] = data
;
1271 vir_uniform(struct v3d_compile
*c
,
1272 enum quniform_contents contents
,
1275 struct qinst
*inst
= vir_NOP(c
);
1276 inst
->qpu
.sig
.ldunif
= true;
1277 inst
->uniform
= vir_get_uniform_index(c
, contents
, data
);
1278 inst
->dst
= vir_get_temp(c
);
1279 c
->defs
[inst
->dst
.index
] = inst
;
1283 #define OPTPASS(func) \
1285 bool stage_progress = func(c); \
1286 if (stage_progress) { \
1288 if (print_opt_debug) { \
1290 "VIR opt pass %2d: %s progress\n", \
1293 /*XXX vir_validate(c);*/ \
1298 vir_optimize(struct v3d_compile
*c
)
1300 bool print_opt_debug
= false;
1304 bool progress
= false;
1306 OPTPASS(vir_opt_copy_propagate
);
1307 OPTPASS(vir_opt_redundant_flags
);
1308 OPTPASS(vir_opt_dead_code
);
1309 OPTPASS(vir_opt_small_immediates
);
1319 vir_get_stage_name(struct v3d_compile
*c
)
1321 if (c
->vs_key
&& c
->vs_key
->is_coord
)
1322 return "MESA_SHADER_VERTEX_BIN";
1323 else if (c
->gs_key
&& c
->gs_key
->is_coord
)
1324 return "MESA_SHADER_GEOMETRY_BIN";
1326 return gl_shader_stage_name(c
->s
->info
.stage
);