2 * Copyright © 2016-2017 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "broadcom/common/v3d_device_info.h"
25 #include "v3d_compiler.h"
28 vir_get_non_sideband_nsrc(struct qinst
*inst
)
30 switch (inst
->qpu
.type
) {
31 case V3D_QPU_INSTR_TYPE_BRANCH
:
33 case V3D_QPU_INSTR_TYPE_ALU
:
34 if (inst
->qpu
.alu
.add
.op
!= V3D_QPU_A_NOP
)
35 return v3d_qpu_add_op_num_src(inst
->qpu
.alu
.add
.op
);
37 return v3d_qpu_mul_op_num_src(inst
->qpu
.alu
.mul
.op
);
44 vir_get_nsrc(struct qinst
*inst
)
46 int nsrc
= vir_get_non_sideband_nsrc(inst
);
48 if (vir_has_implicit_uniform(inst
))
55 vir_has_implicit_uniform(struct qinst
*inst
)
57 switch (inst
->qpu
.type
) {
58 case V3D_QPU_INSTR_TYPE_BRANCH
:
60 case V3D_QPU_INSTR_TYPE_ALU
:
61 switch (inst
->dst
.file
) {
65 return inst
->has_implicit_uniform
;
71 /* The sideband uniform for textures gets stored after the normal ALU
75 vir_get_implicit_uniform_src(struct qinst
*inst
)
77 return vir_get_nsrc(inst
) - 1;
81 * Returns whether the instruction has any side effects that must be
85 vir_has_side_effects(struct v3d_compile
*c
, struct qinst
*inst
)
87 switch (inst
->qpu
.type
) {
88 case V3D_QPU_INSTR_TYPE_BRANCH
:
90 case V3D_QPU_INSTR_TYPE_ALU
:
91 switch (inst
->qpu
.alu
.add
.op
) {
92 case V3D_QPU_A_SETREVF
:
93 case V3D_QPU_A_SETMSF
:
94 case V3D_QPU_A_VPMSETUP
:
95 case V3D_QPU_A_STVPMV
:
96 case V3D_QPU_A_STVPMD
:
97 case V3D_QPU_A_STVPMP
:
104 switch (inst
->qpu
.alu
.mul
.op
) {
105 case V3D_QPU_M_MULTOP
:
112 if (inst
->qpu
.sig
.ldtmu
||
113 inst
->qpu
.sig
.wrtmuc
||
114 inst
->qpu
.sig
.thrsw
) {
122 vir_is_float_input(struct qinst
*inst
)
124 /* XXX: More instrs */
125 switch (inst
->qpu
.type
) {
126 case V3D_QPU_INSTR_TYPE_BRANCH
:
128 case V3D_QPU_INSTR_TYPE_ALU
:
129 switch (inst
->qpu
.alu
.add
.op
) {
134 case V3D_QPU_A_FTOIN
:
140 switch (inst
->qpu
.alu
.mul
.op
) {
142 case V3D_QPU_M_VFMUL
:
154 vir_is_raw_mov(struct qinst
*inst
)
156 if (inst
->qpu
.type
!= V3D_QPU_INSTR_TYPE_ALU
||
157 (inst
->qpu
.alu
.mul
.op
!= V3D_QPU_M_FMOV
&&
158 inst
->qpu
.alu
.mul
.op
!= V3D_QPU_M_MOV
)) {
162 if (inst
->qpu
.alu
.add
.output_pack
!= V3D_QPU_PACK_NONE
||
163 inst
->qpu
.alu
.mul
.output_pack
!= V3D_QPU_PACK_NONE
) {
167 if (inst
->qpu
.flags
.ac
!= V3D_QPU_COND_NONE
||
168 inst
->qpu
.flags
.mc
!= V3D_QPU_COND_NONE
)
175 vir_is_add(struct qinst
*inst
)
177 return (inst
->qpu
.type
== V3D_QPU_INSTR_TYPE_ALU
&&
178 inst
->qpu
.alu
.add
.op
!= V3D_QPU_A_NOP
);
182 vir_is_mul(struct qinst
*inst
)
184 return (inst
->qpu
.type
== V3D_QPU_INSTR_TYPE_ALU
&&
185 inst
->qpu
.alu
.mul
.op
!= V3D_QPU_M_NOP
);
189 vir_is_tex(struct qinst
*inst
)
191 if (inst
->dst
.file
== QFILE_MAGIC
)
192 return v3d_qpu_magic_waddr_is_tmu(inst
->dst
.index
);
198 vir_depends_on_flags(struct qinst
*inst
)
200 if (inst
->qpu
.type
== V3D_QPU_INSTR_TYPE_BRANCH
) {
201 return (inst
->qpu
.branch
.cond
!= V3D_QPU_BRANCH_COND_ALWAYS
);
203 return (inst
->qpu
.flags
.ac
!= V3D_QPU_COND_NONE
&&
204 inst
->qpu
.flags
.mc
!= V3D_QPU_COND_NONE
);
209 vir_writes_r3(const struct v3d_device_info
*devinfo
, struct qinst
*inst
)
211 for (int i
= 0; i
< vir_get_nsrc(inst
); i
++) {
212 switch (inst
->src
[i
].file
) {
221 if (devinfo
->ver
< 41 && (inst
->qpu
.sig
.ldvary
||
222 inst
->qpu
.sig
.ldtlb
||
223 inst
->qpu
.sig
.ldtlbu
||
224 inst
->qpu
.sig
.ldvpm
)) {
232 vir_writes_r4(const struct v3d_device_info
*devinfo
, struct qinst
*inst
)
234 switch (inst
->dst
.file
) {
236 switch (inst
->dst
.index
) {
237 case V3D_QPU_WADDR_RECIP
:
238 case V3D_QPU_WADDR_RSQRT
:
239 case V3D_QPU_WADDR_EXP
:
240 case V3D_QPU_WADDR_LOG
:
241 case V3D_QPU_WADDR_SIN
:
249 if (devinfo
->ver
< 41 && inst
->qpu
.sig
.ldtmu
)
256 vir_set_unpack(struct qinst
*inst
, int src
,
257 enum v3d_qpu_input_unpack unpack
)
259 assert(src
== 0 || src
== 1);
261 if (vir_is_add(inst
)) {
263 inst
->qpu
.alu
.add
.a_unpack
= unpack
;
265 inst
->qpu
.alu
.add
.b_unpack
= unpack
;
267 assert(vir_is_mul(inst
));
269 inst
->qpu
.alu
.mul
.a_unpack
= unpack
;
271 inst
->qpu
.alu
.mul
.b_unpack
= unpack
;
276 vir_set_cond(struct qinst
*inst
, enum v3d_qpu_cond cond
)
278 if (vir_is_add(inst
)) {
279 inst
->qpu
.flags
.ac
= cond
;
281 assert(vir_is_mul(inst
));
282 inst
->qpu
.flags
.mc
= cond
;
287 vir_set_pf(struct qinst
*inst
, enum v3d_qpu_pf pf
)
289 if (vir_is_add(inst
)) {
290 inst
->qpu
.flags
.apf
= pf
;
292 assert(vir_is_mul(inst
));
293 inst
->qpu
.flags
.mpf
= pf
;
299 vir_channels_written(struct qinst
*inst
)
301 if (vir_is_mul(inst
)) {
302 switch (inst
->dst
.pack
) {
303 case QPU_PACK_MUL_NOP
:
304 case QPU_PACK_MUL_8888
:
306 case QPU_PACK_MUL_8A
:
308 case QPU_PACK_MUL_8B
:
310 case QPU_PACK_MUL_8C
:
312 case QPU_PACK_MUL_8D
:
316 switch (inst
->dst
.pack
) {
318 case QPU_PACK_A_8888
:
319 case QPU_PACK_A_8888_SAT
:
320 case QPU_PACK_A_32_SAT
:
323 case QPU_PACK_A_8A_SAT
:
326 case QPU_PACK_A_8B_SAT
:
329 case QPU_PACK_A_8C_SAT
:
332 case QPU_PACK_A_8D_SAT
:
335 case QPU_PACK_A_16A_SAT
:
338 case QPU_PACK_A_16B_SAT
:
342 unreachable("Bad pack field");
347 vir_get_temp(struct v3d_compile
*c
)
351 reg
.file
= QFILE_TEMP
;
352 reg
.index
= c
->num_temps
++;
354 if (c
->num_temps
> c
->defs_array_size
) {
355 uint32_t old_size
= c
->defs_array_size
;
356 c
->defs_array_size
= MAX2(old_size
* 2, 16);
357 c
->defs
= reralloc(c
, c
->defs
, struct qinst
*,
359 memset(&c
->defs
[old_size
], 0,
360 sizeof(c
->defs
[0]) * (c
->defs_array_size
- old_size
));
367 vir_add_inst(enum v3d_qpu_add_op op
, struct qreg dst
, struct qreg src0
, struct qreg src1
)
369 struct qinst
*inst
= calloc(1, sizeof(*inst
));
371 inst
->qpu
= v3d_qpu_nop();
372 inst
->qpu
.alu
.add
.op
= op
;
383 vir_mul_inst(enum v3d_qpu_mul_op op
, struct qreg dst
, struct qreg src0
, struct qreg src1
)
385 struct qinst
*inst
= calloc(1, sizeof(*inst
));
387 inst
->qpu
= v3d_qpu_nop();
388 inst
->qpu
.alu
.mul
.op
= op
;
399 vir_branch_inst(enum v3d_qpu_branch_cond cond
, struct qreg src
)
401 struct qinst
*inst
= calloc(1, sizeof(*inst
));
403 inst
->qpu
= v3d_qpu_nop();
404 inst
->qpu
.type
= V3D_QPU_INSTR_TYPE_BRANCH
;
405 inst
->qpu
.branch
.cond
= cond
;
406 inst
->qpu
.branch
.msfign
= V3D_QPU_MSFIGN_NONE
;
407 inst
->qpu
.branch
.bdi
= V3D_QPU_BRANCH_DEST_REL
;
408 inst
->qpu
.branch
.ub
= true;
409 inst
->qpu
.branch
.bdu
= V3D_QPU_BRANCH_DEST_REL
;
411 inst
->dst
= vir_reg(QFILE_NULL
, 0);
419 vir_emit(struct v3d_compile
*c
, struct qinst
*inst
)
421 list_addtail(&inst
->link
, &c
->cur_block
->instructions
);
424 /* Updates inst to write to a new temporary, emits it, and notes the def. */
426 vir_emit_def(struct v3d_compile
*c
, struct qinst
*inst
)
428 assert(inst
->dst
.file
== QFILE_NULL
);
430 inst
->dst
= vir_get_temp(c
);
432 if (inst
->dst
.file
== QFILE_TEMP
)
433 c
->defs
[inst
->dst
.index
] = inst
;
441 vir_emit_nondef(struct v3d_compile
*c
, struct qinst
*inst
)
443 if (inst
->dst
.file
== QFILE_TEMP
)
444 c
->defs
[inst
->dst
.index
] = NULL
;
452 vir_new_block(struct v3d_compile
*c
)
454 struct qblock
*block
= rzalloc(c
, struct qblock
);
456 list_inithead(&block
->instructions
);
458 block
->predecessors
= _mesa_set_create(block
,
460 _mesa_key_pointer_equal
);
462 block
->index
= c
->next_block_index
++;
468 vir_set_emit_block(struct v3d_compile
*c
, struct qblock
*block
)
470 c
->cur_block
= block
;
471 list_addtail(&block
->link
, &c
->blocks
);
475 vir_entry_block(struct v3d_compile
*c
)
477 return list_first_entry(&c
->blocks
, struct qblock
, link
);
481 vir_exit_block(struct v3d_compile
*c
)
483 return list_last_entry(&c
->blocks
, struct qblock
, link
);
487 vir_link_blocks(struct qblock
*predecessor
, struct qblock
*successor
)
489 _mesa_set_add(successor
->predecessors
, predecessor
);
490 if (predecessor
->successors
[0]) {
491 assert(!predecessor
->successors
[1]);
492 predecessor
->successors
[1] = successor
;
494 predecessor
->successors
[0] = successor
;
498 const struct v3d_compiler
*
499 v3d_compiler_init(const struct v3d_device_info
*devinfo
)
501 struct v3d_compiler
*compiler
= rzalloc(NULL
, struct v3d_compiler
);
505 compiler
->devinfo
= devinfo
;
507 if (!vir_init_reg_sets(compiler
)) {
508 ralloc_free(compiler
);
516 v3d_compiler_free(const struct v3d_compiler
*compiler
)
518 ralloc_free((void *)compiler
);
521 static struct v3d_compile
*
522 vir_compile_init(const struct v3d_compiler
*compiler
,
525 int program_id
, int variant_id
)
527 struct v3d_compile
*c
= rzalloc(NULL
, struct v3d_compile
);
529 c
->compiler
= compiler
;
530 c
->devinfo
= compiler
->devinfo
;
532 c
->program_id
= program_id
;
533 c
->variant_id
= variant_id
;
536 s
= nir_shader_clone(c
, s
);
539 list_inithead(&c
->blocks
);
540 vir_set_emit_block(c
, vir_new_block(c
));
542 c
->output_position_index
= -1;
543 c
->output_point_size_index
= -1;
544 c
->output_sample_mask_index
= -1;
546 c
->def_ht
= _mesa_hash_table_create(c
, _mesa_hash_pointer
,
547 _mesa_key_pointer_equal
);
553 v3d_lower_nir(struct v3d_compile
*c
)
555 struct nir_lower_tex_options tex_options
= {
557 .lower_rect
= false, /* XXX */
559 /* Apply swizzles to all samplers. */
560 .swizzle_result
= ~0,
563 /* Lower the format swizzle and (for 32-bit returns)
564 * ARB_texture_swizzle-style swizzle.
566 for (int i
= 0; i
< ARRAY_SIZE(c
->key
->tex
); i
++) {
567 for (int j
= 0; j
< 4; j
++)
568 tex_options
.swizzles
[i
][j
] = c
->key
->tex
[i
].swizzle
[j
];
570 if (c
->key
->tex
[i
].clamp_s
)
571 tex_options
.saturate_s
|= 1 << i
;
572 if (c
->key
->tex
[i
].clamp_t
)
573 tex_options
.saturate_t
|= 1 << i
;
574 if (c
->key
->tex
[i
].clamp_r
)
575 tex_options
.saturate_r
|= 1 << i
;
578 NIR_PASS_V(c
->s
, nir_lower_tex
, &tex_options
);
582 v3d_lower_nir_late(struct v3d_compile
*c
)
584 NIR_PASS_V(c
->s
, v3d_nir_lower_io
, c
);
585 NIR_PASS_V(c
->s
, v3d_nir_lower_txf_ms
, c
);
586 NIR_PASS_V(c
->s
, nir_lower_idiv
);
590 v3d_set_prog_data_uniforms(struct v3d_compile
*c
,
591 struct v3d_prog_data
*prog_data
)
593 int count
= c
->num_uniforms
;
594 struct v3d_uniform_list
*ulist
= &prog_data
->uniforms
;
596 ulist
->count
= count
;
597 ulist
->data
= ralloc_array(prog_data
, uint32_t, count
);
598 memcpy(ulist
->data
, c
->uniform_data
,
599 count
* sizeof(*ulist
->data
));
600 ulist
->contents
= ralloc_array(prog_data
, enum quniform_contents
, count
);
601 memcpy(ulist
->contents
, c
->uniform_contents
,
602 count
* sizeof(*ulist
->contents
));
605 /* Copy the compiler UBO range state to the compiled shader, dropping out
606 * arrays that were never referenced by an indirect load.
608 * (Note that QIR dead code elimination of an array access still leaves that
609 * array alive, though)
612 v3d_set_prog_data_ubo(struct v3d_compile
*c
,
613 struct v3d_prog_data
*prog_data
)
615 if (!c
->num_ubo_ranges
)
618 prog_data
->num_ubo_ranges
= 0;
619 prog_data
->ubo_ranges
= ralloc_array(prog_data
, struct v3d_ubo_range
,
621 for (int i
= 0; i
< c
->num_ubo_ranges
; i
++) {
622 if (!c
->ubo_range_used
[i
])
625 struct v3d_ubo_range
*range
= &c
->ubo_ranges
[i
];
626 prog_data
->ubo_ranges
[prog_data
->num_ubo_ranges
++] = *range
;
627 prog_data
->ubo_size
+= range
->size
;
630 if (prog_data
->ubo_size
) {
631 if (V3D_DEBUG
& V3D_DEBUG_SHADERDB
) {
632 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
633 vir_get_stage_name(c
),
634 c
->program_id
, c
->variant_id
,
635 prog_data
->ubo_size
/ 4);
641 v3d_set_prog_data(struct v3d_compile
*c
,
642 struct v3d_prog_data
*prog_data
)
644 prog_data
->threads
= c
->threads
;
645 prog_data
->single_seg
= !c
->last_thrsw
;
647 v3d_set_prog_data_uniforms(c
, prog_data
);
648 v3d_set_prog_data_ubo(c
, prog_data
);
652 v3d_return_qpu_insts(struct v3d_compile
*c
, uint32_t *final_assembly_size
)
654 *final_assembly_size
= c
->qpu_inst_count
* sizeof(uint64_t);
656 uint64_t *qpu_insts
= malloc(*final_assembly_size
);
660 memcpy(qpu_insts
, c
->qpu_insts
, *final_assembly_size
);
662 vir_compile_destroy(c
);
667 uint64_t *v3d_compile_vs(const struct v3d_compiler
*compiler
,
668 struct v3d_vs_key
*key
,
669 struct v3d_vs_prog_data
*prog_data
,
671 int program_id
, int variant_id
,
672 uint32_t *final_assembly_size
)
674 struct v3d_compile
*c
= vir_compile_init(compiler
, &key
->base
, s
,
675 program_id
, variant_id
);
681 if (key
->clamp_color
)
682 NIR_PASS_V(c
->s
, nir_lower_clamp_color_outputs
);
684 if (key
->base
.ucp_enables
) {
685 NIR_PASS_V(c
->s
, nir_lower_clip_vs
, key
->base
.ucp_enables
);
686 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar
,
690 /* Note: VS output scalarizing must happen after nir_lower_clip_vs. */
691 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar
, nir_var_shader_out
);
693 v3d_lower_nir_late(c
);
694 v3d_optimize_nir(c
->s
);
695 NIR_PASS_V(c
->s
, nir_convert_from_ssa
, true);
699 v3d_set_prog_data(c
, &prog_data
->base
);
701 prog_data
->base
.num_inputs
= c
->num_inputs
;
703 /* The vertex data gets format converted by the VPM so that
704 * each attribute channel takes up a VPM column. Precompute
705 * the sizes for the shader record.
707 for (int i
= 0; i
< ARRAY_SIZE(prog_data
->vattr_sizes
); i
++) {
708 prog_data
->vattr_sizes
[i
] = c
->vattr_sizes
[i
];
709 prog_data
->vpm_input_size
+= c
->vattr_sizes
[i
];
712 /* Input/output segment size are in 8x32-bit multiples. */
713 prog_data
->vpm_input_size
= align(prog_data
->vpm_input_size
, 8) / 8;
714 prog_data
->vpm_output_size
= align(c
->num_vpm_writes
, 8) / 8;
716 prog_data
->uses_vid
= (s
->info
.system_values_read
&
717 (1ull << SYSTEM_VALUE_VERTEX_ID
));
718 prog_data
->uses_iid
= (s
->info
.system_values_read
&
719 (1ull << SYSTEM_VALUE_INSTANCE_ID
));
721 return v3d_return_qpu_insts(c
, final_assembly_size
);
725 v3d_set_fs_prog_data_inputs(struct v3d_compile
*c
,
726 struct v3d_fs_prog_data
*prog_data
)
728 prog_data
->base
.num_inputs
= c
->num_inputs
;
729 memcpy(prog_data
->input_slots
, c
->input_slots
,
730 c
->num_inputs
* sizeof(*c
->input_slots
));
732 STATIC_ASSERT(ARRAY_SIZE(prog_data
->flat_shade_flags
) >
733 (V3D_MAX_FS_INPUTS
- 1) / 24);
734 for (int i
= 0; i
< V3D_MAX_FS_INPUTS
; i
++) {
735 if (BITSET_TEST(c
->flat_shade_flags
, i
))
736 prog_data
->flat_shade_flags
[i
/ 24] |= 1 << (i
% 24);
740 uint64_t *v3d_compile_fs(const struct v3d_compiler
*compiler
,
741 struct v3d_fs_key
*key
,
742 struct v3d_fs_prog_data
*prog_data
,
744 int program_id
, int variant_id
,
745 uint32_t *final_assembly_size
)
747 struct v3d_compile
*c
= vir_compile_init(compiler
, &key
->base
, s
,
748 program_id
, variant_id
);
754 if (key
->light_twoside
)
755 NIR_PASS_V(c
->s
, nir_lower_two_sided_color
);
757 if (key
->clamp_color
)
758 NIR_PASS_V(c
->s
, nir_lower_clamp_color_outputs
);
760 if (key
->alpha_test
) {
761 NIR_PASS_V(c
->s
, nir_lower_alpha_test
, key
->alpha_test_func
,
765 if (key
->base
.ucp_enables
)
766 NIR_PASS_V(c
->s
, nir_lower_clip_fs
, key
->base
.ucp_enables
);
768 /* Note: FS input scalarizing must happen after
769 * nir_lower_two_sided_color, which only handles a vec4 at a time.
771 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar
, nir_var_shader_in
);
773 v3d_lower_nir_late(c
);
774 v3d_optimize_nir(c
->s
);
775 NIR_PASS_V(c
->s
, nir_convert_from_ssa
, true);
779 v3d_set_prog_data(c
, &prog_data
->base
);
780 v3d_set_fs_prog_data_inputs(c
, prog_data
);
781 prog_data
->writes_z
= (c
->s
->info
.outputs_written
&
782 (1 << FRAG_RESULT_DEPTH
));
783 prog_data
->discard
= c
->s
->info
.fs
.uses_discard
;
785 return v3d_return_qpu_insts(c
, final_assembly_size
);
789 vir_remove_instruction(struct v3d_compile
*c
, struct qinst
*qinst
)
791 if (qinst
->dst
.file
== QFILE_TEMP
)
792 c
->defs
[qinst
->dst
.index
] = NULL
;
794 list_del(&qinst
->link
);
799 vir_follow_movs(struct v3d_compile
*c
, struct qreg reg
)
804 while (reg.file == QFILE_TEMP &&
805 c->defs[reg.index] &&
806 (c->defs[reg.index]->op == QOP_MOV ||
807 c->defs[reg.index]->op == QOP_FMOV) &&
808 !c->defs[reg.index]->dst.pack &&
809 !c->defs[reg.index]->src[0].pack) {
810 reg = c->defs[reg.index]->src[0];
819 vir_compile_destroy(struct v3d_compile
*c
)
821 vir_for_each_block(block
, c
) {
822 while (!list_empty(&block
->instructions
)) {
823 struct qinst
*qinst
=
824 list_first_entry(&block
->instructions
,
826 vir_remove_instruction(c
, qinst
);
834 vir_uniform(struct v3d_compile
*c
,
835 enum quniform_contents contents
,
838 for (int i
= 0; i
< c
->num_uniforms
; i
++) {
839 if (c
->uniform_contents
[i
] == contents
&&
840 c
->uniform_data
[i
] == data
) {
841 return vir_reg(QFILE_UNIF
, i
);
845 uint32_t uniform
= c
->num_uniforms
++;
847 if (uniform
>= c
->uniform_array_size
) {
848 c
->uniform_array_size
= MAX2(MAX2(16, uniform
+ 1),
849 c
->uniform_array_size
* 2);
851 c
->uniform_data
= reralloc(c
, c
->uniform_data
,
853 c
->uniform_array_size
);
854 c
->uniform_contents
= reralloc(c
, c
->uniform_contents
,
855 enum quniform_contents
,
856 c
->uniform_array_size
);
859 c
->uniform_contents
[uniform
] = contents
;
860 c
->uniform_data
[uniform
] = data
;
862 return vir_reg(QFILE_UNIF
, uniform
);
866 vir_PF(struct v3d_compile
*c
, struct qreg src
, enum v3d_qpu_pf pf
)
868 struct qinst
*last_inst
= NULL
;
870 if (!list_empty(&c
->cur_block
->instructions
))
871 last_inst
= (struct qinst
*)c
->cur_block
->instructions
.prev
;
873 if (src
.file
!= QFILE_TEMP
||
874 !c
->defs
[src
.index
] ||
875 last_inst
!= c
->defs
[src
.index
]) {
876 /* XXX: Make the MOV be the appropriate type */
877 last_inst
= vir_MOV_dest(c
, vir_reg(QFILE_NULL
, 0), src
);
878 last_inst
= (struct qinst
*)c
->cur_block
->instructions
.prev
;
881 vir_set_pf(last_inst
, pf
);
884 #define OPTPASS(func) \
886 bool stage_progress = func(c); \
887 if (stage_progress) { \
889 if (print_opt_debug) { \
891 "VIR opt pass %2d: %s progress\n", \
894 /*XXX vir_validate(c);*/ \
899 vir_optimize(struct v3d_compile
*c
)
901 bool print_opt_debug
= false;
905 bool progress
= false;
907 OPTPASS(vir_opt_copy_propagate
);
908 OPTPASS(vir_opt_dead_code
);
918 vir_get_stage_name(struct v3d_compile
*c
)
920 if (c
->vs_key
&& c
->vs_key
->is_coord
)
921 return "MESA_SHADER_COORD";
923 return gl_shader_stage_name(c
->s
->info
.stage
);