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v3d: Fix setup of the VCM cache size.
[mesa.git] / src / broadcom / compiler / vir.c
1 /*
2 * Copyright © 2016-2017 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "broadcom/common/v3d_device_info.h"
25 #include "v3d_compiler.h"
26
27 int
28 vir_get_non_sideband_nsrc(struct qinst *inst)
29 {
30 switch (inst->qpu.type) {
31 case V3D_QPU_INSTR_TYPE_BRANCH:
32 return 0;
33 case V3D_QPU_INSTR_TYPE_ALU:
34 if (inst->qpu.alu.add.op != V3D_QPU_A_NOP)
35 return v3d_qpu_add_op_num_src(inst->qpu.alu.add.op);
36 else
37 return v3d_qpu_mul_op_num_src(inst->qpu.alu.mul.op);
38 }
39
40 return 0;
41 }
42
43 int
44 vir_get_nsrc(struct qinst *inst)
45 {
46 int nsrc = vir_get_non_sideband_nsrc(inst);
47
48 if (vir_has_implicit_uniform(inst))
49 nsrc++;
50
51 return nsrc;
52 }
53
54 bool
55 vir_has_implicit_uniform(struct qinst *inst)
56 {
57 switch (inst->qpu.type) {
58 case V3D_QPU_INSTR_TYPE_BRANCH:
59 return true;
60 case V3D_QPU_INSTR_TYPE_ALU:
61 switch (inst->dst.file) {
62 case QFILE_TLBU:
63 return true;
64 default:
65 return inst->has_implicit_uniform;
66 }
67 }
68 return false;
69 }
70
71 /* The sideband uniform for textures gets stored after the normal ALU
72 * arguments.
73 */
74 int
75 vir_get_implicit_uniform_src(struct qinst *inst)
76 {
77 if (!vir_has_implicit_uniform(inst))
78 return -1;
79 return vir_get_nsrc(inst) - 1;
80 }
81
82 /**
83 * Returns whether the instruction has any side effects that must be
84 * preserved.
85 */
86 bool
87 vir_has_side_effects(struct v3d_compile *c, struct qinst *inst)
88 {
89 switch (inst->qpu.type) {
90 case V3D_QPU_INSTR_TYPE_BRANCH:
91 return true;
92 case V3D_QPU_INSTR_TYPE_ALU:
93 switch (inst->qpu.alu.add.op) {
94 case V3D_QPU_A_SETREVF:
95 case V3D_QPU_A_SETMSF:
96 case V3D_QPU_A_VPMSETUP:
97 case V3D_QPU_A_STVPMV:
98 case V3D_QPU_A_STVPMD:
99 case V3D_QPU_A_STVPMP:
100 case V3D_QPU_A_VPMWT:
101 case V3D_QPU_A_TMUWT:
102 return true;
103 default:
104 break;
105 }
106
107 switch (inst->qpu.alu.mul.op) {
108 case V3D_QPU_M_MULTOP:
109 return true;
110 default:
111 break;
112 }
113 }
114
115 if (inst->qpu.sig.ldtmu ||
116 inst->qpu.sig.ldvary ||
117 inst->qpu.sig.wrtmuc ||
118 inst->qpu.sig.thrsw) {
119 return true;
120 }
121
122 return false;
123 }
124
125 bool
126 vir_is_float_input(struct qinst *inst)
127 {
128 /* XXX: More instrs */
129 switch (inst->qpu.type) {
130 case V3D_QPU_INSTR_TYPE_BRANCH:
131 return false;
132 case V3D_QPU_INSTR_TYPE_ALU:
133 switch (inst->qpu.alu.add.op) {
134 case V3D_QPU_A_FADD:
135 case V3D_QPU_A_FSUB:
136 case V3D_QPU_A_FMIN:
137 case V3D_QPU_A_FMAX:
138 case V3D_QPU_A_FTOIN:
139 return true;
140 default:
141 break;
142 }
143
144 switch (inst->qpu.alu.mul.op) {
145 case V3D_QPU_M_FMOV:
146 case V3D_QPU_M_VFMUL:
147 case V3D_QPU_M_FMUL:
148 return true;
149 default:
150 break;
151 }
152 }
153
154 return false;
155 }
156
157 bool
158 vir_is_raw_mov(struct qinst *inst)
159 {
160 if (inst->qpu.type != V3D_QPU_INSTR_TYPE_ALU ||
161 (inst->qpu.alu.mul.op != V3D_QPU_M_FMOV &&
162 inst->qpu.alu.mul.op != V3D_QPU_M_MOV)) {
163 return false;
164 }
165
166 if (inst->qpu.alu.add.output_pack != V3D_QPU_PACK_NONE ||
167 inst->qpu.alu.mul.output_pack != V3D_QPU_PACK_NONE) {
168 return false;
169 }
170
171 if (inst->qpu.flags.ac != V3D_QPU_COND_NONE ||
172 inst->qpu.flags.mc != V3D_QPU_COND_NONE)
173 return false;
174
175 return true;
176 }
177
178 bool
179 vir_is_add(struct qinst *inst)
180 {
181 return (inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU &&
182 inst->qpu.alu.add.op != V3D_QPU_A_NOP);
183 }
184
185 bool
186 vir_is_mul(struct qinst *inst)
187 {
188 return (inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU &&
189 inst->qpu.alu.mul.op != V3D_QPU_M_NOP);
190 }
191
192 bool
193 vir_is_tex(struct qinst *inst)
194 {
195 if (inst->dst.file == QFILE_MAGIC)
196 return v3d_qpu_magic_waddr_is_tmu(inst->dst.index);
197
198 if (inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU &&
199 inst->qpu.alu.add.op == V3D_QPU_A_TMUWT) {
200 return true;
201 }
202
203 return false;
204 }
205
206 bool
207 vir_depends_on_flags(struct qinst *inst)
208 {
209 if (inst->qpu.type == V3D_QPU_INSTR_TYPE_BRANCH) {
210 return (inst->qpu.branch.cond != V3D_QPU_BRANCH_COND_ALWAYS);
211 } else {
212 return (inst->qpu.flags.ac != V3D_QPU_COND_NONE &&
213 inst->qpu.flags.mc != V3D_QPU_COND_NONE);
214 }
215 }
216
217 bool
218 vir_writes_r3(const struct v3d_device_info *devinfo, struct qinst *inst)
219 {
220 for (int i = 0; i < vir_get_nsrc(inst); i++) {
221 switch (inst->src[i].file) {
222 case QFILE_VPM:
223 return true;
224 default:
225 break;
226 }
227 }
228
229 if (devinfo->ver < 41 && (inst->qpu.sig.ldvary ||
230 inst->qpu.sig.ldtlb ||
231 inst->qpu.sig.ldtlbu ||
232 inst->qpu.sig.ldvpm)) {
233 return true;
234 }
235
236 return false;
237 }
238
239 bool
240 vir_writes_r4(const struct v3d_device_info *devinfo, struct qinst *inst)
241 {
242 switch (inst->dst.file) {
243 case QFILE_MAGIC:
244 switch (inst->dst.index) {
245 case V3D_QPU_WADDR_RECIP:
246 case V3D_QPU_WADDR_RSQRT:
247 case V3D_QPU_WADDR_EXP:
248 case V3D_QPU_WADDR_LOG:
249 case V3D_QPU_WADDR_SIN:
250 return true;
251 }
252 break;
253 default:
254 break;
255 }
256
257 if (devinfo->ver < 41 && inst->qpu.sig.ldtmu)
258 return true;
259
260 return false;
261 }
262
263 void
264 vir_set_unpack(struct qinst *inst, int src,
265 enum v3d_qpu_input_unpack unpack)
266 {
267 assert(src == 0 || src == 1);
268
269 if (vir_is_add(inst)) {
270 if (src == 0)
271 inst->qpu.alu.add.a_unpack = unpack;
272 else
273 inst->qpu.alu.add.b_unpack = unpack;
274 } else {
275 assert(vir_is_mul(inst));
276 if (src == 0)
277 inst->qpu.alu.mul.a_unpack = unpack;
278 else
279 inst->qpu.alu.mul.b_unpack = unpack;
280 }
281 }
282
283 void
284 vir_set_cond(struct qinst *inst, enum v3d_qpu_cond cond)
285 {
286 if (vir_is_add(inst)) {
287 inst->qpu.flags.ac = cond;
288 } else {
289 assert(vir_is_mul(inst));
290 inst->qpu.flags.mc = cond;
291 }
292 }
293
294 void
295 vir_set_pf(struct qinst *inst, enum v3d_qpu_pf pf)
296 {
297 if (vir_is_add(inst)) {
298 inst->qpu.flags.apf = pf;
299 } else {
300 assert(vir_is_mul(inst));
301 inst->qpu.flags.mpf = pf;
302 }
303 }
304
305 #if 0
306 uint8_t
307 vir_channels_written(struct qinst *inst)
308 {
309 if (vir_is_mul(inst)) {
310 switch (inst->dst.pack) {
311 case QPU_PACK_MUL_NOP:
312 case QPU_PACK_MUL_8888:
313 return 0xf;
314 case QPU_PACK_MUL_8A:
315 return 0x1;
316 case QPU_PACK_MUL_8B:
317 return 0x2;
318 case QPU_PACK_MUL_8C:
319 return 0x4;
320 case QPU_PACK_MUL_8D:
321 return 0x8;
322 }
323 } else {
324 switch (inst->dst.pack) {
325 case QPU_PACK_A_NOP:
326 case QPU_PACK_A_8888:
327 case QPU_PACK_A_8888_SAT:
328 case QPU_PACK_A_32_SAT:
329 return 0xf;
330 case QPU_PACK_A_8A:
331 case QPU_PACK_A_8A_SAT:
332 return 0x1;
333 case QPU_PACK_A_8B:
334 case QPU_PACK_A_8B_SAT:
335 return 0x2;
336 case QPU_PACK_A_8C:
337 case QPU_PACK_A_8C_SAT:
338 return 0x4;
339 case QPU_PACK_A_8D:
340 case QPU_PACK_A_8D_SAT:
341 return 0x8;
342 case QPU_PACK_A_16A:
343 case QPU_PACK_A_16A_SAT:
344 return 0x3;
345 case QPU_PACK_A_16B:
346 case QPU_PACK_A_16B_SAT:
347 return 0xc;
348 }
349 }
350 unreachable("Bad pack field");
351 }
352 #endif
353
354 struct qreg
355 vir_get_temp(struct v3d_compile *c)
356 {
357 struct qreg reg;
358
359 reg.file = QFILE_TEMP;
360 reg.index = c->num_temps++;
361
362 if (c->num_temps > c->defs_array_size) {
363 uint32_t old_size = c->defs_array_size;
364 c->defs_array_size = MAX2(old_size * 2, 16);
365
366 c->defs = reralloc(c, c->defs, struct qinst *,
367 c->defs_array_size);
368 memset(&c->defs[old_size], 0,
369 sizeof(c->defs[0]) * (c->defs_array_size - old_size));
370
371 c->spillable = reralloc(c, c->spillable,
372 BITSET_WORD,
373 BITSET_WORDS(c->defs_array_size));
374 for (int i = old_size; i < c->defs_array_size; i++)
375 BITSET_SET(c->spillable, i);
376 }
377
378 return reg;
379 }
380
381 struct qinst *
382 vir_add_inst(enum v3d_qpu_add_op op, struct qreg dst, struct qreg src0, struct qreg src1)
383 {
384 struct qinst *inst = calloc(1, sizeof(*inst));
385
386 inst->qpu = v3d_qpu_nop();
387 inst->qpu.alu.add.op = op;
388
389 inst->dst = dst;
390 inst->src[0] = src0;
391 inst->src[1] = src1;
392 inst->uniform = ~0;
393
394 return inst;
395 }
396
397 struct qinst *
398 vir_mul_inst(enum v3d_qpu_mul_op op, struct qreg dst, struct qreg src0, struct qreg src1)
399 {
400 struct qinst *inst = calloc(1, sizeof(*inst));
401
402 inst->qpu = v3d_qpu_nop();
403 inst->qpu.alu.mul.op = op;
404
405 inst->dst = dst;
406 inst->src[0] = src0;
407 inst->src[1] = src1;
408 inst->uniform = ~0;
409
410 return inst;
411 }
412
413 struct qinst *
414 vir_branch_inst(enum v3d_qpu_branch_cond cond, struct qreg src)
415 {
416 struct qinst *inst = calloc(1, sizeof(*inst));
417
418 inst->qpu = v3d_qpu_nop();
419 inst->qpu.type = V3D_QPU_INSTR_TYPE_BRANCH;
420 inst->qpu.branch.cond = cond;
421 inst->qpu.branch.msfign = V3D_QPU_MSFIGN_NONE;
422 inst->qpu.branch.bdi = V3D_QPU_BRANCH_DEST_REL;
423 inst->qpu.branch.ub = true;
424 inst->qpu.branch.bdu = V3D_QPU_BRANCH_DEST_REL;
425
426 inst->dst = vir_reg(QFILE_NULL, 0);
427 inst->src[0] = src;
428 inst->uniform = ~0;
429
430 return inst;
431 }
432
433 static void
434 vir_emit(struct v3d_compile *c, struct qinst *inst)
435 {
436 switch (c->cursor.mode) {
437 case vir_cursor_add:
438 list_add(&inst->link, c->cursor.link);
439 break;
440 case vir_cursor_addtail:
441 list_addtail(&inst->link, c->cursor.link);
442 break;
443 }
444
445 c->cursor = vir_after_inst(inst);
446 c->live_intervals_valid = false;
447 }
448
449 /* Updates inst to write to a new temporary, emits it, and notes the def. */
450 struct qreg
451 vir_emit_def(struct v3d_compile *c, struct qinst *inst)
452 {
453 assert(inst->dst.file == QFILE_NULL);
454
455 /* If we're emitting an instruction that's a def, it had better be
456 * writing a register.
457 */
458 if (inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU) {
459 assert(inst->qpu.alu.add.op == V3D_QPU_A_NOP ||
460 v3d_qpu_add_op_has_dst(inst->qpu.alu.add.op));
461 assert(inst->qpu.alu.mul.op == V3D_QPU_M_NOP ||
462 v3d_qpu_mul_op_has_dst(inst->qpu.alu.mul.op));
463 }
464
465 inst->dst = vir_get_temp(c);
466
467 if (inst->dst.file == QFILE_TEMP)
468 c->defs[inst->dst.index] = inst;
469
470 vir_emit(c, inst);
471
472 return inst->dst;
473 }
474
475 struct qinst *
476 vir_emit_nondef(struct v3d_compile *c, struct qinst *inst)
477 {
478 if (inst->dst.file == QFILE_TEMP)
479 c->defs[inst->dst.index] = NULL;
480
481 vir_emit(c, inst);
482
483 return inst;
484 }
485
486 struct qblock *
487 vir_new_block(struct v3d_compile *c)
488 {
489 struct qblock *block = rzalloc(c, struct qblock);
490
491 list_inithead(&block->instructions);
492
493 block->predecessors = _mesa_set_create(block,
494 _mesa_hash_pointer,
495 _mesa_key_pointer_equal);
496
497 block->index = c->next_block_index++;
498
499 return block;
500 }
501
502 void
503 vir_set_emit_block(struct v3d_compile *c, struct qblock *block)
504 {
505 c->cur_block = block;
506 c->cursor = vir_after_block(block);
507 list_addtail(&block->link, &c->blocks);
508 }
509
510 struct qblock *
511 vir_entry_block(struct v3d_compile *c)
512 {
513 return list_first_entry(&c->blocks, struct qblock, link);
514 }
515
516 struct qblock *
517 vir_exit_block(struct v3d_compile *c)
518 {
519 return list_last_entry(&c->blocks, struct qblock, link);
520 }
521
522 void
523 vir_link_blocks(struct qblock *predecessor, struct qblock *successor)
524 {
525 _mesa_set_add(successor->predecessors, predecessor);
526 if (predecessor->successors[0]) {
527 assert(!predecessor->successors[1]);
528 predecessor->successors[1] = successor;
529 } else {
530 predecessor->successors[0] = successor;
531 }
532 }
533
534 const struct v3d_compiler *
535 v3d_compiler_init(const struct v3d_device_info *devinfo)
536 {
537 struct v3d_compiler *compiler = rzalloc(NULL, struct v3d_compiler);
538 if (!compiler)
539 return NULL;
540
541 compiler->devinfo = devinfo;
542
543 if (!vir_init_reg_sets(compiler)) {
544 ralloc_free(compiler);
545 return NULL;
546 }
547
548 return compiler;
549 }
550
551 void
552 v3d_compiler_free(const struct v3d_compiler *compiler)
553 {
554 ralloc_free((void *)compiler);
555 }
556
557 static struct v3d_compile *
558 vir_compile_init(const struct v3d_compiler *compiler,
559 struct v3d_key *key,
560 nir_shader *s,
561 int program_id, int variant_id)
562 {
563 struct v3d_compile *c = rzalloc(NULL, struct v3d_compile);
564
565 c->compiler = compiler;
566 c->devinfo = compiler->devinfo;
567 c->key = key;
568 c->program_id = program_id;
569 c->variant_id = variant_id;
570 c->threads = 4;
571
572 s = nir_shader_clone(c, s);
573 c->s = s;
574
575 list_inithead(&c->blocks);
576 vir_set_emit_block(c, vir_new_block(c));
577
578 c->output_position_index = -1;
579 c->output_point_size_index = -1;
580 c->output_sample_mask_index = -1;
581
582 c->def_ht = _mesa_hash_table_create(c, _mesa_hash_pointer,
583 _mesa_key_pointer_equal);
584
585 return c;
586 }
587
588 static void
589 v3d_lower_nir(struct v3d_compile *c)
590 {
591 struct nir_lower_tex_options tex_options = {
592 .lower_txd = true,
593 .lower_rect = false, /* XXX: Use this on V3D 3.x */
594 .lower_txp = ~0,
595 /* Apply swizzles to all samplers. */
596 .swizzle_result = ~0,
597 };
598
599 /* Lower the format swizzle and (for 32-bit returns)
600 * ARB_texture_swizzle-style swizzle.
601 */
602 for (int i = 0; i < ARRAY_SIZE(c->key->tex); i++) {
603 for (int j = 0; j < 4; j++)
604 tex_options.swizzles[i][j] = c->key->tex[i].swizzle[j];
605
606 if (c->key->tex[i].clamp_s)
607 tex_options.saturate_s |= 1 << i;
608 if (c->key->tex[i].clamp_t)
609 tex_options.saturate_t |= 1 << i;
610 if (c->key->tex[i].clamp_r)
611 tex_options.saturate_r |= 1 << i;
612 }
613
614 NIR_PASS_V(c->s, nir_lower_tex, &tex_options);
615 }
616
617 static void
618 v3d_lower_nir_late(struct v3d_compile *c)
619 {
620 NIR_PASS_V(c->s, v3d_nir_lower_io, c);
621 NIR_PASS_V(c->s, v3d_nir_lower_txf_ms, c);
622 NIR_PASS_V(c->s, nir_lower_idiv);
623 }
624
625 static void
626 v3d_set_prog_data_uniforms(struct v3d_compile *c,
627 struct v3d_prog_data *prog_data)
628 {
629 int count = c->num_uniforms;
630 struct v3d_uniform_list *ulist = &prog_data->uniforms;
631
632 ulist->count = count;
633 ulist->data = ralloc_array(prog_data, uint32_t, count);
634 memcpy(ulist->data, c->uniform_data,
635 count * sizeof(*ulist->data));
636 ulist->contents = ralloc_array(prog_data, enum quniform_contents, count);
637 memcpy(ulist->contents, c->uniform_contents,
638 count * sizeof(*ulist->contents));
639 }
640
641 /* Copy the compiler UBO range state to the compiled shader, dropping out
642 * arrays that were never referenced by an indirect load.
643 *
644 * (Note that QIR dead code elimination of an array access still leaves that
645 * array alive, though)
646 */
647 static void
648 v3d_set_prog_data_ubo(struct v3d_compile *c,
649 struct v3d_prog_data *prog_data)
650 {
651 if (!c->num_ubo_ranges)
652 return;
653
654 prog_data->num_ubo_ranges = 0;
655 prog_data->ubo_ranges = ralloc_array(prog_data, struct v3d_ubo_range,
656 c->num_ubo_ranges);
657 for (int i = 0; i < c->num_ubo_ranges; i++) {
658 if (!c->ubo_range_used[i])
659 continue;
660
661 struct v3d_ubo_range *range = &c->ubo_ranges[i];
662 prog_data->ubo_ranges[prog_data->num_ubo_ranges++] = *range;
663 prog_data->ubo_size += range->size;
664 }
665
666 if (prog_data->ubo_size) {
667 if (V3D_DEBUG & V3D_DEBUG_SHADERDB) {
668 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
669 vir_get_stage_name(c),
670 c->program_id, c->variant_id,
671 prog_data->ubo_size / 4);
672 }
673 }
674 }
675
676 static void
677 v3d_set_prog_data(struct v3d_compile *c,
678 struct v3d_prog_data *prog_data)
679 {
680 prog_data->threads = c->threads;
681 prog_data->single_seg = !c->last_thrsw;
682 prog_data->spill_size = c->spill_size;
683
684 v3d_set_prog_data_uniforms(c, prog_data);
685 v3d_set_prog_data_ubo(c, prog_data);
686 }
687
688 static uint64_t *
689 v3d_return_qpu_insts(struct v3d_compile *c, uint32_t *final_assembly_size)
690 {
691 *final_assembly_size = c->qpu_inst_count * sizeof(uint64_t);
692
693 uint64_t *qpu_insts = malloc(*final_assembly_size);
694 if (!qpu_insts)
695 return NULL;
696
697 memcpy(qpu_insts, c->qpu_insts, *final_assembly_size);
698
699 vir_compile_destroy(c);
700
701 return qpu_insts;
702 }
703
704 uint64_t *v3d_compile_vs(const struct v3d_compiler *compiler,
705 struct v3d_vs_key *key,
706 struct v3d_vs_prog_data *prog_data,
707 nir_shader *s,
708 int program_id, int variant_id,
709 uint32_t *final_assembly_size)
710 {
711 struct v3d_compile *c = vir_compile_init(compiler, &key->base, s,
712 program_id, variant_id);
713
714 c->vs_key = key;
715
716 v3d_lower_nir(c);
717
718 if (key->clamp_color)
719 NIR_PASS_V(c->s, nir_lower_clamp_color_outputs);
720
721 if (key->base.ucp_enables) {
722 NIR_PASS_V(c->s, nir_lower_clip_vs, key->base.ucp_enables);
723 NIR_PASS_V(c->s, nir_lower_io_to_scalar,
724 nir_var_shader_out);
725 }
726
727 /* Note: VS output scalarizing must happen after nir_lower_clip_vs. */
728 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_out);
729
730 v3d_lower_nir_late(c);
731 v3d_optimize_nir(c->s);
732 NIR_PASS_V(c->s, nir_convert_from_ssa, true);
733
734 v3d_nir_to_vir(c);
735
736 v3d_set_prog_data(c, &prog_data->base);
737
738 prog_data->base.num_inputs = c->num_inputs;
739
740 /* The vertex data gets format converted by the VPM so that
741 * each attribute channel takes up a VPM column. Precompute
742 * the sizes for the shader record.
743 */
744 for (int i = 0; i < ARRAY_SIZE(prog_data->vattr_sizes); i++) {
745 prog_data->vattr_sizes[i] = c->vattr_sizes[i];
746 prog_data->vpm_input_size += c->vattr_sizes[i];
747 }
748
749 prog_data->uses_vid = (s->info.system_values_read &
750 (1ull << SYSTEM_VALUE_VERTEX_ID));
751 prog_data->uses_iid = (s->info.system_values_read &
752 (1ull << SYSTEM_VALUE_INSTANCE_ID));
753
754 if (prog_data->uses_vid)
755 prog_data->vpm_input_size++;
756 if (prog_data->uses_iid)
757 prog_data->vpm_input_size++;
758
759 /* Input/output segment size are in sectors (8 rows of 32 bits per
760 * channel).
761 */
762 prog_data->vpm_input_size = align(prog_data->vpm_input_size, 8) / 8;
763 prog_data->vpm_output_size = align(c->num_vpm_writes, 8) / 8;
764
765 /* Compute VCM cache size. We set up our program to take up less than
766 * half of the VPM, so that any set of bin and render programs won't
767 * run out of space. We need space for at least one input segment,
768 * and then allocate the rest to output segments (one for the current
769 * program, the rest to VCM). The valid range of the VCM cache size
770 * field is 1-4 16-vertex batches, but GFXH-1744 limits us to 2-4
771 * batches.
772 */
773 assert(c->devinfo->vpm_size);
774 int sector_size = 16 * sizeof(uint32_t) * 8;
775 int vpm_size_in_sectors = c->devinfo->vpm_size / sector_size;
776 int half_vpm = vpm_size_in_sectors / 2;
777 int vpm_output_sectors = half_vpm - prog_data->vpm_input_size;
778 int vpm_output_batches = vpm_output_sectors / prog_data->vpm_output_size;
779 assert(vpm_output_batches >= 2);
780 prog_data->vcm_cache_size = CLAMP(vpm_output_batches - 1, 2, 4);
781
782 return v3d_return_qpu_insts(c, final_assembly_size);
783 }
784
785 static void
786 v3d_set_fs_prog_data_inputs(struct v3d_compile *c,
787 struct v3d_fs_prog_data *prog_data)
788 {
789 prog_data->base.num_inputs = c->num_inputs;
790 memcpy(prog_data->input_slots, c->input_slots,
791 c->num_inputs * sizeof(*c->input_slots));
792
793 STATIC_ASSERT(ARRAY_SIZE(prog_data->flat_shade_flags) >
794 (V3D_MAX_FS_INPUTS - 1) / 24);
795 for (int i = 0; i < V3D_MAX_FS_INPUTS; i++) {
796 if (BITSET_TEST(c->flat_shade_flags, i))
797 prog_data->flat_shade_flags[i / 24] |= 1 << (i % 24);
798
799 if (BITSET_TEST(c->noperspective_flags, i))
800 prog_data->noperspective_flags[i / 24] |= 1 << (i % 24);
801
802 if (BITSET_TEST(c->centroid_flags, i))
803 prog_data->centroid_flags[i / 24] |= 1 << (i % 24);
804 }
805 }
806
807 static void
808 v3d_fixup_fs_output_types(struct v3d_compile *c)
809 {
810 nir_foreach_variable(var, &c->s->outputs) {
811 uint32_t mask = 0;
812
813 switch (var->data.location) {
814 case FRAG_RESULT_COLOR:
815 mask = ~0;
816 break;
817 case FRAG_RESULT_DATA0:
818 case FRAG_RESULT_DATA1:
819 case FRAG_RESULT_DATA2:
820 case FRAG_RESULT_DATA3:
821 mask = 1 << (var->data.location - FRAG_RESULT_DATA0);
822 break;
823 }
824
825 if (c->fs_key->int_color_rb & mask) {
826 var->type =
827 glsl_vector_type(GLSL_TYPE_INT,
828 glsl_get_components(var->type));
829 } else if (c->fs_key->uint_color_rb & mask) {
830 var->type =
831 glsl_vector_type(GLSL_TYPE_UINT,
832 glsl_get_components(var->type));
833 }
834 }
835 }
836
837 uint64_t *v3d_compile_fs(const struct v3d_compiler *compiler,
838 struct v3d_fs_key *key,
839 struct v3d_fs_prog_data *prog_data,
840 nir_shader *s,
841 int program_id, int variant_id,
842 uint32_t *final_assembly_size)
843 {
844 struct v3d_compile *c = vir_compile_init(compiler, &key->base, s,
845 program_id, variant_id);
846
847 c->fs_key = key;
848
849 if (key->int_color_rb || key->uint_color_rb)
850 v3d_fixup_fs_output_types(c);
851
852 v3d_lower_nir(c);
853
854 if (key->light_twoside)
855 NIR_PASS_V(c->s, nir_lower_two_sided_color);
856
857 if (key->clamp_color)
858 NIR_PASS_V(c->s, nir_lower_clamp_color_outputs);
859
860 if (key->alpha_test) {
861 NIR_PASS_V(c->s, nir_lower_alpha_test, key->alpha_test_func,
862 false);
863 }
864
865 if (key->base.ucp_enables)
866 NIR_PASS_V(c->s, nir_lower_clip_fs, key->base.ucp_enables);
867
868 /* Note: FS input scalarizing must happen after
869 * nir_lower_two_sided_color, which only handles a vec4 at a time.
870 */
871 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_in);
872
873 v3d_lower_nir_late(c);
874 v3d_optimize_nir(c->s);
875 NIR_PASS_V(c->s, nir_convert_from_ssa, true);
876
877 v3d_nir_to_vir(c);
878
879 v3d_set_prog_data(c, &prog_data->base);
880 v3d_set_fs_prog_data_inputs(c, prog_data);
881 prog_data->writes_z = (c->s->info.outputs_written &
882 (1 << FRAG_RESULT_DEPTH));
883 prog_data->discard = (c->s->info.fs.uses_discard ||
884 c->fs_key->sample_alpha_to_coverage);
885 prog_data->uses_center_w = c->uses_center_w;
886
887 return v3d_return_qpu_insts(c, final_assembly_size);
888 }
889
890 void
891 vir_remove_instruction(struct v3d_compile *c, struct qinst *qinst)
892 {
893 if (qinst->dst.file == QFILE_TEMP)
894 c->defs[qinst->dst.index] = NULL;
895
896 assert(&qinst->link != c->cursor.link);
897
898 list_del(&qinst->link);
899 free(qinst);
900
901 c->live_intervals_valid = false;
902 }
903
904 struct qreg
905 vir_follow_movs(struct v3d_compile *c, struct qreg reg)
906 {
907 /* XXX
908 int pack = reg.pack;
909
910 while (reg.file == QFILE_TEMP &&
911 c->defs[reg.index] &&
912 (c->defs[reg.index]->op == QOP_MOV ||
913 c->defs[reg.index]->op == QOP_FMOV) &&
914 !c->defs[reg.index]->dst.pack &&
915 !c->defs[reg.index]->src[0].pack) {
916 reg = c->defs[reg.index]->src[0];
917 }
918
919 reg.pack = pack;
920 */
921 return reg;
922 }
923
924 void
925 vir_compile_destroy(struct v3d_compile *c)
926 {
927 /* Defuse the assert that we aren't removing the cursor's instruction.
928 */
929 c->cursor.link = NULL;
930
931 vir_for_each_block(block, c) {
932 while (!list_empty(&block->instructions)) {
933 struct qinst *qinst =
934 list_first_entry(&block->instructions,
935 struct qinst, link);
936 vir_remove_instruction(c, qinst);
937 }
938 }
939
940 ralloc_free(c);
941 }
942
943 struct qreg
944 vir_uniform(struct v3d_compile *c,
945 enum quniform_contents contents,
946 uint32_t data)
947 {
948 for (int i = 0; i < c->num_uniforms; i++) {
949 if (c->uniform_contents[i] == contents &&
950 c->uniform_data[i] == data) {
951 return vir_reg(QFILE_UNIF, i);
952 }
953 }
954
955 uint32_t uniform = c->num_uniforms++;
956
957 if (uniform >= c->uniform_array_size) {
958 c->uniform_array_size = MAX2(MAX2(16, uniform + 1),
959 c->uniform_array_size * 2);
960
961 c->uniform_data = reralloc(c, c->uniform_data,
962 uint32_t,
963 c->uniform_array_size);
964 c->uniform_contents = reralloc(c, c->uniform_contents,
965 enum quniform_contents,
966 c->uniform_array_size);
967 }
968
969 c->uniform_contents[uniform] = contents;
970 c->uniform_data[uniform] = data;
971
972 return vir_reg(QFILE_UNIF, uniform);
973 }
974
975 static bool
976 vir_can_set_flags(struct v3d_compile *c, struct qinst *inst)
977 {
978 if (c->devinfo->ver >= 40 && (v3d_qpu_reads_vpm(&inst->qpu) ||
979 v3d_qpu_uses_sfu(&inst->qpu))) {
980 return false;
981 }
982
983 return true;
984 }
985
986 void
987 vir_PF(struct v3d_compile *c, struct qreg src, enum v3d_qpu_pf pf)
988 {
989 struct qinst *last_inst = NULL;
990
991 if (!list_empty(&c->cur_block->instructions)) {
992 last_inst = (struct qinst *)c->cur_block->instructions.prev;
993
994 /* Can't stuff the PF into the last last inst if our cursor
995 * isn't pointing after it.
996 */
997 struct vir_cursor after_inst = vir_after_inst(last_inst);
998 if (c->cursor.mode != after_inst.mode ||
999 c->cursor.link != after_inst.link)
1000 last_inst = NULL;
1001 }
1002
1003 if (src.file != QFILE_TEMP ||
1004 !c->defs[src.index] ||
1005 last_inst != c->defs[src.index] ||
1006 !vir_can_set_flags(c, last_inst)) {
1007 /* XXX: Make the MOV be the appropriate type */
1008 last_inst = vir_MOV_dest(c, vir_reg(QFILE_NULL, 0), src);
1009 }
1010
1011 vir_set_pf(last_inst, pf);
1012 }
1013
1014 #define OPTPASS(func) \
1015 do { \
1016 bool stage_progress = func(c); \
1017 if (stage_progress) { \
1018 progress = true; \
1019 if (print_opt_debug) { \
1020 fprintf(stderr, \
1021 "VIR opt pass %2d: %s progress\n", \
1022 pass, #func); \
1023 } \
1024 /*XXX vir_validate(c);*/ \
1025 } \
1026 } while (0)
1027
1028 void
1029 vir_optimize(struct v3d_compile *c)
1030 {
1031 bool print_opt_debug = false;
1032 int pass = 1;
1033
1034 while (true) {
1035 bool progress = false;
1036
1037 OPTPASS(vir_opt_copy_propagate);
1038 OPTPASS(vir_opt_dead_code);
1039 OPTPASS(vir_opt_small_immediates);
1040
1041 if (!progress)
1042 break;
1043
1044 pass++;
1045 }
1046 }
1047
1048 const char *
1049 vir_get_stage_name(struct v3d_compile *c)
1050 {
1051 if (c->vs_key && c->vs_key->is_coord)
1052 return "MESA_SHADER_COORD";
1053 else
1054 return gl_shader_stage_name(c->s->info.stage);
1055 }